diff options
| author | Margarita Olaya Cabrera <magi.olaya@ti.com> | 2010-08-30 11:54:20 -0500 |
|---|---|---|
| committer | Ricardo Perez Olivares <x0081762@ti.com> | 2010-09-09 15:13:39 -0500 |
| commit | 9ee855e3b487cc2369010a64b2525a672ffa037d (patch) | |
| tree | f4fa7c7bc097b5c5b6a32a8a1be28eedf02c0750 | |
| parent | 67a51d55a0c1a3a8e9ffdedab8ce83dd92db8864 (diff) | |
ASoC: ABE DSP: Update to HAL0800
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>
41 files changed, 35634 insertions, 10224 deletions
diff --git a/sound/soc/omap/abe/C_ABE_FW.CM b/sound/soc/omap/abe/C_ABE_FW.CM index 977ccdf03cde..fa9594ad74b0 100644 --- a/sound/soc/omap/abe/C_ABE_FW.CM +++ b/sound/soc/omap/abe/C_ABE_FW.CM @@ -8,7 +8,7 @@ 0x001000, 0x001000, 0x151000, -0x141000, +0x201000, 0x001000, 0x001000, 0x001000, @@ -92,21 +92,21 @@ 0x001001, 0x000001, 0x001000, -0x002e04, +0x002e34, 0x001000, 0x001001, 0x000001, 0x001000, -0x002e04, +0x002e34, 0x151000, -0x002e04, -0x002e04, +0x002e34, +0x002e34, 0x151000, 0x001000, 0x001001, 0x000001, 0x001000, -0x002e44, +0x002e74, 0x001000, 0x001001, 0x001000, @@ -297,11 +297,10 @@ 0x000000, 0x000000, 0x000000, +0x001000, +0x001001, 0x000000, -0x000000, -0x000000, -0x000000, -0x000000, +0x011001, 0x000000, 0x000008, 0x700001, @@ -385,440 +384,440 @@ 0x000000, 0x000000, 0x000000, -0x023c94, -0x5ed280, -0x6a9a5d, -0xbf42f0, -0x056260, -0x0f02e8, -0xeb9d08, -0x13f0e8, -0xeed498, -0x0d8628, -0xf610e8, -0x06dac8, -0xfb8ca8, -0x02b6a8, -0x9d1d03, -0x3411d3, -0xe7110b, -0x0a8b43, 0xfc4793, -0x0208b8, -0x6d23e0, -0x66c791, -0xb09170, -0x142c90, -0x03c304, -0xf376f8, -0x0eb9d8, -0xf220d0, -0x0b9710, -0xf71850, -0x0661c0, -0xfbb618, -0x02b430, -0x99fe5b, -0x37ceab, -0xe408e3, -0x0c8ac3, +0x0a8b43, +0xe7110b, +0x3411d3, +0x9d1cfb, +0x02b6a8, +0xfb8ca8, +0x06dac8, +0xf610e8, +0x0d8628, +0xeed498, +0x13f0e8, +0xeb9d08, +0x0f02e8, +0x056260, +0xbf42f0, +0x6a9a5d, +0x5ed280, +0x023c94, 0xfb2e83, -0x0464a8, -0x782010, -0x61b101, -0xa7ab80, -0x1ef5c0, -0xfadbf0, -0xfa10a0, -0x0a1678, -0xf53c30, -0x09a2c0, -0xf83d98, -0x05c418, -0xfc0144, -0x0296d8, -0x9badf3, -0x386703, -0xe2e293, -0x0d8413, +0x0c8ac3, +0xe408e3, +0x37ceab, +0x99fe5b, +0x02b430, +0xfbb618, +0x0661c0, +0xf71850, +0x0b9710, +0xf220d0, +0x0eb9d8, +0xf37700, +0x03c304, +0x142c90, +0xb09170, +0x66c791, +0x6d23e0, +0x0208b8, 0xfa9443, -0x05d8f0, -0x42ccf5, -0x5b6439, -0x9fa4a8, -0x2a0528, -0xf141c8, -0x5c184b, -0x04be58, -0xf8ea80, -0x073f50, -0xf9b218, -0x04f108, -0xfc6e8c, -0x0264f0, -0xa04a13, -0x3770b3, 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-0x2a1533, -0xda3733, -0x1be75b, -0xee2313, -0x09f65b, +0x0b83a3, +0xea894b, +0x236a23, +0xcbda13, +0x4398b3, +0xb6e5bb, +0x3575db, +0x0eee5b, +0xfd6ac0, +0x06e2f8, +0xf20c30, +0x18d298, +0xd68e40, +0x423000, +0x9cd148, +0x716ee8, +0x5b537d, +0x12b270, 0xfb4feb, -0x1db640, -0x64f695, -0x4768e0, -0xaaa7f0, -0x41db98, -0xd1bd70, -0x1f1310, -0xebf900, -0x0c0d48, -0xf961f0, -0x032d94, -0xb409ab, -0x0aabc3, -0x108f73, -0xe8fccb, -0x13f29b, -0xf2141b, -0x08330b, +0x09f65b, +0xee2313, +0x1be763, +0xda372b, +0x2a1533, +0xe15813, +0xf2fbd3, +0x7127a3, +0xfb4778, +0x09ae08, +0xeeab88, +0x1c7728, +0xd365f8, +0x4306e0, +0xa2a0d0, +0x5cd070, +0x606a75, +0x17d078, 0xfc00bb, -0x2477b8, -0x68d739, -0x318e40, -0xb4aec0, -0x3ebd10, -0xd19bf0, -0x2095b8, -0xea0778, -0x0def88, -0xf7c838, -0x046be0, -0xfdea24, -0x319613, -0xf7da9b, -0xf7ab83, -0x0bd423, -0xf635fb, -0x064ca3, +0x08330b, +0xf2141b, +0x13f29b, +0xe8fcc3, +0x108f73, +0x0aabc3, +0xb409ab, +0x032d94, +0xf961f0, +0x0c0d48, +0xebf900, +0x1f1310, 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+0x1012a8, +0xf6b500, +0x054a20, +0xfd2bf0, +0x56a233, +0xddc993, +0x08d62b, 0x147503, -0x0e4b13, -0xcd04b3, -0x7d228f, -0xfbfbf8, -0x076f18, -0xf30060, -0x1688a8, -0xd5b880, -0x76d0d4, -0x63ddc5, -0xccb738, -0x1a0988, -0xf11b68, -0x089470, -0xfb4790, -0x025f04, -0xbeae3b, +0xc1a1c3, +0x023c70, +0xfb9490, +0x07fff0, +0xf221f8, +0x185148, +0xcf5d50, +0x6c0395, +0x60f058, +0xdb9f08, +0x139340, +0xf4b188, +0x067398, +0xfc8844, +0x6b2573, +0xd501e3, +0x0b96fb, 0x14d9d3, -0x10c49b, -0xc650c3, -0x022e24, -0xfb8f00, -0x082ea8, -0xf1b920, -0x18ca30, -0xd0ff50, -0x4640a1, -0x5ab67d, -0xcc3da8, -0x1aa578, -0xf0b7e8, -0x08ca48, -0xfb2f48, -0x0266a0, -0xbeb5b3, +0xbeae3b, +0x025f04, +0xfb4790, +0x089470, +0xf11b68, +0x1a0988, +0xccb738, +0x63ddc5, +0x76d0d4, +0xd5b880, +0x1688a8, +0xf30060, +0x076f18, +0xfbfbf8, +0x7d228f, +0xcd04b3, +0x0e4b13, 0x143ecb, +0xbeb5b3, +0x0266a0, +0xfb2f48, +0x08ca48, +0xf0b7e8, +0x1aa578, +0xcc3da8, +0x5ab67d, +0x4640a1, +0xd0ff50, +0x18ca30, +0xf1b920, +0x082ea8, +0xfb8f00, +0x022e24, +0xc650c3, +0x10c49b, 0x12d1ab, 0xc1642b, 0x02555c, @@ -837,132 +836,132 @@ 0x02555c, 0xc1642b, 0x12d1ab, -0x143ecb, -0xbeb5b3, -0x0266a0, -0xfb2f48, -0x08ca48, -0xf0b7e8, -0x1aa578, -0xcc3da8, -0x5ab67d, -0x4640a1, -0xd0ff50, -0x18ca30, -0xf1b920, -0x082ea8, -0xfb8f00, -0x022e24, -0xc650c3, 0x10c49b, -0x14d9d3, -0xbeae3b, -0x025f04, -0xfb4790, -0x089470, -0xf11b68, -0x1a0988, -0xccb738, -0x63ddc5, -0x76d0d4, -0xd5b880, -0x1688a8, -0xf30060, -0x076f18, -0xfbfbf8, -0x7d228f, -0xcd04b3, +0xc650c3, +0x022e24, +0xfb8f00, +0x082ea8, +0xf1b920, +0x18ca30, +0xd0ff50, +0x4640a1, +0x5ab67d, +0xcc3da8, +0x1aa578, +0xf0b7e8, +0x08ca48, +0xfb2f48, +0x0266a0, +0xbeb5b3, +0x143ecb, 0x0e4b13, -0x147503, -0xc1a1c3, -0x023c70, -0xfb9490, -0x07fff0, -0xf221f8, -0x185148, -0xcf5d50, -0x6c0395, -0x60f058, -0xdb9f08, -0x139340, -0xf4b188, -0x067398, -0xfc8844, -0x6b2573, -0xd501e3, +0xcd04b3, +0x7d228f, +0xfbfbf8, +0x076f18, +0xf30060, +0x1688a8, +0xd5b880, +0x76d0d4, +0x63ddc5, +0xccb738, +0x1a0988, +0xf11b68, +0x089470, +0xfb4790, +0x025f04, +0xbeae3b, +0x14d9d3, 0x0b96fb, -0x12ea3b, -0xc7c91b, -0x7f746f, -0xfc1754, -0x070c10, -0xf3cc50, -0x157878, -0xd45408, -0x72f70d, -0x4b56d0, -0xe26390, -0x1012a8, -0xf6b500, -0x054a20, -0xfd2bf0, -0x56a233, -0xddc993, +0xd501e3, +0x6b2573, +0xfc8844, +0x067398, +0xf4b188, +0x139340, +0xdb9f08, +0x60f058, +0x6c0395, +0xcf5d50, +0x185148, +0xf221f8, +0x07fff0, +0xfb9490, +0x023c70, +0xc1a1c3, +0x147503, 0x08d62b, -0x101e33, -0xd13c0b, -0x68d11b, -0xfcce9c, -0x05bc08, -0xf61488, -0x1185c8, -0xdbb070, -0x788dfd, -0x367598, -0xe9b5b8, -0x0c31f8, -0xf8f1a0, -0x040178, -0xfdde98, -0x40ab93, -0xe6e21b, +0xddc993, +0x56a233, +0xfd2bf0, +0x054a20, +0xf6b500, +0x1012a8, +0xe26390, +0x4b56d0, +0x72f70d, +0xd45408, +0x157878, +0xf3cc50, +0x070c10, +0xfc1754, +0x7f746f, +0xc7c91b, +0x12ea3b, 0x06309b, -0x0c0373, -0xddec9b, -0x4b880b, -0xfdb6d0, -0x041728, -0xf8ede8, -0x0c8b38, -0xe57730, -0x7ca649, -0x22b568, -0xf146b8, -0x081d20, -0xfb4da0, -0x02a8ac, -0xa5ff43, -0x2a4a93, -0xefdbfb, +0xe6e21b, +0x40ab93, +0xfdde98, +0x040178, +0xf8f1a0, +0x0c31f8, +0xe9b5b8, +0x367598, +0x788dfd, +0xdbb070, +0x1185c8, +0xf61488, +0x05bc08, +0xfcce9c, +0x68d11b, +0xd13c0b, +0x101e33, 0x03c6eb, -0x069cf3, -0xeda3d3, -0x284343, -0xb2821b, -0x0228bc, -0xfc4508, -0x06a660, -0xf19bc0, -0x7f26c5, -0x107398, -0xf8cbc0, -0x03fef8, -0xfdafb8, -0x539323, -0xd40cc3, -0x14740b, -0xf855f3, +0xefdbfb, +0x2a4a93, +0xa5ff43, +0x02a8ac, +0xfb4da0, +0x081d20, +0xf146b8, +0x22b568, +0x7ca649, +0xe57730, +0x0c8b38, +0xf8ede8, +0x041728, +0xfdb6d0, +0x4b880b, +0xddec9b, +0x0c0373, 0x01b16b, +0xf855f3, +0x14740b, +0xd40cc3, +0x539323, +0xfdafb8, +0x03fef8, +0xf8cbc0, +0x107398, +0x7f26c5, +0xf19bc0, +0x06a660, +0xfc4508, +0x0228bc, +0xb2821b, +0x284343, +0xeda3d3, +0x069cf3, 0x000003, 0x000003, 0x000003, @@ -971,8 +970,8 @@ 0x000003, 0x000003, 0x000003, -0x040002, 0x000003, +0x040002, 0x000003, 0x000003, 0x000003, @@ -1058,59 +1057,59 @@ 0x000000, 0x000000, 0x000000, -0x066c0c, -0x02f7d4, -0x08e904, -0x08e904, -0x02f7d4, -0x066c0c, -0x3fed7c, -0xfad3ae, -0x0bd74e, -0xf0b986, -0x0b091e, -0x268848, -0x11cef8, -0x357618, -0x357618, -0x11cef8, -0x268848, -0x3fed7c, -0xfad3ae, -0x0bd74e, -0xf0b986, -0x0b091e, -0x7e553d, -0xf81aae, -0x7e553d, -0x82cfe5, -0x07e942, -0x024414, -0xfbd614, -0x029540, -0x029540, -0xfbd614, -0x024414, -0x42e57d, -0xf4c9ee, -0x18b80e, -0xe3f162, -0x107002, -0x0d9878, -0xe70478, -0x0f7f80, -0x0f7f80, -0xe70478, -0x0d9878, -0x42e57d, -0xf4c9ee, -0x18b80e, -0xe3f162, -0x107002, -0x8f5ee9, -0x0a8f1e, -0xf570e6, -0x70a119, +0x0695c4, +0x7cdb3b, +0x0870d8, +0x0870d8, +0x7cdb3b, +0x0695c4, +0x4470ec, +0xfa825a, +0x0c7322, +0xf02316, +0x0b4d9e, +0x13c14c, +0x05da48, +0x195288, +0x195288, +0x05da48, +0x13c14c, +0x4470ec, +0xfa825a, +0x0c7322, +0xf02316, +0x0b4d9e, +0x7de295, +0xf821da, +0x7de295, +0x8431e5, +0x07dde2, +0x0271f8, +0xfb6e08, +0x02d334, +0x02d334, +0xfb6e08, +0x0271f8, +0x421c2d, +0xf4e40e, +0x188dd6, +0xe410d6, +0x1066c6, +0x0eabd0, +0xe49430, +0x10f338, +0x10f338, +0xe49430, +0x0eabd0, +0x421c2d, +0xf4e40e, +0x188dd6, +0xe410d6, +0x1066c6, +0x8e3ba9, +0x0aaa6a, +0xf5559a, +0x71c459, 0x651dd9, 0xf5c6b6, 0x0b0ede, @@ -1281,14 +1280,14 @@ 0x18a312, 0xe445b2, 0x10419e, -0x0b778c, -0x2223a0, -0x449ef0, -0x5cd51c, -0x5cd51c, -0x449ef0, -0x2223a0, -0x0b778c, +0x0b68e0, +0x21f7f0, +0x44471c, +0x5c5e48, +0x5c5e48, +0x44471c, +0x21f7f0, +0x0b68e0, 0x20ff38, 0xb24b3d, 0x062d86, @@ -1296,24 +1295,27 @@ 0x0d3f5a, 0xf2ea1a, 0x075f92, -0xc7b44f, -0xfd5ef4, -0xfb5588, -0xfb3e38, -0xfdee64, -0x02119c, -0x04c1c8, -0x04aa78, -0x02a10c, -0x384bb3, -0x1d48f4, -0x970ef1, -0x0bbdae, -0xe4af72, -0x2d79c2, -0xc7f1fa, -0x33c2ca, -0xdd52be, -0x0fe02e, +0xc1248b, +0xfd1080, +0xfaca4c, +0xfab048, +0xfdb0ac, +0x024f54, +0x054fb8, +0x0535b4, +0x02ef80, +0x3edb7b, +0x1d92ec, +0x962b59, +0x0bd422, +0xe48132, +0x2dbdc2, +0xc7a94a, +0x33fbe6, +0xdd3502, +0x0fea26, 0x3c0001, 0x080002, +0x000000, +0x040002, +0x040002, diff --git a/sound/soc/omap/abe/C_ABE_FW.PM b/sound/soc/omap/abe/C_ABE_FW.PM index 9ee53142d224..27e14d1c7b42 100644 --- a/sound/soc/omap/abe/C_ABE_FW.PM +++ b/sound/soc/omap/abe/C_ABE_FW.PM @@ -3,7 +3,7 @@ 0x08200000, 0x08200000, 0x07800000, -0x1602cfce, +0x1602d2ce, 0x014000e0, 0x014000e1, 0x014000e2, @@ -22,31 +22,31 @@ 0x014000ef, 0x144000e4, 0x9e000000, -0x0a202c30, +0x0a202d80, 0x9e000040, -0x0a202c30, +0x0a202d80, 0x9e000080, -0x0a202c30, +0x0a202d80, 0x9e0000c0, -0x0a202c30, +0x0a202d80, 0x9e080000, -0x0a202c30, +0x0a202d80, 0x9e080100, -0x0a202c30, +0x0a202d80, 0x9e080200, -0x0a202c30, +0x0a202d80, 0x9e080300, -0x0a202c30, +0x0a202d80, 0x9e080400, -0x0a202c30, +0x0a202d80, 0x9e080500, -0x0a202c30, +0x0a202d80, 0x9e080600, -0x0a202c30, +0x0a202d80, 0x9e080700, -0x0a202c30, +0x0a202d80, 0x9c050800, -0x0a202c30, +0x0a202d80, 0x16000010, 0x16000001, 0x17000102, @@ -101,11 +101,11 @@ 0x9d01b260, 0x9d02bc70, 0x08200000, -0x1602c548, +0x1602c888, 0x00000089, -0x1602c4ea, +0x1602c82a, 0x400000ac, -0x1602c486, +0x1602c7c6, 0x40000066, 0x0600000c, 0x0400069b, @@ -113,18 +113,18 @@ 0x1600274d, 0x0a200480, 0x4000009c, -0x1602c4ce, +0x1602c80e, 0x410000ec, 0x0600000c, 0x1600274d, 0x0a800890, -0x1602e703, +0x1602ea03, 0x00000030, 0x00000231, 0x00000435, 0x04800211, 0x04400511, -0x1602c604, +0x1602c944, 0x0000004e, 0x0300010e, 0x04800211, @@ -139,11 +139,11 @@ 0x41000089, 0x05c00b90, 0x4ac00720, -0x1602c4a5, +0x1602c7e5, 0x40000055, -0x1602c584, +0x1602c8c4, 0x40000047, -0x1602c60e, +0x1602c94e, 0x04000599, 0x400000e1, 0x04800177, @@ -153,9 +153,9 @@ 0x410000e1, 0x06000001, 0x4aa00a40, -0x1602c5cd, +0x1602c90d, 0x400000d6, -0x16022b49, +0x16022e89, 0x400002d7, 0x04800166, 0x41000089, @@ -163,10 +163,10 @@ 0x010000d6, 0x010002d7, 0x1600c005, -0x1602cf41, +0x1602d241, 0x16000002, 0x40000011, -0x1602cf00, +0x1602d200, 0x9e0e0550, 0xdd140530, 0x160ffff4, @@ -206,7 +206,7 @@ 0x07800000, 0x07800000, 0x07800000, -0x9d188108, +0x9d188148, 0x98800c90, 0x08200000, 0x9f158048, @@ -226,7 +226,7 @@ 0x9d1e8148, 0x98800da0, 0x08200000, -0x9c0c0018, +0x9f158018, 0x9f040010, 0x07800000, 0x9f03fc10, @@ -269,7 +269,7 @@ 0x9d0c8118, 0x98801070, 0x08200000, -0x9c1e0000, +0x9c1e0008, 0x9f1d0010, 0x07800000, 0x07800000, @@ -496,13 +496,13 @@ 0x413ffefe, 0x16000040, 0x9c010910, -0x0a203270, +0x0a2033c0, 0x14400040, 0x9c030810, 0x16000171, 0x9c009f30, 0x9c019220, -0x0a202d70, +0x0a202ec0, 0x9c009830, 0x003ffefe, 0x048ffeff, @@ -545,46 +545,66 @@ 0x160000f0, 0x9c100400, 0x9c100480, -0x9c1d06c8, +0x9c1d06c4, 0x9f085030, -0x9c180678, +0x9c180674, 0x9c180650, 0x058001a0, -0x0aa02540, +0x0aa02680, 0x04800144, 0x04400044, -0x07800000, +0x160ffff9, 0x05800040, -0x9d180658, -0x0a802350, -0x9d040008, -0x9e090000, -0x07800000, -0x07800000, -0x9e0d0500, -0x0a002420, +0x9d044690, +0x0aa023d0, 0x05800160, -0x0ac023d0, +0x0ac02370, 0x9e090000, 0x07800000, 0x07800000, 0x9e0d0500, 0x9d040508, -0x0a002420, +0x0a002540, 0x9d040008, 0x9e090000, 0x07800000, 0x9d040008, 0x9e0d0500, +0x0a002540, +0x9d040008, +0x9e090000, +0x07800000, +0x07800000, +0x9e0d0500, +0x1280010a, +0x048001a9, +0x05800940, +0x0aa02540, 0x05800160, -0x0ac02480, -0x0480014b, -0x044000bb, -0x4a0024b0, -0x1440004a, +0x00000628, +0x0ac024f0, +0x05800180, +0x0ae02540, +0x160ffff6, +0x160ffff7, +0x04a00144, +0x0a002540, +0x05800810, +0x0ae02540, +0x16000016, +0x16000007, +0x04a00144, +0x05800160, +0x9d180674, +0x9d180654, +0x0ac025c0, 0x0420040a, 0x04a001ab, +0x4a0025f0, +0x044000bb, +0x0480014b, 0x044000bb, +0x1440004a, 0x120001aa, 0x42000a38, 0x120001bb, @@ -592,66 +612,67 @@ 0x12000288, 0x12000299, 0x9e0e8280, -0xca002650, +0xca002790, 0x1e0e8390, -0xdd040608, +0xdd040604, 0x05800160, -0x0ac025f0, +0x0ac02730, 0x9d040008, 0x9e090000, 0x07800000, 0x05800040, 0x9e0d0500, -0x0aa02650, +0x0aa02790, 0x9d040508, -0x0a002650, +0x0a002790, 0x9e090000, 0x05800040, 0x9d040008, 0x9e0d0500, -0x0a802650, +0x0a802790, 0x9d040508, -0x9c1d06c8, -0xdc1d0648, +0x9c1d06c4, +0xdc1d0644, 0x1f0400b0, 0x9c100700, -0xdc1d06c8, +0xdc1d06c4, 0x1f040010, 0x9d108480, 0x9f0940b0, 0x9d108700, 0x00000cc9, 0x06000008, -0x0aa02840, -0xdc1d0688, +0x0aa02990, +0xdc1d0684, 0x14400005, -0x9c1d0608, +0xdc1d0604, +0x160fff8a, 0x04a00255, 0xdd108480, 0x16000017, 0xdd108700, 0x160ffff8, 0x05800540, -0x0aa02800, +0x0aa02950, 0x05800160, -0x0ac027f0, +0x0ac02940, 0x01000027, -0x0a002800, +0x0a002950, 0x01000028, 0x9e088000, 0xa0054dba, 0xa005c81a, -0x0a0028e0, -0xdd040608, -0x1e088000, +0x0a002a20, +0x9e088000, 0xa0054dba, 0xa005c81a, +0x160fffaa, 0x9f1f80b0, 0x9f1e0010, 0x9f040020, 0x9f040070, 0x9f020810, -0x9d040608, +0x9d0446a0, 0x9e0f0070, 0x9d0c8118, 0x98802210, @@ -673,7 +694,7 @@ 0x9d0c82b8, 0x07800000, 0x9d0c8318, -0x988029d0, +0x98802b20, 0x07800000, 0xa00602ba, 0x9c0c0118, @@ -687,9 +708,9 @@ 0x9c1d0548, 0x9f093860, 0x06000006, -0x0aa02b50, +0x0aa02ca0, 0x06000017, -0x0aa02b50, +0x0aa02ca0, 0x01800025, 0x9c0c0118, 0x9c0c01b0, @@ -700,9 +721,9 @@ 0x9c1d0548, 0x9f083860, 0x06000006, -0x0aa02c20, +0x0aa02d70, 0x06000017, -0x0aa02c20, +0x0aa02d70, 0x01800125, 0x08200000, 0x07800000, @@ -736,7 +757,7 @@ 0x9d0c8318, 0x9d0c81b8, 0x9d0c02b8, -0x98802dc0, +0x98802f10, 0x07800000, 0xa00602ba, 0x07800000, @@ -761,7 +782,7 @@ 0x07800000, 0x9d0c8318, 0x9d0c02b8, -0x98802ef0, +0x98803040, 0x9c0c0018, 0xa00602ba, 0x07800000, @@ -786,7 +807,7 @@ 0x9d0c8298, 0x9d0c8338, 0x9d0c8198, -0x988030d0, +0x98803220, 0x07800000, 0xa00602ba, 0xa006821a, @@ -801,9 +822,9 @@ 0xdd040008, 0x06000001, 0x04a00111, -0x0aa031f0, +0x0aa03340, 0x9d0c8118, -0x988031d0, +0x98803320, 0x08200000, 0x9c0c02b0, 0x9c0c0018, @@ -813,8 +834,8 @@ 0xdd0c81b8, 0x06000005, 0x04a00155, -0x0aa032c0, -0x98803280, +0x0aa03410, +0x988033d0, 0x08200000, 0x9f160028, 0x9f168298, @@ -824,7 +845,7 @@ 0x07800000, 0x9f160028, 0x9f168298, -0x98803360, +0x988034b0, 0x9d0c8128, 0x08200000, 0x9f160020, @@ -832,14 +853,14 @@ 0x07800000, 0x9d0c8108, 0x9d0c8258, -0x988033d0, +0x98803520, 0x08200000, 0x9f160010, 0x9f168068, 0x07800000, 0x07800000, 0x9d0c8128, -0x98803440, +0x98803590, 0x08200000, 0x9d008810, 0x1280020d, @@ -863,7 +884,7 @@ 0x9d0c87b8, 0x9d1082c8, 0x9d108288, -0x98803510, +0x98803660, 0x08200000, 0x00000003, 0x00000205, @@ -876,21 +897,21 @@ 0x07800000, 0x07800000, 0x9d0c8128, -0x98803690, +0x988037e0, 0x08200000, 0x010002fe, 0x00801605, -0x16002a63, +0x16002a83, 0x12000155, 0x0200035e, 0x0b200000, 0x00800405, -0x16002a63, +0x16002a83, 0x12000155, 0x0200035e, 0x0b200000, 0x00801705, -0x16002a63, +0x16002a83, 0x12000155, 0x0200035e, 0x0b200000, @@ -899,68 +920,6 @@ 0x08200000, 0x16000181, 0x04000101, -0x40000215, -0x048002ff, -0x00800b03, -0x00000017, -0x9e0e0450, -0x06000003, -0x16000004, -0x0aa03990, -0x01800354, -0x9c01b970, -0x00800715, -0x16002a66, -0x9c180404, -0x9c180480, -0x413ffefe, -0x12000155, -0x00800d0d, -0x0200056e, -0x9c051820, -0x0a003a40, -0x01800054, -0x9c01b870, -0x00800715, -0x16002a66, -0x9c180404, -0x9c180480, -0x413ffefe, -0x12000155, -0x00800d0d, -0x0200056e, -0x9c041920, -0x16014946, -0x16014987, -0x04a001dd, -0x9e0e0260, -0x9e0e0370, -0x0b200000, -0x00800b05, -0x0000021d, -0x003ffefe, -0x40000806, -0x06000005, -0x008007d7, -0x00000014, -0x4a803b50, -0x04500273, -0x9d03a040, -0x0a003b60, -0x9d03a140, -0x40800f02, -0x04c07f77, -0x9e0e0560, -0x40800a02, -0x04500273, -0x418007d3, -0x16000003, -0x048ffeff, -0x07800000, -0x9d140530, -0x08200000, -0x16000181, -0x04000101, 0x00800b03, 0x00000212, 0x00000017, @@ -969,7 +928,7 @@ 0xdc180404, 0x06000003, 0x9c180480, -0x0aa04000, +0x0aa03d10, 0x9c052b20, 0x9c042820, 0x9c023970, @@ -981,29 +940,25 @@ 0x00800e04, 0x00800503, 0x05800420, -0x17c00565, -0x0ae03ed0, +0x0ae03c00, 0x04000344, 0x05800420, -0x17c00565, -0x0ae03fc0, +0x0ae03cf0, 0x04000344, 0x05800420, -0x17c00565, -0x0ae03fc0, +0x0ae03cf0, +0x16000006, 0x04000344, 0x05800420, -0x0ae03ff0, +0x0ae03cf0, 0x16000016, 0x04000344, 0x05800420, -0x0ae03fc0, +0x0ae03cf0, 0x04000344, 0x05800420, -0x17c00565, -0x0ae03fc0, -0x14400065, -0x010000f5, +0x0ae03cf0, +0x010000f6, 0x12000132, 0x04000233, 0x9e088300, @@ -1017,11 +972,9 @@ 0x17800523, 0x04000377, 0x9e0f0070, -0x000000f5, -0x00000602, -0x04000522, -0x01000602, -0x0a004330, +0x000000f6, +0x01000606, +0x0a003fd0, 0x9c042b20, 0x9c052920, 0x9c023870, @@ -1033,30 +986,25 @@ 0x160ffff6, 0x00800503, 0x05800420, -0x17c00565, -0x0ae04220, +0x0ae03ee0, 0x04000344, 0x05800420, -0x17c00565, -0x0ae04300, +0x0ae03fc0, 0x04000344, 0x05800420, -0x17c00565, -0x0ae04300, +0x0ae03fc0, +0x16000006, 0x04000344, 0x05800420, -0x0ae04330, +0x0ae03fc0, 0x16000016, 0x04000344, 0x05800420, -0x17c00565, -0x0ae04300, +0x0ae03fc0, 0x04000344, 0x05800420, -0x17c00565, -0x0ae04300, -0x14400065, -0x010000f5, +0x0ae03fc0, +0x010000f6, 0x12000132, 0x04000233, 0x9e088300, @@ -1069,19 +1017,17 @@ 0x17800523, 0x04000377, 0x9e0f0170, -0x000000f5, -0x00000602, -0x04000522, -0x01000602, +0x000000f6, +0x01000606, 0x00800715, -0x16002a66, +0x16002a86, 0x410004fe, 0x12000155, 0x00000202, 0x00800d04, 0x0200056e, -0x16014946, -0x16014987, +0x16014906, +0x16014947, 0x0400042d, 0x04a001dd, 0x9e0e0260, @@ -1096,7 +1042,7 @@ 0x06000005, 0x40800f02, 0x04c07f77, -0x4a804560, +0x4a804200, 0x04500273, 0x00800a02, 0x9e088100, @@ -1132,7 +1078,7 @@ 0x07800000, 0x16000003, 0x9e0c8100, -0x1602da06, +0x1602dd06, 0x00000064, 0x1600003d, 0x04a00122, @@ -1147,17 +1093,19 @@ 0x9d0c810c, 0x9d0c815c, 0x9d0c81ac, -0x98804770, -0x0aa046f0, +0x98804410, +0x0aa04390, 0x9e0f0120, 0x08200000, +0x16014906, 0x40800605, 0x048004ff, 0x413ffcf8, 0x144000d3, 0x413ffef9, 0x144000e8, -0x16002a6e, +0x16002a8e, +0x9e0e0260, 0x12000155, 0x420005ee, 0x04a001dd, @@ -1172,20 +1120,20 @@ 0x04200355, 0x01000e05, 0x06000005, -0x0aa04b30, +0x0aa047f0, 0x40000403, 0x12000f98, 0x40800a06, 0x12800f88, 0x06000008, -0x4a804a40, +0x4a804700, 0x1600024d, 0x40001604, 0x04800199, 0x00001405, 0x01000e04, 0x01000c05, -0x0a004a90, +0x0a004750, 0x40001204, 0x04800199, 0x00001005, @@ -1195,11 +1143,11 @@ 0x16000014, 0x05c00d30, 0x9e0e8050, -0x0a804b20, +0x0a8047e0, 0x12000233, 0x9e0e0530, 0x9d140570, -0x0a004b30, +0x0a0047f0, 0x01800014, 0x003ffef9, 0x003ffcf8, @@ -1214,20 +1162,20 @@ 0x00000e04, 0x9c03a950, 0x06000004, -0x0a804ce0, +0x0a8049a0, 0x058004d0, -0x0ae04cd0, +0x0ae04990, 0x042004d2, 0x1440004d, -0x0a204810, +0x0a2044b0, 0x00000e04, 0x05800420, -0x0ae04ca0, -0x0a004ce0, +0x0ae04960, +0x0a0049a0, 0x1440002d, -0x0a204810, -0x0a004ce0, -0x0a204810, +0x0a2044b0, +0x0a0049a0, +0x0a2044b0, 0x003ffefe, 0x40800905, 0x048ffeff, @@ -1238,15 +1186,15 @@ 0x1440001d, 0x013ffaf9, 0x413ffcfa, -0x1602c5c9, +0x1602c909, 0x413ffefb, -0x16020002, +0x1601fe02, 0x00000095, 0x00000296, 0x9c018202, 0x01000025, 0x41400226, -0x16020803, +0x16020603, 0x04800122, 0x9e088200, 0x9e090300, @@ -1256,19 +1204,19 @@ 0x01c00127, 0x01c0012b, 0x9c018202, -0x98804e20, +0x98804ae0, 0x04800633, 0x04800122, 0x1440001d, 0x00000034, 0x04802833, 0x01400224, -0x98804ee0, -0x1602e6ca, +0x98804ba0, +0x1602e9ca, 0x16002102, 0x12000222, 0x408000a4, -0x1602e9cd, +0x1602eccd, 0x408001a5, 0x16000007, 0x9e0e0220, @@ -1288,7 +1236,7 @@ 0x408002d6, 0x04500944, 0x410000d7, -0x1602ea0a, +0x1602ed0a, 0x408003d9, 0x12000455, 0x410002d7, @@ -1307,8 +1255,8 @@ 0x04500944, 0x12000855, 0x04500544, -0x1602d98a, -0x1602d9cb, +0x1602dc8a, +0x1602dccb, 0x12000922, 0x04500244, 0x12000a88, @@ -1322,28 +1270,28 @@ 0x16000005, 0x16000006, 0x06000008, -0x0aa052f0, +0x0aa04fb0, 0x16000015, 0x000002a8, 0x06000009, -0x0aa05330, +0x0aa04ff0, 0x16000016, 0x000002b9, -0x1602cd82, +0x1602d0c2, 0x410000a8, 0x12000166, 0x410000b9, 0x04500655, 0x40800021, -0x1602c5cd, +0x1602c90d, 0x41800027, 0x06000004, -0x0aa05420, +0x0aa050e0, 0x06000005, -0x0aa054a0, +0x0aa05160, 0x06000001, -0x0aa05530, -0x0a005620, +0x0aa051f0, +0x0a0052e0, 0x160000a8, 0x400000d6, 0x12000c88, @@ -1351,7 +1299,7 @@ 0x07800000, 0x06000005, 0x9d180078, -0x0a805510, +0x0a8051d0, 0x160000c8, 0x400000d6, 0x12000c88, @@ -1360,7 +1308,7 @@ 0x07800000, 0x9d180078, 0x06000001, -0x0a8055a0, +0x0a805260, 0x160000d8, 0x400000d6, 0x12000c88, @@ -1376,23 +1324,23 @@ 0x9d03c890, 0x07800000, 0x9d140570, -0x1602c641, +0x1602c981, 0x16000013, 0x00000014, -0x1602c602, -0x00800041, +0x1602c942, +0x00000041, 0x16000005, 0x160ffff6, 0x05800510, -0x01800045, +0x01000045, 0x17000353, 0x17800363, 0x04800233, 0x01000023, -0x16008b60, +0x16008b50, 0x12000200, -0x1602f3c1, -0x16014983, +0x1602f6c1, +0x16014943, 0x9e0e0000, 0x9e0e0110, 0x9e0e0330, @@ -1416,6 +1364,58 @@ 0x003ff8f8, 0x048ff8ff, 0x08200000, +0x00000004, +0x00000405, +0x00000806, +0x00000c07, +0x05c00540, +0x0b800000, +0x9e0e8040, +0x9c180034, +0x07800000, +0x07800000, +0x06000033, +0x9e0e8220, +0x0aa05680, +0x9c1d0004, +0x9c1d0044, +0x07800000, +0x9d0c0210, +0x0a005730, +0x06000023, +0x0aa056e0, +0x9c1d0004, +0x9d040004, +0x9d100200, +0x0a005730, +0x06000043, +0x0aa05730, +0x9c180024, +0x9d040004, +0x9d180200, +0x04800c44, +0x05c00740, +0x17800644, +0x01000004, +0x0a0055a0, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, diff --git a/sound/soc/omap/abe/C_ABE_FW.SM32 b/sound/soc/omap/abe/C_ABE_FW.SM32 index 6db0c1468249..34822afed7e1 100644 --- a/sound/soc/omap/abe/C_ABE_FW.SM32 +++ b/sound/soc/omap/abe/C_ABE_FW.SM32 @@ -3,297 +3,297 @@ 0x00000000, 0x00000000, 0x00000000, -0x00044A03, +0x00044903, 0x00000000, -0x00044D02, +0x00044C02, 0x00000000, -0x0006C603, +0x0006C503, 0x00000000, -0x00049705, +0x00049605, 0x00000000, -0x00049C04, +0x00049B04, 0x00000000, -0x0006C105, +0x0006C005, 0x00000000, -0x00017D0C, +0x00017C0C, 0x00000000, -0x0004A028, +0x00049F28, 0x00000000, -0x0004F028, +0x0004EF28, 0x00000000, -0x00074E06, +0x00074D06, 0x00000000, -0x00022218, +0x00022118, 0x00000000, -0x00013412, +0x00013312, 0x00000000, -0x00014612, -0x00013100, -0x00015624, -0x00013212, -0x00014412, +0x00014512, +0x00013000, +0x00015524, +0x00013112, +0x00014312, 0x00120024, -0x00056000, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001560E, -0x0001590C, -0x00016404, -0x0001590C, -0x00016804, -0x00000000, -0x00016C02, -0x00000000, -0x00016E02, -0x0001650C, -0x00017004, -0x0001650C, -0x00017404, -0x00000000, -0x0001890C, -0x00000000, -0x0001950C, -0x00000000, -0x0001710C, -0x00000000, -0x0001650C, -0x00000000, -0x0001590C, -0x0001650C, -0x0001710C, -0x00000000, -0x0001A10C, -0x00000000, -0x0001B90C, -0x00000000, -0x0001C50C, -0x00000000, -0x0001F50C, -0x00020109, -0x00020109, -0x00000000, -0x00017A09, +0x00055C00, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001550E, +0x0001580C, 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0x00000000, -0x0003F618, +0x0003F518, 0x00000000, -0x00040E18, -0x00067C01, +0x00040D18, +0x00067B01, 0x00000202, 0x00000000, -0x00043E0C, +0x00043D0C, 0x000B0019, 0x00000000, 0x000B0009, 0x00000000, 0x00000000, -0x00044F18, +0x00044E18, 0x00000000, -0x00046718, +0x00046618, 0x00000000, -0x00047F18, -0x000B2DB8, +0x00047E18, +0x000B2DE8, 0x00000000, -0x000B2DB4, +0x000B2DE4, 0x00000000, -0x000B2DA0, +0x000B2DD0, 0x00000000, 0x00000000, -0x0004A028, -0x00019613, -0x00018313, -0x0004A028, +0x00049F28, +0x00028C13, +0x00029F13, +0x00049F28, +0x0002B400, 0x0002B500, -0x0002B600, -0x000B7108, +0x000B7D00, 0x005D0002, -0x00219800, +0x00217800, 0x00000000, -0x0004C828, -0x00019613, -0x00018313, -0x0004C828, +0x0004C728, +0x00028C13, +0x00029F13, +0x0004C728, +0x0002B200, 0x0002B300, -0x0002B400, -0x000B7908, +0x000B8500, 0x00620002, -0x00214800, +0x00212800, 0x00000000, -0x0004C828, +0x0004C728, 0x005D0004, -0x00219800, +0x00217800, 0x00620004, -0x00214800, +0x00212800, 0x00000000, -0x0004C828, +0x0004C728, 0x00000000, -0x0004F028, -0x0002C912, -0x0002B712, -0x0004F028, +0x0004EF28, +0x0003B212, +0x0003C412, +0x0004EF28, +0x0003D600, 0x0003D700, -0x0003D800, -0x000B8908, +0x000B9500, 0x006B000C, -0x00208000, -0x00000000, -0x0005180C, -0x0001B90C, -0x0001590C, -0x00000000, -0x0005240C, -0x00000000, -0x0005300C, -0x00022218, -0x00053C0C, -0x00022218, -0x0005480C, -0x00056D19, -0x00056D19, -0x00000000, -0x00040B19, -0x00055419, -0x00055419, -0x0003F219, -0x0003D919, -0x00000000, -0x00043F0B, -0x00000000, -0x00044A0B, -0x00000000, -0x00045507, -0x00000000, -0x0004240B, -0x00000000, -0x00042F0B, -0x00000000, -0x00043A05, -0x0005AA0B, -0x0005AA0B, -0x0005B507, -0x0005B507, -0x0005BC0B, -0x0005BC0B, -0x0005C705, -0x0005C705, -0x0005CC0B, -0x0005CC0B, -0x0005D707, -0x0005D707, -0x0005DE0B, -0x0005DE0B, -0x0005E905, -0x0005E905, -0x0005F00B, -0x0005F00B, -0x0005FB07, -0x0005FB07, -0x0006020B, -0x0006020B, -0x00060D05, -0x00060D05, -0x0006120B, -0x0006120B, -0x00061D07, -0x00061D07, -0x0006240B, -0x0006240B, -0x00062F05, -0x00062F05, -0x0006460B, -0x0006460B, -0x00065107, -0x00065107, -0x0006340B, -0x0006340B, -0x00063F05, -0x00063F05, -0x00000000, -0x00069928, -0x00000000, -0x0005A402, -0x00000000, -0x0005A604, +0x00215000, +0x00000000, +0x0005170C, +0x0001B80C, +0x0001580C, +0x00000000, +0x0005230C, +0x00000000, +0x00052F0C, +0x00022118, +0x00053B0C, +0x00022118, +0x0005470C, +0x00056C19, +0x00056C19, +0x00000000, +0x00040A19, +0x00055319, +0x00055319, +0x0003F119, +0x0003D819, +0x00000000, +0x00043E0B, +0x00000000, +0x0004490B, +0x00000000, +0x00045407, +0x00000000, +0x0004230B, +0x00000000, +0x00042E0B, +0x00000000, +0x00043905, +0x0005A90B, +0x0005A90B, +0x0005B407, +0x0005B407, +0x0005BB0B, +0x0005BB0B, +0x0005C605, +0x0005C605, +0x0005CB0B, +0x0005CB0B, +0x0005D607, +0x0005D607, +0x0005DD0B, +0x0005DD0B, +0x0005E805, +0x0005E805, +0x0005EF0B, +0x0005EF0B, +0x0005FA07, +0x0005FA07, +0x0006010B, +0x0006010B, +0x00060C05, +0x00060C05, +0x0006110B, +0x0006110B, +0x00061C07, +0x00061C07, +0x0006230B, +0x0006230B, +0x00062E05, +0x00062E05, +0x0006450B, +0x0006450B, +0x00065007, +0x00065007, +0x0006330B, +0x0006330B, +0x00063E05, +0x00063E05, +0x00000000, +0x00069828, +0x00000000, +0x0005A302, +0x00000000, +0x0005A504, 0x00000006, 0x00000000, 0x00000003, @@ -306,193 +306,193 @@ 0x00000000, 0x00030005, 0x00000000, -0x0005860F, -0x0005860F, +0x0005850F, +0x0005850F, 0x000B000F, 0x00000000, -0x0005950F, -0x0005950F, +0x0005940F, +0x0005940F, 0x00030007, 0x00000000, -0x00067E09, -0x00067E09, -0x0004AA09, -0x0004AA09, +0x00067D09, +0x00067D09, +0x0004A909, +0x0004A909, 0x000B0009, 0x00000000, 0x00000000, -0x00068D02, -0x00068703, -0x00068703, -0x000B9902, -0x0004B303, -0x00000003, -0x002E6C00, +0x00068C02, +0x00068603, +0x00068603, +0x000BA502, +0x0004B203, 0x00000003, 0x002E9C00, 0x00000003, -0x002EA000, -0x00000000, -0x00068F02, -0x00068A03, -0x00068A03, -0x000BA902, -0x0004B603, +0x002ECC00, 0x00000003, -0x002E6E00, -0x0006F909, -0x0006F909, -0x00070209, -0x00070209, -0x00000000, -0x0004B909, -0x00000000, -0x0004C209, -0x00000000, -0x00069102, -0x00070B03, -0x00070B03, -0x000BAB02, -0x0004CB03, -0x00000000, -0x00069502, -0x00070E03, -0x00070E03, -0x000BAF02, -0x0004CE03, -0x00000000, -0x00069302, -0x00071103, -0x00071103, -0x000BAD02, -0x0004D103, +0x002ED000, +0x00000000, +0x00068E02, +0x00068903, +0x00068903, +0x000BB502, +0x0004B503, 0x00000003, 0x002E9E00, +0x0006F809, +0x0006F809, +0x00070109, +0x00070109, +0x00000000, +0x0004B809, +0x00000000, +0x0004C109, +0x00000000, +0x00069002, +0x00070A03, +0x00070A03, +0x000BB702, +0x0004CA03, +0x00000000, +0x00069402, +0x00070D03, +0x00070D03, +0x000BBB02, +0x0004CD03, +0x00000000, +0x00069202, +0x00071003, +0x00071003, +0x000BB902, +0x0004D003, +0x00000003, +0x002ECE00, 0x00000000, -0x00069702, -0x00071403, -0x00071403, -0x000BB102, -0x0004D403, +0x00069602, +0x00071303, +0x00071303, +0x000BBD02, +0x0004D303, 0x00000003, -0x002EA200, +0x002ED200, 0x00000000, -0x0007170C, -0x00022218, -0x0007230C, -0x00022218, -0x00072F0C, +0x0007160C, +0x00022118, +0x0007220C, +0x00022118, +0x00072E0C, 0x00000000, -0x00067C01, +0x00067B01, 0x00000000, -0x00067D01, -0x00065611, -0x00065611, -0x00066715, -0x00066715, -0x00045C02, -0x00045E15, -0x00067D01, -0x00066715, -0x00047311, 0x00067C01, +0x00065511, +0x00065511, +0x00066615, +0x00066615, +0x00045B02, +0x00045D15, +0x00067C01, +0x00066615, +0x00047211, +0x00067B01, 0x00C40011, 0x0000C500, -0x00073B09, -0x00073B09, -0x00000000, -0x0004D909, -0x00074409, -0x00074409, -0x0004EB09, -0x0004E209, -0x000B6300, -0x00074D01, -0x00002D90, -0x00000000, -0x00000000, -0x00078606, -0x00022200, -0x0007A418, -0x0007BC0B, -0x0007BC0B, -0x00000000, -0x0004F80B, -0x00013100, -0x00078C18, -0x0007BC0B, -0x0007BC0B, -0x0007A418, -0x00078606, +0x00073A09, +0x00073A09, +0x00000000, +0x0004D809, +0x00074309, +0x00074309, +0x0004EA09, +0x0004E109, +0x000B6F00, +0x00074C01, +0x00002DC0, +0x00000000, +0x00000000, +0x00078506, +0x00022100, +0x0007A318, +0x0007BB0B, +0x0007BB0B, +0x00000000, +0x0004F70B, +0x00013000, +0x00078B18, +0x0007BB0B, +0x0007BB0B, +0x0007A318, +0x00078506, 0x00D2000B, 0x0000D300, 0x00000000, -0x00075406, -0x00022218, -0x00075B18, -0x0004F404, -0x00075A00, -0x00013100, -0x00077300, -0x000BA600, -0x00077412, +0x00075306, +0x00022118, +0x00075A18, +0x0004F304, +0x00075900, +0x00013000, +0x00077200, +0x000BB200, +0x00077312, 0x00EA00DA, 0x000026FF, 0x00000000, -0x00074E06, +0x00074D06, 0x00000000, 0x00100020, -0x00D82CA8, -0x0000002C, +0x000C2CDC, +0x0000002D, 0x00000000, -0x0005030F, -0x0007DF13, -0x0007DF13, +0x0005020F, +0x0007DE13, +0x0007DE13, 0x00000000, -0x00051213, +0x00051113, 0x00170013, 0x00000000, -0x0007F213, -0x0007F213, -0x00080513, -0x00080513, -0x00081813, -0x00081813, -0x00082B13, -0x00082B13, -0x00F82D90, +0x0007F113, +0x0007F113, +0x00080413, +0x00080413, +0x00081713, +0x00081713, +0x00082A13, +0x00082A13, +0x00F82DC0, 0x00000000, -0x00002080, +0x00002060, 0x00000000, -0x000020A8, +0x00002088, 0x00000000, -0x000020D0, +0x000020B0, 0x00000000, -0x000020F8, +0x000020D8, 0x00000000, -0x00002120, +0x00002100, 0x00000000, -0x00002148, +0x00002128, 0x00000000, -0x00002170, +0x00002150, 0x00000000, -0x00002198, +0x00002178, 0x00000000, -0x000021C0, +0x000021A0, 0x00000000, -0x000021E8, +0x000021C8, 0x00000000, -0x00002210, +0x000021F0, 0x00000000, -0x00002238, +0x00002218, 0x00000000, -0x00002260, +0x00002240, 0x00000000, -0x00002288, +0x00002268, 0x00000000, -0x000022B0, +0x00002290, 0x00000000, -0x000022D8, +0x000022B8, 0x00000000, 0x00000000, 0x00000000, @@ -527,59 +527,47 @@ 0x00000000, 0x00000000, 0x00000000, -0x000B1A10, +0x000B2710, 0x000F00F8, 0x00000000, 0x00000002, 0x00000000, 0x00000000, -0x00013100, +0x00013000, 0x00000000, -0x00013B0C, +0x00013A0C, 0x00000000, -0x00083E02, +0x00083D02, 0x00000000, -0x00084004, +0x00083F04, 0x00000000, -0x00084406, +0x00084306, 0x00000000, -0x00084A0C, +0x0008490C, 0x00000000, -0x00085648, +0x00085548, 0x00000000, -0x0004260C, +0x0004250C, 0x00000000, -0x0004320C, +0x0004310C, 0x00000000, -0x0001D10C, +0x0001D00C, 0x00000000, -0x0001DD0C, +0x0001DC0C, 0x00000000, -0x0001E902, +0x0001E802, 0x00000000, -0x0001EB04, +0x0001EA04, 0x00000000, -0x0001EF02, +0x0001EE02, 0x00000000, -0x0001F104, -0x00000000, -0x00086E0C, -0x00022218, -0x00087A0C, -0x00022218, -0x0008860C, -0x00002ECC, -0x00000000, -0x00002ED4, -0x00000000, -0x00002EDC, -0x00000000, -0x00002EE4, -0x00000000, -0x00002EEC, -0x00000000, -0x00002EF4, +0x0001F004, 0x00000000, +0x00086D0C, +0x00022118, +0x0008790C, +0x00022118, +0x0008850C, 0x00002EFC, 0x00000000, 0x00002F04, @@ -594,18 +582,28 @@ 0x00000000, 0x00002F2C, 0x00000000, +0x00002F34, 0x00000000, +0x00002F3C, 0x00000000, +0x00002F44, 0x00000000, +0x00002F4C, 0x00000000, +0x00002F54, 0x00000000, +0x00002F5C, 0x00000000, 0x00000000, +0x0008B800, 0x00000000, +0x000E4000, +0x0008B800, +0x00013000, +0x00003C18, 0x00000000, -0x00000000, -0x00000000, -0x00000000, +0x00052700, +0x00052701, 0x00000000, 0x00000000, 0x00000000, diff --git a/sound/soc/omap/abe/C_ABE_FW.lDM b/sound/soc/omap/abe/C_ABE_FW.lDM index 315022719db0..72e7b72a01b0 100644 --- a/sound/soc/omap/abe/C_ABE_FW.lDM +++ b/sound/soc/omap/abe/C_ABE_FW.lDM @@ -154,30 +154,43 @@ 0x00000000, 0x00000000, 0x00000000, -0x00006540, -0x033202D7, -0x031D033D, -0x00430327, -0x0344003A, -0x034B0363, -0x019E0308, -0x037004B7, -0x02C904D3, +0x00006582, +0x034702EC, +0x03320352, +0x0043033C, +0x0359003A, +0x03600378, +0x019E031D, +0x03850483, +0x02DE049F, 0x01EC01C0, -0x02EA0297, +0x02FF02AC, 0x018E00B3, 0x020B0157, -0x000201FD, -0x00C900C3, -0x00DA00D3, -0x00F100E4, -0x00FF00F8, -0x010F0107, -0x01310116, -0x00030148, -0x01550154, -0x04600156, -0x03C10383, +0x055601FD, +0x00C30002, +0x00D300C9, +0x00E400DA, +0x00F800F1, +0x010700FF, +0x0116010F, +0x01480131, +0x01540003, +0x01560155, +0x0398042A, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -2629,7 +2642,7 @@ 0x00000000, 0x00CF0001, 0x00D70056, -0x00000019, +0x0000012E, 0x00000000, 0x00030004, 0x000C0023, @@ -2783,9 +2796,9 @@ 0x00E50038, 0x00E200E1, 0x00000000, -0x00000000, -0x00000000, -0x00000000, +0x012B0019, +0x012C0001, +0x012D0001, 0x00000000, 0x00000000, 0x00000000, @@ -2835,12 +2848,11 @@ 0x00000010, 0x00000000, 0x00000000, -0x000022B4, +0x000022E8, 0x00000000, 0x0000FFF8, 0x00000018, -0x000022B0, -0x00000000, +0x000022E0, 0x00000000, 0x00000000, 0x00000000, @@ -2943,14 +2955,14 @@ 0x003FFFF0, 0x00000000, 0x00400000, -0x01960183, -0x01BC01A9, -0x01E201CF, -0x020801F5, -0x022E021B, -0x02540241, -0x027A0267, -0x02A0028D, +0x01950182, +0x01BB01A8, +0x01E101CE, +0x020701F4, +0x022D021A, +0x02530240, +0x02790266, +0x029F028C, 0x00000004, 0x00000001, 0x00000000, @@ -2959,14 +2971,14 @@ 0x003FFFF0, 0x00000000, 0x00400000, -0x02C902B7, -0x02ED02DB, -0x031102FF, -0x03350323, -0x03590347, -0x037D036B, -0x03A1038F, -0x03C503B3, +0x02C802B6, +0x02EC02DA, +0x031002FE, +0x03340322, +0x03580346, +0x037C036A, +0x03A0038E, +0x03C403B2, 0x00008363, 0x00000428, 0x00000000, @@ -2993,53 +3005,37 @@ 0x00000428, 0x00008363, 0x00000428, -0x25542704, -0x00002714, -0x254426E4, -0x000026F4, -0x29542694, -0x00002684, -0x29442674, -0x00002664, -0x253426C4, -0x000026D4, -0x252426A4, -0x000026B4, -0x29342614, -0x00002604, -0x292425F4, -0x000025E4, -0x25142644, -0x00002654, -0x25042624, -0x00002634, -0x27342454, -0x00002444, -0x25742474, -0x00002464, -0x25842494, -0x00002484, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, -0x00000000, +0x25882738, +0x00002748, +0x25782718, +0x00002728, +0x298826C8, +0x000026B8, +0x297826A8, +0x00002698, +0x256826F8, +0x00002708, +0x255826D8, +0x000026E8, +0x29682648, +0x00002638, +0x29582628, +0x00002618, +0x25482678, +0x00002688, +0x25382658, +0x00002668, +0x27682488, +0x00002478, +0x25A824A8, +0x00002498, +0x25B824C8, +0x000024B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x00003000, 0x00000000, 0x00000000, 0x00000000, @@ -3848,6 +3844,10 @@ 0x00000000, 0x00000000, 0x00000000, +0x00003900, +0x00003900, +0x00003900, +0x00003C17, 0x00000000, 0x00000000, 0x00000000, diff --git a/sound/soc/omap/abe/Makefile b/sound/soc/omap/abe/Makefile index a9e0a917d36a..ed3ac9ad0bf8 100644 --- a/sound/soc/omap/abe/Makefile +++ b/sound/soc/omap/abe/Makefile @@ -1,5 +1,6 @@ snd-soc-abe-hal-objs += abe_api.o \ abe_dbg.o \ + abe_dat.o \ abe_ext.o \ abe_ini.o \ abe_irq.o \ diff --git a/sound/soc/omap/abe/abe_api.c b/sound/soc/omap/abe/abe_api.c index f8038813e57c..3ec70e1ca619 100644 --- a/sound/soc/omap/abe/abe_api.c +++ b/sound/soc/omap/abe/abe_api.c @@ -1,11 +1,22 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" @@ -13,134 +24,170 @@ #include "abe_initxxx_labels.h" #include "abe_dbg.h" -static abe_uint32 ABE_FW_PM[ABE_PMEM_SIZE / 4] = { -#include "C_ABE_FW.PM" -}; -static abe_uint32 ABE_FW_CM[ABE_CMEM_SIZE / 4] = { -#include "C_ABE_FW.CM" -}; -static abe_uint32 ABE_FW_DM[ABE_DMEM_SIZE / 4] = { -#include "C_ABE_FW.lDM" -}; -static abe_uint32 ABE_FW_SM[ABE_SMEM_SIZE / 4] = { -#include "C_ABE_FW.SM32" -}; +//#include <linux/module.h> + /** -* @fn abe_reset_hal() -* -* Operations : reset the HAL by reloading the static variables and default AESS registers. -* Called after a PRCM cold-start reset of ABE -* -* @see ABE_API.h -*/ -void abe_reset_hal(void) + * abe_reset_hal - reset the ABE/HAL + * @rdev: regulator source + * @constraints: constraints to apply + * + * Operations : reset the HAL by reloading the static variables and + * default AESS registers. + * Called after a PRCM cold-start reset of ABE + */ +abehal_status abe_reset_hal (void) { - _lock_enter _log(id_reset_hal,0,0,0) - +#if 0 abe_dbg_output = TERMINAL_OUTPUT; - abe_irq_dbg_read_ptr = 0; /* IRQ & DBG circular read pointer in DMEM */ - abe_dbg_mask = (abe_dbg_t)(-1); /* set debug mask to "enable all traces" */ - abe_hw_configuration(); - _lock_exit + abe_dbg_activity_log_write_pointer = 0; + + /* IRQ & DBG circular read pointer in DMEM */ + abe_irq_dbg_read_ptr = 0; + + /* set debug mask to "enable all traces" */ + abe_dbg_mask = (abe_dbg_t)(0); +#endif + abe_hw_configuration(); + return 0; } +EXPORT_SYMBOL(abe_reset_hal); + + /** -* @fn abe_load_fwl() -* -* Operations : -* loads the Audio Engine firmware, generate a single pulse on the Event generator -* to let execution start, read the version number returned from this execution. -* -* @see ABE_API.h -*/ -void abe_load_fw_param(abe_uint32 *PMEM, abe_uint32 PMEM_SIZE, - abe_uint32 *CMEM, abe_uint32 CMEM_SIZE, - abe_uint32 *SMEM, abe_uint32 SMEM_SIZE, - abe_uint32 *DMEM, abe_uint32 DMEM_SIZE) + * abe_load_fw_param - Load ABE Firmware memories + * @PMEM: Pointer of Program memory data + * @PMEM_SIZE: Size of PMEM data + * @CMEM: Pointer of Coeffients memory data + * @CMEM_SIZE: Size of CMEM data + * @SMEM: Pointer of Sample memory data + * @SMEM_SIZE: Size of SMEM data + * @DMEM: Pointer of Data memory data + * @DMEM_SIZE: Size of DMEM data + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw_param (u32 *ABE_FW) { - static abe_uint32 warm_boot; - abe_uint32 event_gen; + static u32 warm_boot; + u32 event_gen; + u32 pmem_size, dmem_size, smem_size, cmem_size; + u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr; - _lock_enter _log(id_load_fw_param,0,0,0) - #if PC_SIMULATION - /* the code is loaded from the Checkers */ + /* the code is loaded from the Checkers */ #else +#define ABE_FW_OFFSET 5 + + fw_ptr = ABE_FW; + abe_firmware_version_number = *fw_ptr++; + pmem_size = *fw_ptr++; + cmem_size = *fw_ptr++; + dmem_size = *fw_ptr++; + smem_size = *fw_ptr++; + + pmem_ptr = fw_ptr; + cmem_ptr = pmem_ptr + (pmem_size >> 2); + dmem_ptr = cmem_ptr + (cmem_size >> 2); + smem_ptr = dmem_ptr + (dmem_size >> 2); + /* do not load PMEM */ if (warm_boot) { /* Stop the event Generator */ event_gen = 0; abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, - EVENT_GENERATOR_START, &event_gen, 4); + EVENT_GENERATOR_START, &event_gen, 4); /* Now we are sure the firmware is stalled */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, CMEM, CMEM_SIZE); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, SMEM, SMEM_SIZE); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, DMEM, DMEM_SIZE); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr, + cmem_size); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr, + smem_size); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr, + dmem_size); /* Restore the event Generator status */ event_gen = 1; abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, - EVENT_GENERATOR_START, &event_gen, 4); + EVENT_GENERATOR_START, &event_gen, 4); } else { - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, PMEM, PMEM_SIZE); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, CMEM, CMEM_SIZE); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, SMEM, SMEM_SIZE); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, DMEM, DMEM_SIZE); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, pmem_ptr, + pmem_size); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr, + cmem_size); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr, + smem_size); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr, + dmem_size); } warm_boot = 1; #endif - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_load_fw_param); + +/** + * abe_load_fw - Load ABE Firmware and initialize memories + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ -void abe_load_fw(void) +abehal_status abe_load_fw (void) { - _lock_enter + _log(id_load_fw,0,0,0) - abe_load_fw_param(ABE_FW_PM, sizeof (ABE_FW_PM), - ABE_FW_CM, sizeof(ABE_FW_CM), - ABE_FW_SM, sizeof(ABE_FW_SM), - ABE_FW_DM, sizeof(ABE_FW_DM)); + abe_load_fw_param ((u32 *)abe_firmware_array); abe_reset_all_ports(); - abe_build_scheduler_table(); - abe_reset_all_sequence(); + abe_build_scheduler_table (); + abe_reset_all_sequence (); abe_select_main_port(PDM_DL_PORT); - _lock_exit - + return 0; } +EXPORT_SYMBOL(abe_load_fw); -/* - * ABE_HARDWARE_CONFIGURATION - * - * Parameter : - * U : use-case description list (pointer) - * H : pointer to the output structure +/** + * abe_read_hardware_configuration - Return default HW periferals configuration + * @u: use-case description list (pointer) + * @o: opp mode (pointer) + * @hw: pointer to the output HW structure * - * Operations : - * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC - * will be upgraded in FW06 + + * Parameter : + * U : use-case description list (pointer) + * H : pointer to the output structure * - * Return value : - * None. + * Operations : + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + * will be upgraded in FW06 + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC */ -void abe_read_hardware_configuration(abe_use_case_id *u, abe_opp_t *o, abe_hw_config_init_t *hw) +abehal_status abe_read_hardware_configuration (u32 *u, u32 *o, abe_hw_config_init_t *hw) { - _lock_enter - _log(id_read_hardware_configuration,(abe_uint32)(u),(abe_uint32)u>>8,(abe_uint32)u>>16) - abe_read_use_case_opp(u, o); + _log(id_read_hardware_configuration, (u32)u, (u32)u>>8, (u32)u>>16) - hw->MCPDM_CTRL__DIV_SEL = 0; /* 0: 96kHz 1:192kHz */ - hw->MCPDM_CTRL__CMD_INT = 1; /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */ - hw->MCPDM_CTRL__PDMOUTFORMAT = 0; /* 0:MSB aligned 1:LSB aligned */ + abe_read_use_case_opp (u, o); + + /* 0: 96kHz 1:192kHz */ + hw->MCPDM_CTRL__DIV_SEL = 0; + + /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */ + hw->MCPDM_CTRL__CMD_INT = 1; + + /* 0:MSB aligned 1:LSB aligned */ + hw->MCPDM_CTRL__PDMOUTFORMAT = 0; hw->MCPDM_CTRL__PDM_DN5_EN = 1; hw->MCPDM_CTRL__PDM_DN4_EN = 1; hw->MCPDM_CTRL__PDM_DN3_EN = 1; @@ -149,73 +196,92 @@ void abe_read_hardware_configuration(abe_use_case_id *u, abe_opp_t *o, abe_hw_co hw->MCPDM_CTRL__PDM_UP3_EN = 0; hw->MCPDM_CTRL__PDM_UP2_EN = 1; hw->MCPDM_CTRL__PDM_UP1_EN = 1; - hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER/6; /* All the McPDM_DL FIFOs are enabled simultaneously */ - hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER/2; /* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels are enabled */ - hw->DMIC_CTRL__DMIC_CLK_DIV = 0; /* 0:2.4MHz 1:3.84MHz */ - hw->DMIC_CTRL__DMICOUTFORMAT = 0; /* 0:MSB aligned 1:LSB aligned */ + /* All the McPDM_DL FIFOs are enabled simultaneously */ + hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER/6; + + /* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels + are enabled */ + hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER/2; + + /* 0:2.4MHz 1:3.84MHz */ + hw->DMIC_CTRL__DMIC_CLK_DIV = 0; + + /* 0:MSB aligned 1:LSB aligned */ + hw->DMIC_CTRL__DMICOUTFORMAT = 0; hw->DMIC_CTRL__DMIC_UP3_EN = 1; hw->DMIC_CTRL__DMIC_UP2_EN = 1; hw->DMIC_CTRL__DMIC_UP1_EN = 1; - hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER/6; /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ - /* MCBSP SPECIFICATION + /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ + hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER/6; + + /* MCBSP SPECIFICATION RJUST = 00 Right justify data and zero fill MSBs in DRR[1,2] - RJUST = 01 Right justify data and sign extend it into the MSBs in DRR[1,2] + RJUST = 01 Right justify data and sign extend it into the MSBs + in DRR[1,2] RJUST = 10 Left justify data and zero fill LSBs in DRR[1,2] MCBSPLP_RJUST_MODE_RIGHT_ZERO = 0x0, MCBSPLP_RJUST_MODE_RIGHT_SIGN = 0x1, - MCBSPLP_RJUST_MODE_LEFT_ZERO = 0x2, + MCBSPLP_RJUST_MODE_LEFT_ZERO = 0x2, MCBSPLP_RJUST_MODE_MAX = MCBSPLP_RJUST_MODE_LEFT_ZERO */ hw->MCBSP_SPCR1_REG__RJUST = 2; - hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1; /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ - hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1; /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ - hw->SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD = 1; /* Slimbus IP FIFO thresholds */ + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1; + + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1; + + /* Slimbus IP FIFO thresholds */ + hw->SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD = 1; - hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE = EVENT_GENERATOR_COUNTER_DEFAULT; /* 2050 gives about 96kHz */ - hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1; /* 0: DMAreq, 1:Counter */ - hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION = ABE_ATC_MCPDMDL_DMA_REQ; /* 5bits DMAreq selection */ + /* 2050 gives about 96kHz */ + hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE = + EVENT_GENERATOR_COUNTER_DEFAULT; - hw->HAL_EVENT_SELECTION = EVENT_TIMER; /* THE famous EVENT timer ! */ - _lock_exit + /* 0: DMAreq, 1:Counter */ + hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1; + /* 5bits DMAreq selection */ + hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION = + ABE_ATC_MCPDMDL_DMA_REQ; + + /* THE famous EVENT timer ! */ + hw->HAL_EVENT_SELECTION = EVENT_TIMER; + return 0; } +EXPORT_SYMBOL(abe_read_hardware_configuration); -/* - * ABE_IRQ_PROCESSING - * - * Parameter : - * No parameter - * - * Operations : - * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" ABE interrupt - * This subroutine will check the IRQ_FIFO from the AE and act accordingly. - * Some IRQ source are originated for the delivery of "end of time sequenced tasks" - * notifications, some are originated from the Ping-Pong protocols, some are generated from - * the embedded debugger when the firmware stops on programmable break-points, etc … - * - * Return value : - * None. +/** + * abe_irq_processing - Process ABE interrupt + * + * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio + * back-end interrupt. This subroutine will check the ATC Hrdware, the + * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated + * for the delivery of "end of time sequenced tasks" notifications, some are + * originated from the Ping-Pong protocols, some are generated from + * the embedded debugger when the firmware stops on programmable break-points, + * etc … */ -void abe_irq_processing(void) +abehal_status abe_irq_processing (void) { - abe_uint32 clear_abe_irq; - abe_uint32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm = 0; + u32 clear_abe_irq; + u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm; abe_irq_data_t IRQ_data; - _lock_enter - _log(id_irq_processing,0,0,0) +#define IrqFiFoMask ((D_McuIrqFifo_sizeof >> 2) -1) -#define IrqFiFoMask ((D_McuIrqFifo_sizeof >> 2) - 1) + _log(id_irq_processing,0,0,0) /* extract the write pointer index from CMEM memory (INITPTR format) */ /* CMEM address of the write pointer in bytes */ cmem_src = MCU_IRQ_FIFO_ptr_labelID * 4; abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_CMEM, cmem_src, - (abe_uint32*)&abe_irq_dbg_write_ptr, - sizeof (abe_irq_dbg_write_ptr)); - abe_irq_dbg_write_ptr = sm_cm >> 16; /* AESS left-pointer index located on MSBs */ + &sm_cm, sizeof (abe_irq_dbg_write_ptr)); + + /* AESS left-pointer index located on MSBs */ + abe_irq_dbg_write_ptr = sm_cm >> 16; abe_irq_dbg_write_ptr &= 0xFF; /* loop on the IRQ FIFO content */ @@ -225,14 +291,16 @@ void abe_irq_processing(void) break; /* read the IRQ/DBG FIFO */ abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, - D_McuIrqFifo_ADDR + (i << 2), (abe_uint32 *)&IRQ_data, - sizeof (IRQ_data)); - abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) & IrqFiFoMask; + (D_McuIrqFifo_ADDR + (i << 2)), + (u32 *)&IRQ_data, + sizeof (IRQ_data)); + abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) & + IrqFiFoMask; /* select the source of the interrupt */ switch (IRQ_data.tag) { case IRQtag_APS: - _log(id_irq_processing,(abe_uint32)(IRQ_data.data),0,1) + _log(id_irq_processing,IRQ_data.data,0,1) abe_irq_aps (IRQ_data.data); break; case IRQtag_PP: @@ -240,75 +308,64 @@ void abe_irq_processing(void) abe_irq_ping_pong (); break; case IRQtag_COUNT: - _log(id_irq_processing,(abe_uint32)(IRQ_data.data),0,3) + _log(id_irq_processing,IRQ_data.data,0,3) abe_irq_check_for_sequences (IRQ_data.data); break; default: - break; + break; } } - abe_monitoring(); + abe_monitoring (); clear_abe_irq = 1; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS, - &clear_abe_irq, 4); - _lock_exit + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS, + &clear_abe_irq, 4); + return 0; } +EXPORT_SYMBOL(abe_irq_processing); -/* - * ABE_SELECT_MAIN_PORT - * - * Parameter : - * id : audio port name - * - * Operations : - * tells the FW which is the reference stream for adjusting - * the processing on 23/24/25 slots +/** + * abe_select_main_port - Select stynchronization port for Event generator. + * @id: audio port name * - * Return value: - * None. + * tells the FW which is the reference stream for adjusting + * the processing on 23/24/25 slots */ -void abe_select_main_port (abe_port_id id) +abehal_status abe_select_main_port (u32 id) { - abe_uint32 selection; + u32 selection; - _lock_enter _log(id_select_main_port,id,0,0) /* flow control */ - selection = D_IOdescr_ADDR + id*sizeof(ABE_SIODescriptor) + flow_counter_; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR, &selection, 4); - - _lock_exit + selection = D_IOdescr_ADDR + id*sizeof(ABE_SIODescriptor) + + flow_counter_; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR, + &selection, 4); + return 0; } +EXPORT_SYMBOL(abe_select_main_port); -/* - * ABE_WRITE_EVENT_GENERATOR - * - * Parameter : - * e: Event Generation Counter, McPDM, DMIC or default. - * - * Operations : - * load the AESS event generator hardware source. Loads the firmware parameters - * accordingly. Indicates to the FW which data stream is the most important to preserve - * in case all the streams are asynchronous. If the parameter is "default", let the HAL - * decide which Event source is the best appropriate based on the opened ports. - * - * When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed - * with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher - * than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz - * The ratio is (MCLK/96000)+(1<<1) = 2050 - * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%) - * - * Return value : - * None. +/** + * abe_write_event_generator - Select event generator source + * @e: Event Generation Counter, McPDM, DMIC or default. + * + * load the AESS event generator hardware source. Loads the firmware parameters + * accordingly. Indicates to the FW which data stream is the most important to preserve + * in case all the streams are asynchronous. If the parameter is "default", let the HAL + * decide which Event source is the best appropriate based on the opened ports. + * + * When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed + * with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher + * than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz + * The ratio is (MCLK/96000)+(1<<1) = 2050 + * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%) */ -void abe_write_event_generator(abe_event_id e) +abehal_status abe_write_event_generator (u32 e) { - abe_uint32 event, selection, counter, start; + u32 event, selection, counter, start; - _lock_enter _log(id_write_event_generator,e,0,0) counter = EVENT_GENERATOR_COUNTER_DEFAULT; @@ -316,87 +373,56 @@ void abe_write_event_generator(abe_event_id e) abe_current_event_id = e; switch (e) { - case EVENT_MCPDM: - selection = EVENT_SOURCE_DMA; - event = ABE_ATC_MCPDMDL_DMA_REQ; - break; - case EVENT_DMIC: - selection = EVENT_SOURCE_DMA; - event = ABE_ATC_DMIC_DMA_REQ; - break; - case EVENT_TIMER: - selection = EVENT_SOURCE_COUNTER; - event = 0; - break; - case EVENT_McBSP: - selection = EVENT_SOURCE_COUNTER; - event = 0; - break; - case EVENT_McASP: - selection = EVENT_SOURCE_COUNTER; - event = 0; - break; - case EVENT_SLIMBUS: + case EVENT_TIMER : selection = EVENT_SOURCE_COUNTER; event = 0; break; - case EVENT_44100: + case EVENT_44100 : selection = EVENT_SOURCE_COUNTER; event = 0; counter = EVENT_GENERATOR_COUNTER_44100; break; - case EVENT_DEFAULT: - selection = EVENT_SOURCE_COUNTER; - event = 0; - break; - default: + default : abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_BLOCK_COPY_ERR); + abe_dbg_error_log (ABE_BLOCK_COPY_ERR); } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_GENERATOR_COUNTER, &counter, 4); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_SOURCE_SELECTION, &selection, 4); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, EVENT_GENERATOR_START, &start, 4); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, AUDIO_ENGINE_SCHEDULER, &event, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_COUNTER, &counter, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_SOURCE_SELECTION, &selection, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, + EVENT_GENERATOR_START, &start, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, + AUDIO_ENGINE_SCHEDULER, &event, 4); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_write_event_generator); /** -* abe_read_use_case_opp() description for void abe_read_use_case_opp(). -* -* Operations : returns the expected min OPP for a given use_case list -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o) + * abe_read_use_case_opp() - description for void abe_read_use_case_opp(). + * + * returns the expected min OPP for a given use_case list + */ +abehal_status abe_read_use_case_opp (u32 *u, u32 *o) { - abe_uint32 opp, i; - abe_use_case_id *ptr = u; + u32 opp, i; + u32 *ptr = u; +#define MAX_READ_USE_CASE_OPP 10 +#define OPP_25 1 +#define OPP_50 2 +#define OPP_100 4 - #define MAX_READ_USE_CASE_OPP 10 /* there is no reason to have more use_cases */ - #define OPP_25 1 - #define OPP_50 2 - #define OPP_100 4 - _lock_enter - _log(id_read_use_case_opp,(abe_uint32)(u),(abe_uint32)u>>8,(abe_uint32)u>>16) + _log(id_read_use_case_opp,(u32)u,(u32)u>>8,(u32)u>>16) opp = i = 0; do { /* check for pointer errors */ if (i > MAX_READ_USE_CASE_OPP) { abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_READ_USE_CASE_OPP_ERR); + abe_dbg_error_log (ABE_READ_USE_CASE_OPP_ERR); break; } @@ -406,37 +432,36 @@ void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o) /* OPP selection based on current firmware implementation */ switch (*ptr) { - case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE: + case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE : opp |= OPP_25; break; - case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER: + case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER : opp |= OPP_100; break; - case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL: + case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL : opp |= OPP_100; break; - case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT: + case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT : opp |= OPP_50; break; - case ABE_MULTIMEDIA_AUDIO_RECORDER: + case ABE_MULTIMEDIA_AUDIO_RECORDER : opp |= OPP_50; break; - case ABE_VIBRATOR_OR_HAPTICS: + case ABE_VIBRATOR_OR_HAPTICS : opp |= OPP_100; break; - case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER: + case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER : opp |= OPP_100; break; - case ABE_RINGER_TONES: + case ABE_RINGER_TONES : opp |= OPP_100; break; - case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER: + case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER : opp |= OPP_100; break; default: break; } - i++; ptr++; } while (*ptr != 0); @@ -448,37 +473,35 @@ void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o) else *o = ABE_OPP25; - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_read_use_case_opp); - - -/* - * ABE_SET_OPP_PROCESSING +/** + * abe_set_opp_processing - Set OPP mode for ABE Firmware + * @opp: OOPP mode * - * Parameter : - * New processing network and OPP: - * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer) - * 1: OPP 25% (simple multimedia features, including low-power player) - * 2: OPP 50% (multimedia and voice calls) - * 3: OPP100% (EANC, multimedia complex use-cases) + * New processing network and OPP: + * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer) + * 1: OPP 25% (simple multimedia features, including low-power player) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% ( multimedia complex use-cases) * - * Operations : - * Rearranges the FW task network to the corresponding OPP list of features. - * The corresponding AE ports are supposed to be set/reset accordingly before this switch. + * Rearranges the FW task network to the corresponding OPP list of features. + * The corresponding AE ports are supposed to be set/reset accordingly before + * this switch. * - * Return value : - * error code when the new OPP do not corresponds the list of activated features */ -void abe_set_opp_processing(abe_opp_t opp) +abehal_status abe_set_opp_processing (u32 opp) { - abe_uint32 dOppMode32, sio_desc_address; + u32 dOppMode32, sio_desc_address, sio_desc_address_pp; ABE_SIODescriptor desc; + ABE_SPingPongDescriptor desc_pp; - _lock_enter + _lock_enter; _log(id_set_opp_processing,opp,0,0) - switch(opp){ + switch (opp) { case ABE_OPP25: /* OPP25% */ dOppMode32 = DOPPMODE32_OPP25; @@ -489,728 +512,687 @@ void abe_set_opp_processing(abe_opp_t opp) break; default: abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_BLOCK_COPY_ERR); - case ABE_OPP100: + abe_dbg_error_log (ABE_BLOCK_COPY_ERR); + case ABE_OPP100: /* OPP100% */ dOppMode32 = DOPPMODE32_OPP100; break; } /* Write Multiframe inside DMEM */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(abe_uint32)); - - sio_desc_address = dmem_port_descriptors + (MM_DL_PORT * sizeof(ABE_SIODescriptor)); - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc, sizeof (desc)); - if (dOppMode32 == DOPPMODE32_OPP100) - desc.smem_addr1 = smem_mm_dl_opp100; /* ASRC input buffer, size 40 */ - else - desc.smem_addr1 = smem_mm_dl_opp25; /* at OPP 25/50 or without ASRC */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc, sizeof (desc)); - - _lock_exit - + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof (u32)); + + sio_desc_address = dmem_port_descriptors + (MM_DL_PORT * + sizeof(ABE_SIODescriptor)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, + (u32*)&desc, sizeof (desc)); + + sio_desc_address_pp = D_PingPongDesc_ADDR; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address_pp, + (u32*)&desc_pp, sizeof (desc_pp)); + + if (dOppMode32 == DOPPMODE32_OPP100) { + /* ASRC input buffer, size 40 */ + desc.smem_addr1 = smem_mm_dl_opp100; + desc_pp.smem_addr = smem_mm_dl_opp100; + } else { + /* at OPP 25/50 or without ASRC */ + desc.smem_addr1 = smem_mm_dl_opp25; + desc_pp.smem_addr = smem_mm_dl_opp25; + } + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32*)&desc, sizeof (desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address_pp, + (u32*)&desc_pp, sizeof (desc_pp)); + return 0; } -/* - * ABE_SET_PING_PONG_BUFFER - * - * Parameter : - * Port_ID : - * New data +EXPORT_SYMBOL(abe_set_opp_processing); + +/** + * abe_set_ping_pong_buffer + * @port: ABE port ID + * @n_bytes: Size of Ping/Pong buffer * - * Operations : - * Updates the next ping-pong buffer with "size" bytes copied from the - * host processor. This API notifies the FW that the data transfer is done. + * Updates the next ping-pong buffer with "size" bytes copied from the + * host processor. This API notifies the FW that the data transfer is done. */ -void abe_set_ping_pong_buffer(abe_port_id port, abe_uint32 n_bytes) +abehal_status abe_set_ping_pong_buffer (u32 port, u32 n_bytes) { - abe_uint32 sio_pp_desc_address, struct_offset, *src, n_samples, datasize, base_and_size; + u32 sio_pp_desc_address, struct_offset, n_samples, datasize, + base_and_size, *src; ABE_SPingPongDescriptor desc_pp; - _lock_enter + _log(id_set_ping_pong_buffer,port,n_bytes,n_bytes>>8) /* ping_pong is only supported on MM_DL */ if (port != MM_DL_PORT) { - abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_PARAMETER_ERROR); + abe_dbg_param |= ERR_API; + abe_dbg_error_log (ABE_PARAMETER_ERROR); } /* translates the number of bytes in samples */ /* data size in DMEM words */ datasize = abe_dma_port_iter_factor(&((abe_port[port]).format)); + /* data size in bytes */ datasize = datasize << 2; n_samples = n_bytes / datasize; abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_PingPongDesc_ADDR, - (abe_uint32 *)&desc_pp, sizeof(desc_pp)); + (u32 *)&desc_pp, sizeof(desc_pp)); /* * read the port SIO descriptor and extract the current pointer - * address after reading the counter + * address after reading the counter */ if ((desc_pp.counter & 0x1) == 0) { - struct_offset = (abe_uint32)&(desc_pp.nextbuff0_BaseAddr) - - (abe_uint32)&(desc_pp); + struct_offset = (u32)&(desc_pp.nextbuff0_BaseAddr) - + (u32)&(desc_pp); base_and_size = desc_pp.nextbuff0_BaseAddr; } else { - struct_offset = (abe_uint32)&(desc_pp.nextbuff1_BaseAddr) - - (abe_uint32)&(desc_pp); + struct_offset = (u32)&(desc_pp.nextbuff1_BaseAddr) - + (u32)&(desc_pp); base_and_size = desc_pp.nextbuff1_BaseAddr; } - base_and_size = (base_and_size & 0xFFFFL) + ((abe_uint32)n_samples << 16); + base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16); sio_pp_desc_address = D_PingPongDesc_ADDR + struct_offset; src = &base_and_size; abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_pp_desc_address, - (abe_uint32 *)&base_and_size, sizeof(abe_uint32)); + (u32 *)&base_and_size, sizeof(u32)); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_set_ping_pong_buffer); -/* - * ABE_READ_NEXT_PING_PONG_BUFFER - * - * Parameter : - * Port_ID : - * Returned address to the next buffer (byte offset from DMEM start) - * - * Operations : - * Tell the next base address of the next ping_pong Buffer and its size - * +/** + * abe_read_next_ping_pong_buffer + * @port: ABE portID + * @p: Next buffer address (pointer) + * @n: Next buffer size (pointer) * + * Tell the next base address of the next ping_pong Buffer and its size */ -void abe_read_next_ping_pong_buffer(abe_port_id port, abe_uint32 *p, abe_uint32 *n) +abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n) { - abe_uint32 sio_pp_desc_address; + u32 sio_pp_desc_address; ABE_SPingPongDescriptor desc_pp; - _lock_enter + _log(id_read_next_ping_pong_buffer,port,0,0) /* ping_pong is only supported on MM_DL */ if (port != MM_DL_PORT) { abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_PARAMETER_ERROR); + abe_dbg_error_log (ABE_PARAMETER_ERROR); } - /* read the port SIO descriptor and extract the current pointer address after reading the counter */ + /* read the port SIO descriptor and extract the current pointer + address after reading the counter */ sio_pp_desc_address = D_PingPongDesc_ADDR; - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, (abe_uint32*)&desc_pp, sizeof(ABE_SPingPongDescriptor)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, + (u32*)&desc_pp, sizeof(ABE_SPingPongDescriptor)); if ((desc_pp.counter & 0x1) == 0) { - (*p) = desc_pp.nextbuff0_BaseAddr; + _log(id_read_next_ping_pong_buffer,port,0,0) + *p = desc_pp.nextbuff0_BaseAddr; } else { - (*p) = desc_pp.nextbuff1_BaseAddr; + _log(id_read_next_ping_pong_buffer,port,1,0) + *p = desc_pp.nextbuff1_BaseAddr; } /* translates the number of samples in bytes */ - (*n) = abe_size_pingpong; + *n = abe_size_pingpong; - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_read_next_ping_pong_buffer); -/* - * ABE_INIT_PING_PONG_BUFFER - * - * Parameter : - * size of the ping pong - * number of buffers (2 = ping/pong) - * returned address of the ping-pong list of base address (byte offset from DMEM start) - * - * Operations : - * Computes the base address of the ping_pong buffers - * +/** + * abe_init_ping_pong_buffer + * @id: ABE port ID + * @size_bytes:size of the ping pong + * @n_buffers:number of buffers (2 = ping/pong) + * @p:returned address of the ping-pong list of base address (byte offset + from DMEM start) + * + * Computes the base address of the ping_pong buffers */ -void abe_init_ping_pong_buffer(abe_port_id id, abe_uint32 size_bytes, abe_uint32 n_buffers, abe_uint32 *p) +abehal_status abe_init_ping_pong_buffer (u32 id, u32 size_bytes, u32 n_buffers, u32 *p) { - abe_uint32 i, dmem_addr; + u32 i, dmem_addr; - _lock_enter _log(id_init_ping_pong_buffer,id,size_bytes,n_buffers) - /* ping_pong is supported in 2 buffers configuration right now but FW is ready for ping/pong/pung/pang... */ + /* ping_pong is supported in 2 buffers configuration right now but FW + is ready for ping/pong/pung/pang... */ if (id != MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) { abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_PARAMETER_ERROR); + abe_dbg_error_log (ABE_PARAMETER_ERROR); } for (i = 0; i < n_buffers; i++) { dmem_addr = dmem_ping_pong_buffer + (i * size_bytes); - abe_base_address_pingpong [i] = dmem_addr; /* base addresses of the ping pong buffers in U8 unit */ + + /* base addresses of the ping pong buffers in U8 unit */ + abe_base_address_pingpong [i] = dmem_addr; } - abe_size_pingpong = size_bytes; /* global data */ - *p = (abe_uint32)dmem_ping_pong_buffer; - _lock_exit + /* global data */ + abe_size_pingpong = size_bytes; + *p = (u32)dmem_ping_pong_buffer; + + return 0; } +EXPORT_SYMBOL(abe_init_ping_pong_buffer); -/* - * ABE_PLUG_SUBROUTINE - * - * Parameter : - * id: returned sequence index after plugging a new subroutine - * f : subroutine address to be inserted - * n : number of parameters of this subroutine - * - * Returned value : error code - * - * Operations : register a list of subroutines for call-back purpose +/** + * abe_plug_subroutine + * @id: returned sequence index after plugging a new subroutine + * @f: subroutine address to be inserted + * @n: number of parameters of this subroutine + * @params: pointer on parameters * + * register a list of subroutines for call-back purpose */ -void abe_plug_subroutine(abe_uint32 *id, abe_subroutine2 f, abe_uint32 n, abe_uint32* params) +abehal_status abe_plug_subroutine (u32 *id, abe_subroutine2 f, u32 n, u32* params) { - _lock_enter - _log(id_plug_subroutine,(abe_uint32)(*id),(abe_uint32)f,n) - abe_add_subroutine((abe_uint32 *)id, (abe_subroutine2)f, - (abe_uint32)n, (abe_uint32*)params); - _lock_exit + _log(id_plug_subroutine,(u32)(*id),(u32)f,n) + abe_add_subroutine(id, (abe_subroutine2)f, n, (u32*)params); + return 0; } +EXPORT_SYMBOL(abe_plug_subroutine); -/* - * ABE_SET_SEQUENCE_TIME_ACCURACY - * - * Parameter : - * patch bit field used to guarantee the code compatibility without conditionnal compilation - * Sequence index - * - * Operations : two counters are implemented in the firmware: - * - one "fast" counter, generating an IRQ to the HAL for sequences scheduling, the rate is in the range 1ms .. 100ms - * - one "slow" counter, generating an IRQ to the HAL for the management of ASRC drift, the rate is in the range 1s .. 100s +/** + * abe_set_sequence_time_accuracy + * @fast: fast counter + * @slow: slow counter * - * Return value : - * None. */ -void abe_set_sequence_time_accuracy(abe_micros_t fast, abe_micros_t slow) +abehal_status abe_set_sequence_time_accuracy (u32 fast, u32 slow) { - abe_uint32 data; + u32 data; - _lock_enter _log(id_set_sequence_time_accuracy,fast,slow,0) - data = minimum(MAX_UINT16, (abe_uint32) fast / FW_SCHED_LOOP_FREQ_DIV1000); + data = minimum(MAX_UINT16, fast / FW_SCHED_LOOP_FREQ_DIV1000); abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_fastCounter_ADDR, - (abe_uint32 *)&data, sizeof (data)); + &data, sizeof (data)); - data = minimum(MAX_UINT16, (abe_uint32) slow / FW_SCHED_LOOP_FREQ_DIV1000); + data = minimum(MAX_UINT16, slow / FW_SCHED_LOOP_FREQ_DIV1000); abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_slowCounter_ADDR, - (abe_uint32 *)&data, sizeof (data)); + &data, sizeof (data)); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_set_sequence_time_accuracy); -/* - * ABE_RESET_PORT - * - * Parameters : - * id: port name - * - * Returned value : error code - * - * Operations : stop the port activity and reload default parameters on the associated processing features. - * Clears the internal AE buffers. +/** + * abe_reset_port + * @id: ABE port ID * + * stop the port activity and reload default parameters on the associated + * processing features. + * Clears the internal AE buffers. */ -void abe_reset_port(abe_port_id id) +abehal_status abe_reset_port (u32 id) { - _lock_enter + _log(id_reset_port,id,0,0) - abe_port[id] = ((abe_port_t *) abe_port_init) [id]; - _lock_exit + abe_port [id] = ((abe_port_t *)abe_port_init) [id]; + return 0; } +EXPORT_SYMBOL(abe_reset_port); -/* - * ABE_READ_REMAINING_DATA - * - * Parameter : - * Port_ID : - * size : pointer to the remaining number of 32bits words - * - * Operations : - * computes the remaining amount of data in the buffer. +/** + * abe_read_remaining_data + * @id: ABE port_ID + * @n: size pointer to the remaining number of 32bits words * - * Return value : - * error code + * computes the remaining amount of data in the buffer. */ -void abe_read_remaining_data(abe_port_id port, abe_uint32 *n) +abehal_status abe_read_remaining_data (u32 port, u32 *n) { - abe_uint32 sio_pp_desc_address; + u32 sio_pp_desc_address; ABE_SPingPongDescriptor desc_pp; - _lock_enter + _log(id_read_remaining_data,port,0,0) /* * read the port SIO descriptor and extract the - * current pointer address after reading the counter + * current pointer address after reading the counter */ sio_pp_desc_address = D_PingPongDesc_ADDR; abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address, - (abe_uint32*)&desc_pp, sizeof(ABE_SPingPongDescriptor)); - (*n) = desc_pp.workbuff_Samples; - - _lock_exit + (u32*)&desc_pp, sizeof(ABE_SPingPongDescriptor)); + *n = desc_pp.workbuff_Samples; + + return 0; } +EXPORT_SYMBOL(abe_read_remaining_data); -/* - * ABE_DISABLE_DATA_TRANSFER - * - * Parameter : - * p: port indentifier - * - * Operations : - * disables the ATC descriptor and stop IO/port activities - * disable the IO task (@f = 0) - * clear ATC DMEM buffer, ATC enabled +/** + * abe_disable_data_transfer + * @id: ABE port id * - * Return value : - * None. + * disables the ATC descriptor and stop IO/port activities + * disable the IO task (@f = 0) + * clear ATC DMEM buffer, ATC enabled */ -void abe_disable_data_transfer(abe_port_id id) +abehal_status abe_disable_data_transfer (u32 id) { - _lock_enter _log(id_disable_data_transfer,id,0,0) /* local host variable status= "port is running" */ - abe_port[id].status = IDLE_P; + abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE; + /* disable DMA requests */ abe_disable_dma_request(id); + /* disable ATC transfers */ abe_init_atc(id); - abe_clean_temporary_buffers(id); - - _lock_exit + abe_clean_temporary_buffers (id); + return 0; } +EXPORT_SYMBOL(abe_disable_data_transfer); -/* - * ABE_ENABLE_DATA_TRANSFER - * - * Parameter : - * p: port indentifier - * - * Operations : - * enables the ATC descriptor - * reset ATC pointers - * enable the IO task (@f <> 0) +/** + * abe_enable_data_transfer + * @ip: ABE port id * - * Return value : - * None. + * enables the ATC descriptor + * reset ATC pointers + * enable the IO task (@f <> 0) */ -void abe_enable_data_transfer(abe_port_id id) +abehal_status abe_enable_data_transfer (u32 id) { abe_port_protocol_t *protocol; abe_data_format_t format; - _lock_enter _log(id_enable_data_transfer,id,0,0) - abe_clean_temporary_buffers(id); + /* check firmware status bit for this */ + /*if (abe_port[id].status == OMAP_ABE_PORT_ACTIVITY_RUNNING) + return 0;*/ + + abe_clean_temporary_buffers (id); if (id == PDM_UL_PORT) { /* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */ protocol = &(abe_port[PDM_UL_PORT].protocol); format = abe_port[PDM_UL_PORT].format; - abe_init_atc(PDM_UL_PORT); - abe_init_io_tasks(PDM_UL_PORT, &format, protocol); + abe_init_atc (PDM_UL_PORT); + abe_init_io_tasks (PDM_UL_PORT, &format, protocol); } if (id == PDM_DL_PORT) { /* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */ protocol = &(abe_port[PDM_DL_PORT].protocol); format = abe_port[PDM_DL_PORT].format; - abe_init_atc(PDM_DL_PORT); - abe_init_io_tasks(PDM_DL_PORT, &format, protocol); + abe_init_atc (PDM_DL_PORT); + abe_init_io_tasks (PDM_DL_PORT, &format, protocol); } if (id == DMIC_PORT) { /* one DMIC port enabled = all DMICs enabled, * since there is a single DMIC path for all DMICs */ protocol = &(abe_port[DMIC_PORT].protocol); format = abe_port[DMIC_PORT].format; - abe_init_atc(DMIC_PORT); - abe_init_io_tasks(DMIC_PORT, &format, protocol); + abe_init_atc (DMIC_PORT); + abe_init_io_tasks (DMIC_PORT, &format, protocol); + } + if (id == VX_UL_PORT) { + /* Init VX_UL ASRC and enable its adaptation */ + abe_init_asrc_vx_ul (250); + } + if (id == VX_DL_PORT) { + /* Init VX_DL ASRC and enable its adaptation */ + abe_init_asrc_vx_dl (250); } /* local host variable status= "port is running" */ - abe_port[id].status = RUN_P; + abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; /* enable DMA requests */ abe_enable_dma_request(id); - _lock_exit + + return 0; } +EXPORT_SYMBOL(abe_enable_data_transfer); -/* - * ABE_SET_DMIC_FILTER - * - * Parameter : - * DMIC decimation ratio : 16/25/32/40 - * - * Operations : - * Loads in CMEM a specific list of coefficients depending on the DMIC sampling - * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator roll-off at 20kHz. - * The default table is loaded with the DMIC 2.4MHz recommended configuration. +/** + * abe_set_dmic_filter + * @d: DMIC decimation ratio : 16/25/32/40 * - * Return value : - * None. + * Loads in CMEM a specific list of coefficients depending on the DMIC sampling + * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator + * roll-off at 20kHz. + * The default table is loaded with the DMIC 2.4MHz recommended configuration. */ -void abe_set_dmic_filter(abe_dmic_ratio_t d) +abehal_status abe_set_dmic_filter (u32 d) { - abe_int32 *src; + s32 *src; + - _lock_enter _log(id_set_dmic_filter,d,0,0) - switch(d) { - case ABE_DEC16: - src = (abe_int32 *)abe_dmic_16; + switch (d) { + case ABE_DEC16 : + src = (s32 *)abe_dmic_16; break; - case ABE_DEC25: - src = (abe_int32 *) abe_dmic_25; + case ABE_DEC25 : + src = (s32 *)abe_dmic_25; break; - case ABE_DEC32: - src = (abe_int32 *) abe_dmic_32; + case ABE_DEC32 : + src = (s32 *)abe_dmic_32; break; default: - case ABE_DEC40: - src = (abe_int32 *) abe_dmic_40; + case ABE_DEC40 : + src = (s32 *)abe_dmic_40; break; } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, - C_98_48_LP_Coefs_ADDR, - (abe_uint32 *)src, C_98_48_LP_Coefs_sizeof << 2); - _lock_exit + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, + C_98_48_LP_Coefs_ADDR, + (u32 *)src, C_98_48_LP_Coefs_sizeof << 2); + + return 0; } +EXPORT_SYMBOL(abe_set_dmic_filter); /** -* @fn abe_connect_cbpr_dmareq_port() -* -* Operations : enables the data echange between a DMA and the ABE through the -* CBPr registers of AESS. -* -* Parameters : -* id: port name -* f : desired data format -* d : desired dma_request line (0..7) -* a : returned pointer to the base address of the CBPr register and number of -* samples to exchange during a DMA_request. -* -* @see ABE_API.h -*/ -void abe_connect_cbpr_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *returned_dma_t) + * abe_connect_cbpr_dmareq_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @a: returned pointer to the base address of the CBPr register and number of + * samples to exchange during a DMA_request. + * + * enables the data echange between a DMA and the ABE through the + * CBPr registers of AESS. + */ + +abehal_status abe_connect_cbpr_dmareq_port (u32 id, abe_data_format_t *f, u32 d, + abe_dma_t *returned_dma_t) { - _lock_enter - _log(id_connect_cbpr_dmareq_port,id,f->f,f->samp_format) - abe_port[id] = ((abe_port_t *)abe_port_init)[id]; + _log(id_connect_cbpr_dmareq_port,id,f->f,f->samp_format) - abe_port[id].format = *f; + abe_port [id] = ((abe_port_t *) abe_port_init) [id]; + (abe_port [id]).format = (*f); abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT; abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f); abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW; abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d); - abe_port[id].status = RUN_P; + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; /* load the micro-task parameters */ - abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol)); + abe_init_io_tasks (id, &((abe_port [id]).format), + &((abe_port [id]).protocol)); /* load the dma_t with physical information from AE memory mapping */ - abe_init_dma_t(id, &((abe_port [id]).protocol)); + abe_init_dma_t (id, &((abe_port [id]).protocol)); /* load the ATC descriptors - disabled */ - abe_init_atc(id); + abe_init_atc (id); /* return the dma pointer address */ - abe_read_port_address(id, returned_dma_t); + abe_read_port_address (id, returned_dma_t); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_connect_cbpr_dmareq_port); /** -* @fn abe_connect_dmareq_ping_pong_port() -* -* Operations : enables the data echanges between a DMA and a direct access to -* the DMEM memory of ABE. On each dma_request activation the DMA will exchange -* "s" bytes and switch to the "pong" buffer for a new buffer exchange. -* -* Parameters : -* id: port name -* f : desired data format -* d : desired dma_request line (0..7) -* s : half-buffer (ping) size -* -* a : returned pointer to the base address of the ping-pong buffer and number of samples to exchange during a DMA_request. -* -* @see ABE_API.h -*/ -void abe_connect_dmareq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_uint32 s, abe_dma_t *returned_dma_t) + * abe_connect_dmareq_ping_pong_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @s: half-buffer (ping) size + * @a: returned pointer to the base address of the ping-pong buffer and number + * of samples to exchange during a DMA_request. + * + * enables the data echanges between a DMA and a direct access to + * the DMEM memory of ABE. On each dma_request activation the DMA will exchange + * "s" bytes and switch to the "pong" buffer for a new buffer exchange. + */ +abehal_status abe_connect_dmareq_ping_pong_port (u32 id, abe_data_format_t *f, + u32 d, u32 s, abe_dma_t *returned_dma_t) { abe_dma_t dma1; - _lock_enter + _log(id_connect_dmareq_ping_pong_port,id,f->f,f->samp_format) /* ping_pong is only supported on MM_DL */ - if (id != MM_DL_PORT) - { - abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_PARAMETER_ERROR); + if (id != MM_DL_PORT) { + abe_dbg_param |= ERR_API; + abe_dbg_error_log (ABE_PARAMETER_ERROR); } /* declare PP buffer and prepare the returned dma_t */ - abe_init_ping_pong_buffer(MM_DL_PORT, s, 2, (abe_uint32 *)&(returned_dma_t->data)); + abe_init_ping_pong_buffer (MM_DL_PORT, s, 2, + (u32 *)&(returned_dma_t->data)); + - abe_port[id] = ((abe_port_t *) abe_port_init) [id]; + abe_port [id] = ((abe_port_t *) abe_port_init) [id]; - (abe_port[id]).format = (*f); - (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT; - (abe_port[id]).protocol.p.prot_pingpong.buf_addr = dmem_ping_pong_buffer; - (abe_port[id]).protocol.p.prot_pingpong.buf_size = s; - (abe_port[id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW; - (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1 << d); + (abe_port [id]).format = (*f); + (abe_port [id]).protocol.protocol_switch = PINGPONG_PORT_PROT; + (abe_port [id]).protocol.p.prot_pingpong.buf_addr = + dmem_ping_pong_buffer; + (abe_port [id]).protocol.p.prot_pingpong.buf_size = s; + (abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW; + (abe_port [id]).protocol.p.prot_pingpong.irq_data = (1 << d); - abe_port [id].status = RUN_P; + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; /* load the micro-task parameters DESC_IO_PP */ - abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol)); + abe_init_io_tasks (id, &((abe_port [id]).format), + &((abe_port [id]).protocol)); /* load the dma_t with physical information from AE memory mapping */ - abe_init_dma_t(id, &((abe_port [id]).protocol)); + abe_init_dma_t (id, &((abe_port [id]).protocol)); - dma1.data = (abe_uint32 *)(abe_port [id].dma.data + ABE_DMEM_BASE_ADDRESS_L3); + dma1.data = (u32 *)(abe_port [id].dma.data + ABE_DMEM_BASE_ADDRESS_L3); dma1.iter = abe_port [id].dma.iter; - (*returned_dma_t) = dma1; + *returned_dma_t = dma1; - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_connect_dmareq_ping_pong_port); /** -* @fn abe_connect_irq_ping_pong_port() -* -* Operations : enables the data echanges between a direct access to the DMEM -* memory of ABE using cache flush. On each IRQ activation a subroutine -* registered with "abe_plug_subroutine" will be called. This subroutine -* will generate an amount of samples, send them to DMEM memory and call -* "abe_set_ping_pong_buffer" to notify the new amount of samples in the -* pong buffer. -* -* Parameters : -* id: port name -* f : desired data format -* I : index of the call-back subroutine to call -* s : half-buffer (ping) size -* -* p: returned base address of the first (ping) buffer) -* -* @see ABE_API.h -*/ -void abe_connect_irq_ping_pong_port(abe_port_id id, abe_data_format_t *f, - abe_uint32 subroutine_id, abe_uint32 size, - abe_uint32 *sink, abe_uint32 dsp_mcu_flag) + * abe_connect_irq_ping_pong_port + * @id: port name + * @f: desired data format + * @I: index of the call-back subroutine to call + * @s: half-buffer (ping) size + * @p: returned base address of the first (ping) buffer) + * + * enables the data echanges between a direct access to the DMEM + * memory of ABE using cache flush. On each IRQ activation a subroutine + * registered with "abe_plug_subroutine" will be called. This subroutine + * will generate an amount of samples, send them to DMEM memory and call + * "abe_set_ping_pong_buffer" to notify the new amount of samples in the + * pong buffer. + */ +abehal_status abe_connect_irq_ping_pong_port (u32 id, abe_data_format_t *f, + u32 subroutine_id, u32 size, + u32 *sink, u32 dsp_mcu_flag) { - _lock_enter + + _log(id_connect_irq_ping_pong_port,id,f->f,f->samp_format) /* ping_pong is only supported on MM_DL */ if (id != MM_DL_PORT) { abe_dbg_param |= ERR_API; - abe_dbg_error_log(ABE_PARAMETER_ERROR); + abe_dbg_error_log (ABE_PARAMETER_ERROR); } - abe_port[id] = ((abe_port_t *) abe_port_init)[id]; - (abe_port[id]).format = (*f); - (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT; - (abe_port[id]).protocol.p.prot_pingpong.buf_addr = dmem_ping_pong_buffer; - (abe_port[id]).protocol.p.prot_pingpong.buf_size = size; - (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1); + abe_port [id] = ((abe_port_t *) abe_port_init) [id]; + (abe_port [id]).format = (*f); + (abe_port [id]).protocol.protocol_switch = PINGPONG_PORT_PROT; + (abe_port [id]).protocol.p.prot_pingpong.buf_addr = + dmem_ping_pong_buffer; + (abe_port [id]).protocol.p.prot_pingpong.buf_size = size; + (abe_port [id]).protocol.p.prot_pingpong.irq_data = (1); - abe_init_ping_pong_buffer(MM_DL_PORT, size, 2, sink); + abe_init_ping_pong_buffer (MM_DL_PORT, size, 2, sink); if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ) - (abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_MCU_IRQSTATUS_RAW; + (abe_port [id]).protocol.p.prot_pingpong.irq_addr = + ABE_MCU_IRQSTATUS_RAW; if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ) - (abe_port [id]).protocol.p.prot_pingpong.irq_addr = ABE_DSP_IRQSTATUS_RAW; + (abe_port [id]).protocol.p.prot_pingpong.irq_addr = + ABE_DSP_IRQSTATUS_RAW; - abe_port[id].status = RUN_P; + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; /* load the micro-task parameters */ - abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol)); + abe_init_io_tasks (id, &((abe_port [id]).format), + &((abe_port [id]).protocol)); /* load the ATC descriptors - disabled */ - abe_init_atc(id); + abe_init_atc (id); + + *sink = (abe_port [id]).protocol.p.prot_pingpong.buf_addr; - (*sink)= (abe_port [id]).protocol.p.prot_pingpong.buf_addr; - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_connect_irq_ping_pong_port); /** -* @fn abe_connect_serial_port() -* -* Operations : enables the data echanges between a McBSP and an ATC buffer in -* DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz -* voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the -* abe_write_port API. -* -* Parameters : -* id: port name -* f : data format -* i : peripheral ID (McBSP #1, #2, #3) -* -* @see ABE_API.h -*/ -void abe_connect_serial_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id mcbsp_id) + * abe_connect_serial_port() + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * + * Operations : enables the data echanges between a McBSP and an ATC buffer in + * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz + * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the + * abe_write_port API. + */ +abehal_status abe_connect_serial_port (u32 id, abe_data_format_t *f, u32 mcbsp_id) { - abe_use_case_id UC_NULL[] = {(abe_use_case_id)0}; - abe_opp_t OPP; + u32 UC_NULL[] = {0}; + u32 OPP; abe_hw_config_init_t CONFIG; - _lock_enter _log(id_connect_serial_port,id,f->samp_format,mcbsp_id) abe_port [id] = ((abe_port_t *) abe_port_init) [id]; (abe_port [id]).format = (*f); + (abe_port [id]).protocol.protocol_switch = SERIAL_PORT_PROT; + /* McBSP peripheral connected to ATC */ (abe_port [id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE; - abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG); /* check the iteration of ATC */ + /* check the iteration of ATC */ + abe_read_hardware_configuration (UC_NULL, &OPP, &CONFIG); - (abe_port[id]).protocol.p.prot_serial.iter = abe_dma_port_iter_factor(f); + (abe_port [id]).protocol.p.prot_serial.iter = + abe_dma_port_iter_factor (f); - abe_port[id].status = RUN_P; + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; /* load the micro-task parameters */ - abe_init_io_tasks(id, &((abe_port[id]).format), &((abe_port[id]).protocol)); - abe_init_atc(id); /* load the ATC descriptors - disabled */ - - _lock_exit -} + abe_init_io_tasks(id, &((abe_port[id]).format), + &((abe_port[id]).protocol)); -/* - * ABE_READ_PORT_DESCRIPTOR - * - * Parameter : - * id: port name - * f : input pointer to the data format - * p : input pointer to the protocol description - * dma : output pointer to the DMA iteration and data destination pointer : - * - * Operations : - * returns the port parameters from the HAL internal buffer. - * - * Return value : - * error code in case the Port_id is not compatible with the current OPP value - */ -void abe_read_port_descriptor(abe_port_id port, abe_data_format_t *f, abe_port_protocol_t *p) -{ - (*f) = (abe_port[port]).format; - (*p) = (abe_port[port]).protocol; -} - -/* - * ABE_READ_APS_ENERGY - * - * Parameter : - * Port_ID : port ID supporting APS - * APS data struct pointer - * - * Operations : - * Returns the estimated amount of energy - * - * Return value : - * error code when the Port is not activated. - */ -void abe_read_aps_energy(abe_port_id *p, abe_gain_t *a) -{ - just_to_avoid_the_many_warnings_abe_port_id = *p; - just_to_avoid_the_many_warnings_abe_gain_t = *a; + /* load the ATC descriptors - disabled */ + abe_init_atc (id); + return 0; } +EXPORT_SYMBOL(abe_connect_serial_port); /** -* @fn abe_connect_slimbus_port() -* -* Operations : enables the data echanges between 1/2 SB and an ATC buffers in -* DMEM. -* -* Parameters : -* id: port name -* f : data format -* i : peripheral ID (McBSP #1, #2, #3) -* j : peripheral ID (McBSP #1, #2, #3) -* -* @see ABE_API.h -*/ -void abe_connect_slimbus_port(abe_port_id id, abe_data_format_t *f, - abe_slimbus_id sb_port1, abe_slimbus_id sb_port2) + * abe_connect_slimbus_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between 1/2 SB and an ATC buffers in + * DMEM. + */ +abehal_status abe_connect_slimbus_port (u32 id, abe_data_format_t *f, + u32 sb_port1, u32 sb_port2) { - abe_use_case_id UC_NULL[] = {(abe_use_case_id)0}; - abe_opp_t OPP; + u32 UC_NULL[] = {0}; + u32 OPP; abe_hw_config_init_t CONFIG; - abe_uint32 iter; + u32 iter; + - _lock_enter _log(id_connect_slimbus_port,id,f->samp_format,sb_port2) - abe_port[id] = ((abe_port_t *) abe_port_init) [id]; - (abe_port[id]).format = (*f); - (abe_port[id]).protocol.protocol_switch = SLIMBUS_PORT_PROT; + abe_port [id] = ((abe_port_t *) abe_port_init) [id]; + (abe_port [id]).format = (*f); + (abe_port [id]).protocol.protocol_switch = SLIMBUS_PORT_PROT; + /* SB1 peripheral connected to ATC */ - (abe_port[id]).protocol.p.prot_slimbus.desc_addr1= sb_port1*ATC_SIZE; + (abe_port [id]).protocol.p.prot_slimbus.desc_addr1= + sb_port1*ATC_SIZE; + /* SB2 peripheral connected to ATC */ - (abe_port[id]).protocol.p.prot_slimbus.desc_addr2= sb_port2*ATC_SIZE; + (abe_port [id]).protocol.p.prot_slimbus.desc_addr2= + sb_port2*ATC_SIZE; /* check the iteration of ATC */ - abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG); + abe_read_hardware_configuration (UC_NULL, &OPP, &CONFIG); iter = CONFIG.SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD; + /* SLIMBUS iter should be 1 */ - (abe_port[id]).protocol.p.prot_serial.iter = iter; + (abe_port [id]).protocol.p.prot_serial.iter = iter; + + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; - abe_port[id].status = RUN_P; /* load the micro-task parameters */ - abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol)); + abe_init_io_tasks (id, &((abe_port [id]).format), + &((abe_port [id]).protocol)); + /* load the ATC descriptors - disabled */ - abe_init_atc(id); + abe_init_atc (id); - _lock_exit + return 0; } - +EXPORT_SYMBOL(abe_connect_slimbus_port); /** -* @fn abe_connect_tdm_port() -* -* Operations : enables the data echanges between TDM McBSP ATC buffers in -* DMEM and 1/2 SMEM buffers -* -* Parameters : -* id: port name -* f : data format -* i : peripheral ID (McBSP #1, #2, #3) -* j : peripheral ID (McBSP #1, #2, #3) -* -* @see ABE_API.h -*/ - -void abe_connect_tdm_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id mcbsp_id) + * abe_connect_tdm_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between TDM McBSP ATC buffers in + * DMEM and 1/2 SMEM buffers + */ +abehal_status abe_connect_tdm_port (u32 id, abe_data_format_t *f, u32 mcbsp_id) { - abe_use_case_id UC_NULL[] = {(abe_use_case_id)0}; - abe_opp_t OPP; + u32 UC_NULL[] = {0}; + u32 OPP; abe_hw_config_init_t CONFIG; - abe_uint32 iter; + u32 iter; + - _lock_enter _log(id_connect_tdm_port,id,f->samp_format,mcbsp_id) abe_port [id] = ((abe_port_t *) abe_port_init) [id]; (abe_port [id]).format = (*f); (abe_port [id]).protocol.protocol_switch = TDM_SERIAL_PORT_PROT; /* McBSP peripheral connected to ATC */ - (abe_port [id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE; + (abe_port [id]).protocol.p.prot_serial.desc_addr = + mcbsp_id*ATC_SIZE; /* check the iteration of ATC */ - abe_read_hardware_configuration (UC_NULL, &OPP, &CONFIG); + abe_read_hardware_configuration (UC_NULL, &OPP, &CONFIG); if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) iter = CONFIG.MCBSP_THRSH1_REG_REG__RTHRESHOLD; else @@ -1218,316 +1200,309 @@ void abe_connect_tdm_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id mcb /* McBSP iter should be 1 */ (abe_port[id]).protocol.p.prot_serial.iter = iter; - abe_port[id].status = RUN_P; + abe_port [id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING; + /* load the micro-task parameters */ - abe_init_io_tasks(id, &((abe_port [id]).format), &((abe_port [id]).protocol)); + abe_init_io_tasks(id, &((abe_port [id]).format), + &((abe_port [id]).protocol)); + /* load the ATC descriptors - disabled */ abe_init_atc(id); - _lock_exit + + return 0; } +EXPORT_SYMBOL(abe_connect_tdm_port); -/* - * ABE_READ_PORT_ADDRESS - * - * Parameter : - * dma : output pointer to the DMA iteration and data destination pointer - * - * Operations : - * This API returns the address of the DMA register used on this audio port. - * Depending on the protocol being used, adds the base address offset L3 (DMA) or MPU (ARM) +/** + * abe_read_port_address + * @dma: output pointer to the DMA iteration and data destination pointer * - * Return value : + * This API returns the address of the DMA register used on this audio port. + * Depending on the protocol being used, adds the base address offset L3 + * (DMA) or MPU (ARM) */ -void abe_read_port_address(abe_port_id port, abe_dma_t *dma2) +abehal_status abe_read_port_address (u32 port, abe_dma_t *dma2) { abe_dma_t_offset dma1; - abe_uint32 protocol_switch; + u32 protocol_switch; + - _lock_enter _log(id_read_port_address,port,0,0) - dma1 = (abe_port[port]).dma; + dma1 = (abe_port[port]).dma; protocol_switch = abe_port[port].protocol.protocol_switch; switch (protocol_switch) { case PINGPONG_PORT_PROT: - /* return the base address of the ping buffer in L3 and L4 spaces */ - (*dma2).data = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3); + /* return the base address of the buffer in L3 and L4 spaces */ + (*dma2).data =(void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3); (*dma2).l3_dmem = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3); (*dma2).l4_dmem = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L4); break; - case DMAREQ_PORT_PROT: + case DMAREQ_PORT_PROT : /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */ - (*dma2).data = (void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3); + (*dma2).data =(void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3); (*dma2).l3_dmem = - (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr + - ABE_DMEM_BASE_ADDRESS_L3); - (*dma2).l4_dmem = (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr + ABE_DMEM_BASE_ADDRESS_L4); + (void *)((abe_port[port]).protocol.p. + prot_dmareq.buf_addr + + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).l4_dmem = + (void *)((abe_port[port]).protocol.p. + prot_dmareq.buf_addr + + ABE_DMEM_BASE_ADDRESS_L4); break; default: break; } - - (*dma2).iter = (dma1.iter); - - _lock_exit + (*dma2).iter = (dma1.iter); + return 0; } +EXPORT_SYMBOL(abe_read_port_address); -/* - * ABE_WRITE_EQUALIZER - * - * Parameter : - * Id : name of the equalizer - * Param : equalizer coefficients - * - * Operations : - * Load the coefficients in CMEM. This API can be called when the corresponding equalizer - * is not activated. After reloading the firmware the default coefficients corresponds to - * "no equalizer feature". Loading all coefficients with zeroes disables the feature. +/** + * abe_write_equalizer + * @id: name of the equalizer + * @param : equalizer coefficients * - * Return value : - * None. + * Load the coefficients in CMEM. */ -void abe_write_equalizer(abe_equ_id id, abe_equ_t *param) +abehal_status abe_write_equalizer (u32 id, abe_equ_t *param) { - abe_uint32 eq_offset, length, *src; + u32 eq_offset, length, *src; - _lock_enter _log(id_write_equalizer,id,0,0) - switch(id) { + switch (id) { default: - case EQ1: + case EQ1 : eq_offset = C_DL1_Coefs_ADDR; break; - case EQ2L: + case EQ2L : eq_offset = C_DL2_L_Coefs_ADDR; break; - case EQ2R: + case EQ2R : eq_offset = C_DL2_R_Coefs_ADDR; break; - case EQSDT: + case EQSDT : eq_offset = C_SDT_Coefs_ADDR; break; - case EQMIC: + case EQMIC : eq_offset = C_98_48_LP_Coefs_ADDR; break; - case APS1: + case APS1 : eq_offset = C_APS_DL1_coeffs1_ADDR; break; - case APS2L: + case APS2L : eq_offset = C_APS_DL2_L_coeffs1_ADDR; break; - case APS2R: + case APS2R : eq_offset = C_APS_DL2_R_coeffs1_ADDR; break; } - length = param->equ_length; - src = (abe_uint32 *)((param->coef).type1); + src = (u32 *)((param->coef).type1); - eq_offset <<=2; /* translate in bytes */ - length <<=2; /* translate in bytes */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, src, length); - _lock_exit -} + /* translate in bytes */ + eq_offset <<=2; -/* - * ABE_SET_ASRC_DRIFT_CONTROL - * - * Parameter : - * Id : name of the asrc - * f: flag which enables (1) the automatic computation of drift parameters - * - * Operations : - * When an audio port is connected to an hardware peripheral (MM_DL connected to a McBSP for - * example), the drift compensation can be managed in "forced mode" (f=0) or "adaptive mode" - * (f=1). In the first case the drift is managed with the usage of the API "abe_write_asrc". - * In the second case the firmware will generate on periodic basis an information about the - * observed drift, the HAL will reload the drift parameter based on those observations. - * - * Return value : - * None. - */ -void abe_set_asrc_drift_control(abe_asrc_id id, abe_uint32 f) -{ - _lock_enter - _log(id_set_asrc_drift_control,id,f,f>>8) - _lock_exit + /* translate in bytes */ + length <<=2; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, + src, length); + + return 0; } +EXPORT_SYMBOL(abe_write_equalizer); -/* - * ABE_WRITE_ASRC - * - * Parameter : - * Id : name of the asrc - * param : drift value t compensate - * - * Operations : - * Load the drift coefficients in FW memory. This API can be called when the corresponding - * ASRC is not activated. After reloading the firmware the default coefficients corresponds - * to "no ASRC activated". Loading the drift value with zero disables the feature. - * - * Return value : - * None. +/** + * abe_write_asrc + * @id: name of the port + * @param: drift value to compensate [ppm] + * + * Load the drift variables to the FW memory. This API can be called only + * when the corresponding port has been already opened and the ASRC has + * been correctly initialized with API abe_init_asrc_... If this API is + * used such that the drift has been changed from positive to negative drift + * or vice versa, there will be click in the output signal. Loading the drift + * value with zero disables the feature. */ -void abe_write_asrc(abe_asrc_id id, abe_drift_t dppm) +abehal_status abe_write_asrc (u32 port, s32 dppm) { - _lock_enter - _log(id_write_asrc,id,dppm,dppm>>8) + s32 dtempvalue, adppm, drift_sign, drift_sign_addr, alpha_params_addr; + s32 alpha_params[3]; + + + _log(id_write_asrc, port, dppm, dppm>>8) -#if 0 - abe_int32 dtempvalue, adppm, alpha_current, beta_current, asrc_params; - abe_int32 atempvalue32[8]; /* * x = ppm - * - 1000000/x must be multiple of 16 - * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits. then shifted by 2bits - * - minusdeltaalpha - * - oneminusepsilon = 1-deltaalpha/2. - * ppm = 250 - * - 1000000/250=4000 - * - deltaalpha = 4194.3 ~ 4195 => 0x00418c + * + * - 1000000/x must be multiple of 16 + * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits. + * then shifted by 2bits + * - minusdeltaalpha + * - oneminusepsilon = 1-deltaalpha/2. + * + * ppm = 250 + * - 1000000/250=4000 + * - deltaalpha = 4194.3 ~ 4195 => 0x00418c */ - /* examples for -6250 ppm */ - // atempvalue32[0] = 4; /* d_constalmost0 */ - // atempvalue32[1] = -1; /* d_driftsign */ - // atempvalue32[2] = 15; /* d_subblock */ - // atempvalue32[3] = 0x00066668; /* d_deltaalpha */ - // atempvalue32[4] = 0xfff99998; /* d_minusdeltaalpha */ - // atempvalue32[5] = 0x003ccccc; /* d_oneminusepsilon */ - // atempvalue32[6] = 0x00000000; /* d_alphazero */ - // atempvalue32[7] = 0x00400000; /* d_betaone */ + + /* examples for -6250 ppm */ + /* atempvalue32[1] = -1; d_driftsign */ + /* atempvalue32[3] = 0x00066668; d_deltaalpha */ + /* atempvalue32[4] = 0xfff99998; d_minusdeltaalpha */ + /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */ + + /* example for 100 ppm */ + /* atempvalue32[1] = 1;* d_driftsign */ + /* atempvalue32[3] = 0x00001a38; d_deltaalpha */ + /* atempvalue32[4] = 0xffffe5c8; d_minusdeltaalpha */ + /* atempvalue32[5] = 0x003ccccc; d_oneminusepsilon */ /* compute new value for the ppm */ - if (dppm > 0){ - atempvalue32[1] = 1; /* d_driftsign */ + if (dppm >= 0) { + /* d_driftsign */ + drift_sign = 1; adppm = dppm; } else { - atempvalue32[1] = -1; /* d_driftsign */ + /* d_driftsign */ + drift_sign = -1; adppm = (-1*dppm); } + if (dppm == 0) { + /* delta_alpha */ + alpha_params[0] = 0; - dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L)/15625L); - atempvalue32[3] = dtempvalue<<2; - atempvalue32[4] = (-dtempvalue)<<2; - atempvalue32[5] = (0x00100000-(dtempvalue/2))<<2; + /* minusdelta_alpha */ + alpha_params[1] = 0; - switch (id) { - case ASRC2: /* asynchronous sample-rate-converter for the uplink voice path */ - alpha_current = C_AlphaCurrent_UL_VX_ADDR; - beta_current = C_BetaCurrent_UL_VX_ADDR; - asrc_params = D_AsrcVars_UL_VX_ADDR; + /* one_minusepsilon */ + alpha_params[2] = 0x003ffff0; + } else { + dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L)/15625L); + + /* delta_alpha */ + alpha_params[0] = dtempvalue<<2; + + /* minusdelta_alpha */ + alpha_params[1] = (-dtempvalue)<<2; + + /* one_minusepsilon */ + alpha_params[2] = (0x00100000-(dtempvalue/2))<<2; + } + + switch (port) { + + /* asynchronous sample-rate-converter for the uplink voice path */ + case VX_DL_PORT: + drift_sign_addr = D_AsrcVars_DL_VX_ADDR + 1*sizeof(s32); + alpha_params_addr = D_AsrcVars_DL_VX_ADDR + 3*sizeof(s32); break; - case ASRC1: /* asynchronous sample-rate-converter for the downlink voice path */ - alpha_current = C_AlphaCurrent_DL_VX_ADDR; - beta_current = C_BetaCurrent_DL_VX_ADDR; - asrc_params = D_AsrcVars_DL_VX_ADDR; + + /* asynchronous sample-rate-converter for the downlink voice path */ + case VX_UL_PORT: + drift_sign_addr = D_AsrcVars_UL_VX_ADDR + 1*sizeof(s32); + alpha_params_addr = D_AsrcVars_UL_VX_ADDR + 3*sizeof(s32); break; + default: - case ASRC3: /* asynchronous sample-rate-converter for the multimedia player */ - alpha_current = C_AlphaCurrent_DL_MM_ADDR; - beta_current = C_BetaCurrent_DL_MM_ADDR; - asrc_params = D_AsrcVars_DL_MM_ADDR; + + /* asynchronous sample-rate-converter for the multimedia player */ + case MM_DL_PORT: + drift_sign_addr = D_AsrcVars_DL_MM_ADDR + 1*sizeof(s32); + alpha_params_addr = D_AsrcVars_DL_MM_ADDR + 3*sizeof(s32); break; } - dtempvalue = 0x00000000; - abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, alpha_current,(abe_uint32 *)&dtempvalue, 4); - dtempvalue = 0x00400000; - abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, beta_current, (abe_uint32 *)&dtempvalue, 4); - abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, asrc_params , (abe_uint32 *)&atempvalue32, sizeof(atempvalue32)); -#endif - _lock_exit + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, drift_sign_addr, + (u32 *)&drift_sign, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, alpha_params_addr , + (u32 *)&alpha_params[0], 12); + + return 0; } +EXPORT_SYMBOL(abe_write_asrc); -/* - * ABE_WRITE_APS - * - * Parameter : - * Id : name of the aps filter - * param : table of filter coefficients - * - * Operations : - * Load the filters and thresholds coefficients in FW memory. This API can be called when - * the corresponding APS is not activated. After reloading the firmware the default coefficients - * corresponds to "no APS activated". Loading all the coefficients value with zero disables - * the feature. - * - * Return value : - * None. +/** + * abe_write_aps + * @id: name of the aps filter + * @param: table of filter coefficients + * + * Load the filters and thresholds coefficients in FW memory. This API + * can be called when the corresponding APS is not activated. After + * reloading the firmware the default coefficients corresponds to "no APS + * activated". + * Loading all the coefficients value with zero disables the feature. */ -void abe_write_aps(abe_aps_id id, abe_aps_t *param) +abehal_status abe_write_aps (u32 id, abe_aps_t *param) { - _lock_enter _log(id_write_aps,id,0,0) - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_write_aps); -/* - * ABE_WRITE_MIXER - * - * Parameter : - * Id : name of the mixer - * param : list of input gains of the mixer - * p : list of port corresponding to the above gains - * - * Operations : - * Load the gain coefficients in FW memory. This API can be called when the corresponding - * MIXER is not activated. After reloading the firmware the default coefficients corresponds - * to "all input and output mixer's gain in mute state". A mixer is disabled with a network - * reconfiguration corresponding to an OPP value. - * - * Return value : - * None. +/** + * abe_write_mixer + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's gain + * in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. */ -void abe_write_gain(abe_gain_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p) +abehal_status abe_write_gain (u32 id, u32 f_g, u32 ramp, u32 p) { - abe_uint32 lin_g, mixer_target, mixer_offset; - abe_int32 gain_index; + u32 lin_g, mixer_target, mixer_offset; + s32 gain_index; + u32 alpha, beta; + u32 ramp_index; - _lock_enter _log(id_write_gain,id,f_g,p) gain_index = ((f_g - min_mdb) / 100); - gain_index = maximum(gain_index, 0); - gain_index = minimum(gain_index, sizeof_db2lin_table); + gain_index = maximum (gain_index, 0); + gain_index = minimum (gain_index, sizeof_db2lin_table); lin_g = abe_db2lin_table [gain_index]; - switch(id) { + switch (id) { default: - case GAINS_DMIC1: + case GAINS_DMIC1 : mixer_offset = dmic1_gains_offset; break; - case GAINS_DMIC2: + case GAINS_DMIC2 : mixer_offset = dmic2_gains_offset; break; - case GAINS_DMIC3: + case GAINS_DMIC3 : mixer_offset = dmic3_gains_offset; break; - case GAINS_AMIC: + case GAINS_AMIC : mixer_offset = amic_gains_offset; break; - case GAINS_DL1: + case GAINS_DL1 : mixer_offset = dl1_gains_offset; break; - case GAINS_DL2: + case GAINS_DL2 : mixer_offset = dl2_gains_offset; break; - case GAINS_SPLIT: + case GAINS_SPLIT : mixer_offset = splitters_gains_offset; break; - case MIXDL1: + + case MIXDL1 : mixer_offset = mixer_dl1_offset; break; - case MIXDL2: + case MIXDL2 : mixer_offset = mixer_dl2_offset; break; - case MIXECHO: + case MIXECHO : mixer_offset = mixer_echo_offset; break; - case MIXSDT: + case MIXSDT : mixer_offset = mixer_sdt_offset; break; case MIXVXREC: @@ -1538,211 +1513,333 @@ void abe_write_gain(abe_gain_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_ break; } - mixer_target = (smem_target_gain_base << 1);/* SMEM word32 address */ + /* SMEM word32 address */ + mixer_target = (S_GTarget1_ADDR << 1); mixer_target += mixer_offset; mixer_target += p; - mixer_target <<= 2; /* translate coef address in Bytes */ + + /* translate coef address in Bytes */ + mixer_target <<= 2; /* load the S_G_Target SMEM table */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target, - (abe_uint32*)&lin_g, sizeof(lin_g)); - _lock_exit + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target, + (u32*)&lin_g, sizeof(lin_g)); + + + ramp = maximum(minimum (RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH); + + /* ramp data should be interpolated in the table instead */ + if (ramp < RAMP_5MS) + ramp_index = 8; + if ((RAMP_5MS <= ramp) && (ramp < RAMP_50MS)) + ramp_index = 24; + if ((RAMP_50MS <= ramp) && (ramp < RAMP_500MS)) + ramp_index = 36; + if (ramp > RAMP_500MS) + ramp_index = 48; + + beta = abe_alpha_iir [ramp_index]; + alpha = abe_1_alpha_iir [ramp_index]; + + /* CMEM word32 address */ + mixer_target = C_1_Alpha_ADDR; + + /* a pair of gains is updated once in the firmware */ + mixer_target += (p + mixer_offset) >> 1; + + /* translate coef address in Bytes */ + mixer_target <<= 2; + + /* load the ramp delay data */ + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target, + (u32*)&alpha, sizeof(alpha)); + + /* CMEM word32 address */ + mixer_target = C_Alpha_ADDR; + + /* a pair of gains is updated once in the firmware */ + mixer_target += (p + mixer_offset) >> 1; + + /* translate coef address in Bytes */ + mixer_target <<= 2; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target, + (u32*)&beta, sizeof(beta)); + + return 0; } +EXPORT_SYMBOL(abe_write_gain); -void abe_write_mixer(abe_mixer_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p) +/** + * abe_write_mixer + * @id: name of the mixer + * @param: input gains and delay ramp of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_mixer (u32 id, u32 f_g, u32 f_ramp, u32 p) { - _lock_enter _log(id_write_mixer,id,f_ramp,p) - abe_write_gain ((abe_gain_id)id, f_g, f_ramp, p); - - _lock_exit + abe_write_gain (id, f_g, f_ramp, p); + return 0; } +EXPORT_SYMBOL(abe_write_mixer); -/* - * ABE_SET_ROUTER_CONFIGURATION - * - * Parameter : - * Id : name of the router - * Conf : id of the configuration - * param : list of output index of the route +/** + * abe_read_gain + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains * - * Operations : - * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) and - * PORT1/2 (2 stereo ports). Each sample will be individually stored in an intermediate - * table of 10 elements. The intermediate table is used to route the samples to - * three directions : REC1 mixer, 2 EANC DMIC source of filtering and MM recording audio path. - * For example, a use case consisting in AMIC used for uplink voice communication, DMIC 0,1,2,3 - * used for multimedia recording, , DMIC 5 used for EANC filter, DMIC 4 used for the feedback channel, - * will be implemented with the following routing table index list : - * [3, 2 , 1, 0, 0, 0 (two dummy indexes to data that will not be on MM_UL), 4, 5, 7, 6] - * example - * abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_AMIC, abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); - * Return value : - * None. */ -void abe_set_router_configuration(abe_router_id id, abe_uint32 unused, abe_router_t *param) +abehal_status abe_read_gain (u32 id, u32 *f_g, u32 p) { - _lock_enter - _log(id_set_router_configuration,id,(abe_uint32)param,(abe_uint32)param>>8) + u32 mixer_target, mixer_offset; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, - (abe_uint32 *)param, D_aUplinkRouting_ADDR_END - D_aUplinkRouting_ADDR + 1); + _log(id_read_gain,id,(u32)f_g,p) - _lock_exit + switch (id) { + default: + case GAINS_DMIC1 : + mixer_offset = dmic1_gains_offset; + break; + case GAINS_DMIC2 : + mixer_offset = dmic2_gains_offset; + break; + case GAINS_DMIC3 : + mixer_offset = dmic3_gains_offset; + break; + case GAINS_AMIC : + mixer_offset = amic_gains_offset; + break; + case GAINS_DL1 : + mixer_offset = dl1_gains_offset; + break; + case GAINS_DL2 : + mixer_offset = dl2_gains_offset; + break; + case GAINS_SPLIT : + mixer_offset = splitters_gains_offset; + break; + + case MIXDL1 : + mixer_offset = mixer_dl1_offset; + break; + case MIXDL2 : + mixer_offset = mixer_dl2_offset; + break; + case MIXECHO : + mixer_offset = mixer_echo_offset; + break; + case MIXSDT : + mixer_offset = mixer_sdt_offset; + break; + case MIXVXREC: + mixer_offset = mixer_vxrec_offset; + break; + case MIXAUDUL: + mixer_offset = mixer_audul_offset; + break; + } + + /* SMEM word32 address */ + mixer_target = (S_GTarget1_ADDR << 1); + mixer_target += mixer_offset; + mixer_target += p; + + /* translate coef address in Bytes */ + mixer_target <<= 2; + + /* load the S_G_Target SMEM table */ + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_SMEM, mixer_target, + (u32*)f_g, sizeof(*f_g)); + + return 0; } +EXPORT_SYMBOL(abe_read_gain); -/* - * ABE_SELECT_DATA_SOURCE - * - * Parameter : - * - * Operations : - * - * Return value : - * None. +/** + * abe_read_mixer + * @id: name of the mixer + * @param: gains of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_read_mixer (u32 id, u32 *f_g, u32 p) +{ + _log(id_read_mixer,id,0,p) + + abe_read_gain (id, f_g, p); + return 0; +} +EXPORT_SYMBOL(abe_read_mixer); + +/** + * abe_set_router_configuration + * @Id: name of the router + * @Conf: id of the configuration + * @param: list of output index of the route + * + * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) + * and PORT1/2 (2 stereo ports). Each sample will be individually stored in + * an intermediate table of 10 elements. + * + * Example of router table parameter for voice uplink with phoenix microphones + * + * indexes 0 .. 9 = MM_UL description (digital MICs and MMEXTIN) + * DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + * MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID, + * ZERO_labelID, ZERO_labelID, + * indexes 10 .. 11 = MM_UL2 description (recording on DMIC3) + * DMIC3_L_labelID, DMIC3_R_labelID, + * indexes 12 .. 13 = VX_UL description (VXUL based on PDMUL data) + * AMIC_L_labelID, AMIC_R_labelID, + * indexes 14 .. 15 = RESERVED (NULL) + * ZERO_labelID, ZERO_labelID, + */ +abehal_status abe_set_router_configuration (u32 id, u32 k, u32 *param) +{ + + _log(id_set_router_configuration,id,(u32)param,(u32)param>>8) + + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_aUplinkRouting_ADDR, + param, D_aUplinkRouting_sizeof); + + return 0; +} +EXPORT_SYMBOL(abe_set_router_configuration); + +/** + * abe_select_data_source + * @@@ */ -void abe_select_data_source (abe_port_id port_id, abe_dl_src_id smem_source) +abehal_status abe_select_data_source (u32 port_id, u32 smem_source) { ABE_SIODescriptor desc; - abe_uint32 sio_desc_address; + u32 sio_desc_address; - _lock_enter _log(id_select_data_source,port_id,smem_source,smem_source>>8) - sio_desc_address = dmem_port_descriptors + (port_id * sizeof(ABE_SIODescriptor)); - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc, sizeof (desc)); - desc.smem_addr1 = (abe_uint16) smem_source; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc, sizeof (desc)); + sio_desc_address = dmem_port_descriptors + (port_id * + sizeof(ABE_SIODescriptor)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, + (u32*)&desc, sizeof (desc)); + desc.smem_addr1 = (u16) smem_source; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32*)&desc, sizeof (desc)); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_select_data_source); - -/* - * ABE_READ_DEBUG_TRACE +/** + * ABE_READ_DEBUG_TRACE * - * Parameter : + * Parameter : * data destination pointer * max number of data read * - * Operations : - * reads the AE circular data pointer holding pairs of debug data+timestamps, and store - * the pairs in linear addressing to the parameter pointer. Stops the copy when the max - * parameter is reached or when the FIFO is empty. + * Operations : + * reads the AE circular data pointer holding pairs of debug data+ + * timestamps, and store the pairs in linear addressing to the parameter + * pointer. Stops the copy when the max parameter is reached or when the + * FIFO is empty. * - * Return value : + * Return value : * None. */ -void abe_read_debug_trace(abe_uint32 *data, abe_uint32 *n) +abehal_status abe_read_debug_trace (u32 *data, u32 *n) { - _lock_enter _log(id_select_data_source,0,0,0) - - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_read_debug_trace); -/* - * ABE_CONNECT_DEBUG_TRACE - * - * Parameter : - * pointer to the DMEM trace buffer - * - * Operations : - * returns the address and size of the real-time debug trace buffer, - * the content of which will vary from one firmware release to an other +/** + * abe_connect_debug_trace + * @dma2:pointer to the DMEM trace buffer * - * Return value : - * None. + * returns the address and size of the real-time debug trace buffer, + * the content of which will vary from one firmware release to an other */ - -void abe_connect_debug_trace (abe_dma_t *dma2) +abehal_status abe_connect_debug_trace (abe_dma_t *dma2) { - _lock_enter + _log(id_connect_debug_trace,0,0,0) /* return the base address of the ping buffer in L3 and L4 spaces */ - (*dma2).data = (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3); + (*dma2).data =(void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3); (*dma2).l3_dmem = (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3); (*dma2).l4_dmem = (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L4); - (*dma2).iter = D_DEBUG_FIFO_ADDR_END - D_DEBUG_FIFO_ADDR; + (*dma2).iter = D_DEBUG_FIFO_sizeof; - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_connect_debug_trace); - -/* - * ABE_SET_DEBUG_TRACE - * - * Parameter : - * debug ID from a list to be defined - * - * Operations : - * load a mask which filters the debug trace to dedicated types of data +/** + * abe_set_debug_trace + * @debug: debug ID from a list to be defined * - * Return value : - * None. + * load a mask which filters the debug trace to dedicated types of data */ -void abe_set_debug_trace(abe_dbg_t debug) +abehal_status abe_set_debug_trace (abe_dbg_t debug) { - _lock_enter + _log(id_set_debug_trace,0,0,0) abe_dbg_mask = debug; - - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_set_debug_trace); -/* - * ABE_REMOTE_DEBUGGER_INTERFACE - * - * Parameter : - * - * Operations : - * interpretation of the UART stream from the remote debugger commands. - * The commands consist in setting break points, loading parameter +/** + * abe_remote_debugger_interface * - * Return value : - * None. + * interpretation of the UART stream from the remote debugger commands. + * The commands consist in setting break points, loading parameter */ -void abe_remote_debugger_interface(abe_uint32 n, abe_uint8 *p) +abehal_status abe_remote_debugger_interface (u32 n, u8 *p) { - _lock_enter - _log(id_remote_debugger_interface,n,0,0) - - _lock_exit + _log(id_remote_debugger_interface,n,0,0) + return 0; } +EXPORT_SYMBOL(abe_remote_debugger_interface); -/* - * ABE_ENABLE_TEST_PATTERN - * - * Parameter: - * - * Operations : + +/** + * abe_enable_test_pattern * - * Return value : - * None. */ -void abe_enable_test_pattern (abe_patched_pattern_id smem_id, abe_uint32 on_off) +abehal_status abe_enable_test_pattern (u32 smem_id, u32 on_off) { - abe_uint16 dbg_on, dbg_off, idx_patch, task_patch, addr_patch; - abe_uint32 patch, task32; + u16 dbg_on, dbg_off, idx_patch, task_patch, addr_patch; + u32 patch, task32; + - _lock_enter _log(id_enable_test_pattern,on_off,smem_id,smem_id>>8) switch (smem_id) { - case DBG_PATCH_AMIC: + case DBG_PATCH_AMIC : dbg_on = DBG_48K_PATTERN_labelID; dbg_off = AMIC_labelID; task_patch = C_ABE_FW_TASK_AMIC_SPLIT; idx_patch = 1; break; - case DBG_PATCH_DMIC1: + case DBG_PATCH_DMIC1 : dbg_on = DBG_48K_PATTERN_labelID; dbg_off = DMIC1_labelID; task_patch = C_ABE_FW_TASK_DMIC1_SPLIT; @@ -1808,6 +1905,7 @@ void abe_enable_test_pattern (abe_patched_pattern_id smem_id, abe_uint32 on_off) task_patch = C_ABE_FW_TASK_MIC4_SPLIT; idx_patch = 1; break; + case DBG_PATCH_MM_DL_MIXDL1: dbg_on = DBG_48K_PATTERN_labelID; dbg_off = AMIC_labelID; @@ -1821,21 +1919,25 @@ void abe_enable_test_pattern (abe_patched_pattern_id smem_id, abe_uint32 on_off) idx_patch = 1; break; default: - return; + return 0; } - patch = (on_off != 0)? dbg_on: dbg_off; + /* address is on 16bits boundary */ addr_patch = D_tasksList_ADDR + 16 * task_patch + 2 * idx_patch; + /* read on 32bits words' boundary */ - abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, addr_patch & (~0x03), &task32, 4); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, addr_patch & (~0x03), + &task32, 4); if (addr_patch & 0x03) task32 = (0x0000FFFFL & task32) | (patch << 16); else task32 = (0xFFFF0000L & task32) | (0x0000FFFF & patch); - abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, addr_patch & (~0x03), &task32, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, addr_patch & (~0x03), + &task32, 4); - _lock_exit + return 0; } +EXPORT_SYMBOL(abe_enable_test_pattern); diff --git a/sound/soc/omap/abe/abe_api.h b/sound/soc/omap/abe/abe_api.h index 2752530796ff..e88019d6a0fd 100644 --- a/sound/soc/omap/abe/abe_api.h +++ b/sound/soc/omap/abe/abe_api.h @@ -1,649 +1,500 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #ifndef _ABE_API_H_ #define _ABE_API_H_ -#ifdef __cplusplus -extern "C" { -#endif - -/* - * External API - */ -#if PC_SIMULATION -extern void target_server_read_pmem(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_write_pmem(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_read_cmem(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_write_cmem(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_read_atc(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_write_atc(abe_uint32 address, abe_uint32 *data, abe_uint32 nb_words_32bits); -extern void target_server_read_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits); -extern void target_server_write_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits); -extern void target_server_read_dmem(abe_uint32 address_byte, abe_uint32 *data, abe_uint32 nb_byte); -extern void target_server_write_dmem(abe_uint32 address_byte, abe_uint32 *data, abe_uint32 nb_byte); - -extern void target_server_activate_mcpdm_ul(void); -extern void target_server_activate_mcpdm_dl(void); -extern void target_server_activate_dmic(void); -extern void target_server_set_voice_sampling(int dVirtAudioVoiceMode, int dVirtAudioVoiceSampleFrequency); -extern void target_server_set_dVirtAudioMultimediaMode(int dVirtAudioMultimediaMode); -#endif -/* - * Internal API - */ - -/** -* abe_read_sys_clock() description for void abe_read_sys_clock(). -* -* Operations : returns the current time indication for the LOG -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_read_sys_clock(abe_micros_t *time); - -/** -* abe_fprintf() description for void abe_fprintf(). -* -* Operations : returns the current time indication for the LOG -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -//void abe_fprintf(char *line); +/** + * abe_reset_hal - reset the ABE/HAL + * @rdev: regulator source + * @constraints: constraints to apply + * + * Operations : reset the HAL by reloading the static variables and + * default AESS registers. + * Called after a PRCM cold-start reset of ABE + */ +abehal_status abe_reset_hal (void); -/* - * API as part of the HAL paper documentation - */ - -/** -* abe_reset_hal() description for void abe_reset_hal(). -* -* Operations : reset the HAL by reloading the static variables and default AESS registers. -* Called after a PRCM cold-start reset of ABE -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_reset_hal(void); - -/** -* abe_read_use_case_opp() description for void abe_read_use_case_opp(). -* -* Operations : returns the expected min OPP for a given use_case list -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_read_use_case_opp(abe_use_case_id *u, abe_opp_t *o); - -/** -* abe_load_fw() description for void abe_load_fw(). -* -* Operations : -* loads the Audio Engine firmware, generate a single pulse on the Event generator -* to let execution start, read the version number returned from this execution. -* -* Parameter : No parameter -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code in case the firmware does not start. -* -* @see -*/ -void abe_load_fw(void); - -/** -* abe_read_port_address() description for void abe_read_port_address(). -* -* Operations : -* This API returns the address of the DMA register used on this audio port. -* -* Parameter : No parameter -* @param dma : output pointer to the DMA iteration and data destination pointer -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_read_port_address(abe_port_id port, abe_dma_t *dma); - -/** -* abe_irq_processing() description for void abe_irq_processing(). -* -* Parameter : -* No parameter -* -* Operations : -* This subroutine will check the IRQ_FIFO from the AE and act accordingly. -* Some IRQ source are originated for the delivery of "end of time sequenced tasks" -* notifications, some are originated from the Ping-Pong protocols, some are generated from -* the embedded debugger when the firmware stops on programmable break-points, etc … -* -* @param dma : output pointer to the DMA iteration and data destination pointer -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_irq_processing(void); - -/** -* abe_write_event_generator () description for void abe_event_generator_switch(). -* -* Operations : -* load the AESS event generator hardware source. Loads the firmware parameters -* accordingly. Indicates to the FW which data stream is the most important to preserve -* in case all the streams are asynchronous. If the parameter is "default", let the HAL -* decide which Event source is the best appropriate based on the opened ports. -* -* @param e: Event Generation Counter, McPDM, DMIC or default. -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_write_event_generator(abe_event_id e); - -/** -* abe_set_opp_processing() description for void abe_set_opp_processing(). -* -* Parameter : -* New processing network and OPP: -* 0: Ultra Lowest power consumption audio player (no post-processing, no mixer); -* 1: OPP 25% (simple multimedia features, including low-power player); -* 2: OPP 50% (multimedia and voice calls); -* 3: OPP100% (EANC, multimedia complex use-cases); -* -* Operations : -* Rearranges the FW task network to the corresponding OPP list of features. -* The corresponding AE ports are supposed to be set/reset accordingly before this switch. -* -* @param o: desired opp -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_set_opp_processing(abe_opp_t opp); - -/** -* abe_set_ping_pong_bufferg() description for void abe_set_ping_pong_buffer(). -* -* Parameter : -* Port_ID : -* Pointer name : Read or Write pointer -* New data -* -* Operations : -* Updates the ping-pong read/write pointer with the input data. -* -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_set_ping_pong_buffer(abe_port_id port, abe_uint32 n); - -/** -* @fn abe_connect_irq_ping_pong_port() -* -* Operations : enables the data echanges between a direct access to the DMEM -* memory of ABE using cache flush. On each IRQ activation a subroutine -* registered with "abe_plug_subroutine" will be called. This subroutine -* will generate an amount of samples, send them to DMEM memory and call -* "abe_set_ping_pong_buffer" to notify the new amount of samples in the -* pong buffer. -* -* Parameters : -* id: port name -* f : desired data format -* I : index of the call-back subroutine to call -* s : half-buffer (ping) size -* -* p: returned base address of the first (ping) buffer) -* -* @see ABE_API.h -*/ -void abe_connect_irq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, - abe_uint32 s, abe_uint32 *p, abe_uint32 dsp_mcu_flag); - -/** -* abe_plug_subroutine() description for void abe_plug_subroutine(). -* -* Parameter : -* id: returned sequence index after plugging a new subroutine -* f : subroutine address to be inserted -* -* Operations : -* register a list of subroutines for call-back purpose. -* -* @param -* -* @pre no pre-condition -* -* @post -* -* @return error code -* -* @see -*/ -void abe_plug_subroutine(abe_uint32 *id, abe_subroutine2 f, abe_uint32 n, abe_uint32 *params); +/** + * abe_load_fw_param - Load ABE Firmware memories + * @PMEM: Pointer of Program memory data + * @PMEM_SIZE: Size of PMEM data + * @CMEM: Pointer of Coeffients memory data + * @CMEM_SIZE: Size of CMEM data + * @SMEM: Pointer of Sample memory data + * @SMEM_SIZE: Size of SMEM data + * @DMEM: Pointer of Data memory data + * @DMEM_SIZE: Size of DMEM data + * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. + */ +abehal_status abe_load_fw_param (u32 *FW); -/* - * ABE_RESET_PORT - * - * Parameters : - * id: port name - * - * Returned value : error code - * - * Operations : stop the port activity and reload default parameters on the associated processing features. +/** + * abe_load_fw - Load ABE Firmware and initialize memories * + * loads the Audio Engine firmware, generate a single pulse on the Event + * generator to let execution start, read the version number returned from + * this execution. */ -void abe_reset_port(abe_port_id id); +abehal_status abe_load_fw (void); -/* - * ABE_READ_REMAINING_DATA - * - * Parameter : - * Port_ID : - * size : pointer to the remaining number of 32bits words +/** + * abe_read_hardware_configuration - Return default HW periferals configuration + * @u: use-case description list (pointer) + * @o: opp mode (pointer) + * @hw: pointer to the output HW structure * - * Operations : - * computes the remaining amount of data in the buffer. + + * Parameter : + * U : use-case description list (pointer) + * H : pointer to the output structure * - * Return value : - * error code + * Operations : + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC + * will be upgraded in FW06 + * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC */ -void abe_read_remaining_data(abe_port_id port, abe_uint32 *n); +abehal_status abe_read_hardware_configuration (u32 *u, u32 *o, abe_hw_config_init_t *hw); -/* - * ABE_DISABLE_DATA_TRANSFER - * - * Parameter : - * p: port indentifier +/** + * abe_irq_processing - Process ABE interrupt + * + * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio + * back-end interrupt. This subroutine will check the ATC Hrdware, the + * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated + * for the delivery of "end of time sequenced tasks" notifications, some are + * originated from the Ping-Pong protocols, some are generated from + * the embedded debugger when the firmware stops on programmable break-points, + * etc … + */ +abehal_status abe_irq_processing (void); + +/** + * abe_select_main_port - Select stynchronization port for Event generator. + * @id: audio port name * - * Operations : - * disables the ATC descriptor + * tells the FW which is the reference stream for adjusting + * the processing on 23/24/25 slots + */ +abehal_status abe_select_main_port (u32 id); + +/** + * abe_write_event_generator - Select event generator source + * @e: Event Generation Counter, McPDM, DMIC or default. + * + * load the AESS event generator hardware source. Loads the firmware parameters + * accordingly. Indicates to the FW which data stream is the most important to preserve + * in case all the streams are asynchronous. If the parameter is "default", let the HAL + * decide which Event source is the best appropriate based on the opened ports. + * + * When neither the DMIC and the McPDM are activated the AE will have its EVENT generator programmed + * with the EVENT_COUNTER. The event counter will be tuned in order to deliver a pulse frequency higher + * than 96 kHz. The DPLL output at 100% OPP is MCLK = (32768kHz x6000) = 196.608kHz + * The ratio is (MCLK/96000)+(1<<1) = 2050 + * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%) + */ +abehal_status abe_write_event_generator (u32 e); + +/** + * abe_read_use_case_opp() - description for void abe_read_use_case_opp(). * - * Return value : - * None. + * returns the expected min OPP for a given use_case list */ -void abe_disable_data_transfer (abe_port_id p); +abehal_status abe_read_use_case_opp (u32 *u, u32 *o); -/* - * ABE_ENABLE_DATA_TRANSFER +/** + * abe_set_opp_processing - Set OPP mode for ABE Firmware + * @opp: OOPP mode * - * Parameter : - * p: port indentifier + * New processing network and OPP: + * 0: Ultra Lowest power consumption audio player (no post-processing, no mixer) + * 1: OPP 25% (simple multimedia features, including low-power player) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (EANC, multimedia complex use-cases) * - * Operations : - * enables the ATC descriptor + * Rearranges the FW task network to the corresponding OPP list of features. + * The corresponding AE ports are supposed to be set/reset accordingly before + * this switch. * - * Return value : - * None. */ -void abe_enable_data_transfer(abe_port_id p); +abehal_status abe_set_opp_processing (u32 opp); -/* - * ABE_SET_DMIC_FILTER - * - * Parameter : - * DMIC decimation ratio : 16/25/32/40 - * - * Operations : - * Loads in CMEM a specific list of coefficients depending on the DMIC sampling - * frequency (2.4MHz or 3.84MHz);. This table compensates the DMIC decimator roll-off at 20kHz. - * The default table is loaded with the DMIC 2.4MHz recommended configuration. - * - * Return value : - * None. - */ -void abe_set_dmic_filter(abe_dmic_ratio_t d); - -/** -* @fn abe_connect_cbpr_dmareq_port() -* -* Operations : enables the data echange between a DMA and the ABE through the -* CBPr registers of AESS. -* -* Parameters : -* id: port name -* f : desired data format -* d : desired dma_request line (0..7) -* a : returned pointer to the base address of the CBPr register and number of -* samples to exchange during a DMA_request. -* -* @see ABE_API.h -*/ -void abe_connect_cbpr_dmareq_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_dma_t *a); - -/** -* @fn abe_connect_dmareq_ping_pong_port() -* -* Operations : enables the data echanges between a DMA and a direct access to the -* DMEM memory of ABE. On each dma_request activation the DMA will exchange "s" -* bytes and switch to the "pong" buffer for a new buffer exchange.ABE -* -* Parameters : -* id: port name -* f : desired data format -* d : desired dma_request line (0..7) -* s : half-buffer (ping) size -* -* a : returned pointer to the base address of the ping-pong buffer and number of samples to exchange during a DMA_request. -* -* @see ABE_API.h -*/ -void abe_connect_dmareq_ping_pong_port(abe_port_id id, abe_data_format_t *f, abe_uint32 d, abe_uint32 s, abe_dma_t *a); - -/** -* @fn abe_connect_serial_port() -* -* Operations : enables the data echanges between a McBSP and an ATC buffer in -* DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz -* voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the -* abe_write_port API. -* -* Parameters : -* id: port name -* f : data format -* i : peripheral ID (McBSP #1, #2, #3) -* -* @see ABE_API.h -*/ -void abe_connect_serial_port(abe_port_id id, abe_data_format_t *f, abe_mcbsp_id i); - -/** -* @fn abe_connect_slimbus_port() -* -* Operations : enables the data echanges between 1/2 SB and an ATC buffers in -* DMEM. -* -* Parameters : -* id: port name -* f : data format -* i : peripheral ID (McBSP #1, #2, #3) -* j : peripheral ID (McBSP #1, #2, #3) -* -* @see ABE_API.h -*/ -void abe_connect_slimbus_port(abe_port_id id, abe_data_format_t *f, - abe_slimbus_id sb_port1, abe_slimbus_id sb_port2); +/** + * abe_set_ping_pong_buffer + * @port: ABE port ID + * @n_bytes: Size of Ping/Pong buffer + * + * Updates the next ping-pong buffer with "size" bytes copied from the + * host processor. This API notifies the FW that the data transfer is done. + */ +abehal_status abe_set_ping_pong_buffer (u32 port, u32 n_bytes); -/* - * ABE_WRITE_GAIN - * - * Parameter : - * port : name of the port (VX_DL_PORT, MM_DL_PORT, MM_EXT_DL_PORT, TONES_DL_PORT, …); - * dig_gain_port pointer to returned port gain and time constant - * - * Operations : - * saves the gain data in the local HAL-L0 table of gains in native format. - * Translate the gain to the AE-FW format and load it in CMEM +/** + * abe_read_next_ping_pong_buffer + * @port: ABE portID + * @p: Next buffer address (pointer) + * @n: Next buffer size (pointer) * - * Return value : - * error code in case the gain_id is not compatible with the current OPP value. + * Tell the next base address of the next ping_pong Buffer and its size */ +abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n); -void abe_write_gain(abe_gain_id id, abe_gain_t f_g, abe_ramp_t f_ramp, abe_port_id p); +/** + * abe_init_ping_pong_buffer + * @id: ABE port ID + * @size_bytes:size of the ping pong + * @n_buffers:number of buffers (2 = ping/pong) + * @p:returned address of the ping-pong list of base address (byte offset + from DMEM start) + * + * Computes the base address of the ping_pong buffers + */ +abehal_status abe_init_ping_pong_buffer (u32 id, u32 size_bytes, u32 n_buffers, u32 *p); -/* - * ABE_WRITE_EQUALIZER - * - * Parameter : - * Id : name of the equalizer - * Param : equalizer coefficients - * - * Operations : - * Load the coefficients in CMEM. This API can be called when the corresponding equalizer - * is not activated. After reloading the firmware the default coefficients corresponds to - * "no equalizer feature". Loading all coefficients with zeroes disables the feature. +/** + * abe_plug_subroutine + * @id: returned sequence index after plugging a new subroutine + * @f: subroutine address to be inserted + * @n: number of parameters of this subroutine + * @params: pointer on parameters * - * Return value : - * None. + * register a list of subroutines for call-back purpose */ -void abe_write_equalizer(abe_equ_id id, abe_equ_t *param); +abehal_status abe_plug_subroutine (u32 *id, abe_subroutine2 f, u32 n, u32* params); -/* - * ABE_SELECT_MAIN_PORT - * - * Parameter : - * id : audio port name - * Operations : - * tells the FW which is the reference stream for adjusting the processing on 23/24/25 slots +/** + * abe_set_sequence_time_accuracy + * @fast: fast counter + * @slow: slow counter * - * Return value : - * None. */ -void abe_select_main_port(abe_port_id id); +abehal_status abe_set_sequence_time_accuracy (u32 fast, u32 slow); -/* - * ABE_WRITE_ASRC - * - * Parameter : - * Id : name of the asrc - * param : drift value t compensate - * - * Operations : - * Load the drift coefficients in FW memory. This API can be called when the corresponding - * ASRC is not activated. After reloading the firmware the default coefficients corresponds - * to "no ASRC activated". Loading the drift value with zero disables the feature. +/** + * abe_reset_port + * @id: ABE port ID * - * Return value : - * None. + * stop the port activity and reload default parameters on the associated + * processing features. + * Clears the internal AE buffers. */ -void abe_write_asrc(abe_asrc_id id, abe_drift_t param); -void abe_set_asrc_drift_control(abe_asrc_id id, abe_uint32 f); +abehal_status abe_reset_port (u32 id); -/* - * ABE_WRITE_APS - * - * Parameter : - * Id : name of the aps filter - * param : table of filter coefficients - * - * Operations : - * Load the filters and thresholds coefficients in FW memory. This API can be called when - * the corresponding APS is not activated. After reloading the firmware the default coefficients - * corresponds to "no APS activated". Loading all the coefficients value with zero disables - * the feature. +/** + * abe_read_remaining_data + * @id: ABE port_ID + * @n: size pointer to the remaining number of 32bits words * - * Return value : - * None. + * computes the remaining amount of data in the buffer. */ -void abe_write_aps(abe_aps_id id, abe_aps_t *param); +abehal_status abe_read_remaining_data (u32 port, u32 *n); -/* - * ABE_WRITE_MIXER - * - * Parameter : - * Id : name of the mixer - * param : list of input gains of the mixer - * p : list of ports corresponding to the above gains - * - * Operations : - * Load the gain coefficients in FW memory. This API can be called when the corresponding - * MIXER is not activated. After reloading the firmware the default coefficients corresponds - * to "all input and output mixer's gain in mute state". A mixer is disabled with a network - * reconfiguration corresponding to an OPP value. +/** + * abe_disable_data_transfer + * @id: ABE port id * - * Return value : - * None. + * disables the ATC descriptor and stop IO/port activities + * disable the IO task (@f = 0) + * clear ATC DMEM buffer, ATC enabled */ -void abe_write_mixer(abe_mixer_id id, abe_gain_t g, abe_ramp_t ramp, abe_port_id p); +abehal_status abe_disable_data_transfer (u32 id); -/* - * ABE_SET_ROUTER_CONFIGURATION - * - * Parameter : - * Id : name of the router - * Conf : id of the configuration - * param : list of output index of the route - * - * Operations : - * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) and - * PORT1/2 (2 stereo ports). Each sample will be individually stored in an intermediate - * table of 10 elements. The intermediate table is used to route the samples to - * three directions : REC1 mixer, 2 EANC DMIC source of filtering and MM recording audio path. - * For example, a use case consisting in AMIC used for uplink voice communication, DMIC 0,1,2,3 - * used for multimedia recording, , DMIC 5 used for EANC filter, DMIC 4 used for the feedback channel, - * will be implemented with the following routing table index list : - * [3, 2 , 1, 0, 0, 0 (two dummy indexes to data that will not be on MM_UL), 4, 5, 7, 6] +/** + * abe_enable_data_transfer + * @ip: ABE port id * - * Return value : - * None. + * enables the ATC descriptor + * reset ATC pointers + * enable the IO task (@f <> 0) */ -void abe_set_router_configuration(abe_router_id id, abe_uint32 configuration, abe_router_t *param); +abehal_status abe_enable_data_transfer (u32 id); -/* - * ABE_READ_DEBUG_TRACE - * - * Parameter : - * data destination pointer - * max number of data read - * - * Operations : - * reads the AE circular data pointer holding pairs of debug data+timestamps, and store - * the pairs in linear addressing to the parameter pointer. Stops the copy when the max - * parameter is reached or when the FIFO is empty. +/** + * abe_set_dmic_filter + * @d: DMIC decimation ratio : 16/25/32/40 * - * Return value : - * None. + * Loads in CMEM a specific list of coefficients depending on the DMIC sampling + * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator + * roll-off at 20kHz. + * The default table is loaded with the DMIC 2.4MHz recommended configuration. */ -void abe_read_debug_trace(abe_uint32 *data, abe_uint32 *n); +abehal_status abe_set_dmic_filter (u32 d); -/* - * ABE_READ_DEBUG_TRACE - * - * Parameter : - * data destination pointer - * max number of data read - * - * Operations : - * reads the AE circular data pointer holding pairs of debug data+timestamps, and store - * the pairs in linear addressing to the parameter pointer. Stops the copy when the max - * parameter is reached or when the FIFO is empty. - * - * Return value : - * None. +/** + * abe_connect_cbpr_dmareq_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @a: returned pointer to the base address of the CBPr register and number of + * samples to exchange during a DMA_request. + * + * enables the data echange between a DMA and the ABE through the + * CBPr registers of AESS. */ -void abe_read_debug_trace(abe_uint32 *data, abe_uint32 *n); +abehal_status abe_connect_cbpr_dmareq_port (u32 id, abe_data_format_t *f, u32 d, + abe_dma_t *returned_dma_t); -/* - * ABE_CONNECT_DEBUG_TRACE +/** + * abe_connect_dmareq_ping_pong_port + * @id: port name + * @f: desired data format + * @d: desired dma_request line (0..7) + * @s: half-buffer (ping) size + * @a: returned pointer to the base address of the ping-pong buffer and number + * of samples to exchange during a DMA_request. + * + * enables the data echanges between a DMA and a direct access to + * the DMEM memory of ABE. On each dma_request activation the DMA will exchange + * "s" bytes and switch to the "pong" buffer for a new buffer exchange. + */ +abehal_status abe_connect_dmareq_ping_pong_port (u32 id, abe_data_format_t *f, + u32 d, u32 s, abe_dma_t *returned_dma_t); + +/** + * abe_connect_irq_ping_pong_port + * @id: port name + * @f: desired data format + * @I: index of the call-back subroutine to call + * @s: half-buffer (ping) size + * @p: returned base address of the first (ping) buffer) + * + * enables the data echanges between a direct access to the DMEM + * memory of ABE using cache flush. On each IRQ activation a subroutine + * registered with "abe_plug_subroutine" will be called. This subroutine + * will generate an amount of samples, send them to DMEM memory and call + * "abe_set_ping_pong_buffer" to notify the new amount of samples in the + * pong buffer. + */ +abehal_status abe_connect_irq_ping_pong_port (u32 id, abe_data_format_t *f, + u32 subroutine_id, u32 size, + u32 *sink, u32 dsp_mcu_flag); + +/** + * abe_connect_serial_port() + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * + * Operations : enables the data echanges between a McBSP and an ATC buffer in + * DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz + * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the + * abe_write_port API. + */ +abehal_status abe_connect_serial_port (u32 id, abe_data_format_t *f, u32 mcbsp_id); + +/** + * abe_connect_slimbus_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between 1/2 SB and an ATC buffers in + * DMEM. + */ +abehal_status abe_connect_slimbus_port (u32 id, abe_data_format_t *f, + u32 sb_port1, u32 sb_port2); + +/** + * abe_connect_tdm_port + * @id: port name + * @f: data format + * @i: peripheral ID (McBSP #1, #2, #3) + * @j: peripheral ID (McBSP #1, #2, #3) + * + * enables the data echanges between TDM McBSP ATC buffers in + * DMEM and 1/2 SMEM buffers + */ +abehal_status abe_connect_tdm_port (u32 id, abe_data_format_t *f, u32 mcbsp_id); + +/** + * abe_read_port_address + * @dma: output pointer to the DMA iteration and data destination pointer * - * Parameter : - * pointer to the DMEM trace buffer + * This API returns the address of the DMA register used on this audio port. + * Depending on the protocol being used, adds the base address offset L3 + * (DMA) or MPU (ARM) + */ +abehal_status abe_read_port_address (u32 port, abe_dma_t *dma2); + +/** + * abe_write_equalizer + * @id: name of the equalizer + * @param : equalizer coefficients * - * Operations : - * returns the address and size of the real-time debug trace buffer, - * the content of which will vary from one firmware release to an other + * Load the coefficients in CMEM. + */ +abehal_status abe_write_equalizer (u32 id, abe_equ_t *param); + +/** + * abe_write_asrc + * @id: name of the port + * @param: drift value to compensate [ppm] + * + * Load the drift variables to the FW memory. This API can be called only + * when the corresponding port has been already opened and the ASRC has + * been correctly initialized with API abe_init_asrc_... If this API is + * used such that the drift has been changed from positive to negative drift + * or vice versa, there will be click in the output signal. Loading the drift + * value with zero disables the feature. + */ +abehal_status abe_write_asrc (u32 port, s32 dppm); + +/** + * abe_write_aps + * @id: name of the aps filter + * @param: table of filter coefficients + * + * Load the filters and thresholds coefficients in FW memory. This API + * can be called when the corresponding APS is not activated. After + * reloading the firmware the default coefficients corresponds to "no APS + * activated". + * Loading all the coefficients value with zero disables the feature. + */ +abehal_status abe_write_aps (u32 id, abe_aps_t *param); + +/** + * abe_write_mixer + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's gain + * in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_gain (u32 id, u32 f_g, u32 ramp, u32 p); + +/** + * abe_write_mixer + * @id: name of the mixer + * @param: input gains and delay ramp of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_write_mixer (u32 id, u32 f_g, u32 f_ramp, u32 p); + +/** + * abe_read_gain + * @id: name of the mixer + * @param: list of input gains of the mixer + * @p: list of port corresponding to the above gains * - * Return value : - * None. */ +abehal_status abe_read_gain (u32 id, u32 *f_g, u32 p); -void abe_connect_debug_trace(abe_dma_t *a); +/** + * abe_read_mixer + * @id: name of the mixer + * @param: gains of the mixer + * @p: port corresponding to the above gains + * + * Load the gain coefficients in FW memory. This API can be called when + * the corresponding MIXER is not activated. After reloading the firmware + * the default coefficients corresponds to "all input and output mixer's + * gain in mute state". A mixer is disabled with a network reconfiguration + * corresponding to an OPP value. + */ +abehal_status abe_read_mixer (u32 id, u32 *f_g, u32 p); +/** + * abe_set_router_configuration + * @Id: name of the router + * @Conf: id of the configuration + * @param: list of output index of the route + * + * The uplink router takes its input from DMIC (6 samples), AMIC (2 samples) + * and PORT1/2 (2 stereo ports). Each sample will be individually stored in + * an intermediate table of 10 elements. The intermediate table is used to + * route the samples to three directions : REC1 mixer, 2 EANC DMIC source of + * filtering and MM recording audio path. + */ +abehal_status abe_set_router_configuration (u32 id, u32 k, u32 *param); -/* - * ABE_SET_DEBUG_TRACE +/** + * abe_select_data_source + * @@@ + */ +abehal_status abe_select_data_source (u32 port_id, u32 smem_source); + +/** + * ABE_READ_DEBUG_TRACE * - * Parameter : - * debug ID from a list to be defined + * Parameter : + * data destination pointer + * max number of data read * - * Operations : - * load a mask which filters the debug trace to dedicated types of data + * Operations : + * reads the AE circular data pointer holding pairs of debug data+ + * timestamps, and store the pairs in linear addressing to the parameter + * pointer. Stops the copy when the max parameter is reached or when the + * FIFO is empty. * - * Return value : - * None. + * Return value : + * None. */ -void abe_set_debug_trace(abe_dbg_t debug); +abehal_status abe_read_debug_trace (u32 *data, u32 *n); -/* - * ABE_ENABLE_TEST_PATTERN +/** + * abe_connect_debug_trace + * @dma2:pointer to the DMEM trace buffer * - * Parameter : + * returns the address and size of the real-time debug trace buffer, + * the content of which will vary from one firmware release to an other + */ +abehal_status abe_connect_debug_trace (abe_dma_t *dma2); + +/** + * abe_set_debug_trace + * @debug: debug ID from a list to be defined * - * Operations : + * load a mask which filters the debug trace to dedicated types of data + */ +abehal_status abe_set_debug_trace (abe_dbg_t debug); + +/** + * abe_remote_debugger_interface * - * Return value : - * None. + * interpretation of the UART stream from the remote debugger commands. + * The commands consist in setting break points, loading parameter */ +abehal_status abe_remote_debugger_interface (u32 n, u8 *p); -void abe_enable_test_pattern(abe_patched_pattern_id smem_id, abe_uint32 on_off); +/** + * abe_enable_test_pattern + * + */ +abehal_status abe_enable_test_pattern (u32 smem_id, u32 on_off); -#ifdef __cplusplus -} -#endif -#endif /* _ABE_API_H_ */ +#endif/* _ABE_API_H_ */ diff --git a/sound/soc/omap/abe/abe_cm_addr.h b/sound/soc/omap/abe/abe_cm_addr.h index 71edea36a338..1096e28ab9a8 100644 --- a/sound/soc/omap/abe/abe_cm_addr.h +++ b/sound/soc/omap/abe/abe_cm_addr.h @@ -1,354 +1,373 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== */ - #ifndef _ABE_CM_ADDR_H_ #define _ABE_CM_ADDR_H_ -#define init_CM_ADDR 0 -#define init_CM_ADDR_END 304 -#define init_CM_sizeof 305 +#define init_CM_ADDR 0 +#define init_CM_ADDR_END 303 +#define init_CM_sizeof 304 + +#define C_Data_LSB_2_ADDR 304 +#define C_Data_LSB_2_ADDR_END 304 +#define C_Data_LSB_2_sizeof 1 + +#define C_1_Alpha_ADDR 305 +#define C_1_Alpha_ADDR_END 322 +#define C_1_Alpha_sizeof 18 + +#define C_Alpha_ADDR 323 +#define C_Alpha_ADDR_END 340 +#define C_Alpha_sizeof 18 -#define C_Data_LSB_2_ADDR 305 -#define C_Data_LSB_2_ADDR_END 305 -#define C_Data_LSB_2_sizeof 1 +#define C_GainsWRamp_ADDR 341 +#define C_GainsWRamp_ADDR_END 354 +#define C_GainsWRamp_sizeof 14 -#define C_1_Alpha_ADDR 306 -#define C_1_Alpha_ADDR_END 323 -#define C_1_Alpha_sizeof 18 +#define C_Gains_DL1M_ADDR 355 +#define C_Gains_DL1M_ADDR_END 358 +#define C_Gains_DL1M_sizeof 4 -#define C_Alpha_ADDR 324 -#define C_Alpha_ADDR_END 341 -#define C_Alpha_sizeof 18 +#define C_Gains_DL2M_ADDR 359 +#define C_Gains_DL2M_ADDR_END 362 +#define C_Gains_DL2M_sizeof 4 -#define C_GainsWRamp_ADDR 342 -#define C_GainsWRamp_ADDR_END 355 -#define C_GainsWRamp_sizeof 14 +#define C_Gains_EchoM_ADDR 363 +#define C_Gains_EchoM_ADDR_END 364 +#define C_Gains_EchoM_sizeof 2 -#define C_Gains_DL1M_ADDR 356 -#define C_Gains_DL1M_ADDR_END 359 -#define C_Gains_DL1M_sizeof 4 +#define C_Gains_SDTM_ADDR 365 +#define C_Gains_SDTM_ADDR_END 366 +#define C_Gains_SDTM_sizeof 2 -#define C_Gains_DL2M_ADDR 360 -#define C_Gains_DL2M_ADDR_END 363 -#define C_Gains_DL2M_sizeof 4 +#define C_Gains_VxRecM_ADDR 367 +#define C_Gains_VxRecM_ADDR_END 370 +#define C_Gains_VxRecM_sizeof 4 -#define C_Gains_EchoM_ADDR 364 -#define C_Gains_EchoM_ADDR_END 365 -#define C_Gains_EchoM_sizeof 2 +#define C_Gains_ULM_ADDR 371 +#define C_Gains_ULM_ADDR_END 374 +#define C_Gains_ULM_sizeof 4 -#define C_Gains_SDTM_ADDR 366 -#define C_Gains_SDTM_ADDR_END 367 -#define C_Gains_SDTM_sizeof 2 +#define C_Gains_unused_ADDR 375 +#define C_Gains_unused_ADDR_END 376 +#define C_Gains_unused_sizeof 2 -#define C_Gains_VxRecM_ADDR 368 -#define C_Gains_VxRecM_ADDR_END 371 -#define C_Gains_VxRecM_sizeof 4 +#define C_SDT_Coefs_ADDR 377 +#define C_SDT_Coefs_ADDR_END 385 +#define C_SDT_Coefs_sizeof 9 -#define C_Gains_ULM_ADDR 372 -#define C_Gains_ULM_ADDR_END 375 -#define C_Gains_ULM_sizeof 4 +#define C_CoefASRC1_VX_ADDR 386 +#define C_CoefASRC1_VX_ADDR_END 404 +#define C_CoefASRC1_VX_sizeof 19 -#define C_Gains_unused_ADDR 376 -#define C_Gains_unused_ADDR_END 377 -#define C_Gains_unused_sizeof 2 +#define C_CoefASRC2_VX_ADDR 405 +#define C_CoefASRC2_VX_ADDR_END 423 +#define C_CoefASRC2_VX_sizeof 19 -#define C_SDT_Coefs_ADDR 378 -#define C_SDT_Coefs_ADDR_END 386 -#define C_SDT_Coefs_sizeof 9 +#define C_CoefASRC3_VX_ADDR 424 +#define C_CoefASRC3_VX_ADDR_END 442 +#define C_CoefASRC3_VX_sizeof 19 -#define C_CoefASRC1_VX_ADDR 387 -#define C_CoefASRC1_VX_ADDR_END 405 -#define C_CoefASRC1_VX_sizeof 19 +#define C_CoefASRC4_VX_ADDR 443 +#define C_CoefASRC4_VX_ADDR_END 461 +#define C_CoefASRC4_VX_sizeof 19 -#define C_CoefASRC2_VX_ADDR 406 -#define C_CoefASRC2_VX_ADDR_END 424 -#define C_CoefASRC2_VX_sizeof 19 +#define C_CoefASRC5_VX_ADDR 462 +#define C_CoefASRC5_VX_ADDR_END 480 +#define C_CoefASRC5_VX_sizeof 19 -#define C_CoefASRC3_VX_ADDR 425 -#define C_CoefASRC3_VX_ADDR_END 443 -#define C_CoefASRC3_VX_sizeof 19 +#define C_CoefASRC6_VX_ADDR 481 +#define C_CoefASRC6_VX_ADDR_END 499 +#define C_CoefASRC6_VX_sizeof 19 -#define C_CoefASRC4_VX_ADDR 444 -#define C_CoefASRC4_VX_ADDR_END 462 -#define C_CoefASRC4_VX_sizeof 19 +#define C_CoefASRC7_VX_ADDR 500 +#define C_CoefASRC7_VX_ADDR_END 518 +#define C_CoefASRC7_VX_sizeof 19 -#define C_CoefASRC5_VX_ADDR 463 -#define C_CoefASRC5_VX_ADDR_END 481 -#define C_CoefASRC5_VX_sizeof 19 +#define C_CoefASRC8_VX_ADDR 519 +#define C_CoefASRC8_VX_ADDR_END 537 +#define C_CoefASRC8_VX_sizeof 19 -#define C_CoefASRC6_VX_ADDR 482 -#define C_CoefASRC6_VX_ADDR_END 500 -#define C_CoefASRC6_VX_sizeof 19 +#define C_CoefASRC9_VX_ADDR 538 +#define C_CoefASRC9_VX_ADDR_END 556 +#define C_CoefASRC9_VX_sizeof 19 -#define C_CoefASRC7_VX_ADDR 501 -#define C_CoefASRC7_VX_ADDR_END 519 -#define C_CoefASRC7_VX_sizeof 19 +#define C_CoefASRC10_VX_ADDR 557 +#define C_CoefASRC10_VX_ADDR_END 575 +#define C_CoefASRC10_VX_sizeof 19 -#define C_CoefASRC8_VX_ADDR 520 -#define C_CoefASRC8_VX_ADDR_END 538 -#define C_CoefASRC8_VX_sizeof 19 +#define C_CoefASRC11_VX_ADDR 576 +#define C_CoefASRC11_VX_ADDR_END 594 +#define C_CoefASRC11_VX_sizeof 19 -#define C_CoefASRC9_VX_ADDR 539 -#define C_CoefASRC9_VX_ADDR_END 557 -#define C_CoefASRC9_VX_sizeof 19 +#define C_CoefASRC12_VX_ADDR 595 +#define C_CoefASRC12_VX_ADDR_END 613 +#define C_CoefASRC12_VX_sizeof 19 -#define C_CoefASRC10_VX_ADDR 558 -#define C_CoefASRC10_VX_ADDR_END 576 -#define C_CoefASRC10_VX_sizeof 19 +#define C_CoefASRC13_VX_ADDR 614 +#define C_CoefASRC13_VX_ADDR_END 632 +#define C_CoefASRC13_VX_sizeof 19 -#define C_CoefASRC11_VX_ADDR 577 -#define C_CoefASRC11_VX_ADDR_END 595 -#define C_CoefASRC11_VX_sizeof 19 +#define C_CoefASRC14_VX_ADDR 633 +#define C_CoefASRC14_VX_ADDR_END 651 +#define C_CoefASRC14_VX_sizeof 19 -#define C_CoefASRC12_VX_ADDR 596 -#define C_CoefASRC12_VX_ADDR_END 614 -#define C_CoefASRC12_VX_sizeof 19 +#define C_CoefASRC15_VX_ADDR 652 +#define C_CoefASRC15_VX_ADDR_END 670 +#define C_CoefASRC15_VX_sizeof 19 -#define C_CoefASRC13_VX_ADDR 615 -#define C_CoefASRC13_VX_ADDR_END 633 -#define C_CoefASRC13_VX_sizeof 19 +#define C_CoefASRC16_VX_ADDR 671 +#define C_CoefASRC16_VX_ADDR_END 689 +#define C_CoefASRC16_VX_sizeof 19 -#define C_CoefASRC14_VX_ADDR 634 -#define C_CoefASRC14_VX_ADDR_END 652 -#define C_CoefASRC14_VX_sizeof 19 +#define C_AlphaCurrent_UL_VX_ADDR 690 +#define C_AlphaCurrent_UL_VX_ADDR_END 690 +#define C_AlphaCurrent_UL_VX_sizeof 1 -#define C_CoefASRC15_VX_ADDR 653 -#define C_CoefASRC15_VX_ADDR_END 671 -#define C_CoefASRC15_VX_sizeof 19 +#define C_BetaCurrent_UL_VX_ADDR 691 +#define C_BetaCurrent_UL_VX_ADDR_END 691 +#define C_BetaCurrent_UL_VX_sizeof 1 -#define C_CoefASRC16_VX_ADDR 672 -#define C_CoefASRC16_VX_ADDR_END 690 -#define C_CoefASRC16_VX_sizeof 19 +#define C_AlphaCurrent_DL_VX_ADDR 692 +#define C_AlphaCurrent_DL_VX_ADDR_END 692 +#define C_AlphaCurrent_DL_VX_sizeof 1 -#define C_AlphaCurrent_UL_VX_ADDR 691 -#define C_AlphaCurrent_UL_VX_ADDR_END 691 -#define C_AlphaCurrent_UL_VX_sizeof 1 +#define C_BetaCurrent_DL_VX_ADDR 693 +#define C_BetaCurrent_DL_VX_ADDR_END 693 +#define C_BetaCurrent_DL_VX_sizeof 1 -#define C_BetaCurrent_UL_VX_ADDR 692 -#define C_BetaCurrent_UL_VX_ADDR_END 692 -#define C_BetaCurrent_UL_VX_sizeof 1 +#define C_CoefASRC1_DL_MM_ADDR 694 +#define C_CoefASRC1_DL_MM_ADDR_END 711 +#define C_CoefASRC1_DL_MM_sizeof 18 -#define C_AlphaCurrent_DL_VX_ADDR 693 -#define C_AlphaCurrent_DL_VX_ADDR_END 693 -#define C_AlphaCurrent_DL_VX_sizeof 1 +#define C_CoefASRC2_DL_MM_ADDR 712 +#define C_CoefASRC2_DL_MM_ADDR_END 729 +#define C_CoefASRC2_DL_MM_sizeof 18 -#define C_BetaCurrent_DL_VX_ADDR 694 -#define C_BetaCurrent_DL_VX_ADDR_END 694 -#define C_BetaCurrent_DL_VX_sizeof 1 +#define C_CoefASRC3_DL_MM_ADDR 730 +#define C_CoefASRC3_DL_MM_ADDR_END 747 +#define C_CoefASRC3_DL_MM_sizeof 18 -#define C_CoefASRC1_DL_MM_ADDR 695 -#define C_CoefASRC1_DL_MM_ADDR_END 712 -#define C_CoefASRC1_DL_MM_sizeof 18 +#define C_CoefASRC4_DL_MM_ADDR 748 +#define C_CoefASRC4_DL_MM_ADDR_END 765 +#define C_CoefASRC4_DL_MM_sizeof 18 -#define C_CoefASRC2_DL_MM_ADDR 713 -#define C_CoefASRC2_DL_MM_ADDR_END 730 -#define C_CoefASRC2_DL_MM_sizeof 18 +#define C_CoefASRC5_DL_MM_ADDR 766 +#define C_CoefASRC5_DL_MM_ADDR_END 783 +#define C_CoefASRC5_DL_MM_sizeof 18 -#define C_CoefASRC3_DL_MM_ADDR 731 -#define C_CoefASRC3_DL_MM_ADDR_END 748 -#define C_CoefASRC3_DL_MM_sizeof 18 +#define C_CoefASRC6_DL_MM_ADDR 784 +#define C_CoefASRC6_DL_MM_ADDR_END 801 +#define C_CoefASRC6_DL_MM_sizeof 18 -#define C_CoefASRC4_DL_MM_ADDR 749 -#define C_CoefASRC4_DL_MM_ADDR_END 766 -#define C_CoefASRC4_DL_MM_sizeof 18 +#define C_CoefASRC7_DL_MM_ADDR 802 +#define C_CoefASRC7_DL_MM_ADDR_END 819 +#define C_CoefASRC7_DL_MM_sizeof 18 -#define C_CoefASRC5_DL_MM_ADDR 767 -#define C_CoefASRC5_DL_MM_ADDR_END 784 -#define C_CoefASRC5_DL_MM_sizeof 18 +#define C_CoefASRC8_DL_MM_ADDR 820 +#define C_CoefASRC8_DL_MM_ADDR_END 837 +#define C_CoefASRC8_DL_MM_sizeof 18 -#define C_CoefASRC6_DL_MM_ADDR 785 -#define C_CoefASRC6_DL_MM_ADDR_END 802 -#define C_CoefASRC6_DL_MM_sizeof 18 +#define C_CoefASRC9_DL_MM_ADDR 838 +#define C_CoefASRC9_DL_MM_ADDR_END 855 +#define C_CoefASRC9_DL_MM_sizeof 18 -#define C_CoefASRC7_DL_MM_ADDR 803 -#define C_CoefASRC7_DL_MM_ADDR_END 820 -#define C_CoefASRC7_DL_MM_sizeof 18 +#define C_CoefASRC10_DL_MM_ADDR 856 +#define C_CoefASRC10_DL_MM_ADDR_END 873 +#define C_CoefASRC10_DL_MM_sizeof 18 -#define C_CoefASRC8_DL_MM_ADDR 821 -#define C_CoefASRC8_DL_MM_ADDR_END 838 -#define C_CoefASRC8_DL_MM_sizeof 18 +#define C_CoefASRC11_DL_MM_ADDR 874 +#define C_CoefASRC11_DL_MM_ADDR_END 891 +#define C_CoefASRC11_DL_MM_sizeof 18 -#define C_CoefASRC9_DL_MM_ADDR 839 -#define C_CoefASRC9_DL_MM_ADDR_END 856 -#define C_CoefASRC9_DL_MM_sizeof 18 +#define C_CoefASRC12_DL_MM_ADDR 892 +#define C_CoefASRC12_DL_MM_ADDR_END 909 +#define C_CoefASRC12_DL_MM_sizeof 18 -#define C_CoefASRC10_DL_MM_ADDR 857 -#define C_CoefASRC10_DL_MM_ADDR_END 874 -#define C_CoefASRC10_DL_MM_sizeof 18 +#define C_CoefASRC13_DL_MM_ADDR 910 +#define C_CoefASRC13_DL_MM_ADDR_END 927 +#define C_CoefASRC13_DL_MM_sizeof 18 -#define C_CoefASRC11_DL_MM_ADDR 875 -#define C_CoefASRC11_DL_MM_ADDR_END 892 -#define C_CoefASRC11_DL_MM_sizeof 18 +#define C_CoefASRC14_DL_MM_ADDR 928 +#define C_CoefASRC14_DL_MM_ADDR_END 945 +#define C_CoefASRC14_DL_MM_sizeof 18 -#define C_CoefASRC12_DL_MM_ADDR 893 -#define C_CoefASRC12_DL_MM_ADDR_END 910 -#define C_CoefASRC12_DL_MM_sizeof 18 +#define C_CoefASRC15_DL_MM_ADDR 946 +#define C_CoefASRC15_DL_MM_ADDR_END 963 +#define C_CoefASRC15_DL_MM_sizeof 18 -#define C_CoefASRC13_DL_MM_ADDR 911 -#define C_CoefASRC13_DL_MM_ADDR_END 928 -#define C_CoefASRC13_DL_MM_sizeof 18 +#define C_CoefASRC16_DL_MM_ADDR 964 +#define C_CoefASRC16_DL_MM_ADDR_END 981 +#define C_CoefASRC16_DL_MM_sizeof 18 -#define C_CoefASRC14_DL_MM_ADDR 929 -#define C_CoefASRC14_DL_MM_ADDR_END 946 -#define C_CoefASRC14_DL_MM_sizeof 18 +#define C_AlphaCurrent_DL_MM_ADDR 982 +#define C_AlphaCurrent_DL_MM_ADDR_END 982 +#define C_AlphaCurrent_DL_MM_sizeof 1 -#define C_CoefASRC15_DL_MM_ADDR 947 -#define C_CoefASRC15_DL_MM_ADDR_END 964 -#define C_CoefASRC15_DL_MM_sizeof 18 +#define C_BetaCurrent_DL_MM_ADDR 983 +#define C_BetaCurrent_DL_MM_ADDR_END 983 +#define C_BetaCurrent_DL_MM_sizeof 1 -#define C_CoefASRC16_DL_MM_ADDR 965 -#define C_CoefASRC16_DL_MM_ADDR_END 982 -#define C_CoefASRC16_DL_MM_sizeof 18 +#define C_DL2_L_Coefs_ADDR 984 +#define C_DL2_L_Coefs_ADDR_END 1008 +#define C_DL2_L_Coefs_sizeof 25 -#define C_AlphaCurrent_DL_MM_ADDR 983 -#define C_AlphaCurrent_DL_MM_ADDR_END 983 -#define C_AlphaCurrent_DL_MM_sizeof 1 +#define C_DL2_R_Coefs_ADDR 1009 +#define C_DL2_R_Coefs_ADDR_END 1033 +#define C_DL2_R_Coefs_sizeof 25 -#define C_BetaCurrent_DL_MM_ADDR 984 -#define C_BetaCurrent_DL_MM_ADDR_END 984 -#define C_BetaCurrent_DL_MM_sizeof 1 +#define C_DL1_Coefs_ADDR 1034 +#define C_DL1_Coefs_ADDR_END 1058 +#define C_DL1_Coefs_sizeof 25 -#define C_DL2_L_Coefs_ADDR 985 -#define C_DL2_L_Coefs_ADDR_END 1009 -#define C_DL2_L_Coefs_sizeof 25 +#define C_SRC_3_LP_Coefs_ADDR 1059 +#define C_SRC_3_LP_Coefs_ADDR_END 1069 +#define C_SRC_3_LP_Coefs_sizeof 11 -#define C_DL2_R_Coefs_ADDR 1010 -#define C_DL2_R_Coefs_ADDR_END 1034 -#define C_DL2_R_Coefs_sizeof 25 +#define C_SRC_3_LP_GAIN_Coefs_ADDR 1070 +#define C_SRC_3_LP_GAIN_Coefs_ADDR_END 1080 +#define C_SRC_3_LP_GAIN_Coefs_sizeof 11 -#define C_DL1_Coefs_ADDR 1035 -#define C_DL1_Coefs_ADDR_END 1059 -#define C_DL1_Coefs_sizeof 25 +#define C_SRC_3_HP_Coefs_ADDR 1081 +#define C_SRC_3_HP_Coefs_ADDR_END 1085 +#define C_SRC_3_HP_Coefs_sizeof 5 -#define C_SRC_3_LP_Coefs_ADDR 1060 -#define C_SRC_3_LP_Coefs_ADDR_END 1070 -#define C_SRC_3_LP_Coefs_sizeof 11 +#define C_SRC_6_LP_Coefs_ADDR 1086 +#define C_SRC_6_LP_Coefs_ADDR_END 1096 +#define C_SRC_6_LP_Coefs_sizeof 11 -#define C_SRC_3_LP_GAIN_Coefs_ADDR 1071 -#define C_SRC_3_LP_GAIN_Coefs_ADDR_END 1081 -#define C_SRC_3_LP_GAIN_Coefs_sizeof 11 +#define C_SRC_6_LP_GAIN_Coefs_ADDR 1097 +#define C_SRC_6_LP_GAIN_Coefs_ADDR_END 1107 +#define C_SRC_6_LP_GAIN_Coefs_sizeof 11 -#define C_SRC_3_HP_Coefs_ADDR 1082 -#define C_SRC_3_HP_Coefs_ADDR_END 1086 -#define C_SRC_3_HP_Coefs_sizeof 5 +#define C_SRC_6_HP_Coefs_ADDR 1108 +#define C_SRC_6_HP_Coefs_ADDR_END 1114 +#define C_SRC_6_HP_Coefs_sizeof 7 -#define C_SRC_6_LP_Coefs_ADDR 1087 -#define C_SRC_6_LP_Coefs_ADDR_END 1097 -#define C_SRC_6_LP_Coefs_sizeof 11 +#define C_EANC_WarpCoeffs_ADDR 1115 +#define C_EANC_WarpCoeffs_ADDR_END 1116 +#define C_EANC_WarpCoeffs_sizeof 2 -#define C_SRC_6_LP_GAIN_Coefs_ADDR 1098 -#define C_SRC_6_LP_GAIN_Coefs_ADDR_END 1108 -#define C_SRC_6_LP_GAIN_Coefs_sizeof 11 +#define C_EANC_FIRcoeffs_ADDR 1117 +#define C_EANC_FIRcoeffs_ADDR_END 1137 +#define C_EANC_FIRcoeffs_sizeof 21 -#define C_SRC_6_HP_Coefs_ADDR 1109 -#define C_SRC_6_HP_Coefs_ADDR_END 1115 -#define C_SRC_6_HP_Coefs_sizeof 7 +#define C_EANC_IIRcoeffs_ADDR 1138 +#define C_EANC_IIRcoeffs_ADDR_END 1154 +#define C_EANC_IIRcoeffs_sizeof 17 -#define C_EANC_WarpCoeffs_ADDR 1116 -#define C_EANC_WarpCoeffs_ADDR_END 1117 -#define C_EANC_WarpCoeffs_sizeof 2 +#define C_EANC_FIRcoeffs_2nd_ADDR 1155 +#define C_EANC_FIRcoeffs_2nd_ADDR_END 1175 +#define C_EANC_FIRcoeffs_2nd_sizeof 21 -#define C_EANC_FIRcoeffs_ADDR 1118 -#define C_EANC_FIRcoeffs_ADDR_END 1138 -#define C_EANC_FIRcoeffs_sizeof 21 +#define C_EANC_IIRcoeffs_2nd_ADDR 1176 +#define C_EANC_IIRcoeffs_2nd_ADDR_END 1192 +#define C_EANC_IIRcoeffs_2nd_sizeof 17 -#define C_EANC_IIRcoeffs_ADDR 1139 -#define C_EANC_IIRcoeffs_ADDR_END 1155 -#define C_EANC_IIRcoeffs_sizeof 17 +#define C_APS_DL1_coeffs1_ADDR 1193 +#define C_APS_DL1_coeffs1_ADDR_END 1201 +#define C_APS_DL1_coeffs1_sizeof 9 -#define C_EANC_FIRcoeffs_2nd_ADDR 1156 -#define C_EANC_FIRcoeffs_2nd_ADDR_END 1176 -#define C_EANC_FIRcoeffs_2nd_sizeof 21 +#define C_APS_DL1_M_coeffs2_ADDR 1202 +#define C_APS_DL1_M_coeffs2_ADDR_END 1204 +#define C_APS_DL1_M_coeffs2_sizeof 3 -#define C_EANC_IIRcoeffs_2nd_ADDR 1177 -#define C_EANC_IIRcoeffs_2nd_ADDR_END 1193 -#define C_EANC_IIRcoeffs_2nd_sizeof 17 +#define C_APS_DL1_C_coeffs2_ADDR 1205 +#define C_APS_DL1_C_coeffs2_ADDR_END 1207 +#define C_APS_DL1_C_coeffs2_sizeof 3 -#define C_APS_DL1_coeffs1_ADDR 1194 -#define C_APS_DL1_coeffs1_ADDR_END 1202 -#define C_APS_DL1_coeffs1_sizeof 9 +#define C_APS_DL2_L_coeffs1_ADDR 1208 +#define C_APS_DL2_L_coeffs1_ADDR_END 1216 +#define C_APS_DL2_L_coeffs1_sizeof 9 -#define C_APS_DL1_M_coeffs2_ADDR 1203 -#define C_APS_DL1_M_coeffs2_ADDR_END 1205 -#define C_APS_DL1_M_coeffs2_sizeof 3 +#define C_APS_DL2_R_coeffs1_ADDR 1217 +#define C_APS_DL2_R_coeffs1_ADDR_END 1225 +#define C_APS_DL2_R_coeffs1_sizeof 9 -#define C_APS_DL1_C_coeffs2_ADDR 1206 -#define C_APS_DL1_C_coeffs2_ADDR_END 1208 -#define C_APS_DL1_C_coeffs2_sizeof 3 +#define C_APS_DL2_L_M_coeffs2_ADDR 1226 +#define C_APS_DL2_L_M_coeffs2_ADDR_END 1228 +#define C_APS_DL2_L_M_coeffs2_sizeof 3 -#define C_APS_DL2_L_coeffs1_ADDR 1209 -#define C_APS_DL2_L_coeffs1_ADDR_END 1217 -#define C_APS_DL2_L_coeffs1_sizeof 9 +#define C_APS_DL2_R_M_coeffs2_ADDR 1229 +#define C_APS_DL2_R_M_coeffs2_ADDR_END 1231 +#define C_APS_DL2_R_M_coeffs2_sizeof 3 -#define C_APS_DL2_R_coeffs1_ADDR 1218 -#define C_APS_DL2_R_coeffs1_ADDR_END 1226 -#define C_APS_DL2_R_coeffs1_sizeof 9 +#define C_APS_DL2_L_C_coeffs2_ADDR 1232 +#define C_APS_DL2_L_C_coeffs2_ADDR_END 1234 +#define C_APS_DL2_L_C_coeffs2_sizeof 3 -#define C_APS_DL2_L_M_coeffs2_ADDR 1227 -#define C_APS_DL2_L_M_coeffs2_ADDR_END 1229 -#define C_APS_DL2_L_M_coeffs2_sizeof 3 +#define C_APS_DL2_R_C_coeffs2_ADDR 1235 +#define C_APS_DL2_R_C_coeffs2_ADDR_END 1237 +#define C_APS_DL2_R_C_coeffs2_sizeof 3 -#define C_APS_DL2_R_M_coeffs2_ADDR 1230 -#define C_APS_DL2_R_M_coeffs2_ADDR_END 1232 -#define C_APS_DL2_R_M_coeffs2_sizeof 3 +#define C_AlphaCurrent_ECHO_REF_ADDR 1238 +#define C_AlphaCurrent_ECHO_REF_ADDR_END 1238 +#define C_AlphaCurrent_ECHO_REF_sizeof 1 -#define C_APS_DL2_L_C_coeffs2_ADDR 1233 -#define C_APS_DL2_L_C_coeffs2_ADDR_END 1235 -#define C_APS_DL2_L_C_coeffs2_sizeof 3 +#define C_BetaCurrent_ECHO_REF_ADDR 1239 +#define C_BetaCurrent_ECHO_REF_ADDR_END 1239 +#define C_BetaCurrent_ECHO_REF_sizeof 1 -#define C_APS_DL2_R_C_coeffs2_ADDR 1236 -#define C_APS_DL2_R_C_coeffs2_ADDR_END 1238 -#define C_APS_DL2_R_C_coeffs2_sizeof 3 +#define C_APS_DL1_EQ_ADDR 1240 +#define C_APS_DL1_EQ_ADDR_END 1248 +#define C_APS_DL1_EQ_sizeof 9 -#define C_AlphaCurrent_ECHO_REF_ADDR 1239 -#define C_AlphaCurrent_ECHO_REF_ADDR_END 1239 -#define C_AlphaCurrent_ECHO_REF_sizeof 1 +#define C_APS_DL2_L_EQ_ADDR 1249 +#define C_APS_DL2_L_EQ_ADDR_END 1257 +#define C_APS_DL2_L_EQ_sizeof 9 -#define C_BetaCurrent_ECHO_REF_ADDR 1240 -#define C_BetaCurrent_ECHO_REF_ADDR_END 1240 -#define C_BetaCurrent_ECHO_REF_sizeof 1 +#define C_APS_DL2_R_EQ_ADDR 1258 +#define C_APS_DL2_R_EQ_ADDR_END 1266 +#define C_APS_DL2_R_EQ_sizeof 9 -#define C_APS_DL1_EQ_ADDR 1241 -#define C_APS_DL1_EQ_ADDR_END 1249 -#define C_APS_DL1_EQ_sizeof 9 +#define C_Vibra2_consts_ADDR 1267 +#define C_Vibra2_consts_ADDR_END 1270 +#define C_Vibra2_consts_sizeof 4 -#define C_APS_DL2_L_EQ_ADDR 1250 -#define C_APS_DL2_L_EQ_ADDR_END 1258 -#define C_APS_DL2_L_EQ_sizeof 9 +#define C_Vibra1_coeffs_ADDR 1271 +#define C_Vibra1_coeffs_ADDR_END 1281 +#define C_Vibra1_coeffs_sizeof 11 -#define C_APS_DL2_R_EQ_ADDR 1259 -#define C_APS_DL2_R_EQ_ADDR_END 1267 -#define C_APS_DL2_R_EQ_sizeof 9 +#define C_48_96_LP_Coefs_ADDR 1282 +#define C_48_96_LP_Coefs_ADDR_END 1296 +#define C_48_96_LP_Coefs_sizeof 15 -#define C_Vibra2_consts_ADDR 1268 -#define C_Vibra2_consts_ADDR_END 1271 -#define C_Vibra2_consts_sizeof 4 +#define C_98_48_LP_Coefs_ADDR 1297 +#define C_98_48_LP_Coefs_ADDR_END 1315 +#define C_98_48_LP_Coefs_sizeof 19 -#define C_Vibra1_coeffs_ADDR 1272 -#define C_Vibra1_coeffs_ADDR_END 1282 -#define C_Vibra1_coeffs_sizeof 11 +#define C_INPUT_SCALE_ADDR 1316 +#define C_INPUT_SCALE_ADDR_END 1316 +#define C_INPUT_SCALE_sizeof 1 -#define C_48_96_LP_Coefs_ADDR 1283 -#define C_48_96_LP_Coefs_ADDR_END 1297 -#define C_48_96_LP_Coefs_sizeof 15 +#define C_OUTPUT_SCALE_ADDR 1317 +#define C_OUTPUT_SCALE_ADDR_END 1317 +#define C_OUTPUT_SCALE_sizeof 1 -#define C_98_48_LP_Coefs_ADDR 1298 -#define C_98_48_LP_Coefs_ADDR_END 1316 -#define C_98_48_LP_Coefs_sizeof 19 +#define C_MUTE_SCALING_ADDR 1318 +#define C_MUTE_SCALING_ADDR_END 1318 +#define C_MUTE_SCALING_sizeof 1 -#define C_INPUT_SCALE_ADDR 1317 -#define C_INPUT_SCALE_ADDR_END 1317 -#define C_INPUT_SCALE_sizeof 1 +#define C_GAINS_0DB_ADDR 1319 +#define C_GAINS_0DB_ADDR_END 1320 +#define C_GAINS_0DB_sizeof 2 -#define C_OUTPUT_SCALE_ADDR 1318 -#define C_OUTPUT_SCALE_ADDR_END 1318 -#define C_OUTPUT_SCALE_sizeof 1 #endif /* _ABECM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_cof.h b/sound/soc/omap/abe/abe_cof.h index 7426208dee35..f33cf05348f9 100644 --- a/sound/soc/omap/abe/abe_cof.h +++ b/sound/soc/omap/abe/abe_cof.h @@ -1,31 +1,24 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. +/* ============================================================================= +* Texas Instruments OMAP(TM) Platform Software +* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. +* +* Use of this software is controlled by the terms and conditions found +* in the license agreement under which this software has been supplied. +* =========================================================================== */ +/** + * @file ABE_COF.H * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== - */ -const abe_int32 abe_dmic_40[C_98_48_LP_Coefs_sizeof] = { - -4119413, -192384, -341428, -348088, -151380, 151380, - 348088, 341428, 192384, 4119415, 1938156, -6935719, - 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 - }; + * 'ABE_COF.H' coefficients used to tune the firmware + * + * @path + * @rev 01.00 + * =========================================================================== */ -const abe_int32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { - -4119413, -192384, -341428, -348088, -151380, 151380, - 348088, 341428, 192384, 4119415, 1938156, -6935719, - 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 - }; +/* + * ABE CONST AREA FOR DMIC DECIMATION FILTERS ------------------------------------------------------- + */ +const abe_int32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 }; +const abe_int32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 }; +const abe_int32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 }; +const abe_int32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 }; -const abe_int32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { - -4119413, -192384, -341428, -348088, -151380, 151380, - 348088, 341428, 192384, 4119415, 1938156, -6935719, - 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 - }; -const abe_int32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { - -4119413, -192384, -341428, -348088, -151380, 151380, - 348088, 341428, 192384, 4119415, 1938156, -6935719, - 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 - }; diff --git a/sound/soc/omap/abe/abe_dat.c b/sound/soc/omap/abe/abe_dat.c new file mode 100644 index 000000000000..d0c353fde68a --- /dev/null +++ b/sound/soc/omap/abe/abe_dat.c @@ -0,0 +1,934 @@ +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#include "abe_main.h" + +#ifndef abe_dat_c +#define abe_dat_c + + +const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE] = { +#include "abe_firmware.c" +}; + +u32 abe_firmware_version_number; + +/* + * HAL/FW ports status / format / sampling / protocol(call_back) / features + * / gain / name + */ + +abe_port_t abe_port [LAST_PORT_ID]; /* list of ABE ports */ +const abe_port_t abe_port_init [LAST_PORT_ID] = { + + /* Status Data Format Drift Call-Back Protocol+selector desc_addr; + buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features + reseted at start Port Name for the debug trace */ + /* DMIC */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB}, + NODRIFT, NOCALLBACK, 0, 0, + { + SNK_P, DMIC_PORT_PROT, + {dmem_dmic, dmem_dmic_size, DMIC_ITER} + }, + {0, 0}, + {EQMIC, 0}, "DMIC" + }, + /* PDM_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_amic, 0, + { + SNK_P, MCPDMUL_PORT_PROT, + {dmem_amic, dmem_amic_size, MCPDM_UL_ITER} + }, + {0, 0}, + {EQMIC, 0}, "PDM_UL" + }, + /* BT_VX_UL*/ { + OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_bt_vx_ul, 0, + { + SNK_P, SERIAL_PORT_PROT, { + MCBSP1_DMA_TX*ATC_SIZE, + dmem_bt_vx_ul,dmem_bt_vx_ul_size, + 1 * SCHED_LOOP_8kHz + } + }, + {0, 0}, {0}, "BT_VX_UL" + }, + /* MM_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ul, 0, + { + SRC_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX3*ATC_SIZE, + dmem_mm_ul,dmem_mm_ul_size, + 10 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<3) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120}, + {UPROUTE, 0}, "MM_UL" + }, + /* MM_UL2 */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ul2,0, + { + SRC_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX4*ATC_SIZE, + dmem_mm_ul2,dmem_mm_ul2_size, + 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<4) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24}, + {UPROUTE, 0}, "MM_UL2" + }, + /* VX_UL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_vx_ul, 0, + { + SRC_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX2*ATC_SIZE, + dmem_vx_ul,dmem_vx_ul_size, + 1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<2) + } + }, { + CIRCULAR_BUFFER_PERIPHERAL_R__2, 2 + }, + {ASRC2, 0}, "VX_UL" + }, + /* MM_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_dl_opp100, 0, + { + SNK_P, PINGPONG_PORT_PROT, { + CBPr_DMA_RTX0*ATC_SIZE, + dmem_mm_dl,dmem_mm_dl_size, + 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<0) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24}, + {ASRC3, 0}, "MM_DL" + }, + /* VX_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_vx_dl, 0, + { + SNK_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX1*ATC_SIZE, + dmem_vx_dl,dmem_vx_dl_size, + 1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<1) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2}, + {ASRC1, 0}, "VX_DL" + }, + /* TONES_DL*/ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_tones_dl, 0, + { + SNK_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX5*ATC_SIZE, + dmem_tones_dl,dmem_tones_dl_size, + 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<5) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24}, + {0}, "TONES_DL" + }, + /* VIB_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {24000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_vib, 0, + { + SNK_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX6*ATC_SIZE, + dmem_vib_dl,dmem_vib_dl_size, + 2 * SCHED_LOOP_24kHz, ABE_DMASTATUS_RAW,(1<<6) + } + }, + {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12}, + {0}, "VIB_DL" + }, + /* BT_VX_DL*/ { + OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB}, + NODRIFT, NOCALLBACK, smem_bt_vx_dl, 0, + { + SRC_P, SERIAL_PORT_PROT, { + MCBSP1_DMA_RX*ATC_SIZE, + dmem_bt_vx_dl,dmem_bt_vx_dl_size, + 1 * SCHED_LOOP_8kHz, + } + }, + {0, 0}, {0}, "BT_VX_DL" + }, + + /* PDM_DL */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB}, + NODRIFT, NOCALLBACK, 0,0, + {SRC_P, MCPDMDL_PORT_PROT, {dmem_mcpdm, dmem_mcpdm_size}}, {0, 0}, + {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R,0}, "PDM_DL" + }, + + /* MM_EXT_OUT*/ + { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ext_out, 0, + { + SRC_P, SERIAL_PORT_PROT, { + MCBSP1_DMA_TX*ATC_SIZE, + dmem_mm_ext_out,dmem_mm_ext_out_size, + 2 * SCHED_LOOP_48kHz + } + }, {0, 0}, {0}, "MM_EXT_OUT" + }, + + /* MM_EXT_IN */ + { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, smem_mm_ext_in, 0, + { + SNK_P, SERIAL_PORT_PROT, { + MCBSP1_DMA_RX*ATC_SIZE, + dmem_mm_ext_in ,dmem_mm_ext_in_size, + 2 * SCHED_LOOP_48kHz + } + }, + {0, 0}, {0}, "MM_EXT_IN" + }, + + /* PCM3_TX */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, 0, 0, + { + SRC_P, TDM_SERIAL_PORT_PROT,{ + MCBSP3_DMA_TX*ATC_SIZE, + dmem_mm_ext_out,dmem_mm_ext_out_size, + 2 * SCHED_LOOP_48kHz + } + }, + {0, 0}, {0}, "TDM_OUT" + }, + + /* PCM3_RX */ { + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB}, + NODRIFT, NOCALLBACK, 0, 0, + { + SRC_P, TDM_SERIAL_PORT_PROT,{ + MCBSP3_DMA_RX*ATC_SIZE, + dmem_mm_ext_in ,dmem_mm_ext_in_size, + 2 * SCHED_LOOP_48kHz + } + }, + {0, 0}, {0}, "TDM_IN" + }, + + /* SCHD_DBG_PORT */{ + OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, MONO_MSB}, + NODRIFT, NOCALLBACK, 0,0, + { + SRC_P, DMAREQ_PORT_PROT, { + CBPr_DMA_RTX7*ATC_SIZE, + dmem_mm_trace,dmem_mm_trace_size, + 2 * SCHED_LOOP_48kHz,ABE_DMASTATUS_RAW,(1<<4) + } + }, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24}, + {FEAT_SEQ, FEAT_CTL, FEAT_GAINS, 0}, "SCHD_DBG" + }, +}; +/* abe_port_init : smem content for DMIC/PDM must be 0 or Dummy_AM_labelID */ + +/* + * Firmware features + */ +abe_feature_t all_feature [MAXNBFEATURE]; +const abe_feature_t all_feature_init [] = { + /* ON_reset OFF READ WRITE STATUS INPUT OUTPUT SLOT/S OPP NAME */ + /* equalizer downlink path headset + earphone */ + /* EQ1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1, + c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ1" + }, + + /* equalizer downlink path integrated handsfree LEFT */ + /* EQ2L */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2, + c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2L" + }, + + /* equalizer downlink path integrated handsfree RIGHT */ + /* EQ2R */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2R" + }, + + /* equalizer downlink path side-tone */ + /* EQSDT */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQSDT" + }, + + /* SRC+equalizer uplink DMIC 1st pair */ + /* EQDMIC1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC1" + }, + + /* SRC+equalizer uplink DMIC 2nd pair */ + /* EQDMIC2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC2" + }, + + /* SRC+equalizer uplink DMIC 3rd pair */ + /* EQDMIC3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC3" + }, + + /* SRC+equalizer uplink AMIC */ + /* EQAMIC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQAMIC" + }, + + /* Acoustic protection for headset */ + /* APS1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " APS1" + }, + + /* acoustic protection high-pass filter for handsfree "Left" */ + /* APS2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS2" + }, + + /* acoustic protection high-pass filter for handsfree "Right" */ + /* APS3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS3" + }, + + /* asynchronous sample-rate-converter for the downlink voice path */ + /* ASRC1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXDL" + }, + + /* asynchronous sample-rate-converter for the uplink voice path */ + /* ASRC2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXUL" + }, + + /* asynchronous sample-rate-converter for the multimedia player */ + /* ASRC3 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," ASRC_MMDL" + }, + + /* asynchronous sample-rate-converter for the echo reference */ + /* ASRC4 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_ECHO" + }, + + /* mixer of the headset and earphone path */ + /* MXDL1 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " MIX_DL1" + }, + + /* mixer of the hands-free path */ + /* MXDL2 */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," MIX_DL2" + }, + + /* mixer for uplink tone mixer */ + /* MXAUDUL */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXSAUDUL" + }, + + /* mixer for voice recording */ + /* MXVXREC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXVXREC" + }, + + /* mixer for side-tone */ + /* MXSDT */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_SDT" + }, + + /* mixer for echo reference */ + /* MXECHO */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_ECHO" + }, + + /* router of the uplink path */ + /* UPROUTE */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " DLEQ3" + }, + + /* all gains */ + /* GAINS */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" + }, + + /* active noise canceller */ + /* EANC */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ3" + }, + + /* sequencing queue of micro tasks */ + /* SEQ */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" + }, + + /* Phoenix control queue through McPDM */ + /* CTL */ + { + c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, + 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" + }, +}; + + + +/* + * MEMORY MAPPING OF THE DMEM FIFOs + */ + +/* DMEM port map */ +u32 abe_map_dmem [LAST_PORT_ID]; +u32 abe_map_dmem_secondary [LAST_PORT_ID]; + +/* DMEM port buffer sizes */ +u32 abe_map_dmem_size [LAST_PORT_ID]; + + +/* + * AESS/ATC destination and source address translation (except McASPs) + * from the original 64bits words address + */ +const u32 abe_atc_dstid [ABE_ATC_DESC_SIZE>>3] = { + /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */ + 0, 0, 12, 0, 1, 0, 2, 0, + /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */ + 3, 0, 4, 5, 6, 7, 8, 9, + /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */ + 10, 11, 0, 0, 0, 0, 0, 0, + /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */ + 0, 0, 14, 0, 0, 0, 0, 0, + /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */ + 63, 63, 63, 63, 63, 63, 63, 63, + /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 + CBP_T15 48 .. 63 */ + 0, 0, 0, 0, 0, 0, 0, 0, +}; +const u32 abe_atc_srcid [ABE_ATC_DESC_SIZE>>3] = { + /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */ + 0, 12, 0, 13, 0, 1, 0, 2, + /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */ + 0, 3, 0, 0, 0, 0, 0, 0, + /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 */ + 0, 0, 4, 5, 6, 7, 8, 9, + /* SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 */ + 10, 11, 0, 0, 0, 14, 0, 0, + /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 */ + 63, 63, 63, 63, 63, 63, 63, 63, + /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */ + 0, 0, 0, 0, 0, 0, 0, 0, + /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 + CBP_T15 48 .. 63 */ + 0, 0, 0, 0, 0, 0, 0, 0, +}; + + +/* + * preset default routing configurations + * This is given as implementation EXAMPLES + * the programmer uses "abe_set_router_configuration" with its own tables + */ + +const abe_router_t abe_router_ul_table_preset [NBROUTE_CONFIG][NBROUTE_UL] = { { + + /* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */ + + /* 0 .. 9 = MM_UL */ + DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + + /* 10 .. 11 = MM_UL2 */ + DMIC3_L_labelID, DMIC3_R_labelID, + + /* 12 .. 13 = VX_UL */ + AMIC_L_labelID, AMIC_R_labelID, + + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + + /* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1*/ + { + /* 0 .. 9 = MM_UL */ + DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID, + DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + + /* 10 .. 11 = MM_UL2 */ + DMIC1_L_labelID, DMIC1_R_labelID, + + /* 12 .. 13 = VX_UL */ + DMIC1_L_labelID, DMIC1_R_labelID, + + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + + /* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */ + { + /* 0 .. 9 = MM_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, + DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + + /* 10 .. 11 = MM_UL2 */ + DMIC2_L_labelID, DMIC2_R_labelID, + + /* 12 .. 13 = VX_UL */ + DMIC2_L_labelID, DMIC2_R_labelID, + + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + + /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */ + { + /* 0 .. 9 = MM_UL */ + AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + + /* 10 .. 11 = MM_UL2 */ + DMIC3_L_labelID, DMIC3_R_labelID, + + /* 12 .. 13 = VX_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, + + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, + + /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */ + { + /* 0 .. 9 = MM_UL */ + BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, + ZERO_labelID, ZERO_labelID, + + /* 10 .. 11 = MM_UL2 */ + AMIC_L_labelID, AMIC_R_labelID, + + /* 12 .. 13 = VX_UL */ + BT_UL_L_labelID, BT_UL_R_labelID, + + /* 14 .. 15 = RESERVED */ + ZERO_labelID, ZERO_labelID, + }, +}; + +/* all default routing configurations */ +abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL]; + +/* + * ABE SUBROUTINES AND SEQUENCES + */ + + +/* +const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] = + {{0, 0, 0, 0}, {-1, 0, 0, 0}}, + {{0, 0, 0, 0}, {-1, 0, 0, 0}}, +const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1, 0, 0, 0, 0, + -1, C_CALLBACK1, 0, 0, 0, 0 }; + +const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] = + abe_init_atc, 0, 0, + abe_init_atc, 0, 0, + + typedef double (*PtrFun) (double); +PtrFun pFun; +pFun = sin; +y = (* pFun) (x); +*/ /* mask, { time id param tag1} */ +const abe_sequence_t seq_null = {NOMASK, {CL_M1, 0, 0,0,0,0, 0 }, + {CL_M1, 0, 0,0,0,0, 0 } +}; + +/* table of new subroutines called in the sequence */ +abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE]; + +/* number of parameters per calls */ +u32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE]; + +/* index of the subroutine */ +u32 abe_subroutine_id [MAXNBSUBROUTINE]; + +/* paramters of the subroutine (if any) */ +u32* abe_all_subroutine_params[MAXNBSUBROUTINE]; +u32 abe_subroutine_write_pointer; + +/* table of all sequences */ +abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; +u32 abe_sequence_write_pointer; + +/* current number of pending sequences (avoids to look in the table) */ +u32 abe_nb_pending_sequences; + +/* pending sequences due to ressource collision */ +u32 abe_pending_sequences [MAXNBSEQUENCE]; + +/* mask of unsharable ressources among other sequences */ +u32 abe_global_sequence_mask; + +/* table of active sequences */ +abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS]; + +/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */ +u32 abe_irq_pingpong_player_id; + +/* index of the plugged subroutine doing acoustics protection adaptation */ +u32 abe_irq_aps_adaptation_id; + +/* base addresses of the ping pong buffers in bytes addresses */ +u32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS]; + +/* size of each ping/pong buffers */ +u32 abe_size_pingpong; + +/* number of ping/pong buffer being used */ +u32 abe_nb_pingpong; + +/* current EVENT */ +u32 abe_current_event_id; + +/* + * ABE CONST AREA FOR PARAMETERS TRANSLATION + */ +const u32 abe_db2lin_table [sizeof_db2lin_table] = { + + 0x00000000, /* SMEM coding of -120 dB */ + 0x00000000, /* SMEM coding of -119 dB */ + 0x00000000, /* SMEM coding of -118 dB */ + 0x00000000, /* SMEM coding of -117 dB */ + 0x00000000, /* SMEM coding of -116 dB */ + 0x00000000, /* SMEM coding of -115 dB */ + 0x00000000, /* SMEM coding of -114 dB */ + 0x00000000, /* SMEM coding of -113 dB */ + 0x00000000, /* SMEM coding of -112 dB */ + 0x00000000, /* SMEM coding of -111 dB */ + 0x00000000, /* SMEM coding of -110 dB */ + 0x00000000, /* SMEM coding of -109 dB */ + 0x00000001, /* SMEM coding of -108 dB */ + 0x00000001, /* SMEM coding of -107 dB */ + 0x00000001, /* SMEM coding of -106 dB */ + 0x00000001, /* SMEM coding of -105 dB */ + 0x00000001, /* SMEM coding of -104 dB */ + 0x00000001, /* SMEM coding of -103 dB */ + 0x00000002, /* SMEM coding of -102 dB */ + 0x00000002, /* SMEM coding of -101 dB */ + 0x00000002, /* SMEM coding of -100 dB */ + 0x00000002, /* SMEM coding of -99 dB */ + 0x00000003, /* SMEM coding of -98 dB */ + 0x00000003, /* SMEM coding of -97 dB */ + 0x00000004, /* SMEM coding of -96 dB */ + 0x00000004, /* SMEM coding of -95 dB */ + 0x00000005, /* SMEM coding of -94 dB */ + 0x00000005, /* SMEM coding of -93 dB */ + 0x00000006, /* SMEM coding of -92 dB */ + 0x00000007, /* SMEM coding of -91 dB */ + 0x00000008, /* SMEM coding of -90 dB */ + 0x00000009, /* SMEM coding of -89 dB */ + 0x0000000A, /* SMEM coding of -88 dB */ + 0x0000000B, /* SMEM coding of -87 dB */ + 0x0000000D, /* SMEM coding of -86 dB */ + 0x0000000E, /* SMEM coding of -85 dB */ + 0x00000010, /* SMEM coding of -84 dB */ + 0x00000012, /* SMEM coding of -83 dB */ + 0x00000014, /* SMEM coding of -82 dB */ + 0x00000017, /* SMEM coding of -81 dB */ + 0x0000001A, /* SMEM coding of -80 dB */ + 0x0000001D, /* SMEM coding of -79 dB */ + 0x00000021, /* SMEM coding of -78 dB */ + 0x00000025, /* SMEM coding of -77 dB */ + 0x00000029, /* SMEM coding of -76 dB */ + 0x0000002E, /* SMEM coding of -75 dB */ + 0x00000034, /* SMEM coding of -74 dB */ + 0x0000003A, /* SMEM coding of -73 dB */ + 0x00000041, /* SMEM coding of -72 dB */ + 0x00000049, /* SMEM coding of -71 dB */ + 0x00000052, /* SMEM coding of -70 dB */ + 0x0000005D, /* SMEM coding of -69 dB */ + 0x00000068, /* SMEM coding of -68 dB */ + 0x00000075, /* SMEM coding of -67 dB */ + 0x00000083, /* SMEM coding of -66 dB */ + 0x00000093, /* SMEM coding of -65 dB */ + 0x000000A5, /* SMEM coding of -64 dB */ + 0x000000B9, /* SMEM coding of -63 dB */ + 0x000000D0, /* SMEM coding of -62 dB */ + 0x000000E9, /* SMEM coding of -61 dB */ + 0x00000106, /* SMEM coding of -60 dB */ + 0x00000126, /* SMEM coding of -59 dB */ + 0x0000014A, /* SMEM coding of -58 dB */ + 0x00000172, /* SMEM coding of -57 dB */ + 0x0000019F, /* SMEM coding of -56 dB */ + 0x000001D2, /* SMEM coding of -55 dB */ + 0x0000020B, /* SMEM coding of -54 dB */ + 0x0000024A, /* SMEM coding of -53 dB */ + 0x00000292, /* SMEM coding of -52 dB */ + 0x000002E2, /* SMEM coding of -51 dB */ + 0x0000033C, /* SMEM coding of -50 dB */ + 0x000003A2, /* SMEM coding of -49 dB */ + 0x00000413, /* SMEM coding of -48 dB */ + 0x00000492, /* SMEM coding of -47 dB */ + 0x00000521, /* SMEM coding of -46 dB */ + 0x000005C2, /* SMEM coding of -45 dB */ + 0x00000676, /* SMEM coding of -44 dB */ + 0x0000073F, /* SMEM coding of -43 dB */ + 0x00000822, /* SMEM coding of -42 dB */ + 0x00000920, /* SMEM coding of -41 dB */ + 0x00000A3D, /* SMEM coding of -40 dB */ + 0x00000B7D, /* SMEM coding of -39 dB */ + 0x00000CE4, /* SMEM coding of -38 dB */ + 0x00000E76, /* SMEM coding of -37 dB */ + 0x0000103A, /* SMEM coding of -36 dB */ + 0x00001235, /* SMEM coding of -35 dB */ + 0x0000146E, /* SMEM coding of -34 dB */ + 0x000016EC, /* SMEM coding of -33 dB */ + 0x000019B8, /* SMEM coding of -32 dB */ + 0x00001CDC, /* SMEM coding of -31 dB */ + 0x00002061, /* SMEM coding of -30 dB */ + 0x00002455, /* SMEM coding of -29 dB */ + 0x000028C4, /* SMEM coding of -28 dB */ + 0x00002DBD, /* SMEM coding of -27 dB */ + 0x00003352, /* SMEM coding of -26 dB */ + 0x00003995, /* SMEM coding of -25 dB */ + 0x0000409C, /* SMEM coding of -24 dB */ + 0x0000487E, /* SMEM coding of -23 dB */ + 0x00005156, /* SMEM coding of -22 dB */ + 0x00005B43, /* SMEM coding of -21 dB */ + 0x00006666, /* SMEM coding of -20 dB */ + 0x000072E5, /* SMEM coding of -19 dB */ + 0x000080E9, /* SMEM coding of -18 dB */ + 0x000090A4, /* SMEM coding of -17 dB */ + 0x0000A24B, /* SMEM coding of -16 dB */ + 0x0000B618, /* SMEM coding of -15 dB */ + 0x0000CC50, /* SMEM coding of -14 dB */ + 0x0000E53E, /* SMEM coding of -13 dB */ + 0x00010137, /* SMEM coding of -12 dB */ + 0x0001209A, /* SMEM coding of -11 dB */ + 0x000143D1, /* SMEM coding of -10 dB */ + 0x00016B54, /* SMEM coding of -9 dB */ + 0x000197A9, /* SMEM coding of -8 dB */ + 0x0001C967, /* SMEM coding of -7 dB */ + 0x00020137, /* SMEM coding of -6 dB */ + 0x00023FD6, /* SMEM coding of -5 dB */ + 0x00028619, /* SMEM coding of -4 dB */ + 0x0002D4EF, /* SMEM coding of -3 dB */ + 0x00032D64, /* SMEM coding of -2 dB */ + 0x000390A4, /* SMEM coding of -1 dB */ + 0x00040000, /* SMEM coding of 0 dB */ + 0x00047CF2, /* SMEM coding of 1 dB */ + 0x00050923, /* SMEM coding of 2 dB */ + 0x0005A670, /* SMEM coding of 3 dB */ + 0x000656EE, /* SMEM coding of 4 dB */ + 0x00071CF5, /* SMEM coding of 5 dB */ + 0x0007FB26, /* SMEM coding of 6 dB */ + 0x0008F473, /* SMEM coding of 7 dB */ + 0x000A0C2B, /* SMEM coding of 8 dB */ + 0x000B4606, /* SMEM coding of 9 dB */ + 0x000CA62C, /* SMEM coding of 10 dB */ + 0x000E314A, /* SMEM coding of 11 dB */ + 0x000FEC9E, /* SMEM coding of 12 dB */ + 0x0011DE0A, /* SMEM coding of 13 dB */ + 0x00140C28, /* SMEM coding of 14 dB */ + 0x00167E60, /* SMEM coding of 15 dB */ + 0x00193D00, /* SMEM coding of 16 dB */ + 0x001C515D, /* SMEM coding of 17 dB */ + 0x001FC5EB, /* SMEM coding of 18 dB */ + 0x0023A668, /* SMEM coding of 19 dB */ + 0x00280000, /* SMEM coding of 20 dB */ + 0x002CE178, /* SMEM coding of 21 dB */ + 0x00325B65, /* SMEM coding of 22 dB */ + 0x00388062, /* SMEM coding of 23 dB */ + 0x003F654E, /* SMEM coding of 24 dB */ + 0x00472194, /* SMEM coding of 25 dB */ + 0x004FCF7C, /* SMEM coding of 26 dB */ + 0x00598C81, /* SMEM coding of 27 dB */ + 0x006479B7, /* SMEM coding of 28 dB */ + 0x0070BC3D, /* SMEM coding of 29 dB */ + 0x007E7DB9, /* SMEM coding of 30 dB */ + +}; + +const u32 abe_1_alpha_iir [64] = { + 0x040002, 0x040002, 0x040002, 0x040002, /* 0 */ + 0x50E955, 0x48CA65, 0x40E321, 0x72BE78, /* 1 [ms] */ + 0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, /* 2 */ + 0x38A084, 0x308974, 0x297B00, 0x235C7C, /* 4 */ + 0x1E14B0, 0x198AF0, 0x15A800, 0x125660, /* 8 */ + 0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, /* 16 */ + 0x07E054, 0x06A3B8, 0x059844, 0x04B680, /* 32 */ + 0x03F80C, 0x035774, 0x02D018, 0x025E0C, /* 64 */ + 0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, /* 128 */ + 0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, /* 256 */ + 0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, /* 512 */ + 0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, /* 1.024 [s] */ + 0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, /* 2.048 */ + 0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, /* 4.096 */ + 0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, /* 8.192 */ + 0x00FFFF, 0x00D743, 0x00B503, 0x009837, +}; + +const u32 abe_alpha_iir [64] = { + 0x000000, 0x000000, 0x000000, 0x000000, /* 0 */ + 0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, /* 1 [ms] */ + 0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, /* 2 */ + 0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, /* 4 */ + 0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, /* 8 */ + 0x783EB1, 0x797251, 0x7A7761, 0x7B549D, /* 16 */ + 0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, /* 32 */ + 0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, /* 64 */ + 0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, /* 128 */ + 0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, /* 256 */ + 0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, /* 512 */ + 0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, /* 1.024 [s] */ + 0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, /* 2.048 */ + 0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, /* 4.096 */ + 0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, /* 8.192 */ + 0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1, +}; + +/* + * ABE_DEBUG DATA + */ + +/* + * IRQ and trace pointer in DMEM: + * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL + */ +u32 abe_irq_dbg_read_ptr; + +/* + * General circular buffer used to trace APIs calls and AE activity. + */ +u32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof]; +u32 abe_dbg_activity_log_write_pointer; +u32 abe_dbg_mask; + +/* + * Global variable holding parameter errors + */ + +u32 abe_dbg_param; + + +/* + * Output of messages selector + */ +u32 abe_dbg_output; + +/* + * last parameters + */ + +#define SIZE_PARAM 10 + +u32 param1[SIZE_PARAM]; +u32 param2[SIZE_PARAM]; +u32 param3[SIZE_PARAM]; +u32 param4[SIZE_PARAM]; +u32 param5[SIZE_PARAM]; + +/* + * END ABE_DEBUG DATA + */ + + + +/* + * ABE CONST AREA FOR DMIC DECIMATION FILTERS + */ +const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; +const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { + -4119413, -192384, -341428, -348088, -151380, 151380, 348088, + 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, + 2997698, -3692214, 3406822, -2280190, 1042982 }; + + +#endif /* abe_dat_c */ diff --git a/sound/soc/omap/abe/abe_dat.h b/sound/soc/omap/abe/abe_dat.h index dd90ce3964b3..df83490489d7 100644 --- a/sound/soc/omap/abe/abe_dat.h +++ b/sound/soc/omap/abe/abe_dat.h @@ -1,1325 +1,520 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. +/* ============================================================================= +* Texas Instruments OMAP(TM) Platform Software +* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. +* +* Use of this software is controlled by the terms and conditions found +* in the license agreement under which this software has been supplied. +* =========================================================================== */ +/** + * @file ABE_DAT.H + * + * All the visible API for the audio drivers * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * @path + * @rev 01.00 */ - -#ifndef _ABE_DAT_H_ -#define _ABE_DAT_H_ +/* ---------------------------------------------------------------------------- +*! +*! Revision History +*! =================================== +*! 27-Nov-2008 Original (LLF) +*! 05-Jun-2009 V05 release +* =========================================================================== */ + + +#ifndef abe_dat_def +#define abe_dat_def #ifdef __cplusplus + extern "C" { #endif - /* - * Callbacks + * Call-backs */ -abe_subroutine2 callbacks[MAXCALLBACK]; /* 2 parameters subroutine pointers */ -abe_port_t abe_port [LAST_PORT_ID]; /* list of ABE ports */ -const abe_port_t abe_port_init [LAST_PORT_ID] = { -/* status, data format, drift, callback, io-task buffer 1, io-task buffer 2, - * protocol, dma offset, features, name - * - Features reseted at start - */ +abe_subroutine2 callbacks [MAXCALLBACK]; /* 2 parameters subroutine pointers */ - /* DMIC */ - { - IDLE_P, - {96000, SIX_MSB}, - NODRIFT, - NOCALLBACK, - 0, - 0, - { - SNK_P, - DMIC_PORT_PROT, - {{ - dmem_dmic, - dmem_dmic_size, - DMIC_ITER - }}, - }, - {0, 0}, - {EQMIC, 0}, - "DMIC", - }, - /* PDM_UL */ - { - IDLE_P, - {96000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_amic, - 0, - { - SNK_P, - MCPDMUL_PORT_PROT, - {{ - dmem_amic, - dmem_amic_size, - MCPDM_UL_ITER, - }}, - }, - {0, 0}, - {EQMIC, 0}, - "PDM_UL", - }, - /* BT_VX_UL */ - { - IDLE_P, - {8000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_bt_vx_ul, - 0, - { - SNK_P, - SERIAL_PORT_PROT, - {{ - MCBSP1_DMA_TX * ATC_SIZE, - dmem_bt_vx_ul, - dmem_bt_vx_ul_size, - 1 * SCHED_LOOP_8kHz, - }}, - }, - {0, 0}, - {0}, - "BT_VX_UL", - }, - /* MM_UL */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_mm_ul, - 0, - { - SRC_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX3 * ATC_SIZE, - dmem_mm_ul, - dmem_mm_ul_size, - 10 * SCHED_LOOP_48kHz, - ABE_DMASTATUS_RAW, - 1 << 3, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120}, - {UPROUTE, 0}, - "MM_UL", - }, - /* MM_UL2 */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_mm_ul2, - 0, - { - SRC_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX4 * ATC_SIZE, - dmem_mm_ul2, - dmem_mm_ul2_size, - 2 * SCHED_LOOP_48kHz, - ABE_DMASTATUS_RAW, - 1 << 4, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24}, - {UPROUTE, 0}, - "MM_UL2", - }, - /* VX_UL */ - { - IDLE_P, - {8000, MONO_MSB}, - NODRIFT, - NOCALLBACK, - smem_vx_ul, - 0, - { - SRC_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX2*ATC_SIZE, - dmem_vx_ul, - dmem_vx_ul_size / 2, - 1 * SCHED_LOOP_8kHz, - ABE_DMASTATUS_RAW, - 1 << 2, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__2, 2}, - {ASRC2, 0}, - "VX_UL", - }, - /* MM_DL */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_mm_dl_opp100, - 0, - { - SNK_P, - PINGPONG_PORT_PROT, - {{ - CBPr_DMA_RTX0 * ATC_SIZE, - dmem_mm_dl, - dmem_mm_dl_size, - 2 * SCHED_LOOP_48kHz, - ABE_DMASTATUS_RAW, - 1 << 0, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24}, - {ASRC3, 0}, - "MM_DL", - }, - /* VX_DL */ - { - IDLE_P, - {8000, MONO_MSB}, - NODRIFT, - NOCALLBACK, - smem_vx_dl, - 0, - { - SNK_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX1 * ATC_SIZE, - dmem_vx_dl, - dmem_vx_dl_size, - 1 * SCHED_LOOP_8kHz, - ABE_DMASTATUS_RAW, - 1 << 1, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2}, - {ASRC1, 0}, - "VX_DL", - }, - /* TONES_DL */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_tones_dl, - 0, - { - SNK_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX5 * ATC_SIZE, - dmem_tones_dl, - dmem_tones_dl_size, - 2 * SCHED_LOOP_48kHz, - ABE_DMASTATUS_RAW, - 1 << 5, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24}, - {0}, - "TONES_DL", - }, - /* VIB_DL */ - { - IDLE_P, - {24000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_vib, - 0, - { - SNK_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX6 * ATC_SIZE, - dmem_vib_dl, - dmem_vib_dl_size, - 2 * SCHED_LOOP_24kHz, - ABE_DMASTATUS_RAW, - 1 << 6, - }}, - }, - {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12}, - {0}, - "VIB_DL", - }, - /* BT_VX_DL */ - { - IDLE_P, - {8000, MONO_MSB}, - NODRIFT, - NOCALLBACK, - smem_bt_vx_dl, - 0, - { - SRC_P, - SERIAL_PORT_PROT, - {{ - MCBSP1_DMA_RX * ATC_SIZE, - dmem_bt_vx_dl, - dmem_bt_vx_dl_size, - 1 * SCHED_LOOP_8kHz, - }}, - }, - {0, 0}, - {0}, - "BT_VX_DL", - }, - /* PDM_DL1 */ - { - IDLE_P, - {96000, SIX_MSB}, - NODRIFT, - NOCALLBACK, - 0, - 0, - { - SRC_P, - MCPDMDL_PORT_PROT, - {{ - dmem_mcpdm, - dmem_mcpdm_size, - }}, - }, - {0, 0}, - {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R, 0}, - "PDM_DL", - }, - /* MM_EXT_OUT */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_mm_ext_out, - 0, - { - SRC_P, - SERIAL_PORT_PROT, - {{ - MCBSP1_DMA_TX * ATC_SIZE, - dmem_mm_ext_out, - dmem_mm_ext_out_size, - 2 * SCHED_LOOP_48kHz, - }}, - }, - {0, 0}, - {0}, - "MM_EXT_OUT", - }, - /* MM_EXT_IN */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - smem_mm_ext_in, - 0, - { - SRC_P, - SERIAL_PORT_PROT, - {{ - MCBSP1_DMA_RX * ATC_SIZE, - dmem_mm_ext_in, - dmem_mm_ext_in_size, - 2 * SCHED_LOOP_48kHz, - }}, - }, - {0, 0}, - {0}, - "MM_EXT_IN", - }, - /* PCM3_TX */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - 0, - 0, - { - SRC_P, - TDM_SERIAL_PORT_PROT, - {{ - MCBSP3_DMA_TX*ATC_SIZE, - dmem_mm_ext_out, - dmem_mm_ext_out_size, - 2 * SCHED_LOOP_48kHz, - }} - }, - {0, 0}, - {0}, - "MM_EXT_OUT", - }, - /* PCM3_RX */ - { - IDLE_P, - {48000, STEREO_MSB}, - NODRIFT, - NOCALLBACK, - 0, - 0, - { - SRC_P, - TDM_SERIAL_PORT_PROT, - {{ - MCBSP3_DMA_RX*ATC_SIZE, - dmem_mm_ext_in, - dmem_mm_ext_in_size, - 2 * SCHED_LOOP_48kHz - }} - }, - {0, 0}, - {0}, - "MM_EXT_IN" - }, - /* SCHD_DBG_PORT */ - { - IDLE_P, - {48000, MONO_MSB}, - NODRIFT, - NOCALLBACK, - 0, - 0, - { - SRC_P, - DMAREQ_PORT_PROT, - {{ - CBPr_DMA_RTX7*ATC_SIZE, - dmem_mm_trace, - dmem_mm_trace_size, - 2 * SCHED_LOOP_48kHz, - ABE_DMASTATUS_RAW, - (1<<4) - }} - }, - { - CIRCULAR_BUFFER_PERIPHERAL_R__7, - 24 - }, - { - SEQUENCE, - CONTROL, - GAINS, - 0 - }, - "SCHD_DBG" - }, -}; -const abe_port_info_t abe_port_info [LAST_PORT_ID] = { - /* DMIC */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* PDM_UL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* BT_VX_UL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* MM_UL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* MM_UL2 */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* VX_UL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* MM_DL */ - { - ABE_OPP50, - {SUB_WRITE_MIXER, {MM_DL_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* VX_DL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* TONES_DL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* VIB_DL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* BT_VX_DL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* PDM_DL */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* MM_EXT_OUT */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* MM_EXT_IN */ - { - ABE_OPP50, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - /* - SCHD_DBG_PORT - { - ABE_OPP25, - {SUB_WRITE_PORT_GAIN, {DMIC_PORT, MUTE_GAIN, 0, 0}}, - {0, {0, 0, 0, 0}} - }, - */ -}; /* - * Firmware features + * HAL/FW ports status / format / sampling / protocol(call_back) / features / gain / name */ -abe_feature_t all_feature[MAXNBFEATURE]; - -const abe_feature_t all_feature_init[] = { -/* on_reset, off, read, write, status, input, output, slots, opp, name */ - /* EQ1: equalizer downlink path headset + earphone */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq1, - c_write_eq1, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " DLEQ1", - }, - /* EQ2L: equalizer downlink path integrated handsfree left */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq2, - c_write_eq2, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " DLEQ2L", - }, - /* EQ2R: equalizer downlink path integrated handsfree right */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " DLEQ2R", - }, - /* EQSDT: equalizer downlink path side-tone */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " EQSDT", - }, - /* EQDMIC1: SRC+equalizer uplink DMIC 1st pair */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " EQDMIC1", - }, - /* EQDMIC2: SRC+equalizer uplink DMIC 2nd pair */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " EQDMIC2", - }, - /* EQDMIC3: SRC+equalizer uplink DMIC 3rd pair */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " EQDMIC3", - }, - /* EQAMIC: SRC+equalizer uplink AMIC */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " EQAMIC", - }, - /* APS1: Acoustic protection for headset */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " APS1", - }, - /* APS2: acoustic protection high-pass filter for handsfree left */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " APS2", - }, - /* APS3: acoustic protection high-pass filter for handsfree right */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " APS3", - }, - /* ASRC1: asynchronous sample-rate-converter for the downlink voice path */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " ASRC_VXDL" - }, - /* ASRC2: asynchronous sample-rate-converter for the uplink voice path */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " ASRC_VXUL", - }, - /* ASRC3: asynchronous sample-rate-converter for the multimedia player */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " ASRC_MMDL", - }, - /* ASRC4: asynchronous sample-rate-converter for the echo reference */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " ASRC_ECHO", - }, - /* MXDL1: mixer of the headset and earphone path */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " MIX_DL1", - }, - /* MXDL2: mixer of the hands-free path */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " MIX_DL2", - }, - /* MXAUDUL: mixer for uplink tone mixer */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " MXSAUDUL", - }, - /* MXVXREC: mixer for voice recording */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " MXVXREC", - }, - /* MXSDT: mixer for side-tone */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " MIX_SDT", - }, - /* MXECHO: mixer for echo reference */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " MIX_ECHO", - }, - /* UPROUTE: router of the uplink path */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP50, - " DLEQ3", - }, - /* GAINS: all gains */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " DLEQ3", - }, - /* EANC: active noise canceller */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP100, - " DLEQ3", - }, - /* SEQ: sequencing queue of micro tasks */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " DLEQ3", - }, - /* CTL: Phoenix control queue through McPDM */ - { - c_feat_init_eq, - c_feat_init_eq, - c_feat_read_eq3, - c_write_eq3, - 0, - 0x1000, - 0x1010, - 2, - 0, - ABE_OPP25, - " DLEQ3", - }, -}; + abe_port_t abe_port [LAST_PORT_ID]; /* list of ABE ports */ +const abe_port_t abe_port_init [LAST_PORT_ID] = { + + /* Status Data Format Drift Call-Back Protocol+selector desc_addr; buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features reseted at start Port Name for the debug trace */ +/* DMIC */ { IDLE_P, {96000, SIX_MSB}, NODRIFT, NOCALLBACK, 0, 0, {SNK_P, DMIC_PORT_PROT, {dmem_dmic, dmem_dmic_size, DMIC_ITER}}, {0, 0}, {EQMIC, 0}, "DMIC" }, +/* PDM_UL */ { IDLE_P, {96000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_amic, 0, {SNK_P, MCPDMUL_PORT_PROT, {dmem_amic, dmem_amic_size, MCPDM_UL_ITER}}, {0, 0}, {EQMIC, 0}, "PDM_UL" }, +/* BT_VX_UL*/ { IDLE_P, { 8000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_bt_vx_ul, 0, {SNK_P, SERIAL_PORT_PROT, {MCBSP1_DMA_TX*ATC_SIZE,dmem_bt_vx_ul,dmem_bt_vx_ul_size, 1 * SCHED_LOOP_8kHz}}, {0, 0}, {0}, "BT_VX_UL" }, +/* MM_UL */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ul, 0, {SRC_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX3*ATC_SIZE,dmem_mm_ul,dmem_mm_ul_size, 10 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<3)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120}, {UPROUTE, 0}, "MM_UL" }, +/* MM_UL2 */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ul2,0, {SRC_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX4*ATC_SIZE,dmem_mm_ul2,dmem_mm_ul2_size, 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<4)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24}, {UPROUTE, 0}, "MM_UL2" }, +/* VX_UL */ { IDLE_P, { 8000, MONO_MSB}, NODRIFT, NOCALLBACK, smem_vx_ul, 0, {SRC_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX2*ATC_SIZE,dmem_vx_ul,dmem_vx_ul_size, 1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<2)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__2, 2}, {ASRC2, 0}, "VX_UL" }, +/* MM_DL */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_dl_opp100, 0, {SNK_P, PINGPONG_PORT_PROT, {CBPr_DMA_RTX0*ATC_SIZE,dmem_mm_dl,dmem_mm_dl_size, 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<0)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24}, {ASRC3, 0}, "MM_DL" }, +/* VX_DL */ { IDLE_P, { 8000, MONO_MSB}, NODRIFT, NOCALLBACK, smem_vx_dl, 0, {SNK_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX1*ATC_SIZE,dmem_vx_dl,dmem_vx_dl_size, 1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<1)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2}, {ASRC1, 0}, "VX_DL" }, +/* TONES_DL*/ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_tones_dl, 0, {SNK_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX5*ATC_SIZE,dmem_tones_dl,dmem_tones_dl_size, 2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<5)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24}, {0}, "TONES_DL" }, +/* VIB_DL */ { IDLE_P, {24000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_vib, 0, {SNK_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX6*ATC_SIZE,dmem_vib_dl,dmem_vib_dl_size, 2 * SCHED_LOOP_24kHz, ABE_DMASTATUS_RAW,(1<<6)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12}, {0}, "VIB_DL" }, +/* BT_VX_DL*/ { IDLE_P, { 8000, MONO_MSB}, NODRIFT, NOCALLBACK, smem_bt_vx_dl, 0, {SRC_P, SERIAL_PORT_PROT, {MCBSP1_DMA_RX*ATC_SIZE,dmem_bt_vx_dl,dmem_bt_vx_dl_size, 1 * SCHED_LOOP_8kHz,}}, {0, 0}, {0}, "BT_VX_DL" }, +/* PDM_DL */ { IDLE_P, {96000, SIX_MSB}, NODRIFT, NOCALLBACK, 0,0, {SRC_P, MCPDMDL_PORT_PROT, {dmem_mcpdm, dmem_mcpdm_size}}, {0, 0}, {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R,0}, "PDM_DL" }, +/* MM_EXT_OUT*/ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ext_out, 0, {SRC_P, SERIAL_PORT_PROT, {MCBSP1_DMA_TX*ATC_SIZE,dmem_mm_ext_out,dmem_mm_ext_out_size, 2 * SCHED_LOOP_48kHz}}, {0, 0}, {0}, "MM_EXT_OUT" }, +/* MM_EXT_IN */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ext_in, 0, {SNK_P, SERIAL_PORT_PROT, {MCBSP1_DMA_RX*ATC_SIZE,dmem_mm_ext_in ,dmem_mm_ext_in_size, 2 * SCHED_LOOP_48kHz}}, {0, 0}, {0}, "MM_EXT_IN" }, +/* PCM3_TX */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, 0, 0, {SRC_P, TDM_SERIAL_PORT_PROT,{MCBSP3_DMA_TX*ATC_SIZE,dmem_mm_ext_out,dmem_mm_ext_out_size, 2 * SCHED_LOOP_48kHz}}, {0, 0}, {0}, "TDM_OUT" }, +/* PCM3_RX */ { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, 0, 0, {SRC_P, TDM_SERIAL_PORT_PROT,{MCBSP3_DMA_RX*ATC_SIZE,dmem_mm_ext_in ,dmem_mm_ext_in_size, 2 * SCHED_LOOP_48kHz}}, {0, 0}, {0}, "TDM_IN" }, +/* SCHD_DBG_PORT */{ IDLE_P, {48000, MONO_MSB}, NODRIFT, NOCALLBACK, 0,0, {SRC_P, DMAREQ_PORT_PROT, {CBPr_DMA_RTX7*ATC_SIZE,dmem_mm_trace,dmem_mm_trace_size, 2 * SCHED_LOOP_48kHz,ABE_DMASTATUS_RAW,(1<<4)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24}, {SEQUENCE, CONTROL, GAINS, 0}, "SCHD_DBG" }, + }; +// abe_port_init : smem content for DMIC/PDM must be 0 or Dummy_AM_labelID + +const abe_port_info_t abe_port_info [LAST_PORT_ID] = { +/* DMIC */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0}}, +/* PDM_UL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* BT_VX_UL*/ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* MM_UL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* MM_UL2 */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* VX_UL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* MM_DL */ { ABE_OPP50, {SUB_WRITE_MIXER, MM_DL_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* VX_DL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* TONES_DL*/ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* VIB_DL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* BT_VX_DL*/ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* PDM_DL */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* MM_EXT_OUT*/ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* MM_EXT_IN */ { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, +/* SCHD_DBG_PORT { ABE_OPP25, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} }, + */ }; + /* - * Memory mapping of DMEM FIFOs + * Firmware features */ -abe_uint32 abe_map_dmem[LAST_PORT_ID]; /* DMEM port map */ -abe_uint32 abe_map_dmem_secondary[LAST_PORT_ID]; -abe_uint32 abe_map_dmem_size[LAST_PORT_ID]; /* DMEM port buffer sizes */ + abe_feature_t all_feature [MAXNBFEATURE]; +const abe_feature_t all_feature_init [] = { + /* ON_reset OFF READ WRITE STATUS INPUT OUTPUT SLOT/S OPP NAME */ + /* EQ1 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1, c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ1" }, /* equalizer downlink path headset + earphone */ + /* EQ2L */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2, c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2L" }, /* equalizer downlink path integrated handsfree LEFT */ + /* EQ2R */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2R"}, /* equalizer downlink path integrated handsfree RIGHT */ + /* EQSDT */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQSDT" }, /* equalizer downlink path side-tone */ + /* EQDMIC1 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC1" }, /* SRC+equalizer uplink DMIC 1st pair */ + /* EQDMIC2 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC2" }, /* SRC+equalizer uplink DMIC 2nd pair */ + /* EQDMIC3 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC3" }, /* SRC+equalizer uplink DMIC 3rd pair */ + /* EQAMIC */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQAMIC" }, /* SRC+equalizer uplink AMIC */ + /* APS1 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " APS1" }, /* Acoustic protection for headset */ + /* APS2 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS2" }, /* acoustic protection high-pass filter for handsfree "Left" */ + /* APS3 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS3" }, /* acoustic protection high-pass filter for handsfree "Right" */ + /* ASRC1 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXDL" }, /* asynchronous sample-rate-converter for the downlink voice path */ + /* ASRC2 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXUL" }, /* asynchronous sample-rate-converter for the uplink voice path */ + /* ASRC3 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," ASRC_MMDL" }, /* asynchronous sample-rate-converter for the multimedia player */ + /* ASRC4 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_ECHO" }, /* asynchronous sample-rate-converter for the echo reference */ + /* MXDL1 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " MIX_DL1" }, /* mixer of the headset and earphone path */ + /* MXDL2 */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," MIX_DL2" }, /* mixer of the hands-free path */ + /* MXAUDUL */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXSAUDUL" }, /* mixer for uplink tone mixer */ + /* MXVXREC */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXVXREC" }, /* mixer for voice recording */ + /* MXSDT */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_SDT" }, /* mixer for side-tone */ + /* MXECHO */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_ECHO" }, /* mixer for echo reference */ + /* UPROUTE */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " DLEQ3" }, /* router of the uplink path */ + /* GAINS */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" }, /* all gains */ + /* EANC */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ3" }, /* active noise canceller */ + /* SEQ */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" }, /* sequencing queue of micro tasks */ + /* CTL */ { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3" }, /* Phoenix control queue through McPDM */ + }; -/* - * AESS/ATC destination and source address translation - * (except McASPs) from the original 64bits words address - */ -const abe_uint32 abe_atc_dstid[ABE_ATC_DESC_SIZE >> 3] = { - /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0-7 */ - 0, 0, 12, 0, 1, 0, 2, 0, - /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8-15 */ - 3, 0, 4, 5, 6, 7, 8, 9, - /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16-23 */ - 10, 11, 0, 0, 0, 0, 0, 0, - /* SLIMR6 SLIMR7 McASP1X ------ ------ McASP1R ----- ------ 24-31 */ - 0, 0, 14, 0, 0, 0, 0, 0, - /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32-39 */ - 63, 63, 63, 63, 63, 63, 63, 63, - /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40-47 */ - 0, 0, 0, 0, 0, 0, 0, 0, - /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15 48-63 */ - 0, 0, 0, 0, 0, 0, 0, 0, -}; -const abe_uint32 abe_atc_srcid[ABE_ATC_DESC_SIZE >> 3] = { - /* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0-7 */ - 0, 12, 0, 13, 0, 1, 0, 2, - /* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8-15 */ - 0, 3, 0, 0, 0, 0, 0, 0, - /* SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16-23 */ - 0, 0, 4, 5, 6, 7, 8, 9, - /* SLIMR6 SLIMR7 McASP1X ------ ------ McASP1R ------ ------ 24-31 */ - 10, 11, 0, 0, 0, 14, 0, 0, - /* CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32-39 */ - 63, 63, 63, 63, 63, 63, 63, 63, - /* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40-47 */ - 0, 0, 0, 0, 0, 0, 0, 0, - /* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15 48-63 */ - 0, 0, 0, 0, 0, 0, 0, 0, -}; /* - * preset default routing configurations - * This is given as implementation EXAMPLES - * the programmer uses "abe_set_router_configuration" with its own tables -*/ -const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL] = { - /* Voice uplink with Phoenix microphones - Uproute config_dmic1 */ - { - /* 0 .. 9 = MM_UL */ - DMIC1_L_labelID, - DMIC1_R_labelID, - DMIC2_L_labelID, - DMIC2_R_labelID, - MM_EXT_IN_L_labelID, - MM_EXT_IN_R_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - /* 10 .. 11 = MM_UL2 */ - AMIC_L_labelID, - AMIC_R_labelID, - /* 12 .. 13 = VX_UL */ - AMIC_L_labelID, - AMIC_R_labelID, - /* 14 .. 15 = RESERVED */ - ZERO_labelID, - ZERO_labelID, - }, - /* Voice uplink with the first DMIC pair - Uproute config_dmic2 */ - { - /* 0 .. 9 = MM_UL */ - DMIC2_L_labelID, - DMIC2_R_labelID, - DMIC3_L_labelID, - DMIC3_R_labelID, - DMIC1_L_labelID, - DMIC1_R_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - /* 10 .. 11 = MM_UL2 */ - DMIC1_L_labelID, - DMIC1_R_labelID, - /* 12 .. 13 = VX_UL */ - DMIC1_L_labelID, - DMIC1_R_labelID, - /* 14 .. 15 = RESERVED */ - ZERO_labelID, - ZERO_labelID, - }, - /* Voice uplink with the second DMIC pair - Uproute config_dmic3 */ - { - /* 0 .. 9 = MM_UL */ - DMIC3_L_labelID, - DMIC3_R_labelID, - DMIC1_L_labelID, - DMIC1_R_labelID, - DMIC2_L_labelID, - DMIC2_R_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - /* 10 .. 11 = MM_UL2 */ - DMIC2_L_labelID, - DMIC2_R_labelID, - /* 12 .. 13 = VX_UL */ - DMIC2_L_labelID, - DMIC2_R_labelID, - /* 14 .. 15 = RESERVED */ - ZERO_labelID, - ZERO_labelID, - }, - /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */ - { - AMIC_L_labelID, /* 0 .. 9 = MM_UL */ - AMIC_R_labelID, - DMIC2_L_labelID, - DMIC2_R_labelID, - DMIC3_L_labelID, - DMIC3_R_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - ZERO_labelID, - DMIC3_L_labelID, - DMIC3_R_labelID, /* 10 .. 11 = MM_UL2 */ - DMIC3_L_labelID, - DMIC3_R_labelID, /* 12 .. 13 = VX_UL */ - ZERO_labelID, - ZERO_labelID, /* 14 .. 15 = RESERVED */ - }, - /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */ - { - BT_UL_L_labelID, - BT_UL_R_labelID, - DMIC2_L_labelID, - DMIC2_R_labelID, /* 0 .. 9 = MM_UL */ - DMIC3_L_labelID, - DMIC3_R_labelID, - DMIC1_L_labelID, - DMIC1_R_labelID, - ZERO_labelID, - ZERO_labelID, - AMIC_L_labelID, - AMIC_R_labelID, /* 10 .. 11 = MM_UL2 */ - BT_UL_L_labelID, - BT_UL_R_labelID, /* 12 .. 13 = VX_UL */ - ZERO_labelID, - ZERO_labelID, /* 14 .. 15 = RESERVED */ - }, -}; - -/* all default routing configurations */ -abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL]; + * MEMORY MAPPING OF THE DMEM FIFOs + */ + +abe_uint32 abe_map_dmem [LAST_PORT_ID]; /* DMEM port map */ +abe_uint32 abe_map_dmem_secondary [LAST_PORT_ID]; +abe_uint32 abe_map_dmem_size [LAST_PORT_ID]; /* DMEM port buffer sizes */ + /* - * ABE_GLOBAL DATA + * AESS/ATC destination and source address translation (except McASPs) from the original 64bits words address */ -/* flag, indicates the allowed control of Phoenix through McPDM slot 6 */ -abe_uint32 abe_global_mcpdm_control; +const abe_uint32 abe_atc_dstid [ABE_ATC_DESC_SIZE>>3] = + { + // DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 + 0, 0, 12, 0, 1, 0, 2, 0, + // McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 + 3, 0, 4, 5, 6, 7, 8, 9, + // SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 + 10, 11, 0, 0, 0, 0, 0, 0, + // SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 + 0, 0, 14, 0, 0, 0, 0, 0, + // CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 + 63, 63, 63, 63, 63, 63, 63, 63, + // CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 + 0, 0, 0, 0, 0, 0, 0, 0, + // CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15 48 .. 63 + 0, 0, 0, 0, 0, 0, 0, 0, + }; +const abe_uint32 abe_atc_srcid [ABE_ATC_DESC_SIZE>>3] = + { + // DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 + 0, 12, 0, 13, 0, 1, 0, 2, + // McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 + 0, 3, 0, 0, 0, 0, 0, 0, + // SLIMT6 SLIMT7 SLIMR0 SLIMR1 SLIMR2 SLIMR3 SLIMR4 SLIMR5 16 .. 23 + 0, 0, 4, 5, 6, 7, 8, 9, + // SLIMR6 SLIMR7 McASP1X ----- ----- McASP1R ----- ----- 24 .. 31 + 10, 11, 0, 0, 0, 14, 0, 0, + // CBPrT0 CBPrT1 CBPrT2 CBPrT3 CBPrT4 CBPrT5 CBPrT6 CBPrT7 32 .. 39 + 63, 63, 63, 63, 63, 63, 63, 63, + // CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 + 0, 0, 0, 0, 0, 0, 0, 0, + // CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15 48 .. 63 + 0, 0, 0, 0, 0, 0, 0, 0, + }; + + +/* ------------------------------------------------------------------------- + preset default routing configurations + This is given as implementation EXAMPLES + the programmer uses "abe_set_router_configuration" with its own tables +*/ + +const abe_router_t abe_router_ul_table_preset [NBROUTE_CONFIG][NBROUTE_UL] = + { { /* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */ + DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, /* 0 .. 9 = MM_UL */ + MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, /* 10 .. 11 = MM_UL2 */ + AMIC_L_labelID, AMIC_R_labelID, /* 12 .. 13 = VX_UL */ + ZERO_labelID, ZERO_labelID, /* 14 .. 15 = RESERVED */ + }, + { /* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1*/ + DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID, /* 0 .. 9 = MM_UL */ + DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + DMIC1_L_labelID, DMIC1_R_labelID, /* 10 .. 11 = MM_UL2 */ + DMIC1_L_labelID, DMIC1_R_labelID, /* 12 .. 13 = VX_UL */ + ZERO_labelID, ZERO_labelID, /* 14 .. 15 = RESERVED */ + }, + { /* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */ + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, /* 0 .. 9 = MM_UL */ + DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + DMIC2_L_labelID, DMIC2_R_labelID, /* 10 .. 11 = MM_UL2 */ + DMIC2_L_labelID, DMIC2_R_labelID, /* 12 .. 13 = VX_UL */ + ZERO_labelID, ZERO_labelID, /* 14 .. 15 = RESERVED */ + }, + { /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */ + AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, /* 0 .. 9 = MM_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID, + ZERO_labelID, ZERO_labelID, + DMIC3_L_labelID, DMIC3_R_labelID, /* 10 .. 11 = MM_UL2 */ + DMIC3_L_labelID, DMIC3_R_labelID, /* 12 .. 13 = VX_UL */ + ZERO_labelID, ZERO_labelID, /* 14 .. 15 = RESERVED */ + }, + { /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */ + BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID, /* 0 .. 9 = MM_UL */ + DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID, + ZERO_labelID, ZERO_labelID, + AMIC_L_labelID, AMIC_R_labelID, /* 10 .. 11 = MM_UL2 */ + BT_UL_L_labelID, BT_UL_R_labelID, /* 12 .. 13 = VX_UL */ + ZERO_labelID, ZERO_labelID, /* 14 .. 15 = RESERVED */ + }, + }; + +abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL]; /* all default routing configurations */ + +/* + * ABE_GLOBAL DATA ------------------------------------------------------------------------- + */ + +abe_uint32 abe_global_mcpdm_control; /* flag, indicates the allowed control of Phoenix through McPDM slot #6 */ abe_event_id abe_current_event_id; -/* - * ABE SUBROUTINES AND SEQUENCES +/* + * ABE SUBROUTINES AND SEQUENCES ----------------------------------------------------------- */ + /* -const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] = - {{0, 0, 0, 0}, {-1, 0, 0, 0}}, - {{0, 0, 0, 0}, {-1, 0, 0, 0}}, +const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] = + {{0, 0, 0, 0}, {-1, 0, 0, 0}}, + {{0, 0, 0, 0}, {-1, 0, 0, 0}}, const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1, 0, 0, 0, 0, - -1, C_CALLBACK1, 0, 0, 0, 0 }; + -1, C_CALLBACK1, 0, 0, 0, 0 }; -const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] = - abe_init_atc, 0, 0, - abe_init_atc, 0, 0, +const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] = + abe_init_atc, 0, 0, + abe_init_atc, 0, 0, typedef double (*PtrFun) (double); PtrFun pFun; pFun = sin; -y = (* pFun) (x); -*/ +y = (* pFun) (x); +*/ /* mask, { time id param tag1} */ +const abe_sequence_t seq_null = {NOMASK, {CL_M1, 0, 0,0,0,0, 0 }, {CL_M1, 0, 0,0,0,0, 0 } }; + +abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE]; /* table of new subroutines called in the sequence */ +abe_uint32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE]; /* number of parameters per calls */ +abe_uint32 abe_subroutine_id [MAXNBSUBROUTINE]; /* index of the subroutine */ +abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE]; /* paramters of the subroutine (if any) */ +abe_uint32 abe_subroutine_write_pointer; + +abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; /* table of all sequences */ +abe_uint32 abe_sequence_write_pointer; +abe_uint32 abe_nb_pending_sequences; /* current number of pending sequences (avoids to look in the table) */ +abe_uint32 abe_pending_sequences [MAXNBSEQUENCE]; /* pending sequences due to ressource collision */ + +abe_uint32 abe_global_sequence_mask; /* mask of unsharable ressources among other sequences */ + +abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS]; /* table of active sequences */ + +abe_uint32 abe_irq_pingpong_player_id; /* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */ +abe_uint32 abe_irq_aps_adaptation_id; /* index of the plugged subroutine doing acoustics protection adaptation */ + +abe_uint32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS]; /* base addresses of the ping pong buffers in bytes addresses */ +abe_uint32 abe_size_pingpong; /* size of each ping/pong buffers */ +abe_uint32 abe_nb_pingpong; /* number of ping/pong buffer being used */ + +/* @!!! in "ABE_SPingPongDescriptor", the offset address of the field + "nextbuff0_BaseAddr" must be aligned on 32bits boundaries + typedef struct abepingpongdescriptorTag{ + ... + ABE_uint16 workbuff_BaseAddr; 12 * current Base address of the working buffer + ABE_uint16 workbuff_Samples; 14 * samples left in the working buffer * + ABE_uint16 nextbuff0_BaseAddr; 16 * Base address of the pingpong buffer 0 * + ABE_uint16 nextbuff0_Samples; 18 * samples available in the pingpong buffer 0 * + ABE_uint16 nextbuff1_BaseAddr; 20 * Base address of the pingpong buffer 1 * + ABE_uint16 nextbuff1_Samples; 22 * samples available in the pingpong buffer 1 * + } ABE_SPingPongDescriptor; + */ + + +/* + * ABE CONST AREA FOR PARAMETERS TRANSLATION ------------------------------------------------------- + */ +const abe_uint32 abe_db2lin_table [sizeof_db2lin_table] = { -const abe_sequence_t seq_null = { - NOMASK, - { - CL_M1, - 0, - {0, 0, 0, 0}, - 0, - }, - { - CL_M1, - 0, - {0, 0, 0, 0}, - 0, - }, + 0x00000000, /* SMEM coding of -120 dB */ + 0x00000000, /* SMEM coding of -119 dB */ + 0x00000000, /* SMEM coding of -118 dB */ + 0x00000000, /* SMEM coding of -117 dB */ + 0x00000000, /* SMEM coding of -116 dB */ + 0x00000000, /* SMEM coding of -115 dB */ + 0x00000000, /* SMEM coding of -114 dB */ + 0x00000000, /* SMEM coding of -113 dB */ + 0x00000000, /* SMEM coding of -112 dB */ + 0x00000000, /* SMEM coding of -111 dB */ + 0x00000000, /* SMEM coding of -110 dB */ + 0x00000000, /* SMEM coding of -109 dB */ + 0x00000001, /* SMEM coding of -108 dB */ + 0x00000001, /* SMEM coding of -107 dB */ + 0x00000001, /* SMEM coding of -106 dB */ + 0x00000001, /* SMEM coding of -105 dB */ + 0x00000001, /* SMEM coding of -104 dB */ + 0x00000001, /* SMEM coding of -103 dB */ + 0x00000002, /* SMEM coding of -102 dB */ + 0x00000002, /* SMEM coding of -101 dB */ + 0x00000002, /* SMEM coding of -100 dB */ + 0x00000002, /* SMEM coding of -99 dB */ + 0x00000003, /* SMEM coding of -98 dB */ + 0x00000003, /* SMEM coding of -97 dB */ + 0x00000004, /* SMEM coding of -96 dB */ + 0x00000004, /* SMEM coding of -95 dB */ + 0x00000005, /* SMEM coding of -94 dB */ + 0x00000005, /* SMEM coding of -93 dB */ + 0x00000006, /* SMEM coding of -92 dB */ + 0x00000007, /* SMEM coding of -91 dB */ + 0x00000008, /* SMEM coding of -90 dB */ + 0x00000009, /* SMEM coding of -89 dB */ + 0x0000000A, /* SMEM coding of -88 dB */ + 0x0000000B, /* SMEM coding of -87 dB */ + 0x0000000D, /* SMEM coding of -86 dB */ + 0x0000000E, /* SMEM coding of -85 dB */ + 0x00000010, /* SMEM coding of -84 dB */ + 0x00000012, /* SMEM coding of -83 dB */ + 0x00000014, /* SMEM coding of -82 dB */ + 0x00000017, /* SMEM coding of -81 dB */ + 0x0000001A, /* SMEM coding of -80 dB */ + 0x0000001D, /* SMEM coding of -79 dB */ + 0x00000021, /* SMEM coding of -78 dB */ + 0x00000025, /* SMEM coding of -77 dB */ + 0x00000029, /* SMEM coding of -76 dB */ + 0x0000002E, /* SMEM coding of -75 dB */ + 0x00000034, /* SMEM coding of -74 dB */ + 0x0000003A, /* SMEM coding of -73 dB */ + 0x00000041, /* SMEM coding of -72 dB */ + 0x00000049, /* SMEM coding of -71 dB */ + 0x00000052, /* SMEM coding of -70 dB */ + 0x0000005D, /* SMEM coding of -69 dB */ + 0x00000068, /* SMEM coding of -68 dB */ + 0x00000075, /* SMEM coding of -67 dB */ + 0x00000083, /* SMEM coding of -66 dB */ + 0x00000093, /* SMEM coding of -65 dB */ + 0x000000A5, /* SMEM coding of -64 dB */ + 0x000000B9, /* SMEM coding of -63 dB */ + 0x000000D0, /* SMEM coding of -62 dB */ + 0x000000E9, /* SMEM coding of -61 dB */ + 0x00000106, /* SMEM coding of -60 dB */ + 0x00000126, /* SMEM coding of -59 dB */ + 0x0000014A, /* SMEM coding of -58 dB */ + 0x00000172, /* SMEM coding of -57 dB */ + 0x0000019F, /* SMEM coding of -56 dB */ + 0x000001D2, /* SMEM coding of -55 dB */ + 0x0000020B, /* SMEM coding of -54 dB */ + 0x0000024A, /* SMEM coding of -53 dB */ + 0x00000292, /* SMEM coding of -52 dB */ + 0x000002E2, /* SMEM coding of -51 dB */ + 0x0000033C, /* SMEM coding of -50 dB */ + 0x000003A2, /* SMEM coding of -49 dB */ + 0x00000413, /* SMEM coding of -48 dB */ + 0x00000492, /* SMEM coding of -47 dB */ + 0x00000521, /* SMEM coding of -46 dB */ + 0x000005C2, /* SMEM coding of -45 dB */ + 0x00000676, /* SMEM coding of -44 dB */ + 0x0000073F, /* SMEM coding of -43 dB */ + 0x00000822, /* SMEM coding of -42 dB */ + 0x00000920, /* SMEM coding of -41 dB */ + 0x00000A3D, /* SMEM coding of -40 dB */ + 0x00000B7D, /* SMEM coding of -39 dB */ + 0x00000CE4, /* SMEM coding of -38 dB */ + 0x00000E76, /* SMEM coding of -37 dB */ + 0x0000103A, /* SMEM coding of -36 dB */ + 0x00001235, /* SMEM coding of -35 dB */ + 0x0000146E, /* SMEM coding of -34 dB */ + 0x000016EC, /* SMEM coding of -33 dB */ + 0x000019B8, /* SMEM coding of -32 dB */ + 0x00001CDC, /* SMEM coding of -31 dB */ + 0x00002061, /* SMEM coding of -30 dB */ + 0x00002455, /* SMEM coding of -29 dB */ + 0x000028C4, /* SMEM coding of -28 dB */ + 0x00002DBD, /* SMEM coding of -27 dB */ + 0x00003352, /* SMEM coding of -26 dB */ + 0x00003995, /* SMEM coding of -25 dB */ + 0x0000409C, /* SMEM coding of -24 dB */ + 0x0000487E, /* SMEM coding of -23 dB */ + 0x00005156, /* SMEM coding of -22 dB */ + 0x00005B43, /* SMEM coding of -21 dB */ + 0x00006666, /* SMEM coding of -20 dB */ + 0x000072E5, /* SMEM coding of -19 dB */ + 0x000080E9, /* SMEM coding of -18 dB */ + 0x000090A4, /* SMEM coding of -17 dB */ + 0x0000A24B, /* SMEM coding of -16 dB */ + 0x0000B618, /* SMEM coding of -15 dB */ + 0x0000CC50, /* SMEM coding of -14 dB */ + 0x0000E53E, /* SMEM coding of -13 dB */ + 0x00010137, /* SMEM coding of -12 dB */ + 0x0001209A, /* SMEM coding of -11 dB */ + 0x000143D1, /* SMEM coding of -10 dB */ + 0x00016B54, /* SMEM coding of -9 dB */ + 0x000197A9, /* SMEM coding of -8 dB */ + 0x0001C967, /* SMEM coding of -7 dB */ + 0x00020137, /* SMEM coding of -6 dB */ + 0x00023FD6, /* SMEM coding of -5 dB */ + 0x00028619, /* SMEM coding of -4 dB */ + 0x0002D4EF, /* SMEM coding of -3 dB */ + 0x00032D64, /* SMEM coding of -2 dB */ + 0x000390A4, /* SMEM coding of -1 dB */ + 0x00040000, /* SMEM coding of 0 dB */ + 0x00047CF2, /* SMEM coding of 1 dB */ + 0x00050923, /* SMEM coding of 2 dB */ + 0x0005A670, /* SMEM coding of 3 dB */ + 0x000656EE, /* SMEM coding of 4 dB */ + 0x00071CF5, /* SMEM coding of 5 dB */ + 0x0007FB26, /* SMEM coding of 6 dB */ + 0x0008F473, /* SMEM coding of 7 dB */ + 0x000A0C2B, /* SMEM coding of 8 dB */ + 0x000B4606, /* SMEM coding of 9 dB */ + 0x000CA62C, /* SMEM coding of 10 dB */ + 0x000E314A, /* SMEM coding of 11 dB */ + 0x000FEC9E, /* SMEM coding of 12 dB */ + 0x0011DE0A, /* SMEM coding of 13 dB */ + 0x00140C28, /* SMEM coding of 14 dB */ + 0x00167E60, /* SMEM coding of 15 dB */ + 0x00193D00, /* SMEM coding of 16 dB */ + 0x001C515D, /* SMEM coding of 17 dB */ + 0x001FC5EB, /* SMEM coding of 18 dB */ + 0x0023A668, /* SMEM coding of 19 dB */ + 0x00280000, /* SMEM coding of 20 dB */ + 0x002CE178, /* SMEM coding of 21 dB */ + 0x00325B65, /* SMEM coding of 22 dB */ + 0x00388062, /* SMEM coding of 23 dB */ + 0x003F654E, /* SMEM coding of 24 dB */ + 0x00472194, /* SMEM coding of 25 dB */ + 0x004FCF7C, /* SMEM coding of 26 dB */ + 0x00598C81, /* SMEM coding of 27 dB */ + 0x006479B7, /* SMEM coding of 28 dB */ + 0x0070BC3D, /* SMEM coding of 29 dB */ + 0x007E7DB9, /* SMEM coding of 30 dB */ + + }; + +const abe_uint32 abe_1_alpha_iir [64] = { + 0x040002, 0x040002, 0x040002, 0x040002, // 0 + 0x50E955, 0x48CA65, 0x40E321, 0x72BE78, // 1 [ms] + 0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, // 2 + 0x38A084, 0x308974, 0x297B00, 0x235C7C, // 4 + 0x1E14B0, 0x198AF0, 0x15A800, 0x125660, // 8 + 0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, // 16 + 0x07E054, 0x06A3B8, 0x059844, 0x04B680, // 32 + 0x03F80C, 0x035774, 0x02D018, 0x025E0C, // 64 + 0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, // 128 + 0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, // 256 + 0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, // 512 + 0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, //1.024 [s] + 0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, //2.048 + 0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, //4.096 + 0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, //8.192 + 0x00FFFF, 0x00D743, 0x00B503, 0x009837, }; -/* table of new subroutines called in the sequence */ -abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE]; -/* number of parameters per calls */ -abe_uint32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE]; -/* index of the subroutine */ -abe_uint32 abe_subroutine_id[MAXNBSUBROUTINE]; -abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE]; -abe_uint32 abe_subroutine_write_pointer; - -/* table of all sequences */ -abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; - -abe_uint32 abe_sequence_write_pointer; - -/* current number of pending sequences (avoids to look in the table) */ -abe_uint32 abe_nb_pending_sequences; - -/* pending sequences due to ressource collision */ -abe_uint32 abe_pending_sequences[MAXNBSEQUENCE]; - -/* mask of unsharable ressources among other sequences */ -abe_uint32 abe_global_sequence_mask; - -/* table of active sequences */ -abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS]; - -/* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */ -abe_uint32 abe_irq_pingpong_player_id; -/* index of the plugged subroutine doing acoustics protection adaptation */ -abe_uint32 abe_irq_aps_adaptation_id; - -/* base addresses of the ping pong buffers in bytes addresses */ -abe_uint32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS]; - -/* size of each ping/pong buffers */ -abe_uint32 abe_size_pingpong; - -/* number of ping/pong buffer being used */ -abe_uint32 abe_nb_pingpong; +const abe_uint32 abe_alpha_iir [64] = { + 0x000000, 0x000000, 0x000000, 0x000000, // 0 + 0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, // 1 [ms] + 0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, // 2 + 0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, // 4 + 0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, // 8 + 0x783EB1, 0x797251, 0x7A7761, 0x7B549D, // 16 + 0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, // 32 + 0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, // 64 + 0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, // 128 + 0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, // 256 + 0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, // 512 + 0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, //1.024 [s] + 0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, //2.048 + 0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, //4.096 + 0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, //8.192 + 0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1, + }; + +/* + * ABE_DEBUG DATA ------------------------------------------------------------------------- + */ /* - * ABE CONST AREA FOR PARAMETERS TRANSLATION + * IRQ and trace pointer in DMEM: + * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL */ -const abe_uint32 abe_db2lin_table [sizeof_db2lin_table] = { - 0x00000000, /* SMEM coding of -120 dB */ - 0x00000000, /* SMEM coding of -119 dB */ - 0x00000000, /* SMEM coding of -118 dB */ - 0x00000000, /* SMEM coding of -117 dB */ - 0x00000000, /* SMEM coding of -116 dB */ - 0x00000000, /* SMEM coding of -115 dB */ - 0x00000000, /* SMEM coding of -114 dB */ - 0x00000000, /* SMEM coding of -113 dB */ - 0x00000000, /* SMEM coding of -112 dB */ - 0x00000000, /* SMEM coding of -111 dB */ - 0x00000000, /* SMEM coding of -110 dB */ - 0x00000000, /* SMEM coding of -109 dB */ - 0x00000001, /* SMEM coding of -108 dB */ - 0x00000001, /* SMEM coding of -107 dB */ - 0x00000001, /* SMEM coding of -106 dB */ - 0x00000001, /* SMEM coding of -105 dB */ - 0x00000001, /* SMEM coding of -104 dB */ - 0x00000001, /* SMEM coding of -103 dB */ - 0x00000002, /* SMEM coding of -102 dB */ - 0x00000002, /* SMEM coding of -101 dB */ - 0x00000002, /* SMEM coding of -100 dB */ - 0x00000002, /* SMEM coding of -99 dB */ - 0x00000003, /* SMEM coding of -98 dB */ - 0x00000003, /* SMEM coding of -97 dB */ - 0x00000004, /* SMEM coding of -96 dB */ - 0x00000004, /* SMEM coding of -95 dB */ - 0x00000005, /* SMEM coding of -94 dB */ - 0x00000005, /* SMEM coding of -93 dB */ - 0x00000006, /* SMEM coding of -92 dB */ - 0x00000007, /* SMEM coding of -91 dB */ - 0x00000008, /* SMEM coding of -90 dB */ - 0x00000009, /* SMEM coding of -89 dB */ - 0x0000000A, /* SMEM coding of -88 dB */ - 0x0000000B, /* SMEM coding of -87 dB */ - 0x0000000D, /* SMEM coding of -86 dB */ - 0x0000000E, /* SMEM coding of -85 dB */ - 0x00000010, /* SMEM coding of -84 dB */ - 0x00000012, /* SMEM coding of -83 dB */ - 0x00000014, /* SMEM coding of -82 dB */ - 0x00000017, /* SMEM coding of -81 dB */ - 0x0000001A, /* SMEM coding of -80 dB */ - 0x0000001D, /* SMEM coding of -79 dB */ - 0x00000021, /* SMEM coding of -78 dB */ - 0x00000025, /* SMEM coding of -77 dB */ - 0x00000029, /* SMEM coding of -76 dB */ - 0x0000002E, /* SMEM coding of -75 dB */ - 0x00000034, /* SMEM coding of -74 dB */ - 0x0000003A, /* SMEM coding of -73 dB */ - 0x00000041, /* SMEM coding of -72 dB */ - 0x00000049, /* SMEM coding of -71 dB */ - 0x00000052, /* SMEM coding of -70 dB */ - 0x0000005D, /* SMEM coding of -69 dB */ - 0x00000068, /* SMEM coding of -68 dB */ - 0x00000075, /* SMEM coding of -67 dB */ - 0x00000083, /* SMEM coding of -66 dB */ - 0x00000093, /* SMEM coding of -65 dB */ - 0x000000A5, /* SMEM coding of -64 dB */ - 0x000000B9, /* SMEM coding of -63 dB */ - 0x000000D0, /* SMEM coding of -62 dB */ - 0x000000E9, /* SMEM coding of -61 dB */ - 0x00000106, /* SMEM coding of -60 dB */ - 0x00000126, /* SMEM coding of -59 dB */ - 0x0000014A, /* SMEM coding of -58 dB */ - 0x00000172, /* SMEM coding of -57 dB */ - 0x0000019F, /* SMEM coding of -56 dB */ - 0x000001D2, /* SMEM coding of -55 dB */ - 0x0000020B, /* SMEM coding of -54 dB */ - 0x0000024A, /* SMEM coding of -53 dB */ - 0x00000292, /* SMEM coding of -52 dB */ - 0x000002E2, /* SMEM coding of -51 dB */ - 0x0000033C, /* SMEM coding of -50 dB */ - 0x000003A2, /* SMEM coding of -49 dB */ - 0x00000413, /* SMEM coding of -48 dB */ - 0x00000492, /* SMEM coding of -47 dB */ - 0x00000521, /* SMEM coding of -46 dB */ - 0x000005C2, /* SMEM coding of -45 dB */ - 0x00000676, /* SMEM coding of -44 dB */ - 0x0000073F, /* SMEM coding of -43 dB */ - 0x00000822, /* SMEM coding of -42 dB */ - 0x00000920, /* SMEM coding of -41 dB */ - 0x00000A3D, /* SMEM coding of -40 dB */ - 0x00000B7D, /* SMEM coding of -39 dB */ - 0x00000CE4, /* SMEM coding of -38 dB */ - 0x00000E76, /* SMEM coding of -37 dB */ - 0x0000103A, /* SMEM coding of -36 dB */ - 0x00001235, /* SMEM coding of -35 dB */ - 0x0000146E, /* SMEM coding of -34 dB */ - 0x000016EC, /* SMEM coding of -33 dB */ - 0x000019B8, /* SMEM coding of -32 dB */ - 0x00001CDC, /* SMEM coding of -31 dB */ - 0x00002061, /* SMEM coding of -30 dB */ - 0x00002455, /* SMEM coding of -29 dB */ - 0x000028C4, /* SMEM coding of -28 dB */ - 0x00002DBD, /* SMEM coding of -27 dB */ - 0x00003352, /* SMEM coding of -26 dB */ - 0x00003995, /* SMEM coding of -25 dB */ - 0x0000409C, /* SMEM coding of -24 dB */ - 0x0000487E, /* SMEM coding of -23 dB */ - 0x00005156, /* SMEM coding of -22 dB */ - 0x00005B43, /* SMEM coding of -21 dB */ - 0x00006666, /* SMEM coding of -20 dB */ - 0x000072E5, /* SMEM coding of -19 dB */ - 0x000080E9, /* SMEM coding of -18 dB */ - 0x000090A4, /* SMEM coding of -17 dB */ - 0x0000A24B, /* SMEM coding of -16 dB */ - 0x0000B618, /* SMEM coding of -15 dB */ - 0x0000CC50, /* SMEM coding of -14 dB */ - 0x0000E53E, /* SMEM coding of -13 dB */ - 0x00010137, /* SMEM coding of -12 dB */ - 0x0001209A, /* SMEM coding of -11 dB */ - 0x000143D1, /* SMEM coding of -10 dB */ - 0x00016B54, /* SMEM coding of -9 dB */ - 0x000197A9, /* SMEM coding of -8 dB */ - 0x0001C967, /* SMEM coding of -7 dB */ - 0x00020137, /* SMEM coding of -6 dB */ - 0x00023FD6, /* SMEM coding of -5 dB */ - 0x00028619, /* SMEM coding of -4 dB */ - 0x0002D4EF, /* SMEM coding of -3 dB */ - 0x00032D64, /* SMEM coding of -2 dB */ - 0x000390A4, /* SMEM coding of -1 dB */ - 0x00040000, /* SMEM coding of 0 dB */ - 0x00047CF2, /* SMEM coding of 1 dB */ - 0x00050923, /* SMEM coding of 2 dB */ - 0x0005A670, /* SMEM coding of 3 dB */ - 0x000656EE, /* SMEM coding of 4 dB */ - 0x00071CF5, /* SMEM coding of 5 dB */ - 0x0007FB26, /* SMEM coding of 6 dB */ - 0x0008F473, /* SMEM coding of 7 dB */ - 0x000A0C2B, /* SMEM coding of 8 dB */ - 0x000B4606, /* SMEM coding of 9 dB */ - 0x000CA62C, /* SMEM coding of 10 dB */ - 0x000E314A, /* SMEM coding of 11 dB */ - 0x000FEC9E, /* SMEM coding of 12 dB */ - 0x0011DE0A, /* SMEM coding of 13 dB */ - 0x00140C28, /* SMEM coding of 14 dB */ - 0x00167E60, /* SMEM coding of 15 dB */ - 0x00193D00, /* SMEM coding of 16 dB */ - 0x001C515D, /* SMEM coding of 17 dB */ - 0x001FC5EB, /* SMEM coding of 18 dB */ - 0x0023A668, /* SMEM coding of 19 dB */ - 0x00280000, /* SMEM coding of 20 dB */ - 0x002CE178, /* SMEM coding of 21 dB */ - 0x00325B65, /* SMEM coding of 22 dB */ - 0x00388062, /* SMEM coding of 23 dB */ - 0x003F654E, /* SMEM coding of 24 dB */ - 0x00472194, /* SMEM coding of 25 dB */ - 0x004FCF7C, /* SMEM coding of 26 dB */ - 0x00598C81, /* SMEM coding of 27 dB */ - 0x006479B7, /* SMEM coding of 28 dB */ - 0x0070BC3D, /* SMEM coding of 29 dB */ - 0x007E7DB9, /* SMEM coding of 30 dB */ -}; - +abe_uint32 abe_irq_dbg_read_ptr; -const abe_uint32 abe_sin_table [] = { 0 }; /* - * ABE_DEBUG DATA + * General circular buffer used to trace APIs calls and AE activity. */ +abe_uint32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof]; +abe_uint32 abe_dbg_activity_log_write_pointer; +abe_uint32 abe_dbg_mask; /* - * IRQ and trace pointer in DMEM: - * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL + * Global variable holding parameter errors */ -abe_uint32 abe_irq_dbg_read_ptr; -/* General circular buffer used to trace APIs calls and AE activity */ -abe_uint32 abe_dbg_activity_log[D_DEBUG_HAL_TASK_sizeof]; -abe_uint32 abe_dbg_activity_log_write_pointer; -abe_uint32 abe_dbg_mask; +abe_uint32 abe_dbg_param; -/* Global variable holding parameter errors */ -abe_uint32 abe_dbg_param; + +/* + * Output of messages selector + */ +abe_uint32 abe_dbg_output; -/* Output of messages selector */ -abe_uint32 abe_dbg_output; +/* + * last parameters + */ -/* Last parameters */ -#define SIZE_PARAM 10 +#define SIZE_PARAM 10 abe_uint32 param1[SIZE_PARAM]; abe_uint32 param2[SIZE_PARAM]; @@ -1327,24 +522,29 @@ abe_uint32 param3[SIZE_PARAM]; abe_uint32 param4[SIZE_PARAM]; abe_uint32 param5[SIZE_PARAM]; -volatile abe_uint32 just_to_avoid_the_many_warnings; -volatile abe_gain_t just_to_avoid_the_many_warnings_abe_gain_t; -volatile abe_ramp_t just_to_avoid_the_many_warnings_abe_ramp_t; -volatile abe_dma_t just_to_avoid_the_many_warnings_abe_dma_t; -volatile abe_port_id just_to_avoid_the_many_warnings_abe_port_id; -volatile abe_millis_t just_to_avoid_the_many_warnings_abe_millis_t; -volatile abe_micros_t just_to_avoid_the_many_warnings_abe_micros_t; -volatile abe_patch_rev just_to_avoid_the_many_warnings_abe_patch_rev; -volatile abe_sequence_t just_to_avoid_the_many_warnings_abe_sequence_t; -volatile abe_ana_port_id just_to_avoid_the_many_warnings_abe_ana_port_id; -volatile abe_time_stamp_t just_to_avoid_the_many_warnings_abe_time_stamp_t; -volatile abe_data_format_t just_to_avoid_the_many_warnings_abe_data_format_t; -volatile abe_port_protocol_t just_to_avoid_the_many_warnings_abe_port_protocol_t; -volatile abe_router_t just_to_avoid_the_many_warnings_abe_router_t; -volatile abe_router_id just_to_avoid_the_many_warnings_abe_router_id; +/* + * END ABE_DEBUG DATA ------------------------------------------------------------------------- + */ + +volatile abe_uint32 just_to_avoid_the_many_warnings; +volatile abe_gain_t just_to_avoid_the_many_warnings_abe_gain_t; +volatile abe_ramp_t just_to_avoid_the_many_warnings_abe_ramp_t; +volatile abe_dma_t just_to_avoid_the_many_warnings_abe_dma_t; +volatile abe_port_id just_to_avoid_the_many_warnings_abe_port_id; +volatile abe_millis_t just_to_avoid_the_many_warnings_abe_millis_t; +volatile abe_micros_t just_to_avoid_the_many_warnings_abe_micros_t; +volatile abe_patch_rev just_to_avoid_the_many_warnings_abe_patch_rev; +volatile abe_sequence_t just_to_avoid_the_many_warnings_abe_sequence_t; +volatile abe_ana_port_id just_to_avoid_the_many_warnings_abe_ana_port_id; +volatile abe_time_stamp_t just_to_avoid_the_many_warnings_abe_time_stamp_t; +volatile abe_data_format_t just_to_avoid_the_many_warnings_abe_data_format_t; +volatile abe_port_protocol_t just_to_avoid_the_many_warnings_abe_port_protocol_t; +volatile abe_router_t just_to_avoid_the_many_warnings_abe_router_t; +volatile abe_router_id just_to_avoid_the_many_warnings_abe_router_id; + #ifdef __cplusplus } #endif -#endif /* _ABE_DAT_H_ */ +#endif // abe_dat_def diff --git a/sound/soc/omap/abe/abe_dbg.c b/sound/soc/omap/abe/abe_dbg.c index 1592501aa7ac..ec0360f0661d 100644 --- a/sound/soc/omap/abe/abe_dbg.c +++ b/sound/soc/omap/abe/abe_dbg.c @@ -1,49 +1,70 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" - -/* - * ABE_DBG_LOG - * +/** + * abe_dbg_log - Log ABE trace inside circular buffer + * @x: data to be logged + * @y: data to be logged + * @z: data to be logged + * @t: data to be logged * Parameter : - * x : data to be logged * * abe_dbg_activity_log : global circular buffer holding the data * abe_dbg_activity_log_write_pointer : circular write pointer * - * Operations : * saves data in the log file - * - * Return value : - * none */ - -void abe_dbg_log(abe_uint32 x, abe_uint32 y, abe_uint32 z, abe_uint32 t) +void abe_dbg_log (u32 x, u32 y, u32 z, u32 t) { - abe_uint32 time_stamp, data; + u32 time_stamp, data; - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_loopCounter_ADDR, - (abe_uint32 *)&time_stamp, sizeof (time_stamp)); + if (abe_dbg_activity_log_write_pointer >= (D_DEBUG_HAL_TASK_sizeof - 2)) + abe_dbg_activity_log_write_pointer = 0; + + /* copy in DMEM trace buffer and CortexA9 local buffer and a small 7 + words circular buffer of the DMA trace ending with 0x55555555 + (tag for last word) */ + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_loopCounter_ADDR, + (u32 *)&time_stamp, sizeof (time_stamp)); abe_dbg_activity_log [abe_dbg_activity_log_write_pointer] = time_stamp; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + - (abe_dbg_activity_log_write_pointer<<2), - (abe_uint32 *)&time_stamp, sizeof (time_stamp)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + + (abe_dbg_activity_log_write_pointer<<2), (u32 *)&time_stamp, + sizeof (time_stamp)); abe_dbg_activity_log_write_pointer ++; - data = ((x&MAX_UINT8)<< 24) | ((y&MAX_UINT8)<< 16) | ((z&MAX_UINT8)<< 8) | (t&MAX_UINT8); - abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = data; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + - (abe_dbg_activity_log_write_pointer<<2), - (abe_uint32 *)&data, sizeof (data)); + data = ((x&MAX_UINT8)<< 24) | ((y&MAX_UINT8)<< 16) | ((z&MAX_UINT8)<< 8) + | (t&MAX_UINT8); + abe_dbg_activity_log [abe_dbg_activity_log_write_pointer] = data; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR + + (abe_dbg_activity_log_write_pointer<<2), (u32 *)&data, sizeof (data)); + + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR + + ((abe_dbg_activity_log_write_pointer<<2) & (D_DEBUG_FIFO_HAL_sizeof -1)), + (u32 *)&data, sizeof (data)); + data = ABE_DBG_MAGIC_NUMBER; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR + + (((abe_dbg_activity_log_write_pointer+1)<<2) & (D_DEBUG_FIFO_HAL_sizeof -1)), + (u32 *)&data, sizeof (data)); abe_dbg_activity_log_write_pointer ++; if (abe_dbg_activity_log_write_pointer >= D_DEBUG_HAL_TASK_sizeof) @@ -51,156 +72,135 @@ void abe_dbg_log(abe_uint32 x, abe_uint32 y, abe_uint32 z, abe_uint32 t) } -/* - * ABE_DEBUG_OUTPUT_PINS - * - * Parameter : - * x : d - * - * Operations : - * set the debug output pins of AESS - * - * Return value : +/** + * abe_debug_output_pins + * @x: d * + * set the debug output pins of AESS */ -void abe_debug_output_pins (abe_uint32 x) +void abe_debug_output_pins (u32 x) { -just_to_avoid_the_many_warnings = x; } - -/* - * ABE_DBG_ERROR_LOG - * - * Parameter : - * x : d - * - * Operations : - * log the error codes - * - * Return value : +/** + * abe_dbg_error_log - Log ABE error + * @x: error to log * + * log the error codes */ -void abe_dbg_error_log (abe_uint32 x) +void abe_dbg_error_log (u32 x) { abe_dbg_log (x, MAX_UINT8, MAX_UINT8, MAX_UINT8); } - -/* - * ABE_DEBUGGER - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : +/** + * abe_debugger + * @x: error to log * + * log error for debugger */ -void abe_debugger (abe_uint32 x) +void abe_debugger (u32 x) { -just_to_avoid_the_many_warnings = x; } - - - -/* - S = power (2, 31) * 0.25; - N = 4; B = 2; F=[1/N 1/N]; gen_and_save('dbg_8k_2.txt', B, F, N, S); - N = 8; B = 2; F=[1/N 2/N]; gen_and_save('dbg_16k_2.txt', B, F, N, S); - N = 12; B = 2; F=[1/N 2/N]; gen_and_save('dbg_48k_2.txt', B, F, N, S); - N = 60; B = 2; F=[4/N 8/N]; gen_and_save('dbg_amic.txt', B, F, N, S); - N = 10; B = 6; F=[1/N 2/N 3/N 1/N 2/N 3/N]; gen_and_save('dbg_dmic.txt', B, F, N, S); +/** + * abe_load_embeddded_patterns + * + * load test patterns + * + * S = power (2, 31) * 0.25; + * N = 4; B = 2; F=[1/N 1/N]; gen_and_save('dbg_8k_2.txt', B, F, N, S); + * N = 8; B = 2; F=[1/N 2/N]; gen_and_save('dbg_16k_2.txt', B, F, N, S); + * N = 12; B = 2; F=[1/N 2/N]; gen_and_save('dbg_48k_2.txt', B, F, N, S); + * N = 60; B = 2; F=[4/N 8/N]; gen_and_save('dbg_amic.txt', B, F, N, S); + * N = 10; B = 6; F=[1/N 2/N 3/N 1/N 2/N 3/N]; gen_and_save('dbg_dmic.txt', B, F, N, S); */ void abe_load_embeddded_patterns (void) { - abe_uint32 i; + u32 i; #define patterns_96k_len 48 -const long patterns_96k[patterns_96k_len] = { - 1620480, 1452800, - 1452800, 838656, - 1186304, 0, - 838656, -838912, - 434176, -1453056, - 0, -1677824, - -434432, -1453056, - -838912, -838912, - -1186560, -256, - -1453056, 838656, - -1620736, 1452800, - -1677824, 1677568, - -1620736, 1452800, - -1453056, 838656, - -1186560, 0, - -838912, -838912, - -434432, -1453056, - -256, -1677824, - 434176, -1453056, - 838656, -838912, - 1186304, -256, - 1452800, 838656, - 1620480, 1452800, - 1677568, 1677568, -}; + const long patterns_96k[patterns_96k_len] = { + 1620480, 1452800, + 1452800, 838656, + 1186304, 0, + 838656, -838912, + 434176, -1453056, + 0, -1677824, + -434432, -1453056, + -838912, -838912, + -1186560, -256, + -1453056, 838656, + -1620736, 1452800, + -1677824, 1677568, + -1620736, 1452800, + -1453056, 838656, + -1186560, 0, + -838912, -838912, + -434432, -1453056, + -256, -1677824, + 434176, -1453056, + 838656, -838912, + 1186304, -256, + 1452800, 838656, + 1620480, 1452800, + 1677568, 1677568, + }; #define patterns_48k_len 24 -const long patterns_48k[patterns_48k_len] = { - 1452800, 838656, - 838656, -838912, - 0, -1677824, - -838912, -838912, - -1453056, 838656, - -1677824, 1677568, - -1453056, 838656, - -838912, -838912, - -256, -1677824, - 838656, -838912, - 1452800, 838656, - 1677568, 1677568, -}; + const long patterns_48k[patterns_48k_len] = { + 1452800, 838656, + 838656, -838912, + 0, -1677824, + -838912, -838912, + -1453056, 838656, + -1677824, 1677568, + -1453056, 838656, + -838912, -838912, + -256, -1677824, + 838656, -838912, + 1452800, 838656, + 1677568, 1677568, + }; #define patterns_24k_len 12 const long patterns_24k[patterns_24k_len] = { - 838656, -838912, - -838912, -838912, - -1677824, 1677568, - -838912, -838912, - 838656, -838912, - 1677568, 1677568, -}; + 838656, -838912, + -838912, -838912, + -1677824, 1677568, + -838912, -838912, + 838656, -838912, + 1677568, 1677568, + }; #define patterns_16k_len 8 -const long patterns_16k[patterns_16k_len] = { - 0, 0, - -1677824, -1677824, - -256, -256, - 1677568, 1677568, -}; + const long patterns_16k[patterns_16k_len] = { + 0, 0, + -1677824, -1677824, + -256, -256, + 1677568, 1677568, + }; #define patterns_8k_len 4 -const long patterns_8k[patterns_8k_len] = { - 1677568, -1677824, - 1677568, 1677568, -}; + const long patterns_8k[patterns_8k_len] = { + 1677568, -1677824, + 1677568, 1677568, + }; for (i = 0; i < patterns_8k_len; i++) - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, - (S_DBG_8K_PATTERN_ADDR *8)+(i*4), - (abe_uint32 *)(&(patterns_8k[i])), 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_8K_PATTERN_ADDR *8)+(i*4), + (u32 *)(&(patterns_8k[i])), 4); for (i = 0; i < patterns_16k_len; i++) - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, - (S_DBG_16K_PATTERN_ADDR *8)+(i*4), - (abe_uint32 *)(&(patterns_16k[i])), 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_16K_PATTERN_ADDR *8)+(i*4), + (u32 *)(&(patterns_16k[i])), 4); for (i = 0; i < patterns_24k_len; i++) - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, - (S_DBG_24K_PATTERN_ADDR *8)+(i*4), - (abe_uint32 *)(&(patterns_24k[i])), 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_24K_PATTERN_ADDR *8)+(i*4), + (u32 *)(&(patterns_24k[i])), 4); for (i = 0; i < patterns_48k_len; i++) - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, - (S_DBG_48K_PATTERN_ADDR *8)+(i*4), - (abe_uint32 *)(&(patterns_48k[i])), 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_48K_PATTERN_ADDR *8)+(i*4), + (u32 *)(&(patterns_48k[i])), 4); for (i = 0; i < patterns_96k_len; i++) - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, - (S_DBG_96K_PATTERN_ADDR *8)+(i*4), - (abe_uint32 *)(&(patterns_96k[i])), 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, + (S_DBG_96K_PATTERN_ADDR *8)+(i*4), + (u32 *)(&(patterns_96k[i])), 4); } diff --git a/sound/soc/omap/abe/abe_dbg.h b/sound/soc/omap/abe/abe_dbg.h index 66a5f8907c55..8c28ee76895a 100644 --- a/sound/soc/omap/abe/abe_dbg.h +++ b/sound/soc/omap/abe/abe_dbg.h @@ -1,150 +1,170 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" -#ifdef __cplusplus -extern "C" { -#endif - /* * DEFINE */ -#define NO_OUTPUT 0 -#define TERMINAL_OUTPUT 1 -#define LINE_OUTPUT 2 -#define DEBUG_TRACE_OUTPUT 3 +#define NO_OUTPUT 0 +#define TERMINAL_OUTPUT 1 +#define LINE_OUTPUT 2 +#define DEBUG_TRACE_OUTPUT 3 /* * Debug trace format * TIME 2 bytes from ABE : 4kHz period of the FW scheduler * SUBID 1 byte : HAL API index - * From 0 to 16 bytes : parameters of the subroutine - * on every 32 dumps a tag is pushed on the debug trace : 0x55555555 + * From 0 to 16 bytes : parameters of the subroutine + * on every 32 dumps a tag is pushed on the debug trace : 0x55555555 */ -#define dbg_bitfield_offset 8 +#define dbg_bitfield_offset 8 -#define dbg_api_calls 0 -#define dbg_mapi (1L << (dbg_api_calls + dbg_bitfield_offset)) +#define dbg_api_calls 0 +#define dbg_mapi (1L << (dbg_api_calls + dbg_bitfield_offset)) -#define dbg_external_data_access 1 -#define dbg_mdata (1L << (dbg_external_data_access + dbg_bitfield_offset)) +#define dbg_external_data_access 1 +#define dbg_mdata (1L << (dbg_external_data_access + dbg_bitfield_offset)) -#define dbg_err_codes 2 -#define dbg_merr (1L << (dbg_api_calls + dbg_bitfield_offset)) +#define dbg_err_codes 2 +#define dbg_merr (1L << (dbg_api_calls + dbg_bitfield_offset)) + +#define ABE_DBG_MAGIC_NUMBER 0x55555555 /* * IDs used for traces */ -#define id_reset_hal (1 + dbg_mapi) -#define id_load_fw (2 + dbg_mapi) -#define id_default_configuration (3 + dbg_mapi) -#define id_irq_processing (4 + dbg_mapi) -#define id_event_generator_switch (5 + dbg_mapi) -#define id_read_hardware_configuration (6 + dbg_mapi) -#define id_read_lowest_opp (7 + dbg_mapi) -#define id_write_gain (8 + dbg_mapi) -#define id_set_asrc_drift_control (9 + dbg_mapi) -#define id_plug_subroutine (10 + dbg_mapi) -#define id_unplug_subroutine (11 + dbg_mapi) -#define id_plug_sequence (12 + dbg_mapi) -#define id_launch_sequence (13 + dbg_mapi) -#define id_launch_sequence_param (14 + dbg_mapi) -#define id_connect_irq_ping_pong_port (15 + dbg_mapi) -#define id_read_analog_gain_dl (16 + dbg_mapi) -#define id_read_analog_gain_ul (17 + dbg_mapi) -#define id_enable_dyn_ul_gain (18 + dbg_mapi) -#define id_disable_dyn_ul_gain (19 + dbg_mapi) -#define id_enable_dyn_extension (20 + dbg_mapi) -#define id_disable_dyn_extension (21 + dbg_mapi) -#define id_notify_analog_gain_changed (22 + dbg_mapi) -#define id_reset_port (23 + dbg_mapi) -#define id_read_remaining_data (24 + dbg_mapi) -#define id_disable_data_transfer (25 + dbg_mapi) -#define id_enable_data_transfer (26 + dbg_mapi) -#define id_read_global_counter (27 + dbg_mapi) -#define id_set_dmic_filter (28 + dbg_mapi) -#define id_set_opp_processing (29 + dbg_mapi) -#define id_set_ping_pong_buffer (30 + dbg_mapi) -#define id_read_port_address (31 + dbg_mapi) -#define id_load_fw_param (32 + dbg_mapi) -#define id_write_headset_offset (33 + dbg_mapi) -#define id_read_gain_ranges (34 + dbg_mapi) -#define id_write_equalizer (35 + dbg_mapi) -#define id_write_asrc (36 + dbg_mapi) -#define id_write_aps (37 + dbg_mapi) -#define id_write_mixer (38 + dbg_mapi) -#define id_write_eanc (39 + dbg_mapi) -#define id_write_router (40 + dbg_mapi) -#define id_read_port_gain (41 + dbg_mapi) -#define id_read_asrc (42 + dbg_mapi) -#define id_read_aps (43 + dbg_mapi) -#define id_read_aps_energy (44 + dbg_mapi) -#define id_read_mixer (45 + dbg_mapi) -#define id_read_eanc (46 + dbg_mapi) -#define id_read_router (47 + dbg_mapi) -#define id_read_debug_trace (48 + dbg_mapi) -#define id_set_sequence_time_accuracy (49 + dbg_mapi) -#define id_set_debug_pins (50 + dbg_mapi) -#define id_select_main_port (51 + dbg_mapi) -#define id_write_event_generator (52 + dbg_mapi) -#define id_read_use_case_opp (53 + dbg_mapi) -#define id_select_data_source (54 + dbg_mapi) -#define id_read_next_ping_pong_buffer (55 + dbg_mapi) -#define id_init_ping_pong_buffer (56 + dbg_mapi) -#define id_connect_cbpr_dmareq_port (57 + dbg_mapi) -#define id_connect_dmareq_port (58 + dbg_mapi) -#define id_connect_dmareq_ping_pong_port (59 + dbg_mapi) -#define id_connect_serial_port (60 + dbg_mapi) -#define id_connect_slimbus_port (61 + dbg_mapi) -#define id_5 (62 + dbg_mapi) -#define id_set_router_configuration (63 + dbg_mapi) -#define id_connect_debug_trace (64 + dbg_mapi) -#define id_set_debug_trace (65 + dbg_mapi) -#define id_remote_debugger_interface (66 + dbg_mapi) -#define id_enable_test_pattern (67 + dbg_mapi) -#define id_connect_tdm_port (68 + dbg_mapi) +#define id_reset_hal (1 + dbg_mapi) +#define id_load_fw (2 + dbg_mapi) +#define id_default_configuration (3 + dbg_mapi) +#define id_irq_processing (4 + dbg_mapi) +#define id_event_generator_switch (5 + dbg_mapi) +#define id_read_hardware_configuration (6 + dbg_mapi) +#define id_read_lowest_opp (7 + dbg_mapi) +#define id_write_gain (8 + dbg_mapi) +#define id_set_asrc_drift_control (9 + dbg_mapi) +#define id_plug_subroutine (10 + dbg_mapi) +#define id_unplug_subroutine (11 + dbg_mapi) +#define id_plug_sequence (12 + dbg_mapi) +#define id_launch_sequence (13 + dbg_mapi) +#define id_launch_sequence_param (14 + dbg_mapi) +#define id_connect_irq_ping_pong_port (15 + dbg_mapi) +#define id_read_analog_gain_dl (16 + dbg_mapi) +#define id_read_analog_gain_ul (17 + dbg_mapi) +#define id_enable_dyn_ul_gain (18 + dbg_mapi) +#define id_disable_dyn_ul_gain (19 + dbg_mapi) +#define id_enable_dyn_extension (20 + dbg_mapi) +#define id_disable_dyn_extension (21 + dbg_mapi) +#define id_notify_analog_gain_changed (22 + dbg_mapi) +#define id_reset_port (23 + dbg_mapi) +#define id_read_remaining_data (24 + dbg_mapi) +#define id_disable_data_transfer (25 + dbg_mapi) +#define id_enable_data_transfer (26 + dbg_mapi) +#define id_read_global_counter (27 + dbg_mapi) +#define id_set_dmic_filter (28 + dbg_mapi) +#define id_set_opp_processing (29 + dbg_mapi) +#define id_set_ping_pong_buffer (30 + dbg_mapi) +#define id_read_port_address (31 + dbg_mapi) +#define id_load_fw_param (32 + dbg_mapi) +#define id_write_headset_offset (33 + dbg_mapi) +#define id_read_gain_ranges (34 + dbg_mapi) +#define id_write_equalizer (35 + dbg_mapi) +#define id_write_asrc (36 + dbg_mapi) +#define id_write_aps (37 + dbg_mapi) +#define id_write_mixer (38 + dbg_mapi) +#define id_write_eanc (39 + dbg_mapi) +#define id_write_router (40 + dbg_mapi) +#define id_read_port_gain (41 + dbg_mapi) +#define id_read_asrc (42 + dbg_mapi) +#define id_read_aps (43 + dbg_mapi) +#define id_read_aps_energy (44 + dbg_mapi) +#define id_read_mixer (45 + dbg_mapi) +#define id_read_eanc (46 + dbg_mapi) +#define id_read_router (47 + dbg_mapi) +#define id_read_debug_trace (48 + dbg_mapi) +#define id_set_sequence_time_accuracy (49 + dbg_mapi) +#define id_set_debug_pins (50 + dbg_mapi) +#define id_select_main_port (51 + dbg_mapi) +#define id_write_event_generator (52 + dbg_mapi) +#define id_read_use_case_opp (53 + dbg_mapi) +#define id_select_data_source (54 + dbg_mapi) +#define id_read_next_ping_pong_buffer (55 + dbg_mapi) +#define id_init_ping_pong_buffer (56 + dbg_mapi) +#define id_connect_cbpr_dmareq_port (57 + dbg_mapi) +#define id_connect_dmareq_port (58 + dbg_mapi) +#define id_connect_dmareq_ping_pong_port (59 + dbg_mapi) +#define id_connect_serial_port (60 + dbg_mapi) +#define id_connect_slimbus_port (61 + dbg_mapi) +#define id_read_gain (62 + dbg_mapi) +#define id_set_router_configuration (63 + dbg_mapi) +#define id_connect_debug_trace (64 + dbg_mapi) +#define id_set_debug_trace (65 + dbg_mapi) +#define id_remote_debugger_interface (66 + dbg_mapi) +#define id_enable_test_pattern (67 + dbg_mapi) +#define id_connect_tdm_port (68 + dbg_mapi) + /* * IDs used for error codes */ -#define NOERR 0 -#define ABE_SET_MEMORY_CONFIG_ERR (1 + dbg_merr) -#define ABE_BLOCK_COPY_ERR (2 + dbg_merr) -#define ABE_SEQTOOLONG (3 + dbg_merr) -#define ABE_BADSAMPFORMAT (4 + dbg_merr) -#define ABE_SET_ATC_MEMORY_CONFIG_ERR (5 + dbg_merr) -#define ABE_PROTOCOL_ERROR (6 + dbg_merr) -#define ABE_PARAMETER_ERROR (7 + dbg_merr) -/* port programmed while still running */ -#define ABE_PORT_REPROGRAMMING (8 + dbg_merr) -#define ABE_READ_USE_CASE_OPP_ERR (9 + dbg_merr) -#define ABE_PARAMETER_OVERFLOW (10 + dbg_merr) +#define NOERR 0 +#define ABE_SET_MEMORY_CONFIG_ERR (1 + dbg_merr) +#define ABE_BLOCK_COPY_ERR (2 + dbg_merr) +#define ABE_SEQTOOLONG (3 + dbg_merr) +#define ABE_BADSAMPFORMAT (4 + dbg_merr) +#define ABE_SET_ATC_MEMORY_CONFIG_ERR (5 + dbg_merr) +#define ABE_PROTOCOL_ERROR (6 + dbg_merr) +#define ABE_PARAMETER_ERROR (7 + dbg_merr) + +/* port programmed while still running */ +#define ABE_PORT_REPROGRAMMING (8 + dbg_merr) +#define ABE_READ_USE_CASE_OPP_ERR (9 + dbg_merr) +#define ABE_PARAMETER_OVERFLOW (10 + dbg_merr) +#define ABE_FW_FIFO_WRITE_PTR_ERR (11 + dbg_merr) + /* * IDs used for error codes */ -#define ERR_LIB (1 << 1) /* error in the LIB.C file */ -#define ERR_API (1 << 2) /* error in the API.C file */ -#define ERR_INI (1 << 3) /* error in the INI.C file */ -#define ERR_SEQ (1 << 4) /* error in the SEQ.C file */ -#define ERR_DBG (1 << 5) /* error in the DBG.C file */ -#define ERR_EXT (1 << 6) /* error in the EXT.C file */ +/* error in the LIB.C file */ +#define ERR_LIB (1 << 1) + +/* error in the API.C file */ +#define ERR_API (1 << 2) + +/* error in the INI.C file */ +#define ERR_INI (1 << 3) + +/* error in the SEQ.C file */ +#define ERR_SEQ (1 << 4) + +/* error in the DBG.C file */ +#define ERR_DBG (1 << 5) + +/* error in the DBG.C file */ +#define ERR_EXT (1 << 6) /* * MACROS */ -#define _log(x,y,z,t) {if(x&abe_dbg_mask)abe_dbg_log(x,y,z,t);} - -#ifdef __cplusplus -} -#endif +//#define _log(x,y,z,t) {if(x&abe_dbg_mask)abe_dbg_log(x,y,z,t);}
#define _log(x,y,z,t) ; diff --git a/sound/soc/omap/abe/abe_def.h b/sound/soc/omap/abe/abe_def.h index e80e9eb5b700..f524cc266019 100644 --- a/sound/soc/omap/abe/abe_def.h +++ b/sound/soc/omap/abe/abe_def.h @@ -1,11 +1,22 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #ifndef _ABE_DEF_H_ @@ -15,287 +26,332 @@ * HARDWARE AND PERIPHERAL DEFINITIONS */ -#define ABE_DMAREQ_REGISTER(desc) (abe_uint32 *)((desc/8) + CIRCULAR_BUFFER_PERIPHERAL_R__0) +/* MM_DL */ +#define ABE_CBPR0_IDX 0 -//#define ABE_SEND_DMAREQ(dma) (*((abe_uint32 *)(ABE_ATC_BASE_ADDRESS_MPU+ABE_DMASTATUS_RAW)) = (dma)) +/* VX_DL */ +#define ABE_CBPR1_IDX 1 -#define ABE_CBPR0_IDX 0 /* MM_DL */ -#define ABE_CBPR1_IDX 1 /* VX_DL */ -#define ABE_CBPR2_IDX 2 /* VX_UL */ -#define ABE_CBPR3_IDX 3 /* MM_UL */ -#define ABE_CBPR4_IDX 4 /* MM_UL2 */ -#define ABE_CBPR5_IDX 5 /* TONES */ -#define ABE_CBPR6_IDX 6 /* VIB */ -#define ABE_CBPR7_IDX 7 /* DEBUG/CTL */ +/* VX_UL */ +#define ABE_CBPR2_IDX 2 -#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR1_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR2_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR3_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR4_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR5_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR6_IDX * 4) -#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (CIRCULAR_BUFFER_PERIPHERAL_R__0 + ABE_CBPR7_IDX * 4) +/* MM_UL */ +#define ABE_CBPR3_IDX 3 -/* - * cache-flush mechanism - */ -#define NB_BYTES_CACHELINE_SHFT 4 -#define NB_BYTES_IN_CACHE_LINE (1<<NB_BYTES_CACHELINE_SHFT) /* there are 16 bytes in each cache lines */ +/* MM_UL2 */ +#define ABE_CBPR4_IDX 4 -/* - * DEFINITIONS SHARED WITH VIRTAUDIO - */ +/* TONES */ +#define ABE_CBPR5_IDX 5 + +/* VIB */ +#define ABE_CBPR6_IDX 6 + +/* DEBUG/CTL */ +#define ABE_CBPR7_IDX 7 + +#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4) +#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4) -#define UC1_LP 1 /* MP3 low-power player use-case */ -#define UC2_VOICE_CALL_AND_IHF_MMDL 2 /* enables voice ul/dl on earpiece + MM_DL on IHF */ -#define UC5_PINGPONG_MMDL 5 /* Test MM_DL with Ping-Pong */ -#define UC6_PINGPONG_MMDL_WITH_IRQ 6 /* ping-pong with IRQ instead of sDMA */ - -#define UC31_VOICE_CALL_8KMONO 31 -#define UC32_VOICE_CALL_8KSTEREO 32 -#define UC33_VOICE_CALL_16KMONO 33 -#define UC34_VOICE_CALL_16KSTEREO 34 -#define UC35_MMDL_MONO 35 -#define UC36_MMDL_STEREO 36 -#define UC37_MMUL2_MONO 37 -#define UC38_MMUL2_STEREO 38 - -#define UC41_____ 40 -#define UC71_STOP_ALL 71 /* stop all activities */ -#define UC72_ENABLE_ALL 72 /* stop all activities */ -#define UC81_ROUTE_AMIC 81 -#define UC82_ROUTE_DMIC01 82 -#define UC83_ROUTE_DMIC23 83 -#define UC84_ROUTE_DMIC45 84 - -#define UC91_ASRC_DRIFT1 91 -#define UC92_ASRC_DRIFT2 92 -#define UC93_EANC 93 - -#define PING_PONG_WITH_MCU_IRQ 1 -#define PING_PONG_WITH_DSP_IRQ 2 - -#define HAL_RESET_HAL 10 /* abe_reset_hal () */ -#define HAL_WRITE_MIXER 11 /* abe_write_mixer () */ - -#define COPY_FROM_ABE_TO_HOST 1 /* ID used for LIB memory copy subroutines */ -#define COPY_FROM_HOST_TO_ABE 2 +#define PING_PONG_WITH_MCU_IRQ 1 +#define PING_PONG_WITH_DSP_IRQ 2 + +/* ID used for LIB memory copy subroutines */ +#define COPY_FROM_ABE_TO_HOST 1 +#define COPY_FROM_HOST_TO_ABE 2 /* * INTERNAL DEFINITIONS */ -#define CC_M1 0xFF /* unsigned version of (-1) */ -#define CS_M1 0xFFFF /* unsigned version of (-1) */ -#define CL_M1 0xFFFFFFFFL /* unsigned version of (-1) */ - -#define NBEANC1 20 /* 20 Q6.26 coef for the FIR */ -#define NBEANC2 16 /* 16 Q6.26 coef for the IIR */ - -#define NBEQ1 25 /* 24 Q6.26 coefficients */ -#define NBEQ2 13 /* 2x12 Q6.26 coefficients */ - -#define NBAPS1 10 /* TBD APS first set of parameters */ -#define NBAPS2 10 /* TBD APS second set of parameters */ - -#define NBMIX_AUDIO_UL 2 /* Mixer used for sending tones to the uplink voice path */ -#define NBMIX_DL1 4 /* Main downlink mixer */ -#define NBMIX_DL2 4 /* Handsfree downlink mixer */ -#define NBMIX_SDT 2 /* Side-tone mixer */ -#define NBMIX_ECHO 2 /* Echo reference mixer */ -#define NBMIX_VXREC 4 /* Voice record mixer */ - /* - Mixer ID Input port ID Comments - DL1_MIXER 0 MMDL path - 1 MMUL2 path - 2 VXDL path - 3 TONES path - - SDT_MIXER 0 Uplink path - 1 Downlink path - - ECHO_MIXER 0 DL1_MIXER path - 1 DL2_MIXER path - - AUDUL_MIXER 0 TONES_DL path - 1 Uplink path - 2 MM_DL path - - VXREC_MIXER 0 TONES_DL path - 1 VX_DL path - 2 MM_DL path - 3 VX_UL path - */ -#define MIX_VXUL_INPUT_MM_DL (abe_port_id)0 -#define MIX_VXUL_INPUT_TONES (abe_port_id)1 -#define MIX_VXUL_INPUT_VX_UL (abe_port_id)2 -#define MIX_VXUL_INPUT_VX_DL (abe_port_id)3 - -#define MIX_DL1_INPUT_MM_DL (abe_port_id)0 -#define MIX_DL1_INPUT_MM_UL2 (abe_port_id)1 -#define MIX_DL1_INPUT_VX_DL (abe_port_id)2 -#define MIX_DL1_INPUT_TONES (abe_port_id)3 - -#define MIX_DL2_INPUT_MM_DL (abe_port_id)0 -#define MIX_DL2_INPUT_MM_UL2 (abe_port_id)1 -#define MIX_DL2_INPUT_VX_DL (abe_port_id)2 -#define MIX_DL2_INPUT_TONES (abe_port_id)3 - -#define MIX_SDT_INPUT_UP_MIXER (abe_port_id)0 -#define MIX_SDT_INPUT_DL1_MIXER (abe_port_id)1 - -#define MIX_AUDUL_INPUT_MM_DL (abe_port_id)0 -#define MIX_AUDUL_INPUT_TONES (abe_port_id)1 -#define MIX_AUDUL_INPUT_UPLINK (abe_port_id)2 -#define MIX_AUDUL_INPUT_VX_DL (abe_port_id)3 - -#define MIX_VXREC_INPUT_MM_DL (abe_port_id)0 -#define MIX_VXREC_INPUT_TONES (abe_port_id)1 -#define MIX_VXREC_INPUT_VX_UL (abe_port_id)2 -#define MIX_VXREC_INPUT_VX_DL (abe_port_id)3 - -#define NBROUTE_UL 16 /* nb of samples to route */ -#define NBROUTE_CONFIG_MAX 10 /* 10 routing tables max */ - -#define NBROUTE_CONFIG 5 /* 5 pre-computed routing tables */ -#define UPROUTE_CONFIG_AMIC 0 /* AMIC on VX_UL */ -#define UPROUTE_CONFIG_DMIC1 1 /* DMIC first pair on VX_UL */ -#define UPROUTE_CONFIG_DMIC2 2 /* DMIC second pair on VX_UL */ -#define UPROUTE_CONFIG_DMIC3 3 /* DMIC last pair on VX_UL */ -#define UPROUTE_CONFIG_BT 4 /* BT_UL on VX_UL */ - -#define ABE_PMEM 1 -#define ABE_CMEM 2 -#define ABE_SMEM 3 -#define ABE_DMEM 4 -#define ABE_ATC 5 - -#define MAXCALLBACK 100 /* call-back indexes */ -#define MAXNBSUBROUTINE 100 /* subroutines */ - -#define MAXNBSEQUENCE 20 /* time controlled sequenced */ -#define MAXACTIVESEQUENCE 20 /* maximum simultaneous active sequences */ -#define MAXSEQUENCESTEPS 2 /* max number of steps in the sequences */ -#define MAXFEATUREPORT 12 /* max number of feature associated to a port */ -#define SUB_0_PARAM 0 -#define SUB_1_PARAM 1 /* number of parameters per sequence calls */ -#define SUB_2_PARAM 2 -#define SUB_3_PARAM 3 -#define SUB_4_PARAM 4 - -#define FREE_LINE 0 /* active sequence mask = 0 means the line is free */ -#define NOMASK (1 << 0) /* no ask for collision protection */ -#define MASK_PDM_OFF (1 << 1) /* do not allow a PDM OFF during the execution of this sequence */ -#define MASK_PDM_ON (1 << 2) /* do not allow a PDM ON during the execution of this sequence */ - -#define NBCHARFEATURENAME 16 /* explicit name of the feature */ -#define NBCHARPORTNAME 16 /* explicit name of the port */ - -#define SNK_P ABE_ATC_DIRECTION_IN /* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */ -#define SRC_P ABE_ATC_DIRECTION_OUT /* source / ouptut port */ - -#define NODRIFT 0 /* no ASRC applied */ -#define FORCED_DRIFT_CONTROL 1 /* for abe_set_asrc_drift_control */ -#define ADPATIVE_DRIFT_CONTROL 2 /* for abe_set_asrc_drift_control */ - -#define DOPPMODE32_OPP100 (0x00000010 | (0x00000000<<16)) -#define DOPPMODE32_OPP50 (0x0000000C | (0x0000004<<16)) -#define DOPPMODE32_OPP25 (0x0000004 | (0x0000000C<<16)) +#define ABE_FIRMWARE_MAX_SIZE 26629 + +/* 24 Q6.26 coefficients */ +#define NBEQ1 25 + +/* 2x12 Q6.26 coefficients */ +#define NBEQ2 13 + +/* TBD APS first set of parameters */ +#define NBAPS1 10 + +/* TBD APS second set of parameters */ +#define NBAPS2 10 + +/* Mixer used for sending tones to the uplink voice path */ +#define NBMIX_AUDIO_UL 2 + +/* Main downlink mixer */ +#define NBMIX_DL1 4 + +/* Handsfree downlink mixer */ +#define NBMIX_DL2 4 + +/* Side-tone mixer */ +#define NBMIX_SDT 2 + +/* Echo reference mixer */ +#define NBMIX_ECHO 2 + +/* Voice record mixer */ +#define NBMIX_VXREC 4 + +/* unsigned version of (-1) */ +#define CC_M1 0xFF +#define CS_M1 0xFFFF +#define CL_M1 0xFFFFFFFFL + +/* + Mixer ID Input port ID Comments + DL1_MIXER 0 MMDL path + 1 MMUL2 path + 2 VXDL path + 3 TONES path + + SDT_MIXER 0 Uplink path + 1 Downlink path + + ECHO_MIXER 0 DL1_MIXER path + 1 DL2_MIXER path + + AUDUL_MIXER 0 TONES_DL path + 1 Uplink path + 2 MM_DL path + + VXREC_MIXER 0 TONES_DL path + 1 VX_DL path + 2 MM_DL path + 3 VX_UL path +*/ +#define MIX_VXUL_INPUT_MM_DL 0 +#define MIX_VXUL_INPUT_TONES 1 +#define MIX_VXUL_INPUT_VX_UL 2 +#define MIX_VXUL_INPUT_VX_DL 3 + +#define MIX_DL1_INPUT_MM_DL 0 +#define MIX_DL1_INPUT_MM_UL2 1 +#define MIX_DL1_INPUT_VX_DL 2 +#define MIX_DL1_INPUT_TONES 3 + +#define MIX_DL2_INPUT_MM_DL 0 +#define MIX_DL2_INPUT_MM_UL2 1 +#define MIX_DL2_INPUT_VX_DL 2 +#define MIX_DL2_INPUT_TONES 3 + +#define MIX_SDT_INPUT_UP_MIXER 0 +#define MIX_SDT_INPUT_DL1_MIXER 1 + +#define MIX_AUDUL_INPUT_MM_DL 0 +#define MIX_AUDUL_INPUT_TONES 1 +#define MIX_AUDUL_INPUT_UPLINK 2 +#define MIX_AUDUL_INPUT_VX_DL 3 + +#define MIX_VXREC_INPUT_MM_DL 0 +#define MIX_VXREC_INPUT_TONES 1 +#define MIX_VXREC_INPUT_VX_UL 2 +#define MIX_VXREC_INPUT_VX_DL 3 + +/* nb of samples to route */ +#define NBROUTE_UL 16 + +/* 10 routing tables max */ +#define NBROUTE_CONFIG_MAX 10 + +/* 5 pre-computed routing tables */ +#define NBROUTE_CONFIG 5 + +/* AMIC on VX_UL */ +#define UPROUTE_CONFIG_AMIC 0 + +/* DMIC first pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC1 1 + +/* DMIC second pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC2 2 + +/* DMIC last pair on VX_UL */ +#define UPROUTE_CONFIG_DMIC3 3 + +/* BT_UL on VX_UL */ +#define UPROUTE_CONFIG_BT 4 + +/* call-back indexes */ +#define MAXCALLBACK 100 + +/* subroutines */ +#define MAXNBSUBROUTINE 100 + +/* time controlled sequenced */ +#define MAXNBSEQUENCE 20 + +/* maximum simultaneous active sequences */ +#define MAXACTIVESEQUENCE 20 + +/* max number of steps in the sequences */ +#define MAXSEQUENCESTEPS 2 + +/* max number of feature associated to a port */ +#define MAXFEATUREPORT 12 +#define SUB_0_PARAM 0 + +/* number of parameters per sequence calls */ +#define SUB_1_PARAM 1 +#define SUB_2_PARAM 2 +#define SUB_3_PARAM 3 +#define SUB_4_PARAM 4 + +/* active sequence mask = 0 means the line is free */ +#define FREE_LINE 0 + +/* no ask for collision protection */ +#define NOMASK (1 << 0) + +/* do not allow a PDM OFF during the execution of this sequence */ +#define MASK_PDM_OFF (1 << 1) + +/* do not allow a PDM ON during the execution of this sequence */ +#define MASK_PDM_ON (1 << 2) + +/* explicit name of the feature */ +#define NBCHARFEATURENAME 16 + +/* explicit name of the port */ +#define NBCHARPORTNAME 16 + +/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */ +#define SNK_P ABE_ATC_DIRECTION_IN + +/* source / ouptut port */ +#define SRC_P ABE_ATC_DIRECTION_OUT + +/* no ASRC applied */ +#define NODRIFT 0 + +/* for abe_set_asrc_drift_control */ +#define FORCED_DRIFT_CONTROL 1 + +/* for abe_set_asrc_drift_control */ +#define ADPATIVE_DRIFT_CONTROL 2 + +#define DOPPMODE32_OPP100 (0x00000010 | (0x00000000<<16)) +#define DOPPMODE32_OPP50 (0x0000000C | (0x0000004<<16)) +#define DOPPMODE32_OPP25 (0x0000004 | (0x0000000C<<16)) /* * ABE CONST AREA FOR PARAMETERS TRANSLATION */ #define min_mdb (-12000) -#define max_mdb ( 3000) +#define max_mdb ( 3000) #define sizeof_db2lin_table (1+ ((max_mdb - min_mdb)/100)) +#define sizeof_alpha_iir_table 61 +#define sizeof_beta_iir_table 61 + +#define GAIN_MAXIMUM 3000L +#define GAIN_24dB 2400L +#define GAIN_18dB 1800L +#define GAIN_12dB 1200L +#define GAIN_6dB 600L + +/* default gain = 1 */ +#define GAIN_0dB 0L +#define GAIN_M6dB -600L +#define GAIN_M12dB -1200L +#define GAIN_M18dB -1800L +#define GAIN_M24dB -2400L +#define GAIN_M30dB -3000L +#define GAIN_M40dB -4000L +#define GAIN_M50dB -5000L + +/* muted gain = -120 decibels */ +#define MUTE_GAIN -12000L +#define GAIN_MUTE MUTE_GAIN + +#define RAMP_MINLENGTH 3L + +/* ramp_t is in milli- seconds */ +#define RAMP_0MS 0L +#define RAMP_1MS 1L +#define RAMP_2MS 2L +#define RAMP_5MS 5L +#define RAMP_10MS 10L +#define RAMP_20MS 20L +#define RAMP_50MS 50L +#define RAMP_100MS 100L +#define RAMP_200MS 200L +#define RAMP_500MS 500L +#define RAMP_1000MS 1000L +#define RAMP_MAXLENGTH 10000L + +/* for abe_translate_gain_format */ +#define LINABE_TO_DECIBELS 1 +#define DECIBELS_TO_LINABE 2 + +/* for abe_translate_ramp_format */ +#define IIRABE_TO_MICROS 1 +#define MICROS_TO_IIABE 2 + +/* + * ABE CONST AREA FOR PERIPHERAL TUNING + */ + +/* port idled IDLE_P */ +#define OMAP_ABE_PORT_ACTIVITY_IDLE 1 -#define GAIN_MAXIMUM (abe_gain_t)3000L -#define GAIN_24dB (abe_gain_t)2400L -#define GAIN_18dB (abe_gain_t)1800L -#define GAIN_12dB (abe_gain_t)1200L -#define GAIN_6dB (abe_gain_t)600L -#define GAIN_0dB (abe_gain_t) 0L /* default gain = 1 */ -#define GAIN_M6dB (abe_gain_t)-600L -#define GAIN_M12dB (abe_gain_t)-1200L -#define GAIN_M18dB (abe_gain_t)-1800L -#define GAIN_M24dB (abe_gain_t)-2400L -#define GAIN_M30dB (abe_gain_t)-3000L -#define GAIN_M40dB (abe_gain_t)-4000L -#define GAIN_M50dB (abe_gain_t)-5000L -#define MUTE_GAIN (abe_gain_t)-12000L - -#define RAMP_0MS (abe_ramp_t)0L /* ramp_t is in milli- seconds */ -#define RAMP_1MS (abe_ramp_t)1L -#define RAMP_2MS (abe_ramp_t)2L -#define RAMP_5MS (abe_ramp_t)5L -#define RAMP_10MS (abe_ramp_t)10L -#define RAMP_20MS (abe_ramp_t)20L -#define RAMP_50MS (abe_ramp_t)50L -#define RAMP_100MS (abe_ramp_t)100L -#define RAMP_200MS (abe_ramp_t) 200L -#define RAMP_500MS (abe_ramp_t) 500L -#define RAMP_1000MS (abe_ramp_t) 1000L -#define RAMP_MAXLENGTH (abe_ramp_t) 10000L - -#define LINABE_TO_DECIBELS 1 /* for abe_translate_gain_format */ -#define DECIBELS_TO_LINABE 2 -#define IIRABE_TO_MICROS 1 /* for abe_translate_ramp_format */ -#define MICROS_TO_IIABE 2 - -#define IDLE_P 1 /* port idled */ -#define RUN_P 2 /* port running */ -#define NOCALLBACK 0 -#define NOPARAMETER 0 - /* HAL 06: those numbers may be x4 */ -#define MCPDM_UL_ITER 4 /* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */ -#define MCPDM_DL_ITER 12 /* All the McPDM FIFOs are enabled simultaneously */ -#define DMIC_ITER 6 /* All the DMIC FIFOs are enabled simultaneously */ - -#define DEFAULT_THR_READ 1 /* port / flow management */ -#define DEFAULT_THR_WRITE 1 /* port / flow management */ - -#define DEFAULT_CONTROL_MCPDMDL 1 /* allows control on the PDM line */ - -#define MAX_PINGPONG_BUFFERS 2 /* TBD later if needed */ +/* port activated RUN_P */ +#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2 + +#define NOCALLBACK 0 +#define NOPARAMETER 0 + +/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */ +#define MCPDM_UL_ITER 4 + +/* All the McPDM FIFOs are enabled simultaneously */ +#define MCPDM_DL_ITER 12 + +/* All the DMIC FIFOs are enabled simultaneously */ +#define DMIC_ITER 12 + +/* port / flow management */ +#define DEFAULT_THR_READ 1 + +/* port / flow management */ +#define DEFAULT_THR_WRITE 1 + +/* allows control on the PDM line */ +#define DEFAULT_CONTROL_MCPDMDL 1 + +/* TBD later if needed */ +#define MAX_PINGPONG_BUFFERS 2 /* * Indexes to the subroutines */ -#define SUB_WRITE_MIXER 1 -#define SUB_WRITE_PORT_GAIN 2 +#define SUB_WRITE_MIXER 1 +#define SUB_WRITE_PORT_GAIN 2 /* OLD WAY */ -#define c_feat_init_eq 1 -#define c_feat_read_eq1 2 -#define c_write_eq1 3 -#define c_feat_read_eq2 4 -#define c_write_eq2 5 -#define c_feat_read_eq3 6 -#define c_write_eq3 7 +#define c_feat_init_eq 1 +#define c_feat_read_eq1 2 +#define c_write_eq1 3 +#define c_feat_read_eq2 4 +#define c_write_eq2 5 +#define c_feat_read_eq3 6 +#define c_write_eq3 7 /* * MACROS */ -#define LOAD_ABEREG(reg,data) {abe_uint32 *ocp_addr = (abe_uint32 *)((reg)+ABE_ATC_BASE_ADDRESS_MPU); *ocp_addr= (data);} - -#define maximum(a,b) (((a)<(b))?(b):(a)) -#define minimum(a,b) (((a)>(b))?(b):(a)) -#define absolute(a) ( ((a)>0) ? (a):((-1)*(a)) ) - -// Gives 1% errors -//#define abe_power_of_two(x) (abe_float)(1 + x*(0.69315 + x*(0.24022 + x*(0.056614 + x*(0.00975 ))))) /* for x = [-1..+1] */ -//#define abe_log_of_two(i) (abe_float)(-2.4983 + i*(4.0321 + i*(-2.0843 + i*(0.63 + i*(-0.0793))))) /* for i = [+1..+2[ */ -// Gives 0.1% errors -//#define abe_power_of_two(xx) (abe_float)(1 + xx*(0.69314718055995 + xx*(0.24022650695909 + xx*(0.05661419083812 + xx*(0.0096258236109 ))))) /* for x = [-1..+1] */ -//#define abe_log_of_two(i) (abe_float)(-3.02985297173966 + i*(6.07170945221999 + i*(-5.27332161514862 + i*(3.22638187067771 + i*(-1.23767101624897 + i*(0.26766043958616 + i*(-0.02490211314987))))))) /* for i = [+1..+2[ */ - -#if 0 -#define abe_power_of_two(xx) (abe_float)(0.9999999924494 + xx*(0.69314847688495 + xx*(0.24022677604481 + xx*(0.05549256818679 + xx*(0.00961666477618 + xx*(0.0013584351075 + xx*(0.00015654359307))))))) /* for x = [-1..+1] */ -#define abe_log_of_two(xx) (abe_float)(-3.02985297175803 + xx*(6.07170945229365 + xx*(-5.27332161527062 + xx*(3.22638187078450 + xx*(-1.23767101630110 + xx*(0.26766043959961 + xx*(-0.02490211315130))))))) /* for x = [+1..+2] */ -#define abe_sine(xx) (abe_float)(-0.000000389441 + xx*(6.283360925789 + xx*(-0.011140658372 + xx*(-41.073653348384 + xx*(-3.121196875959 + xx*(100.619954580736 + xx*( -59.133359355846))))))) /* for x = [0 .. pi/2] */ -#define abe_sqrt(xx) (abe_float)(0.32298238417665 + xx*(0.93621865220393 + xx*(-0.36276443369703 + xx*(0.13008602653101+ xx*(-0.03017833169073 + xx*(0.00393731964847 + xx*-0.00021858629159 )))))) /* for x = [1 .. 4] */ -#endif +#define maximum(a,b) (((a)<(b))?(b):(a)) +#define minimum(a,b) (((a)>(b))?(b):(a)) +#define absolute(a) (((a)>0)?(a):((-1)*(a))) + #endif /* _ABE_DEF_H_ */ diff --git a/sound/soc/omap/abe/abe_define.h b/sound/soc/omap/abe/abe_define.h index 314f78f3a6f3..49ce1b581a62 100644 --- a/sound/soc/omap/abe/abe_define.h +++ b/sound/soc/omap/abe/abe_define.h @@ -1,51 +1,67 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== */ - #ifndef _ABE_DEFINE_H_ #define _ABE_DEFINE_H_ -#define ATC_DESCRIPTOR_NUMBER 64 -#define PROCESSING_SLOTS 25 -#define TASK_POOL_LENGTH 128 -#define MCU_IRQ 0x24 -#define MCU_IRQ_SHIFT2 0x90 -#define DMA_REQ_SHIFT2 0x210 -#define DSP_IRQ 0x4c -#define IRQtag_APS 0x000a -#define IRQtag_COUNT 0x000c -#define IRQtag_PP 0x000d -#define DMAreq_7 0x0080 -#define IRQ_FIFO_LENGTH 16 -#define SDT_EQ_ORDER 4 -#define DL_EQ_ORDER 12 -#define MIC_FILTER_ORDER 4 -#define GAINS_WITH_RAMP1 14 -#define GAINS_WITH_RAMP2 22 -#define GAINS_WITH_RAMP_TOTAL 36 -#define EANC_FIR_TAPS 21 -#define EANC_IIR_ORDER 8 -#define ASRC_MEMLENGTH 40 -#define ASRC_UL_VX_FIR_L 19 -#define ASRC_DL_VX_FIR_L 19 -#define ASRC_DL_MM_FIR_L 18 -#define ASRC_N_8k 2 -#define ASRC_N_16k 4 -#define ASRC_N_48k 12 -#define VIBRA_N 5 -#define VIBRA1_IIR_MEMSIZE 11 -#define SAMP_LOOP_96K 24 -#define SAMP_LOOP_48K 12 -#define SAMP_LOOP_16K 4 -#define SAMP_LOOP_8K 2 -#define INPUT_SCALE_SHIFTM2 5268 -#define OUTPUT_SCALE_SHIFTM2 5272 - +#define ATC_DESCRIPTOR_NUMBER 64 +#define PROCESSING_SLOTS 25 +#define TASK_POOL_LENGTH 128 +#define MCU_IRQ 0x24 +#define MCU_IRQ_SHIFT2 0x90 +#define DMA_REQ_SHIFT2 0x210 +#define DSP_IRQ 0x4c +#define IRQtag_APS 0x000a +#define IRQtag_COUNT 0x000c +#define IRQtag_PP 0x000d +#define DMAreq_7 0x0080 +#define IRQ_FIFO_LENGTH 16 +#define SDT_EQ_ORDER 4 +#define DL_EQ_ORDER 12 +#define MIC_FILTER_ORDER 4 +#define GAINS_WITH_RAMP1 14 +#define GAINS_WITH_RAMP2 22 +#define GAINS_WITH_RAMP_TOTAL 36 +#define EANC_FIR_TAPS 21 +#define EANC_IIR_ORDER 8 +#define ASRC_MEMLENGTH 40 +#define ASRC_UL_VX_FIR_L 19 +#define ASRC_DL_VX_FIR_L 19 +#define ASRC_DL_MM_FIR_L 18 +#define ASRC_margin 2 +#define ASRC_N_8k 2 +#define ASRC_N_16k 4 +#define ASRC_N_48k 12 +#define VIBRA_N 5 +#define VIBRA1_IIR_MEMSIZE 11 +#define SAMP_LOOP_96K 24 +#define SAMP_LOOP_48K 12 +#define SAMP_LOOP_16K 4 +#define SAMP_LOOP_8K 2 +#define INPUT_SCALE_SHIFTM2 5264 +#define OUTPUT_SCALE_SHIFTM2 5268 +#define MUTE_SCALING 5272 +#define ABE_PMEM 1 +#define ABE_CMEM 2 +#define ABE_SMEM 3 +#define ABE_DMEM 4 +#define ABE_ATC 5 -#endif /* _ABE_DEFINE_H_ */ +#endif /* _ABE_DEFINE_H_ */ diff --git a/sound/soc/omap/abe/abe_dm_addr.h b/sound/soc/omap/abe/abe_dm_addr.h index cd3ce9856558..93243de470f7 100644 --- a/sound/soc/omap/abe/abe_dm_addr.h +++ b/sound/soc/omap/abe/abe_dm_addr.h @@ -1,386 +1,413 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== */ - #ifndef _ABE_DM_ADDR_H_ #define _ABE_DM_ADDR_H_ -#define D_atcDescriptors_ADDR 0 -#define D_atcDescriptors_ADDR_END 511 -#define D_atcDescriptors_sizeof 512 +#define D_atcDescriptors_ADDR 0 +#define D_atcDescriptors_ADDR_END 511 +#define D_atcDescriptors_sizeof 512 + +#define stack_ADDR 512 +#define stack_ADDR_END 623 +#define stack_sizeof 112 + +#define D_version_ADDR 624 +#define D_version_ADDR_END 627 +#define D_version_sizeof 4 + +#define D_BT_DL_FIFO_ADDR 1024 +#define D_BT_DL_FIFO_ADDR_END 1503 +#define D_BT_DL_FIFO_sizeof 480 + +#define D_BT_UL_FIFO_ADDR 1536 +#define D_BT_UL_FIFO_ADDR_END 2015 +#define D_BT_UL_FIFO_sizeof 480 + +#define D_MM_EXT_OUT_FIFO_ADDR 2048 +#define D_MM_EXT_OUT_FIFO_ADDR_END 2527 +#define D_MM_EXT_OUT_FIFO_sizeof 480 -#define stack_ADDR 512 -#define stack_ADDR_END 623 -#define stack_sizeof 112 +#define D_MM_EXT_IN_FIFO_ADDR 2560 +#define D_MM_EXT_IN_FIFO_ADDR_END 3039 +#define D_MM_EXT_IN_FIFO_sizeof 480 -#define D_version_ADDR 624 -#define D_version_ADDR_END 627 -#define D_version_sizeof 4 +#define D_MM_UL2_FIFO_ADDR 3072 +#define D_MM_UL2_FIFO_ADDR_END 3551 +#define D_MM_UL2_FIFO_sizeof 480 -#define D_BT_DL_FIFO_ADDR 1024 -#define D_BT_DL_FIFO_ADDR_END 1503 -#define D_BT_DL_FIFO_sizeof 480 +#define D_VX_UL_FIFO_ADDR 3584 +#define D_VX_UL_FIFO_ADDR_END 4063 +#define D_VX_UL_FIFO_sizeof 480 -#define D_BT_UL_FIFO_ADDR 1536 -#define D_BT_UL_FIFO_ADDR_END 2015 -#define D_BT_UL_FIFO_sizeof 480 +#define D_VX_DL_FIFO_ADDR 4096 +#define D_VX_DL_FIFO_ADDR_END 4575 +#define D_VX_DL_FIFO_sizeof 480 -#define D_MM_EXT_OUT_FIFO_ADDR 2048 -#define D_MM_EXT_OUT_FIFO_ADDR_END 2527 -#define D_MM_EXT_OUT_FIFO_sizeof 480 +#define D_DMIC_UL_FIFO_ADDR 4608 +#define D_DMIC_UL_FIFO_ADDR_END 5087 +#define D_DMIC_UL_FIFO_sizeof 480 -#define D_MM_EXT_IN_FIFO_ADDR 2560 -#define D_MM_EXT_IN_FIFO_ADDR_END 3039 -#define D_MM_EXT_IN_FIFO_sizeof 480 +#define D_MM_UL_FIFO_ADDR 5120 +#define D_MM_UL_FIFO_ADDR_END 5599 +#define D_MM_UL_FIFO_sizeof 480 -#define D_MM_UL2_FIFO_ADDR 3072 -#define D_MM_UL2_FIFO_ADDR_END 3551 -#define D_MM_UL2_FIFO_sizeof 480 +#define D_MM_DL_FIFO_ADDR 5632 +#define D_MM_DL_FIFO_ADDR_END 6111 +#define D_MM_DL_FIFO_sizeof 480 -#define D_VX_UL_FIFO_ADDR 3584 -#define D_VX_UL_FIFO_ADDR_END 4063 -#define D_VX_UL_FIFO_sizeof 480 +#define D_TONES_DL_FIFO_ADDR 6144 +#define D_TONES_DL_FIFO_ADDR_END 6623 +#define D_TONES_DL_FIFO_sizeof 480 -#define D_VX_DL_FIFO_ADDR 4096 -#define D_VX_DL_FIFO_ADDR_END 4575 -#define D_VX_DL_FIFO_sizeof 480 +#define D_VIB_DL_FIFO_ADDR 6656 +#define D_VIB_DL_FIFO_ADDR_END 7135 +#define D_VIB_DL_FIFO_sizeof 480 -#define D_DMIC_UL_FIFO_ADDR 4608 -#define D_DMIC_UL_FIFO_ADDR_END 5087 -#define D_DMIC_UL_FIFO_sizeof 480 +#define D_McPDM_DL_FIFO_ADDR 7168 +#define D_McPDM_DL_FIFO_ADDR_END 7647 +#define D_McPDM_DL_FIFO_sizeof 480 -#define D_MM_UL_FIFO_ADDR 5120 -#define D_MM_UL_FIFO_ADDR_END 5599 -#define D_MM_UL_FIFO_sizeof 480 +#define D_McPDM_UL_FIFO_ADDR 7680 +#define D_McPDM_UL_FIFO_ADDR_END 8159 +#define D_McPDM_UL_FIFO_sizeof 480 -#define D_MM_DL_FIFO_ADDR 5632 -#define D_MM_DL_FIFO_ADDR_END 6111 -#define D_MM_DL_FIFO_sizeof 480 +#define D_DEBUG_FIFO_ADDR 8160 +#define D_DEBUG_FIFO_ADDR_END 8255 +#define D_DEBUG_FIFO_sizeof 96 -#define D_TONES_DL_FIFO_ADDR 6144 -#define D_TONES_DL_FIFO_ADDR_END 6623 -#define D_TONES_DL_FIFO_sizeof 480 +#define D_DEBUG_FIFO_HAL_ADDR 8256 +#define D_DEBUG_FIFO_HAL_ADDR_END 8287 +#define D_DEBUG_FIFO_HAL_sizeof 32 -#define D_VIB_DL_FIFO_ADDR 6656 -#define D_VIB_DL_FIFO_ADDR_END 7135 -#define D_VIB_DL_FIFO_sizeof 480 +#define D_IOdescr_ADDR 8288 +#define D_IOdescr_ADDR_END 8927 +#define D_IOdescr_sizeof 640 -#define D_McPDM_DL_FIFO_ADDR 7168 -#define D_McPDM_DL_FIFO_ADDR_END 7647 -#define D_McPDM_DL_FIFO_sizeof 480 +#define d_zero_ADDR 8928 +#define d_zero_ADDR_END 8931 +#define d_zero_sizeof 4 -#define D_McPDM_UL_FIFO_ADDR 7680 -#define D_McPDM_UL_FIFO_ADDR_END 8159 -#define D_McPDM_UL_FIFO_sizeof 480 +#define dbg_trace1_ADDR 8932 +#define dbg_trace1_ADDR_END 8932 +#define dbg_trace1_sizeof 1 -#define D_DEBUG_FIFO_ADDR 8192 -#define D_DEBUG_FIFO_ADDR_END 8319 -#define D_DEBUG_FIFO_sizeof 128 +#define dbg_trace2_ADDR 8933 +#define dbg_trace2_ADDR_END 8933 +#define dbg_trace2_sizeof 1 -#define D_IOdescr_ADDR 8320 -#define D_IOdescr_ADDR_END 8879 -#define D_IOdescr_sizeof 560 +#define dbg_trace3_ADDR 8934 +#define dbg_trace3_ADDR_END 8934 +#define dbg_trace3_sizeof 1 -#define d_zero_ADDR 8880 -#define d_zero_ADDR_END 8880 -#define d_zero_sizeof 1 +#define D_multiFrame_ADDR 8936 +#define D_multiFrame_ADDR_END 9335 +#define D_multiFrame_sizeof 400 -#define dbg_trace1_ADDR 8881 -#define dbg_trace1_ADDR_END 8881 -#define dbg_trace1_sizeof 1 +#define D_tasksList_ADDR 9336 +#define D_tasksList_ADDR_END 11383 +#define D_tasksList_sizeof 2048 -#define dbg_trace2_ADDR 8882 -#define dbg_trace2_ADDR_END 8882 -#define dbg_trace2_sizeof 1 +#define D_idleTask_ADDR 11384 +#define D_idleTask_ADDR_END 11385 +#define D_idleTask_sizeof 2 -#define dbg_trace3_ADDR 8883 -#define dbg_trace3_ADDR_END 8883 -#define dbg_trace3_sizeof 1 +#define D_typeLengthCheck_ADDR 11386 +#define D_typeLengthCheck_ADDR_END 11387 +#define D_typeLengthCheck_sizeof 2 -#define D_multiFrame_ADDR 8884 -#define D_multiFrame_ADDR_END 9283 -#define D_multiFrame_sizeof 400 +#define D_maxTaskBytesInSlot_ADDR 11388 +#define D_maxTaskBytesInSlot_ADDR_END 11389 +#define D_maxTaskBytesInSlot_sizeof 2 -#define D_tasksList_ADDR 9284 -#define D_tasksList_ADDR_END 11331 -#define D_tasksList_sizeof 2048 +#define D_rewindTaskBytes_ADDR 11390 +#define D_rewindTaskBytes_ADDR_END 11391 +#define D_rewindTaskBytes_sizeof 2 -#define D_idleTask_ADDR 11332 -#define D_idleTask_ADDR_END 11333 -#define D_idleTask_sizeof 2 +#define D_pCurrentTask_ADDR 11392 +#define D_pCurrentTask_ADDR_END 11393 +#define D_pCurrentTask_sizeof 2 -#define D_typeLengthCheck_ADDR 11334 -#define D_typeLengthCheck_ADDR_END 11335 -#define D_typeLengthCheck_sizeof 2 +#define D_pFastLoopBack_ADDR 11394 +#define D_pFastLoopBack_ADDR_END 11395 +#define D_pFastLoopBack_sizeof 2 -#define D_maxTaskBytesInSlot_ADDR 11336 -#define D_maxTaskBytesInSlot_ADDR_END 11337 -#define D_maxTaskBytesInSlot_sizeof 2 +#define D_pNextFastLoopBack_ADDR 11396 +#define D_pNextFastLoopBack_ADDR_END 11399 +#define D_pNextFastLoopBack_sizeof 4 -#define D_rewindTaskBytes_ADDR 11338 -#define D_rewindTaskBytes_ADDR_END 11339 -#define D_rewindTaskBytes_sizeof 2 +#define D_ppCurrentTask_ADDR 11400 +#define D_ppCurrentTask_ADDR_END 11401 +#define D_ppCurrentTask_sizeof 2 -#define D_pCurrentTask_ADDR 11340 -#define D_pCurrentTask_ADDR_END 11341 -#define D_pCurrentTask_sizeof 2 +#define D_slotCounter_ADDR 11404 +#define D_slotCounter_ADDR_END 11405 +#define D_slotCounter_sizeof 2 -#define D_pFastLoopBack_ADDR 11342 -#define D_pFastLoopBack_ADDR_END 11343 -#define D_pFastLoopBack_sizeof 2 +#define D_loopCounter_ADDR 11408 +#define D_loopCounter_ADDR_END 11411 +#define D_loopCounter_sizeof 4 -#define D_pNextFastLoopBack_ADDR 11344 -#define D_pNextFastLoopBack_ADDR_END 11347 -#define D_pNextFastLoopBack_sizeof 4 +#define D_RewindFlag_ADDR 11412 +#define D_RewindFlag_ADDR_END 11413 +#define D_RewindFlag_sizeof 2 -#define D_ppCurrentTask_ADDR 11348 -#define D_ppCurrentTask_ADDR_END 11349 -#define D_ppCurrentTask_sizeof 2 +#define D_Slot23_ctrl_ADDR 11416 +#define D_Slot23_ctrl_ADDR_END 11419 +#define D_Slot23_ctrl_sizeof 4 -#define D_slotCounter_ADDR 11352 -#define D_slotCounter_ADDR_END 11353 -#define D_slotCounter_sizeof 2 +#define D_McuIrqFifo_ADDR 11420 +#define D_McuIrqFifo_ADDR_END 11483 +#define D_McuIrqFifo_sizeof 64 -#define D_loopCounter_ADDR 11356 -#define D_loopCounter_ADDR_END 11359 -#define D_loopCounter_sizeof 4 +#define D_PingPongDesc_ADDR 11484 +#define D_PingPongDesc_ADDR_END 11531 +#define D_PingPongDesc_sizeof 48 -#define D_RewindFlag_ADDR 11360 -#define D_RewindFlag_ADDR_END 11361 -#define D_RewindFlag_sizeof 2 +#define D_PP_MCU_IRQ_ADDR 11532 +#define D_PP_MCU_IRQ_ADDR_END 11533 +#define D_PP_MCU_IRQ_sizeof 2 -#define D_Slot23_ctrl_ADDR 11364 -#define D_Slot23_ctrl_ADDR_END 11367 -#define D_Slot23_ctrl_sizeof 4 +#define D_ctrlPortFifo_ADDR 11536 +#define D_ctrlPortFifo_ADDR_END 11551 +#define D_ctrlPortFifo_sizeof 16 -#define D_McuIrqFifo_ADDR 11368 -#define D_McuIrqFifo_ADDR_END 11431 -#define D_McuIrqFifo_sizeof 64 +#define D_Idle_State_ADDR 11552 +#define D_Idle_State_ADDR_END 11555 +#define D_Idle_State_sizeof 4 -#define D_PingPongDesc_ADDR 11432 -#define D_PingPongDesc_ADDR_END 11479 -#define D_PingPongDesc_sizeof 48 +#define D_Stop_Request_ADDR 11556 +#define D_Stop_Request_ADDR_END 11559 +#define D_Stop_Request_sizeof 4 -#define D_PP_MCU_IRQ_ADDR 11480 -#define D_PP_MCU_IRQ_ADDR_END 11481 -#define D_PP_MCU_IRQ_sizeof 2 +#define D_Ref0_ADDR 11560 +#define D_Ref0_ADDR_END 11561 +#define D_Ref0_sizeof 2 -#define D_ctrlPortFifo_ADDR 11488 -#define D_ctrlPortFifo_ADDR_END 11503 -#define D_ctrlPortFifo_sizeof 16 +#define D_DebugRegister_ADDR 11564 +#define D_DebugRegister_ADDR_END 11703 +#define D_DebugRegister_sizeof 140 -#define D_Idle_State_ADDR 11504 -#define D_Idle_State_ADDR_END 11507 -#define D_Idle_State_sizeof 4 +#define D_Gcount_ADDR 11704 +#define D_Gcount_ADDR_END 11705 +#define D_Gcount_sizeof 2 -#define D_Stop_Request_ADDR 11508 -#define D_Stop_Request_ADDR_END 11511 -#define D_Stop_Request_sizeof 4 +#define D_DCcounter_ADDR 11708 +#define D_DCcounter_ADDR_END 11711 +#define D_DCcounter_sizeof 4 -#define D_Ref0_ADDR 11512 -#define D_Ref0_ADDR_END 11513 -#define D_Ref0_sizeof 2 +#define D_DCsum_ADDR 11712 +#define D_DCsum_ADDR_END 11719 +#define D_DCsum_sizeof 8 -#define D_DebugRegister_ADDR 11516 -#define D_DebugRegister_ADDR_END 11655 -#define D_DebugRegister_sizeof 140 +#define D_fastCounter_ADDR 11720 +#define D_fastCounter_ADDR_END 11723 +#define D_fastCounter_sizeof 4 -#define D_Gcount_ADDR 11656 -#define D_Gcount_ADDR_END 11657 -#define D_Gcount_sizeof 2 +#define D_slowCounter_ADDR 11724 +#define D_slowCounter_ADDR_END 11727 +#define D_slowCounter_sizeof 4 -#define D_DCcounter_ADDR 11660 -#define D_DCcounter_ADDR_END 11663 -#define D_DCcounter_sizeof 4 +#define D_aUplinkRouting_ADDR 11728 +#define D_aUplinkRouting_ADDR_END 11759 +#define D_aUplinkRouting_sizeof 32 -#define D_DCsum_ADDR 11664 -#define D_DCsum_ADDR_END 11671 -#define D_DCsum_sizeof 8 +#define D_VirtAudioLoop_ADDR 11760 +#define D_VirtAudioLoop_ADDR_END 11763 +#define D_VirtAudioLoop_sizeof 4 -#define D_fastCounter_ADDR 11672 -#define D_fastCounter_ADDR_END 11675 -#define D_fastCounter_sizeof 4 +#define D_AsrcVars_DL_VX_ADDR 11764 +#define D_AsrcVars_DL_VX_ADDR_END 11795 +#define D_AsrcVars_DL_VX_sizeof 32 -#define D_slowCounter_ADDR 11676 -#define D_slowCounter_ADDR_END 11679 -#define D_slowCounter_sizeof 4 +#define D_AsrcVars_UL_VX_ADDR 11796 +#define D_AsrcVars_UL_VX_ADDR_END 11827 +#define D_AsrcVars_UL_VX_sizeof 32 -#define D_aUplinkRouting_ADDR 11680 -#define D_aUplinkRouting_ADDR_END 11711 -#define D_aUplinkRouting_sizeof 32 +#define D_CoefAddresses_VX_ADDR 11828 +#define D_CoefAddresses_VX_ADDR_END 11859 +#define D_CoefAddresses_VX_sizeof 32 -#define D_VirtAudioLoop_ADDR 11712 -#define D_VirtAudioLoop_ADDR_END 11715 -#define D_VirtAudioLoop_sizeof 4 +#define D_AsrcVars_DL_MM_ADDR 11860 +#define D_AsrcVars_DL_MM_ADDR_END 11891 +#define D_AsrcVars_DL_MM_sizeof 32 -#define D_AsrcVars_DL_VX_ADDR 11716 -#define D_AsrcVars_DL_VX_ADDR_END 11747 -#define D_AsrcVars_DL_VX_sizeof 32 +#define D_CoefAddresses_DL_MM_ADDR 11892 +#define D_CoefAddresses_DL_MM_ADDR_END 11923 +#define D_CoefAddresses_DL_MM_sizeof 32 -#define D_AsrcVars_UL_VX_ADDR 11748 -#define D_AsrcVars_UL_VX_ADDR_END 11779 -#define D_AsrcVars_UL_VX_sizeof 32 +#define D_APS_DL1_M_thresholds_ADDR 11924 +#define D_APS_DL1_M_thresholds_ADDR_END 11931 +#define D_APS_DL1_M_thresholds_sizeof 8 -#define D_CoefAddresses_VX_ADDR 11780 -#define D_CoefAddresses_VX_ADDR_END 11811 -#define D_CoefAddresses_VX_sizeof 32 +#define D_APS_DL1_M_IRQ_ADDR 11932 +#define D_APS_DL1_M_IRQ_ADDR_END 11933 +#define D_APS_DL1_M_IRQ_sizeof 2 -#define D_AsrcVars_DL_MM_ADDR 11812 -#define D_AsrcVars_DL_MM_ADDR_END 11843 -#define D_AsrcVars_DL_MM_sizeof 32 +#define D_APS_DL1_C_IRQ_ADDR 11934 +#define D_APS_DL1_C_IRQ_ADDR_END 11935 +#define D_APS_DL1_C_IRQ_sizeof 2 -#define D_CoefAddresses_DL_MM_ADDR 11844 -#define D_CoefAddresses_DL_MM_ADDR_END 11875 -#define D_CoefAddresses_DL_MM_sizeof 32 +#define D_TraceBufAdr_ADDR 11936 +#define D_TraceBufAdr_ADDR_END 11937 +#define D_TraceBufAdr_sizeof 2 -#define D_APS_DL1_M_thresholds_ADDR 11876 -#define D_APS_DL1_M_thresholds_ADDR_END 11883 -#define D_APS_DL1_M_thresholds_sizeof 8 +#define D_TraceBufOffset_ADDR 11938 +#define D_TraceBufOffset_ADDR_END 11939 +#define D_TraceBufOffset_sizeof 2 -#define D_APS_DL1_M_IRQ_ADDR 11884 -#define D_APS_DL1_M_IRQ_ADDR_END 11885 -#define D_APS_DL1_M_IRQ_sizeof 2 +#define D_TraceBufLength_ADDR 11940 +#define D_TraceBufLength_ADDR_END 11941 +#define D_TraceBufLength_sizeof 2 -#define D_APS_DL1_C_IRQ_ADDR 11886 -#define D_APS_DL1_C_IRQ_ADDR_END 11887 -#define D_APS_DL1_C_IRQ_sizeof 2 +#define D_AsrcVars_ECHO_REF_ADDR 11944 +#define D_AsrcVars_ECHO_REF_ADDR_END 11975 +#define D_AsrcVars_ECHO_REF_sizeof 32 -#define D_TraceBufAdr_ADDR 11888 -#define D_TraceBufAdr_ADDR_END 11889 -#define D_TraceBufAdr_sizeof 2 +#define D_Pempty_ADDR 11976 +#define D_Pempty_ADDR_END 11979 +#define D_Pempty_sizeof 4 -#define D_TraceBufOffset_ADDR 11890 -#define D_TraceBufOffset_ADDR_END 11891 -#define D_TraceBufOffset_sizeof 2 +#define D_APS_DL2_L_M_IRQ_ADDR 11980 +#define D_APS_DL2_L_M_IRQ_ADDR_END 11981 +#define D_APS_DL2_L_M_IRQ_sizeof 2 -#define D_TraceBufLength_ADDR 11892 -#define D_TraceBufLength_ADDR_END 11893 -#define D_TraceBufLength_sizeof 2 +#define D_APS_DL2_L_C_IRQ_ADDR 11982 +#define D_APS_DL2_L_C_IRQ_ADDR_END 11983 +#define D_APS_DL2_L_C_IRQ_sizeof 2 -#define D_AsrcVars_ECHO_REF_ADDR 11896 -#define D_AsrcVars_ECHO_REF_ADDR_END 11927 -#define D_AsrcVars_ECHO_REF_sizeof 32 +#define D_APS_DL2_R_M_IRQ_ADDR 11984 +#define D_APS_DL2_R_M_IRQ_ADDR_END 11985 +#define D_APS_DL2_R_M_IRQ_sizeof 2 -#define D_Pempty_ADDR 11928 -#define D_Pempty_ADDR_END 11931 -#define D_Pempty_sizeof 4 +#define D_APS_DL2_R_C_IRQ_ADDR 11986 +#define D_APS_DL2_R_C_IRQ_ADDR_END 11987 +#define D_APS_DL2_R_C_IRQ_sizeof 2 -#define D_APS_DL2_L_M_IRQ_ADDR 11932 -#define D_APS_DL2_L_M_IRQ_ADDR_END 11933 -#define D_APS_DL2_L_M_IRQ_sizeof 2 +#define D_APS_DL1_C_thresholds_ADDR 11988 +#define D_APS_DL1_C_thresholds_ADDR_END 11995 +#define D_APS_DL1_C_thresholds_sizeof 8 -#define D_APS_DL2_L_C_IRQ_ADDR 11934 -#define D_APS_DL2_L_C_IRQ_ADDR_END 11935 -#define D_APS_DL2_L_C_IRQ_sizeof 2 +#define D_APS_DL2_L_M_thresholds_ADDR 11996 +#define D_APS_DL2_L_M_thresholds_ADDR_END 12003 +#define D_APS_DL2_L_M_thresholds_sizeof 8 -#define D_APS_DL2_R_M_IRQ_ADDR 11936 -#define D_APS_DL2_R_M_IRQ_ADDR_END 11937 -#define D_APS_DL2_R_M_IRQ_sizeof 2 +#define D_APS_DL2_L_C_thresholds_ADDR 12004 +#define D_APS_DL2_L_C_thresholds_ADDR_END 12011 +#define D_APS_DL2_L_C_thresholds_sizeof 8 -#define D_APS_DL2_R_C_IRQ_ADDR 11938 -#define D_APS_DL2_R_C_IRQ_ADDR_END 11939 -#define D_APS_DL2_R_C_IRQ_sizeof 2 +#define D_APS_DL2_R_M_thresholds_ADDR 12012 +#define D_APS_DL2_R_M_thresholds_ADDR_END 12019 +#define D_APS_DL2_R_M_thresholds_sizeof 8 -#define D_APS_DL1_C_thresholds_ADDR 11940 -#define D_APS_DL1_C_thresholds_ADDR_END 11947 -#define D_APS_DL1_C_thresholds_sizeof 8 +#define D_APS_DL2_R_C_thresholds_ADDR 12020 +#define D_APS_DL2_R_C_thresholds_ADDR_END 12027 +#define D_APS_DL2_R_C_thresholds_sizeof 8 -#define D_APS_DL2_L_M_thresholds_ADDR 11948 -#define D_APS_DL2_L_M_thresholds_ADDR_END 11955 -#define D_APS_DL2_L_M_thresholds_sizeof 8 +#define D_ECHO_REF_48_16_WRAP_ADDR 12028 +#define D_ECHO_REF_48_16_WRAP_ADDR_END 12035 +#define D_ECHO_REF_48_16_WRAP_sizeof 8 -#define D_APS_DL2_L_C_thresholds_ADDR 11956 -#define D_APS_DL2_L_C_thresholds_ADDR_END 11963 -#define D_APS_DL2_L_C_thresholds_sizeof 8 +#define D_ECHO_REF_48_8_WRAP_ADDR 12036 +#define D_ECHO_REF_48_8_WRAP_ADDR_END 12043 +#define D_ECHO_REF_48_8_WRAP_sizeof 8 -#define D_APS_DL2_R_M_thresholds_ADDR 11964 -#define D_APS_DL2_R_M_thresholds_ADDR_END 11971 -#define D_APS_DL2_R_M_thresholds_sizeof 8 +#define D_BT_UL_16_48_WRAP_ADDR 12044 +#define D_BT_UL_16_48_WRAP_ADDR_END 12051 +#define D_BT_UL_16_48_WRAP_sizeof 8 -#define D_APS_DL2_R_C_thresholds_ADDR 11972 -#define D_APS_DL2_R_C_thresholds_ADDR_END 11979 -#define D_APS_DL2_R_C_thresholds_sizeof 8 +#define D_BT_UL_8_48_WRAP_ADDR 12052 +#define D_BT_UL_8_48_WRAP_ADDR_END 12059 +#define D_BT_UL_8_48_WRAP_sizeof 8 -#define D_ECHO_REF_48_16_WRAP_ADDR 11980 -#define D_ECHO_REF_48_16_WRAP_ADDR_END 11987 -#define D_ECHO_REF_48_16_WRAP_sizeof 8 +#define D_BT_DL_48_16_WRAP_ADDR 12060 +#define D_BT_DL_48_16_WRAP_ADDR_END 12067 +#define D_BT_DL_48_16_WRAP_sizeof 8 -#define D_ECHO_REF_48_8_WRAP_ADDR 11988 -#define D_ECHO_REF_48_8_WRAP_ADDR_END 11995 -#define D_ECHO_REF_48_8_WRAP_sizeof 8 +#define D_BT_DL_48_8_WRAP_ADDR 12068 +#define D_BT_DL_48_8_WRAP_ADDR_END 12075 +#define D_BT_DL_48_8_WRAP_sizeof 8 -#define D_BT_UL_16_48_WRAP_ADDR 11996 -#define D_BT_UL_16_48_WRAP_ADDR_END 12003 -#define D_BT_UL_16_48_WRAP_sizeof 8 +#define D_VX_DL_16_48_WRAP_ADDR 12076 +#define D_VX_DL_16_48_WRAP_ADDR_END 12083 +#define D_VX_DL_16_48_WRAP_sizeof 8 -#define D_BT_UL_8_48_WRAP_ADDR 12004 -#define D_BT_UL_8_48_WRAP_ADDR_END 12011 -#define D_BT_UL_8_48_WRAP_sizeof 8 +#define D_VX_DL_8_48_WRAP_ADDR 12084 +#define D_VX_DL_8_48_WRAP_ADDR_END 12091 +#define D_VX_DL_8_48_WRAP_sizeof 8 -#define D_BT_DL_48_16_WRAP_ADDR 12012 -#define D_BT_DL_48_16_WRAP_ADDR_END 12019 -#define D_BT_DL_48_16_WRAP_sizeof 8 +#define D_VX_UL_48_16_WRAP_ADDR 12092 +#define D_VX_UL_48_16_WRAP_ADDR_END 12099 +#define D_VX_UL_48_16_WRAP_sizeof 8 -#define D_BT_DL_48_8_WRAP_ADDR 12020 -#define D_BT_DL_48_8_WRAP_ADDR_END 12027 -#define D_BT_DL_48_8_WRAP_sizeof 8 +#define D_VX_UL_48_8_WRAP_ADDR 12100 +#define D_VX_UL_48_8_WRAP_ADDR_END 12107 +#define D_VX_UL_48_8_WRAP_sizeof 8 -#define D_VX_DL_16_48_WRAP_ADDR 12028 -#define D_VX_DL_16_48_WRAP_ADDR_END 12035 -#define D_VX_DL_16_48_WRAP_sizeof 8 +#define D_APS_DL1_IRQs_WRAP_ADDR 12108 +#define D_APS_DL1_IRQs_WRAP_ADDR_END 12115 +#define D_APS_DL1_IRQs_WRAP_sizeof 8 -#define D_VX_DL_8_48_WRAP_ADDR 12036 -#define D_VX_DL_8_48_WRAP_ADDR_END 12043 -#define D_VX_DL_8_48_WRAP_sizeof 8 +#define D_APS_DL2_L_IRQs_WRAP_ADDR 12116 +#define D_APS_DL2_L_IRQs_WRAP_ADDR_END 12123 +#define D_APS_DL2_L_IRQs_WRAP_sizeof 8 -#define D_VX_UL_48_16_WRAP_ADDR 12044 -#define D_VX_UL_48_16_WRAP_ADDR_END 12051 -#define D_VX_UL_48_16_WRAP_sizeof 8 +#define D_APS_DL2_R_IRQs_WRAP_ADDR 12124 +#define D_APS_DL2_R_IRQs_WRAP_ADDR_END 12131 +#define D_APS_DL2_R_IRQs_WRAP_sizeof 8 -#define D_VX_UL_48_8_WRAP_ADDR 12052 -#define D_VX_UL_48_8_WRAP_ADDR_END 12059 -#define D_VX_UL_48_8_WRAP_sizeof 8 +#define D_nextMultiFrame_ADDR 12132 +#define D_nextMultiFrame_ADDR_END 12139 +#define D_nextMultiFrame_sizeof 8 -#define D_APS_DL1_IRQs_WRAP_ADDR 12060 -#define D_APS_DL1_IRQs_WRAP_ADDR_END 12067 -#define D_APS_DL1_IRQs_WRAP_sizeof 8 +#define D_HW_TEST_ADDR 12140 +#define D_HW_TEST_ADDR_END 12147 +#define D_HW_TEST_sizeof 8 -#define D_APS_DL2_L_IRQs_WRAP_ADDR 12068 -#define D_APS_DL2_L_IRQs_WRAP_ADDR_END 12075 -#define D_APS_DL2_L_IRQs_WRAP_sizeof 8 +#define D_TraceBufAdr_HAL_ADDR 12148 +#define D_TraceBufAdr_HAL_ADDR_END 12151 +#define D_TraceBufAdr_HAL_sizeof 4 -#define D_APS_DL2_R_IRQs_WRAP_ADDR 12076 -#define D_APS_DL2_R_IRQs_WRAP_ADDR_END 12083 -#define D_APS_DL2_R_IRQs_WRAP_sizeof 8 +#define D_DEBUG_HAL_TASK_ADDR 12288 +#define D_DEBUG_HAL_TASK_ADDR_END 14335 +#define D_DEBUG_HAL_TASK_sizeof 2048 -#define D_nextMultiFrame_ADDR 12084 -#define D_nextMultiFrame_ADDR_END 12091 -#define D_nextMultiFrame_sizeof 8 +#define D_DEBUG_FW_TASK_ADDR 14336 +#define D_DEBUG_FW_TASK_ADDR_END 14591 +#define D_DEBUG_FW_TASK_sizeof 256 -#define D_HW_TEST_ADDR 12092 -#define D_HW_TEST_ADDR_END 12099 -#define D_HW_TEST_sizeof 8 +#define D_FwMemInit_ADDR 14592 +#define D_FwMemInit_ADDR_END 15383 +#define D_FwMemInit_sizeof 792 -#define D_DEBUG_HAL_TASK_ADDR 12288 -#define D_DEBUG_HAL_TASK_ADDR_END 14335 -#define D_DEBUG_HAL_TASK_sizeof 2048 +#define D_FwMemInitDescr_ADDR 15384 +#define D_FwMemInitDescr_ADDR_END 15399 +#define D_FwMemInitDescr_sizeof 16 -#define D_DEBUG_FW_TASK_ADDR 14336 -#define D_DEBUG_FW_TASK_ADDR_END 14591 -#define D_DEBUG_FW_TASK_sizeof 256 +#define D_PING_ADDR 16384 +#define D_PING_ADDR_END 40959 +#define D_PING_sizeof 24576 -#define D_PING_ADDR 16384 -#define D_PING_ADDR_END 40959 -#define D_PING_sizeof 24576 +#define D_PONG_ADDR 40960 +#define D_PONG_ADDR_END 65535 +#define D_PONG_sizeof 24576 -#define D_PONG_ADDR 40960 -#define D_PONG_ADDR_END 65535 -#define D_PONG_sizeof 24576 -#endif /* _ABE_DM_ADDR_H_ */ +#endif /* _ABEDM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_ext.c b/sound/soc/omap/abe/abe_ext.c index c609f5684927..de63de534a68 100644 --- a/sound/soc/omap/abe/abe_ext.c +++ b/sound/soc/omap/abe/abe_ext.c @@ -1,176 +1,146 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" -#if 0 -/* - * ABE_DEFAULT_IRQ_PINGPONG_PLAYER - * - * - * Operations : - * generates data for the cache-flush buffer MODE 16+16 +/** + * abe_default_irq_pingpong_player * - * Return value : - * None. + * generates data for the cache-flush buffer MODE 16+16 */ -void abe_default_irq_pingpong_player(void) +void abe_default_irq_pingpong_player (void) { - /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ - #define N_SAMPLES_MAX ((int)(1024)) - - static abe_int32 idx; - abe_uint32 i, dst, n_samples, n_bytes; - abe_int32 temp [N_SAMPLES_MAX], audio_sample; -#define DATA_SIZE 20 - const abe_int32 audio_pattern [DATA_SIZE] = - { - 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630, - 5063, 0, -5063, -9630, -13254, -15581, -16383, -15581, +#define N_SAMPLES_MAX ((int)(1024)) /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp [N_SAMPLES_MAX], audio_sample; +#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ + const s32 audio_pattern [DATA_SIZE] = { + 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630, +5063, 0, -5063, -9630, -13254, -15581, -16383, -15581, -13254, -9630, -5063 }; +#if 0 +#define DATA_SIZE 8 + const s32 audio_pattern [DATA_SIZE] = {0, 11585, 16384, 11585, 0, -11586, -16384, -11586 }; + +#define DATA_SIZE 12 + const s32 audio_pattern [DATA_SIZE] = {0, 8191, 14188, 16383, 14188, 8191, 0, -8192, -14188, -16383, -14188, -8192}; + +const s32 audio_pattern [8] = {16383,16383,16383,16383,-16384,-16384,-16384,-16384}; +#endif /* read the address of the Pong buffer */ - abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + abe_read_next_ping_pong_buffer (MM_DL_PORT, &dst, &n_bytes); + + + n_samples = n_bytes / 4; /* each stereo sample weights 4 bytes (format 16|16) */ - n_samples = n_bytes / 4; /* generate a test pattern */ for (i = 0; i < n_samples; i++) { audio_sample = audio_pattern [idx]; idx = (idx >= (DATA_SIZE-1))? 0: (idx+1); - temp[i] = ((audio_sample << 16) + audio_sample); + temp [i] = ((audio_sample << 16) + audio_sample); /* format 16|16 */ } /* copy the pattern (flush it) to DMEM pointer update * not necessary here because the buffer size do not * change from one ping to the other pong */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (abe_uint32 *)&(temp[0]), n_samples * 4); - abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (u32 *)&(temp[0]), n_bytes); + abe_set_ping_pong_buffer (MM_DL_PORT, n_bytes); } -/* - * ABE_DEFAULT_IRQ_PINGPONG_PLAYER_32BITS +/** + * abe_default_irq_pingpong_player_32bits * - * Operations: * generates data for the cache-flush buffer MODE 32 BITS * Return value: * None. */ -void abe_default_irq_pingpong_player_32bits(void) +void abe_default_irq_pingpong_player_32bits (void) { -/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ -#define N_SAMPLES_MAX ((int)(1024)) - static abe_int32 idx; - abe_uint32 i, dst, n_samples, n_bytes; - abe_int32 temp[N_SAMPLES_MAX], audio_sample; + /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + static s32 idx; + u32 i, dst, n_samples, n_bytes; + s32 temp [N_SAMPLES_MAX], audio_sample; #define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */ - const abe_int32 audio_pattern [DATA_SIZE] = - { + const s32 audio_pattern [DATA_SIZE] = { 0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630, 5063, 0, -5063, -9630, -13254, -15581, -16383, -15581, -13254, -9630, -5063 }; /* read the address of the Pong buffer */ - abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes); + abe_read_next_ping_pong_buffer (MM_DL_PORT, &dst, &n_bytes); n_samples = n_bytes / 8; /* each stereo sample weights 8 bytes (format 32|32) */ /* generate a test pattern */ for (i = 0; i < n_samples; i++) { /* circular addressing */ - audio_sample = audio_pattern[idx]; + audio_sample = audio_pattern [idx]; idx = (idx >= (DATA_SIZE-1))? 0: (idx+1); - temp[i*2 +0] = (audio_sample << 16); - temp[i*2 +1] = (audio_sample << 16); + temp [i*2 +0] = (audio_sample << 16); + temp [i*2 +1] = (audio_sample << 16); } /* copy the pattern (flush it) to DMEM pointer update * not necessary here because the buffer size do not * change from one ping to the other pong */ - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, - (abe_uint32 *)&(temp[0]), n_samples * 4 *2); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (u32 *)&(temp[0]), n_bytes); - abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes); + abe_set_ping_pong_buffer (MM_DL_PORT, n_bytes); } -#endif -/* - * ABE_DEFAULT_IRQ_APS_ADAPTATION + +/** + * abe_default_irq_aps_adaptation * - * Operations : * updates the APS filter and gain - * - * Return value : - * None. */ -void abe_default_irq_aps_adaptation(void) +void abe_default_irq_aps_adaptation (void) { } -/* - * ABE_READ_SYS_CLOCK - * - * Parameter : - * pointer to the system clock - * - * Operations : - * returns the current time indication for the LOG +/** + * abe_read_sys_clock + * @time: pointer to the system clock * - * Return value : - * None. + * returns the current time indication for the LOG */ -void abe_read_sys_clock(abe_micros_t *time) +void abe_read_sys_clock (u32 *time) { - static abe_micros_t clock; + static u32 clock; *time = clock; clock ++; } -/* - * ABE_APS_TUNING - * - * Parameter : - * - * - * Operations : - * +/** + * abe_aps_tuning * - * Return value : + * Tune APS parameters * */ -void abe_aps_tuning(void) -{ -} - -/** -* @fn abe_lock_executione() -* -* Operations : set a spin-lock and wait in case of collision -* -* -* @see ABE_API.h -*/ -void abe_lock_execution(void) -{ -} - -/** -* @fn abe_unlock_executione() -* -* Operations : reset a spin-lock (end of subroutine) -* -* -* @see ABE_API.h -*/ -void abe_unlock_execution(void) +void abe_aps_tuning (void) { } diff --git a/sound/soc/omap/abe/abe_ext.h b/sound/soc/omap/abe/abe_ext.h index d83b4331a904..caab2c697cea 100644 --- a/sound/soc/omap/abe/abe_ext.h +++ b/sound/soc/omap/abe/abe_ext.h @@ -1,18 +1,48 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #ifndef _ABE_EXT_H_ #define _ABE_EXT_H_ -#include <linux/io.h> -#define PC_SIMULATION 0 /* Tuning is done on PC ? */ +/* Tuning is done on PC ? */ +#define PC_SIMULATION 0 + +#if PC_SIMULATION +extern void target_server_read_pmem (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_write_pmem (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_read_cmem (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_write_cmem (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_read_atc (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_write_atc (u32 address, u32 *data, u32 nb_words_32bits); +extern void target_server_read_smem (u32 address_48bits, u32 *data, u32 nb_words_48bits); +extern void target_server_write_smem (u32 address_48bits, u32 *data, u32 nb_words_48bits); +extern void target_server_read_dmem (u32 address_byte, u32 *data, u32 nb_byte); +extern void target_server_write_dmem (u32 address_byte, u32 *data, u32 nb_byte); + +extern void target_server_activate_mcpdm_ul (void); +extern void target_server_activate_mcpdm_dl (void); +extern void target_server_activate_dmic (void); +extern void target_server_set_voice_sampling (int dVirtAudioVoiceMode, int dVirtAudioVoiceSampleFrequency); +extern void target_server_set_dVirtAudioMultimediaMode (int dVirtAudioMultimediaMode); +#endif /* * OS DEPENDENT MMU CONFIGURATION @@ -21,150 +51,255 @@ #define _lock_enter #define _lock_exit -#define ABE_ATC_BASE_ADDRESS_L3 0x490F1000L /* base address used for L3/DMA access */ -#define ABE_ATC_BASE_ADDRESS_L4 0x401F1000L /* base address used for L4/MCU access */ -#define ABE_DMEM_BASE_ADDRESS_L3 0x49080000L /* 64kB as seen from DMA access */ -#define ABE_DMEM_BASE_ADDRESS_L4 0x40180000L /* 64kB as seen from MCU access */ - - -#if 0 -#define ABE_PMEM_BASE_ADDRESS_MPU 0x401E0000L /* 8kB as seen from MPU access */ -#define ABE_CMEM_BASE_ADDRESS_MPU 0x401A0000L /* 8kB +++++++++++++++++++++++ */ -#define ABE_SMEM_BASE_ADDRESS_MPU 0x401C0000L /* 24kB */ -#define ABE_DMEM_BASE_ADDRESS_MPU 0x40180000L /* 64kB */ -#define ABE_ATC_BASE_ADDRESS_MPU 0x401F1000L -#else -#define ABE_PMEM_BASE_ADDRESS_MPU 0x490E0000L /* 8kB as seen from MPU access */ -#define ABE_CMEM_BASE_ADDRESS_MPU 0x490A0000L /* 8kB +++++++++++++++++++++++ */ -#define ABE_SMEM_BASE_ADDRESS_MPU 0x490C0000L /* 24kB */ -#define ABE_DMEM_BASE_ADDRESS_MPU 0x49080000L /* 64kB */ -#define ABE_ATC_BASE_ADDRESS_MPU 0x490F1000L -#endif +/* base address used for L3/DMA access */ +#define ABE_ATC_BASE_ADDRESS_L3 0x490F1000L + +/* base address used for L4/MCU access */ +#define ABE_ATC_BASE_ADDRESS_L4 0x401F1000L + +/* 64kB as seen from DMA access */ +#define ABE_DMEM_BASE_ADDRESS_L3 0x49080000L + +/* 64kB as seen from MCU access */ +#define ABE_DMEM_BASE_ADDRESS_L4 0x40180000L + +/* 8kB as seen from MPU access */ +#define ABE_PMEM_BASE_ADDRESS_MPU 0x490E0000L + +/* 8kB */ +#define ABE_CMEM_BASE_ADDRESS_MPU 0x490A0000L + +/* 24kB */ +#define ABE_SMEM_BASE_ADDRESS_MPU 0x490C0000L + +/* 64kB */ +#define ABE_DMEM_BASE_ADDRESS_MPU 0x49080000L +#define ABE_ATC_BASE_ADDRESS_MPU 0x490F1000L /* * HARDWARE AND PERIPHERAL DEFINITIONS */ -#define ABE_PMEM_SIZE 8192 /* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/ -#define ABE_CMEM_SIZE 8192 /* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/ -#define ABE_SMEM_SIZE 24576 /* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/ -#define ABE_DMEM_SIZE 65536L /* DMEM SIZE in bytes */ -#define ABE_ATC_DESC_SIZE 512 /* ATC REGISTERS SIZE in bytes */ +/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/ +#define ABE_PMEM_SIZE 8192 + +/* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/ +#define ABE_CMEM_SIZE 8192 + +/* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/ +#define ABE_SMEM_SIZE 24576 +/* DMEM SIZE in bytes */ +#define ABE_DMEM_SIZE 65536L -#define ABE_MCU_IRQSTATUS_RAW 0x24 /* holds the MCU Irq signal */ -#define ABE_MCU_IRQSTATUS 0x28 /* status : clear the IRQ */ -#define ABE_DSP_IRQSTATUS_RAW 0x4C /* holds the DSP Irq signal */ -#define ABE_DMASTATUS_RAW 0x84 /* holds the DMA req lines to the sDMA */ +/* ATC REGISTERS SIZE in bytes */ +#define ABE_ATC_DESC_SIZE 512 +/* holds the MCU Irq signal */ +#define ABE_MCU_IRQSTATUS_RAW 0x24 -#define EVENT_GENERATOR_COUNTER 0x68 -#define EVENT_GENERATOR_COUNTER_DEFAULT 2048 /* PLL output/desired sampling rate = (32768 * 6000)/96000 */ -#define EVENT_GENERATOR_COUNTER_44100 2229 /* PLL output/desired sampling rate = (32768 * 6000)/88200 */ +/* status : clear the IRQ */ +#define ABE_MCU_IRQSTATUS 0x28 -#define EVENT_GENERATOR_START 0x6C /* start / stop the EVENT generator */ -#define EVENT_GENERATOR_ON 1 -#define EVENT_GENERATOR_OFF 0 +/* holds the DSP Irq signal */ +#define ABE_DSP_IRQSTATUS_RAW 0x4C -#define EVENT_SOURCE_SELECTION 0x70 /* selection of the EVENT generator source */ -#define EVENT_SOURCE_DMA 0 -#define EVENT_SOURCE_COUNTER 1 +/* holds the DMA req lines to the sDMA */ +#define ABE_DMASTATUS_RAW 0x84 -#define AUDIO_ENGINE_SCHEDULER 0x74 /* selection of the ABE DMA req line from ATC */ -#define ABE_ATC_DMIC_DMA_REQ 1 -#define ABE_ATC_MCPDMDL_DMA_REQ 2 -#define ABE_ATC_MCPDMUL_DMA_REQ 3 -#define ABE_ATC_DIRECTION_IN 0 /* Direction=0 means input from ABE point of view */ -#define ABE_ATC_DIRECTION_OUT 1 /* Direction=1 means output from ABE point of view */ + +#define EVENT_GENERATOR_COUNTER 0x68 + +/* PLL output/desired sampling rate = (32768 * 6000)/96000 */ +#define EVENT_GENERATOR_COUNTER_DEFAULT 2048 + +/* PLL output/desired sampling rate = (32768 * 6000)/88200 */ +#define EVENT_GENERATOR_COUNTER_44100 2228 + +/* start / stop the EVENT generator */ +#define EVENT_GENERATOR_START 0x6C +#define EVENT_GENERATOR_ON 1 +#define EVENT_GENERATOR_OFF 0 + +/* selection of the EVENT generator source */ +#define EVENT_SOURCE_SELECTION 0x70 +#define EVENT_SOURCE_DMA 0 +#define EVENT_SOURCE_COUNTER 1 + +/* selection of the ABE DMA req line from ATC */ +#define AUDIO_ENGINE_SCHEDULER 0x74 +#define ABE_ATC_DMIC_DMA_REQ 1 +#define ABE_ATC_MCPDMDL_DMA_REQ 2 +#define ABE_ATC_MCPDMUL_DMA_REQ 3 + +/* Direction=0 means input from ABE point of view */ +#define ABE_ATC_DIRECTION_IN 0 + +/* Direction=1 means output from ABE point of view */ +#define ABE_ATC_DIRECTION_OUT 1 /* - * * DMA requests - * */ -#define External_DMA_0 0 /*Internal connection doesn't connect at ABE boundary */ -#define DMIC_DMA_REQ 1 /*Transmit request digital microphone */ -#define McPDM_DMA_DL 2 /*Multichannel PDM downlink */ -#define McPDM_DMA_UP 3 /*Multichannel PDM uplink */ -#define MCBSP1_DMA_TX 4 /*MCBSP module 1 - transmit request */ -#define MCBSP1_DMA_RX 5 /*MCBSP module 1 - receive request */ -#define MCBSP2_DMA_TX 6 /*MCBSP module 2 - transmit request */ -#define MCBSP2_DMA_RX 7 /*MCBSP module 2 - receive request */ -#define MCBSP3_DMA_TX 8 /*MCBSP module 3 - transmit request */ -#define MCBSP3_DMA_RX 9 /*MCBSP module 3 - receive request */ -#define SLIMBUS1_DMA_TX0 10 /*SLIMBUS module 1 - transmit request channel 0 */ -#define SLIMBUS1_DMA_TX1 11 /*SLIMBUS module 1 - transmit request channel 1 */ -#define SLIMBUS1_DMA_TX2 12 /*SLIMBUS module 1 - transmit request channel 2 */ -#define SLIMBUS1_DMA_TX3 13 /*SLIMBUS module 1 - transmit request channel 3 */ -#define SLIMBUS1_DMA_TX4 14 /*SLIMBUS module 1 - transmit request channel 4 */ -#define SLIMBUS1_DMA_TX5 15 /*SLIMBUS module 1 - transmit request channel 5 */ -#define SLIMBUS1_DMA_TX6 16 /*SLIMBUS module 1 - transmit request channel 6 */ -#define SLIMBUS1_DMA_TX7 17 /*SLIMBUS module 1 - transmit request channel 7 */ -#define SLIMBUS1_DMA_RX0 18 /*SLIMBUS module 1 - receive request channel 0 */ -#define SLIMBUS1_DMA_RX1 19 /*SLIMBUS module 1 - receive request channel 1 */ -#define SLIMBUS1_DMA_RX2 20 /*SLIMBUS module 1 - receive request channel 2 */ -#define SLIMBUS1_DMA_RX3 21 /*SLIMBUS module 1 - receive request channel 3 */ -#define SLIMBUS1_DMA_RX4 22 /*SLIMBUS module 1 - receive request channel 4 */ -#define SLIMBUS1_DMA_RX5 23 /*SLIMBUS module 1 - receive request channel 5 */ -#define SLIMBUS1_DMA_RX6 24 /*SLIMBUS module 1 - receive request channel 6 */ -#define SLIMBUS1_DMA_RX7 25 /*SLIMBUS module 1 - receive request channel 7 */ -#define McASP1_AXEVT 26 /*McASP - Data transmit DMA request line */ -#define McASP1_AREVT 29 /*McASP - Data receive DMA request line */ -#define _DUMMY_FIFO_ 30 /*DUMMY FIFO @@@ */ -#define CBPr_DMA_RTX0 32 /*DMA of the Circular buffer peripheral 0 */ -#define CBPr_DMA_RTX1 33 /*DMA of the Circular buffer peripheral 1 */ -#define CBPr_DMA_RTX2 34 /*DMA of the Circular buffer peripheral 2 */ -#define CBPr_DMA_RTX3 35 /*DMA of the Circular buffer peripheral 3 */ -#define CBPr_DMA_RTX4 36 /*DMA of the Circular buffer peripheral 4 */ -#define CBPr_DMA_RTX5 37 /*DMA of the Circular buffer peripheral 5 */ -#define CBPr_DMA_RTX6 38 /*DMA of the Circular buffer peripheral 6 */ -#define CBPr_DMA_RTX7 39 /*DMA of the Circular buffer peripheral 7 */ + * DMA requests + */ +/*Internal connection doesn't connect at ABE boundary */ +#define External_DMA_0 0 + +/*Transmit request digital microphone */ +#define DMIC_DMA_REQ 1 + +/*Multichannel PDM downlink */ +#define McPDM_DMA_DL 2 + +/*Multichannel PDM uplink */ +#define McPDM_DMA_UP 3 + +/*MCBSP module 1 - transmit request */ +#define MCBSP1_DMA_TX 4 + +/*MCBSP module 1 - receive request */ +#define MCBSP1_DMA_RX 5 + +/*MCBSP module 2 - transmit request */ +#define MCBSP2_DMA_TX 6 + +/*MCBSP module 2 - receive request */ +#define MCBSP2_DMA_RX 7 + +/*MCBSP module 3 - transmit request */ +#define MCBSP3_DMA_TX 8 + +/*MCBSP module 3 - receive request */ +#define MCBSP3_DMA_RX 9 + +/*SLIMBUS module 1 - transmit request channel 0 */ +#define SLIMBUS1_DMA_TX0 10 + +/*SLIMBUS module 1 - transmit request channel 1 */ +#define SLIMBUS1_DMA_TX1 11 + +/*SLIMBUS module 1 - transmit request channel 2 */ +#define SLIMBUS1_DMA_TX2 12 + +/*SLIMBUS module 1 - transmit request channel 3 */ +#define SLIMBUS1_DMA_TX3 13 + +/*SLIMBUS module 1 - transmit request channel 4 */ +#define SLIMBUS1_DMA_TX4 14 + +/*SLIMBUS module 1 - transmit request channel 5 */ +#define SLIMBUS1_DMA_TX5 15 + +/*SLIMBUS module 1 - transmit request channel 6 */ +#define SLIMBUS1_DMA_TX6 16 + +/*SLIMBUS module 1 - transmit request channel 7 */ +#define SLIMBUS1_DMA_TX7 17 + +/*SLIMBUS module 1 - receive request channel 0 */ +#define SLIMBUS1_DMA_RX0 18 + +/*SLIMBUS module 1 - receive request channel 1 */ +#define SLIMBUS1_DMA_RX1 19 + +/*SLIMBUS module 1 - receive request channel 2 */ +#define SLIMBUS1_DMA_RX2 20 + +/*SLIMBUS module 1 - receive request channel 3 */ +#define SLIMBUS1_DMA_RX3 21 + +/*SLIMBUS module 1 - receive request channel 4 */ +#define SLIMBUS1_DMA_RX4 22 + +/*SLIMBUS module 1 - receive request channel 5 */ +#define SLIMBUS1_DMA_RX5 23 + +/*SLIMBUS module 1 - receive request channel 6 */ +#define SLIMBUS1_DMA_RX6 24 + +/*SLIMBUS module 1 - receive request channel 7 */ +#define SLIMBUS1_DMA_RX7 25 + +/*McASP - Data transmit DMA request line */ +#define McASP1_AXEVT 26 + +/*McASP - Data receive DMA request line */ +#define McASP1_AREVT 29 + +/*DUMMY FIFO @@@ */ +#define _DUMMY_FIFO_ 30 + +/*DMA of the Circular buffer peripheral 0 */ +#define CBPr_DMA_RTX0 32 + +/*DMA of the Circular buffer peripheral 1 */ +#define CBPr_DMA_RTX1 33 + +/*DMA of the Circular buffer peripheral 2 */ +#define CBPr_DMA_RTX2 34 + +/*DMA of the Circular buffer peripheral 3 */ +#define CBPr_DMA_RTX3 35 + +/*DMA of the Circular buffer peripheral 4 */ +#define CBPr_DMA_RTX4 36 + +/*DMA of the Circular buffer peripheral 5 */ +#define CBPr_DMA_RTX5 37 + +/*DMA of the Circular buffer peripheral 6 */ +#define CBPr_DMA_RTX6 38 + +/*DMA of the Circular buffer peripheral 7 */ +#define CBPr_DMA_RTX7 39 /* - * * ATC DESCRIPTORS - DESTINATIONS - * */ + * ATC DESCRIPTORS - DESTINATIONS + */ #define DEST_DMEM_access 0x00 -#define DEST_MCBSP1_TX 0x01 -#define DEST_MCBSP2_TX 0x02 -#define DEST_MCBSP3_TX 0x03 -#define DEST_SLIMBUS1_TX0 0x04 -#define DEST_SLIMBUS1_TX1 0x05 -#define DEST_SLIMBUS1_TX2 0x06 -#define DEST_SLIMBUS1_TX3 0x07 -#define DEST_SLIMBUS1_TX4 0x08 -#define DEST_SLIMBUS1_TX5 0x09 -#define DEST_SLIMBUS1_TX6 0x0A -#define DEST_SLIMBUS1_TX7 0x0B -#define DEST_MCPDM_DL 0x0C -#define DEST_MCASP_TX0 0x0D -#define DEST_MCASP_TX1 0x0E -#define DEST_MCASP_TX2 0x0F -#define DEST_MCASP_TX3 0x10 -#define DEST_EXTPORT0 0x11 -#define DEST_EXTPORT1 0x12 -#define DEST_EXTPORT2 0x13 -#define DEST_EXTPORT3 0x14 -#define DEST_MCPDM_ON 0x15 -#define DEST_CBP_CBPr 0x3F +#define DEST_MCBSP1_ TX 0x01 +#define DEST_MCBSP2_ TX 0x02 +#define DEST_MCBSP3_TX 0x03 +#define DEST_SLIMBUS1_TX0 0x04 +#define DEST_SLIMBUS1_TX1 0x05 +#define DEST_SLIMBUS1_TX2 0x06 +#define DEST_SLIMBUS1_TX3 0x07 +#define DEST_SLIMBUS1_TX4 0x08 +#define DEST_SLIMBUS1_TX5 0x09 +#define DEST_SLIMBUS1_TX6 0x0A +#define DEST_SLIMBUS1_TX7 0x0B +#define DEST_MCPDM_DL 0x0C +#define DEST_MCASP_TX0 0x0D +#define DEST_MCASP_TX1 0x0E +#define DEST_MCASP_TX2 0x0F +#define DEST_MCASP_TX3 0x10 +#define DEST_EXTPORT0 0x11 +#define DEST_EXTPORT1 0x12 +#define DEST_EXTPORT2 0x13 +#define DEST_EXTPORT3 0x14 +#define DEST_MCPDM_ON 0x15 +#define DEST_CBP_CBPr 0x3F /* - * * ATC DESCRIPTORS - SOURCES - * */ -#define SRC_DMEM_access 0x0 -#define SRC_MCBSP1_RX 0x01 -#define SRC_MCBSP2_RX 0x02 -#define SRC_MCBSP3_RX 0x03 -#define SRC_SLIMBUS1_RX0 0x04 -#define SRC_SLIMBUS1_RX1 0x05 -#define SRC_SLIMBUS1_RX2 0x06 -#define SRC_SLIMBUS1_RX3 0x07 -#define SRC_SLIMBUS1_RX4 0x08 -#define SRC_SLIMBUS1_RX5 0x09 -#define SRC_SLIMBUS1_RX6 0x0A -#define SRC_SLIMBUS1_RX7 0x0B -#define SRC_DMIC_UP 0x0C -#define SRC_MCPDM_UP 0x0D -#define SRC_MCASP_RX0 0x0E -#define SRC_MCASP_RX1 0x0F -#define SRC_MCASP_RX2 0x10 -#define SRC_MCASP_RX3 0x11 -#define SRC_CBP_CBPr 0x3F + * ATC DESCRIPTORS - SOURCES + */ +#define SRC_DMEM_access 0x0 +#define SRC_MCBSP1_ RX 0x01 +#define SRC_MCBSP2_RX 0x02 +#define SRC_MCBSP3_RX 0x03 +#define SRC_SLIMBUS1_RX0 0x04 +#define SRC_SLIMBUS1_RX1 0x05 +#define SRC_SLIMBUS1_RX2 0x06 +#define SRC_SLIMBUS1_RX3 0x07 +#define SRC_SLIMBUS1_RX4 0x08 +#define SRC_SLIMBUS1_RX5 0x09 +#define SRC_SLIMBUS1_RX6 0x0A +#define SRC_SLIMBUS1_RX7 0x0B +#define SRC_DMIC_UP 0x0C +#define SRC_MCPDM_UP 0x0D +#define SRC_MCASP_RX0 0x0E +#define SRC_MCASP_RX1 0x0F +#define SRC_MCASP_RX2 0x10 +#define SRC_MCASP_RX3 0x11 +#define SRC_CBP_CBPr 0x3F + #endif /* _ABE_EXT_H_ */ diff --git a/sound/soc/omap/abe/abe_firmware.c b/sound/soc/omap/abe/abe_firmware.c new file mode 100644 index 000000000000..e725cf4ddc3b --- /dev/null +++ b/sound/soc/omap/abe/abe_firmware.c @@ -0,0 +1,24218 @@ +0x00008000, /* VERSION NUMBER */ +0x00002000, /* PMEM LENGTH IN BYTES */ +0x000014A4, /* CMEM LENGTH IN BYTES */ +0x00010000, /* DMEM LENGTH IN BYTES */ +0x000045B0, /* SMEM LENGTH IN BYTES */ +0x1600200f, +0x0a000670, +0x08200000, +0x08200000, +0x07800000, +0x1602d2ce, +0x014000e0, +0x014000e1, +0x014000e2, +0x014000e3, +0x014000e4, +0x014000e5, +0x014000e6, +0x014000e7, +0x014000e8, +0x014000e9, +0x014000ea, +0x014000eb, +0x014000ec, +0x014000ed, +0x014000ef, +0x014000ef, +0x144000e4, +0x9e000000, +0x0a202d70, +0x9e000040, +0x0a202d70, +0x9e000080, +0x0a202d70, +0x9e0000c0, +0x0a202d70, +0x9e080000, +0x0a202d70, +0x9e080100, +0x0a202d70, +0x9e080200, +0x0a202d70, +0x9e080300, +0x0a202d70, +0x9e080400, +0x0a202d70, +0x9e080500, +0x0a202d70, +0x9e080600, +0x0a202d70, +0x9e080700, +0x0a202d70, +0x9c050800, +0x0a202d70, +0x16000010, +0x16000001, +0x17000102, +0x01400042, +0x17800103, +0x01400043, +0x98020000, +0x9d0c8118, +0x07800000, +0x9f16001a, +0x9f12021a, +0x9f12031a, +0x9f12051a, +0x98800380, +0x9d0c8118, +0x08200000, +0x9d0c8118, +0x07800000, +0x9f15001a, +0x9f11041a, +0x98800410, +0x9d0c8118, +0x08200000, +0x400002c0, +0x048002ff, +0x000000c5, +0x000004c6, +0x9c028000, +0x400006c7, +0x12000155, +0x013ffefe, +0xc00008c4, +0x1e080000, +0x020005de, +0x00000ac3, +0xdc02b160, +0x04c3ff2d, +0xdc01ba70, +0x128002dd, +0xdc02a440, +0x048fffdd, +0x9c061830, +0x0b200000, +0x003ffefe, +0x000002c4, +0x400004c5, +0x048ffeff, +0x000006c6, +0x000008c7, +0x9d02a040, +0x9d02a950, +0x9d01b260, +0x9d02bc70, +0x08200000, +0x1602c888, +0x00000089, +0x1602c82a, +0x400000ac, +0x1602c7c6, +0x40000066, +0x0600000c, +0x0400069b, +0x4a800720, +0x1600274d, +0x0a200480, +0x4000009c, +0x1602c80e, +0x410000ec, +0x0600000c, +0x1600274d, +0x0a800890, +0x1602ea03, +0x00000030, +0x00000231, +0x00000435, +0x04800211, +0x04400511, +0x1602c944, +0x0000004e, +0x0300010e, +0x04800211, +0x04400511, +0x0300010c, +0x04800211, +0x04400511, +0x03000109, +0x01000231, +0x0a200480, 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+0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00000000, +0x00010000, +0x00010000, diff --git a/sound/soc/omap/abe/abe_functionsId.h b/sound/soc/omap/abe/abe_functionsId.h deleted file mode 100644 index b4b03983bc0d..000000000000 --- a/sound/soc/omap/abe/abe_functionsId.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. - * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== - */ - -#ifndef _ABE_FUNCTIONSID_H_ -#define _ABE_FUNCTIONSID_H_ - -/* - * TASK function ID definitions - */ -#define C_ABE_FW_FUNCTION_IIR 0 -#define C_ABE_FW_FUNCTION_monoToStereoPack 1 -#define C_ABE_FW_FUNCTION_stereoToMonoSplit 2 -#define C_ABE_FW_FUNCTION_decimator 3 -#define C_ABE_FW_FUNCTION_OS0Fill 4 -#define C_ABE_FW_FUNCTION_mixer2 5 -#define C_ABE_FW_FUNCTION_mixer4 6 -#define C_ABE_FW_FUNCTION_inplaceGain 7 -#define C_ABE_FW_FUNCTION_StreamRouting 8 -#define C_ABE_FW_FUNCTION_gainConverge 9 -#define C_ABE_FW_FUNCTION_dualIir 10 -#define C_ABE_FW_FUNCTION_DCOFFSET 11 -#define C_ABE_FW_FUNCTION_IO_DL_pp 12 -#define C_ABE_FW_FUNCTION_IO_generic 13 -#define C_ABE_FW_FUNCTION_irq_fifo_debug 14 -#define C_ABE_FW_FUNCTION_synchronize_pointers 15 -#define C_ABE_FW_FUNCTION_VIBRA2 16 -#define C_ABE_FW_FUNCTION_VIBRA1 17 -#define C_ABE_FW_FUNCTION_APS_core 18 -#define C_ABE_FW_FUNCTION_IIR_SRC_MIC 19 -#define C_ABE_FW_FUNCTION_wrappers 20 -#define C_ABE_FW_FUNCTION_EANCUpdateOutSample 21 -#define C_ABE_FW_FUNCTION_EANC 22 -#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper 23 -#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper 24 - -/* - * COPY function ID definitions - */ -#define NULL_COPY_CFPID 0 -#define S2D_STEREO_16_16_CFPID 1 -#define S2D_MONO_MSB_CFPID 2 -#define S2D_STEREO_MSB_CFPID 3 -#define S2D_STEREO_RSHIFTED_16_CFPID 4 -#define S2D_MONO_RSHIFTED_16_CFPID 5 -#define D2S_STEREO_16_16_CFPID 6 -#define D2S_MONO_MSB_CFPID 7 -#define D2S_STEREO_MSB_CFPID 8 -#define D2S_STEREO_RSHIFTED_16_CFPID 9 -#define D2S_MONO_RSHIFTED_16_CFPID 10 -#define COPY_DMIC_CFPID 11 -#define COPY_MCPDM_DL_CFPID 12 -#define COPY_MM_UL_CFPID 13 -#define SPLIT_SMEM_CFPID 14 -#define MERGE_SMEM_CFPID 15 -#define SPLIT_TDM_CFPID 16 -#define MERGE_TDM_CFPID 17 -#define ROUTE_MM_UL_CFPID 18 -#define IO_DMAREQ_CFPID 19 -#define IO_IP_CFPID 20 - -#endif /* _ABE_FUNCTIONSID_H_ */ diff --git a/sound/soc/omap/abe/abe_functionsid.h b/sound/soc/omap/abe/abe_functionsid.h new file mode 100644 index 000000000000..6d62ee56b84d --- /dev/null +++ b/sound/soc/omap/abe/abe_functionsid.h @@ -0,0 +1,80 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_FUNCTIONSID_H_ +#define _ABE_FUNCTIONSID_H_ + +/* + * TASK function ID definitions + */ +#define C_ABE_FW_FUNCTION_IIR 0 +#define C_ABE_FW_FUNCTION_monoToStereoPack 1 +#define C_ABE_FW_FUNCTION_stereoToMonoSplit 2 +#define C_ABE_FW_FUNCTION_decimator 3 +#define C_ABE_FW_FUNCTION_OS0Fill 4 +#define C_ABE_FW_FUNCTION_mixer2 5 +#define C_ABE_FW_FUNCTION_mixer4 6 +#define C_ABE_FW_FUNCTION_inplaceGain 7 +#define C_ABE_FW_FUNCTION_StreamRouting 8 +#define C_ABE_FW_FUNCTION_gainConverge 9 +#define C_ABE_FW_FUNCTION_dualIir 10 +#define C_ABE_FW_FUNCTION_DCOFFSET 11 +#define C_ABE_FW_FUNCTION_IO_DL_pp 12 +#define C_ABE_FW_FUNCTION_IO_generic 13 +#define C_ABE_FW_FUNCTION_irq_fifo_debug 14 +#define C_ABE_FW_FUNCTION_synchronize_pointers 15 +#define C_ABE_FW_FUNCTION_VIBRA2 16 +#define C_ABE_FW_FUNCTION_VIBRA1 17 +#define C_ABE_FW_FUNCTION_APS_core 18 +#define C_ABE_FW_FUNCTION_IIR_SRC_MIC 19 +#define C_ABE_FW_FUNCTION_wrappers 20 +#define C_ABE_FW_FUNCTION_EANCUpdateOutSample 21 +#define C_ABE_FW_FUNCTION_EANC 22 +#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper 23 +#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper 24 +#define C_ABE_FW_FUNCTION_mem_init 25 +#define C_ABE_FW_FUNCTION_debug_vx_asrc 26 +#define C_ABE_FW_FUNCTION_IIR_SRC2 27 + +/* + * COPY function ID definitions + */ +#define NULL_COPY_CFPID 0 +#define S2D_STEREO_16_16_CFPID 1 +#define S2D_MONO_MSB_CFPID 2 +#define S2D_STEREO_MSB_CFPID 3 +#define S2D_STEREO_RSHIFTED_16_CFPID 4 +#define S2D_MONO_RSHIFTED_16_CFPID 5 +#define D2S_STEREO_16_16_CFPID 6 +#define D2S_MONO_MSB_CFPID 7 +#define D2S_STEREO_MSB_CFPID 8 +#define D2S_STEREO_RSHIFTED_16_CFPID 9 +#define D2S_MONO_RSHIFTED_16_CFPID 10 +#define COPY_DMIC_CFPID 11 +#define COPY_MCPDM_DL_CFPID 12 +#define COPY_MM_UL_CFPID 13 +#define SPLIT_SMEM_CFPID 14 +#define MERGE_SMEM_CFPID 15 +#define SPLIT_TDM_CFPID 16 +#define MERGE_TDM_CFPID 17 +#define ROUTE_MM_UL_CFPID 18 +#define IO_IP_CFPID 19 + +#endif /* _ABE_FUNCTIONSID_H_ */ diff --git a/sound/soc/omap/abe/abe_fw.h b/sound/soc/omap/abe/abe_fw.h index 71f899f6a885..828f400474f1 100644 --- a/sound/soc/omap/abe/abe_fw.h +++ b/sound/soc/omap/abe/abe_fw.h @@ -1,11 +1,21 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software` + * 02110-1301 USA */ #include "abe_cm_addr.h" @@ -17,288 +27,281 @@ * GLOBAL DEFINITION */ /* one scheduler loop = 4kHz = 12 samples at 48kHz */ -#define FW_SCHED_LOOP_FREQ 4000 +#define FW_SCHED_LOOP_FREQ 4000 + /* one scheduler loop = 4kHz = 12 samples at 48kHz */ #define FW_SCHED_LOOP_FREQ_DIV1000 (FW_SCHED_LOOP_FREQ/1000) -#define EVENT_FREQUENCY 96000 -#define SLOTS_IN_SCHED_LOOP (96000/FW_SCHED_LOOP_FREQ) +#define EVENT_FREQUENCY 96000 +#define SLOTS_IN_SCHED_LOOP (96000/FW_SCHED_LOOP_FREQ) -#define SCHED_LOOP_8kHz ( 8000/FW_SCHED_LOOP_FREQ) -#define SCHED_LOOP_16kHz (16000/FW_SCHED_LOOP_FREQ) -#define SCHED_LOOP_24kHz (24000/FW_SCHED_LOOP_FREQ) -#define SCHED_LOOP_48kHz (48000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_8kHz ( 8000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_16kHz (16000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_24kHz (24000/FW_SCHED_LOOP_FREQ) +#define SCHED_LOOP_48kHz (48000/FW_SCHED_LOOP_FREQ) -#define TASKS_IN_SLOT 8 +#define TASKS_IN_SLOT 8 /* * DMEM AREA - SCHEDULER */ -#define dmem_mm_trace D_DEBUG_FIFO_ADDR -#define dmem_mm_trace_size ((D_DEBUG_FIFO_ADDR_END-D_DEBUG_FIFO_ADDR+1)/4) +#define dmem_mm_trace D_DEBUG_FIFO_ADDR +#define dmem_mm_trace_size ((D_DEBUG_FIFO_ADDR_END-D_DEBUG_FIFO_ADDR+1)/4) -#define ATC_SIZE 8 /* 8 bytes per descriptors */ +#define ATC_SIZE 8 /* 8 bytes per descriptors */ typedef struct { - unsigned rdpt:7; /* first 32bits word of the descriptor */ - unsigned reserved0:1; - unsigned cbsize:7; - unsigned irqdest:1; - unsigned cberr:1; - unsigned reserved1:5; - unsigned cbdir:1; - unsigned nw:1; - unsigned wrpt:7; - unsigned reserved2:1; - unsigned badd:12; /* second 32bits word of the descriptor */ - unsigned iter:7; /* iteration field overlaps the 16 bits boundary */ - unsigned srcid:6; - unsigned destid:6; - unsigned desen:1; +unsigned rdpt : + 7; /* first 32bits word of the descriptor */ +unsigned reserved0 : + 1; +unsigned cbsize : + 7; +unsigned irqdest : + 1; +unsigned cberr : + 1; +unsigned reserved1 : + 5; +unsigned cbdir : + 1; +unsigned nw : + 1; +unsigned wrpt : + 7; +unsigned reserved2 : + 1; +unsigned badd : + 12; /* second 32bits word of the descriptor */ +unsigned iter : + 7; /* iteration field overlaps the 16 bits boundary */ +unsigned srcid : + 6; +unsigned destid : + 6; +unsigned desen : + 1; } abe_satcdescriptor_aess; /* - * table of scheduler tasks : - * char scheduler_table[24 x 4] : four bytes used at OPP100% + * table of scheduler tasks : + * char scheduler_table[24 x 4] : four bytes used at OPP100% */ -#define dmem_scheduler_table D_multiFrame_ADDR +#define dmem_scheduler_table D_multiFrame_ADDR -#define dmem_eanc_task_pointer D_pFastLoopBack_ADDR +#define dmem_eanc_task_pointer D_pFastLoopBack_ADDR /* - * OPP value : - * pointer increment steps in the scheduler table + * OPP value : + * pointer increment steps in the scheduler table */ #define dmem_scheduler_table_step D_taskStep_ADDR /* - * table of scheduler tasks (max 64) : - * char task_descriptors[64 x 8] : eight bytes per task - * TASK INDEX, INITPTR 1,2,3, INITREG, Loop Counter, Reserved 1,2 - */ -#define dmem_task_descriptor D_tasksList_ADDR - -/* - * table of task function addresses: - * short task_function_descriptors[32 x 1] : 16bits addresses to PMEM using TASK_INDEX above - */ - -/* - * IDs of the micro tasks + * table of scheduler tasks (max 64) : + * char task_descriptors[64 x 8] : eight bytes per task + * TASK INDEX, INITPTR 1,2,3, INITREG, Loop Counter, Reserved 1,2 */ - -// from ABE_FunctionsId.h -/*#define id_ copyMultiFrame_TFID -#define id_ inplaceGain_TFID -#define id_ mixer_TFID -#define id_ IIR_TFID -#define id_ gainConverge_TFID -#define id_ sinGen_TFID -#define id_ OSR0Fill_TFID -#define id_ IOtask_TFID - -#define id_mixer -#define id_eq -#define id_upsample_src -#define id_downsample_src -#define id_asrc -#define id_gain_update -#define id_aps_hs -#define id_aps_ihf -#define id_dither -#define id_eanc -#define id_io -#define id_router -#define id_dynamic_dl -#define id_dynamic_ul -#define id_sequence_reader -#define id_ .. -*/ +#define dmem_task_descriptor D_tasksList_ADDR /* - * I/O DESCRIPTORS + * I/O DESCRIPTORS */ -#define dmem_port_descriptors D_IOdescr_ADDR +#define dmem_port_descriptors D_IOdescr_ADDR /* ping_pong_t descriptors table - * structure of 8 bytes: - * uint16 base_address1 - * uint16 size1 (16bits address format) - * uint16 base_address2 - * uint16 size2 - * } ping_pong_t - * ping_pong_t dmem_ping_pong_t [8] + * structure of 8 bytes: + * uint16 base_address1 + * uint16 size1 (16bits address format) + * uint16 base_address2 + * uint16 size2 + * } ping_pong_t + * ping_pong_t dmem_ping_pong_t [8] */ -#define dmem_ping_pong_buffer D_PING_ADDR /* U8 address */ + +/* U8 address */ +#define dmem_ping_pong_buffer D_PING_ADDR /* - * IRQ mask used with ports with IRQ (DMA or host) - * uint32 dmem_irq_masks [8] + * IRQ mask used with ports with IRQ (DMA or host) + * uint32 dmem_irq_masks [8] */ -#define dmem_irq_masks D_IRQMask_ADDR +#define dmem_irq_masks D_IRQMask_ADDR /* - * tables of to the 8 FIFO sequences (delayed commands) holding 12bytes tasks in the format - * structure { - * 1) Down counter delay on 16bits, decremented on each scheduler period - * 2) Code on 8 bits for the type of operation to execute : call or data move. - * 3) Three 16bits parameters (for data move example example : source/destination/counter) - * 4) Three bytes reserved - * } seq_fw_task_t + * tables of to the 8 FIFO sequences (delayed commands) holding 12bytes tasks + * in the format + * structure { + * 1) Down counter delay on 16bits, decremented on each scheduler period + * 2) Code on 8 bits for the type of operation to execute : call or data move. + * 3) Three 16bits parameters (for data move example example : source/ + * destination/counter) + * 4) Three bytes reserved + * } seq_fw_task_t * - * structure { - * uint32 : base address(MSB) + read pointer(LSB) - * uint32 : max address (MSB) + write pointer (LSB) - * } FIFO_generic; - * seq_fw_task_t FIFO_CONTENT [8]; 96 bytes + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * } FIFO_generic; + * seq_fw_task_t FIFO_CONTENT [8]; 96 bytes * - * FIFO_SEQ dmem_fifo_sequences [8]; all FIFO sequences + * FIFO_SEQ dmem_fifo_sequences [8]; all FIFO sequences */ -#define dmem_fifo_sequences D_DCFifo_ADDR +#define dmem_fifo_sequences D_DCFifo_ADDR #define dmem_fifo_sequences_descriptors D_DCFifoDesc_ADDR /* - * IRQ FIFOs + * IRQ FIFOs * - * structure { - * uint32 : base address(MSB) + read pointer(LSB) - * uint32 : max address (MSB) + write pointer (LSB) - * uint32 IRQ_CODES [6]; - * } dmem_fifo_irq_mcu; 32 bytes - * } dmem_fifo_irq_dsp; 32 bytes + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 IRQ_CODES [6]; + * } dmem_fifo_irq_mcu; 32 bytes + * } dmem_fifo_irq_dsp; 32 bytes */ #define dmem_fifo_irq_mcu_descriptor D_McuIrqFifoDesc_ADDR #define dmem_fifo_irq_dsp_descriptor D_DspIrqFifoDesc_ADDR -#define dmem_fifo_irq_mcu D_McuIrqFifo_ADDR -#define dmem_fifo_irq_dsp D_DspIrqFifo_ADDR +#define dmem_fifo_irq_mcu D_McuIrqFifo_ADDR +#define dmem_fifo_irq_dsp D_DspIrqFifo_ADDR /* - * remote debugger exchange buffer - * uint32 dmem_debug_ae2hal [32] - * uint32 dmem_debug_hal2ae [32] + * remote debugger exchange buffer + * uint32 dmem_debug_ae2hal [32] + * uint32 dmem_debug_hal2ae [32] */ -#define dmem_debug_ae2hal D_DebugAbe2hal_ADDR -#define dmem_debug_hal2ae D_Debug_hal2abe_ADDR +#define dmem_debug_ae2hal D_DebugAbe2hal_ADDR +#define dmem_debug_hal2ae D_Debug_hal2abe_ADDR /* - * DMEM address of the ASRC ppm drift parameter for ASRCs (voice and multimedia paths) - * uint32 smem_asrc(x)_drift + * DMEM address of the ASRC ppm drift parameter for ASRCs (voice and multimedia + * paths) + * uint32 smem_asrc(x)_drift */ -#define dmem_asrc1_drift D_ASRC1drift_ADDR -#define dmem_asrc2_drift D_ASRC2drift_ADDR +#define dmem_asrc1_drift D_ASRC1drift_ADDR +#define dmem_asrc2_drift D_ASRC2drift_ADDR /* - * DMEM indexes of the router uplink paths - * uint8 dmem_router_index [8] + * DMEM indexes of the router uplink paths + * uint8 dmem_router_index [8] */ // OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ //#define dmem_router_index + /* - * analog control circular buffer commands to Phoenix - * structure { - * uint32 : base address(MSB) + read pointer(LSB) - * uint32 : max address (MSB) + write pointer (LSB) - * uint32 FIFO_CONTENT [6]; - * } dmem_commands_to_phoenix; 32 bytes + * analog control circular buffer commands to Phoenix + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [6]; + * } dmem_commands_to_phoenix; 32 bytes */ -#define dmem_commands_to_phoenix D_Cmd2PhenixFifo_ADDR -#define dmem_commands_to_phoenix_descriptor D_Cmd2PhenixFifoDesc_ADDR +#define dmem_commands_to_phoenix D_Cmd2PhenixFifo_ADDR +#define dmem_commands_to_phoenix_descriptor D_Cmd2PhenixFifoDesc_ADDR /* - * analog control circular buffer commands from Phoenix (status line) - * structure { - * uint32 : base address(MSB) + read pointer(LSB) - * uint32 : max address (MSB) + write pointer (LSB) - * uint32 FIFO_CONTENT [6]; - * } dmem_commands_to_phoenix; 32 bytes + * analog control circular buffer commands from Phoenix (status line) + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [6]; + * } dmem_commands_to_phoenix; 32 bytes */ -#define dmem_commands_from_phoenix D_StatusFromPhenixFifo_ADDR -#define dmem_commands_from_phoenix_descriptor D_StatusFromPhenixFifoDesc_ADDR +#define dmem_commands_from_phoenix D_StatusFromPhenixFifo_ADDR +#define dmem_commands_from_phoenix_descriptor D_StatusFromPhenixFifoDesc_ADDR /* - * DEBUG mask - * uint16 dmem_debug_trace_mask - * each bit of this word enables a type a trace in the debug circular buffer + * DEBUG mask + * uint16 dmem_debug_trace_mask + * each bit of this word enables a type a trace in the debug circular buffer */ // OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ //#define dmem_debug_trace_mask /* - * DEBUG circular buffer - * structure { - * uint32 : base address(MSB) + read pointer(LSB) - * uint32 : max address (MSB) + write pointer (LSB) - * uint32 FIFO_CONTENT [14]; = TIMESTAMP + CODE - * } dmem_debug_trace_buffer; 64 bytes - * should be much larger (depends on the DMEM mapping...) + * DEBUG circular buffer + * structure { + * uint32 : base address(MSB) + read pointer(LSB) + * uint32 : max address (MSB) + write pointer (LSB) + * uint32 FIFO_CONTENT [14]; = TIMESTAMP + CODE + * } dmem_debug_trace_buffer; 64 bytes + * should be much larger (depends on the DMEM mapping...) */ #define dmem_debug_trace_buffer -#define dmem_debug_trace_fifo D_debugFifo_ADDR +#define dmem_debug_trace_fifo D_debugFifo_ADDR #define dmem_debug_trace_descriptor D_debugFifoDesc_ADDR /* - * Infinite counter incremented on each sheduler periods (~250 us) - * uint16 dmem_debug_time_stamp + * Infinite counter incremented on each sheduler periods (~250 us) + * uint16 dmem_debug_time_stamp */ -#define dmem_debug_time_stamp D_loopCounter_ADDR +#define dmem_debug_time_stamp D_loopCounter_ADDR /* - * ATC BUFFERS + IO TASKS SMEM buffers + * ATC BUFFERS + IO TASKS SMEM buffers */ -#define dmem_dmic D_DMIC_UL_FIFO_ADDR -#define dmem_dmic_size ((D_DMIC_UL_FIFO_ADDR_END-D_DMIC_UL_FIFO_ADDR+1)/4) +#define dmem_dmic D_DMIC_UL_FIFO_ADDR +#define dmem_dmic_size (D_DMIC_UL_FIFO_sizeof/4) + +#define dmem_amic D_McPDM_UL_FIFO_ADDR +#define dmem_amic_size (D_McPDM_UL_FIFO_sizeof/4) +#define smem_amic AMIC_96_labelID -#define dmem_amic D_McPDM_UL_FIFO_ADDR -#define dmem_amic_size ((D_McPDM_UL_FIFO_ADDR_END-D_McPDM_UL_FIFO_ADDR+1)/4) -#define smem_amic AMIC_96_labelID +#define dmem_mcpdm D_McPDM_DL_FIFO_ADDR +#define dmem_mcpdm_size (D_McPDM_DL_FIFO_sizeof/4) -#define dmem_mcpdm D_McPDM_DL_FIFO_ADDR -#define dmem_mcpdm_size ((D_McPDM_DL_FIFO_ADDR_END-D_McPDM_DL_FIFO_ADDR+1)/4) +#define dmem_mm_ul D_MM_UL_FIFO_ADDR +#define dmem_mm_ul_size (D_MM_UL_FIFO_sizeof/4) -#define dmem_mm_ul D_MM_UL_FIFO_ADDR -#define dmem_mm_ul_size ((D_MM_UL_FIFO_ADDR_END-D_MM_UL_FIFO_ADDR+1)/4) -#define smem_mm_ul MM_UL_labelID /* managed directly by the router */ +/* managed directly by the router */ +#define smem_mm_ul MM_UL_labelID -#define dmem_mm_ul2 D_MM_UL2_FIFO_ADDR -#define dmem_mm_ul2_size ((D_MM_UL2_FIFO_ADDR_END-D_MM_UL2_FIFO_ADDR+1)/4) -#define smem_mm_ul2 MM_UL2_labelID /* managed directly by the router */ +#define dmem_mm_ul2 D_MM_UL2_FIFO_ADDR +#define dmem_mm_ul2_size (D_MM_UL2_FIFO_sizeof/4) -#define dmem_mm_dl D_MM_DL_FIFO_ADDR -#define dmem_mm_dl_size ((D_MM_DL_FIFO_ADDR_END-D_MM_DL_FIFO_ADDR+1)/4) -#define smem_mm_dl_opp100 MM_DL_labelID -#define smem_mm_dl_opp25 MM_DL_labelID /* @@@ at OPP 25/50 or without ASRC */ +/* managed directly by the router */ +#define smem_mm_ul2 MM_UL2_labelID -#define dmem_vx_dl D_VX_DL_FIFO_ADDR -#define dmem_vx_dl_size ((D_VX_DL_FIFO_ADDR_END-D_VX_DL_FIFO_ADDR+1)/4) -#define smem_vx_dl IO_VX_DL_ASRC_labelID /* Voice_16k_DL_labelID */ +#define dmem_mm_dl D_MM_DL_FIFO_ADDR +#define dmem_mm_dl_size (D_MM_DL_FIFO_sizeof/4) -#define dmem_vx_ul D_VX_UL_FIFO_ADDR -#define dmem_vx_ul_size ((D_VX_UL_FIFO_ADDR_END-D_VX_UL_FIFO_ADDR+1)/4) -#define smem_vx_ul Voice_16k_UL_labelID +/*IO_MM_DL_ASRC_labelID ASRC input buffer, size 40 */ +#define smem_mm_dl_opp100 MM_DL_labelID -#define dmem_tones_dl D_TONES_DL_FIFO_ADDR -#define dmem_tones_dl_size ((D_TONES_DL_FIFO_ADDR_END-D_TONES_DL_FIFO_ADDR+1)/4) -#define smem_tones_dl Tones_labelID +/* at OPP 25/50 or without ASRC */ +#define smem_mm_dl_opp25 MM_DL_labelID -#define dmem_vib_dl D_VIB_DL_FIFO_ADDR -#define dmem_vib_dl_size ((D_VIB_DL_FIFO_ADDR_END-D_VIB_DL_FIFO_ADDR+1)/4) -#define smem_vib IO_VIBRA_DL_labelID +#define dmem_vx_dl D_VX_DL_FIFO_ADDR +#define dmem_vx_dl_size (D_VX_DL_FIFO_sizeof/4) +#define smem_vx_dl IO_VX_DL_ASRC_labelID /* Voice_16k_DL_labelID */ -#define dmem_mm_ext_out D_MM_EXT_OUT_FIFO_ADDR -#define dmem_mm_ext_out_size ((D_MM_EXT_OUT_FIFO_ADDR_END-D_MM_EXT_OUT_FIFO_ADDR+1)/4) -#define smem_mm_ext_out DL1_GAIN_out_labelID +#define dmem_vx_ul D_VX_UL_FIFO_ADDR +#define dmem_vx_ul_size (D_VX_UL_FIFO_sizeof/4) +#define smem_vx_ul Voice_16k_UL_labelID -#define dmem_mm_ext_in D_MM_EXT_IN_FIFO_ADDR -#define dmem_mm_ext_in_size ((D_MM_EXT_IN_FIFO_ADDR_END-D_MM_EXT_IN_FIFO_ADDR+1)/4) -#define smem_mm_ext_in MM_EXT_IN_labelID +#define dmem_tones_dl D_TONES_DL_FIFO_ADDR +#define dmem_tones_dl_size (D_TONES_DL_FIFO_sizeof/4) +#define smem_tones_dl Tones_labelID -#define dmem_bt_vx_dl D_BT_DL_FIFO_ADDR -#define dmem_bt_vx_dl_size ((D_BT_DL_FIFO_ADDR_END-D_BT_DL_FIFO_ADDR+1)/4) -#define smem_bt_vx_dl BT_DL_8k_labelID +#define dmem_vib_dl D_VIB_DL_FIFO_ADDR +#define dmem_vib_dl_size (D_VIB_DL_FIFO_sizeof/4) +#define smem_vib IO_VIBRA_DL_labelID -#define dmem_bt_vx_ul D_BT_UL_FIFO_ADDR -#define dmem_bt_vx_ul_size ((D_BT_UL_FIFO_ADDR_END-D_BT_UL_FIFO_ADDR+1)/4) -#define smem_bt_vx_ul BT_UL_8k_labelID +#define dmem_mm_ext_out D_MM_EXT_OUT_FIFO_ADDR +#define dmem_mm_ext_out_size (D_MM_EXT_OUT_FIFO_sizeof/4) +#define smem_mm_ext_out DL1_GAIN_out_labelID + +#define dmem_mm_ext_in D_MM_EXT_IN_FIFO_ADDR +#define dmem_mm_ext_in_size (D_MM_EXT_IN_FIFO_sizeof/4) +#define smem_mm_ext_in MM_EXT_IN_labelID + +#define dmem_bt_vx_dl D_BT_DL_FIFO_ADDR +#define dmem_bt_vx_dl_size (D_BT_DL_FIFO_sizeof/4) +#define smem_bt_vx_dl BT_DL_8k_labelID + +#define dmem_bt_vx_ul D_BT_UL_FIFO_ADDR +#define dmem_bt_vx_ul_size (D_BT_UL_FIFO_sizeof/4) +#define smem_bt_vx_ul BT_UL_8k_labelID /* @@ -306,10 +309,10 @@ typedef struct { */ /* - * POINTER - used for the port descriptor programming - * corresponds to 8bits addresses to the INITPTR area + * POINTER - used for the port descriptor programming + * corresponds to 8bits addresses to the INITPTR area * - * List from ABE_INITxxx_labels.h + * List from ABE_INITxxx_labels.h */ #define ptr_ul_rec #define ptr_vx_dl @@ -323,131 +326,128 @@ typedef struct { */ /* - * PHOENIX OFFSET in SMEM - * used to subtract a DC offset on the headset path (power consumption optimization) + * PHOENIX OFFSET in SMEM + * used to subtract a DC offset on the headset path (power consumption optimization) */ /* OC: exact usage to be detailled */ -#define smem_phoenix_offset S_PhoenixOffset_ADDR - -/* - * EQUALIZERS Z AREA - * used to reset the filter memory - IIR-8 (max) - * int24 stereo smem_equ(x) [8x2 + 1] - */ -#define smem_equ1 S_EQU1_data_ADDR -#define smem_equ2 S_EQU2_data_ADDR -#define smem_equ3 S_EQU3_data_ADDR -#define smem_equ4 S_EQU4_data_ADDR -#define smem_sdt S_SDT_data_ADDR - -/* - * GAIN SMEM on PORT - * int32 smem_G0 [18] : desired gain on the ports - * format of G0 = 6 bits left shifted desired gain in linear 24bits format - * int24 stereo G0 [18] = G0 - * int24 stereo GI [18] current value of the gain in the same format of G0 - * List of smoothed gains : - * 6 DMIC 0 1 2 3 4 5 - * 2 AMIC L R - * 4 PORT1/2_RX L R - * 2 MM_EXT L R - * 2 MM_VX_DL L R - * 2 IHF L R +#define smem_phoenix_offset S_PhoenixOffset_ADDR + +/* + * EQUALIZERS Z AREA + * used to reset the filter memory - IIR-8 (max) + * int24 stereo smem_equ(x) [8x2 + 1] + */ +#define smem_equ1 S_EQU1_data_ADDR +#define smem_equ2 S_EQU2_data_ADDR +#define smem_equ3 S_EQU3_data_ADDR +#define smem_equ4 S_EQU4_data_ADDR +#define smem_sdt S_SDT_data_ADDR + +/* + * GAIN SMEM on PORT + * int32 smem_G0 [18] : desired gain on the ports + * format of G0 = 6 bits left shifted desired gain in linear 24bits format + * int24 stereo G0 [18] = G0 + * int24 stereo GI [18] current value of the gain in the same format of G0 + * List of smoothed gains : + * 6 DMIC 0 1 2 3 4 5 + * 2 AMIC L R + * 4 PORT1/2_RX L R + * 2 MM_EXT L R + * 2 MM_VX_DL L R + * 2 IHF L R * --------------- * 18 = TOTAL */ -//#define smem_g0 S_GTarget_ADDR /* [9] 2 gains in 1 SM address */ -//#define smem_g1 S_GCurrent_ADDR /* [9] 2 gains in 1 SM address */ +#if 0 +#define smem_g0 S_GTarget_ADDR // [9] 2 gains in 1 SM address +#define smem_g1 S_GCurrent_ADDR // [9] 2 gains in 1 SM address +#endif /* * COEFFICIENTS AREA */ /* - * delay coefficients used in the IIR-1 filters - * int24 cmem_gain_delay_iir1[9 x 2] (a, (1-a)) + * delay coefficients used in the IIR-1 filters + * int24 cmem_gain_delay_iir1[9 x 2] (a, (1-a)) * - * 3 for 6 DMIC 0 1 2 3 4 5 - * 1 for 2 AMIC L R - * 2 for 4 PORT1/2_RX L R - * 1 for 2 MM_EXT L R - * 1 for 2 MM_VX_DL L R - * 1 for 2 IHF L R + * 3 for 6 DMIC 0 1 2 3 4 5 + * 1 for 2 AMIC L R + * 2 for 4 PORT1/2_RX L R + * 1 for 2 MM_EXT L R + * 1 for 2 MM_VX_DL L R + * 1 for 2 IHF L R */ -#define cmem_gain_alpha C_Alpha_ADDR /* [9] */ +#define cmem_gain_alpha C_Alpha_ADDR #define cmem_gain_1_alpha C_1_Alpha_ADDR /* * gain controls */ -#define GAIN_LEFT_OFFSET (abe_port_id)0 -#define GAIN_RIGHT_OFFSET (abe_port_id)1 +#define GAIN_LEFT_OFFSET 0 +#define GAIN_RIGHT_OFFSET 1 -#define cmem_gains_base C_GainsWRamp_ADDR -#define smem_target_gain_base S_GTarget1_ADDR -#define cmem_1_Alpha_base C_1_Alpha_ADDR -#define cmem_Alpha_base C_Alpha_ADDR +/* stereo gains */ +#define dmic1_gains_offset 0 +#define dmic2_gains_offset 2 +#define dmic3_gains_offset 4 +#define amic_gains_offset 6 +#define dl1_gains_offset 8 +#define dl2_gains_offset 10 +#define splitters_gains_offset 12 + +#define mixer_dl1_offset 14 +#define mixer_dl2_offset 18 +#define mixer_echo_offset 22 +#define mixer_sdt_offset 24 +#define mixer_vxrec_offset 26 +#define mixer_audul_offset 30 +#define gain_unused_offset 34 -#define dmic1_gains_offset 0 /* stereo gains */ -#define dmic2_gains_offset 2 /* stereo gains */ -#define dmic3_gains_offset 4 /* stereo gains */ -#define amic_gains_offset 6 /* stereo gains */ -#define dl1_gains_offset 8 /* stereo gains */ -#define dl2_gains_offset 10 /* stereo gains */ -#define splitters_gains_offset 12 /* stereo gains */ -#define mixer_dl1_offset 14 -#define mixer_dl2_offset 18 -#define mixer_echo_offset 22 -#define mixer_sdt_offset 24 -#define mixer_vxrec_offset 26 -#define mixer_audul_offset 30 -#define gain_unused_offset 34 /* - * DMIC SRC 96->48 - * the filter is changed depending on the decimatio ratio used (16/25/32/40) - * int32 cmem_src2_dmic [6] IIR with 2 coefs in the recursive part and 4 coefs in the direct part + * DMIC SRC 96->48 + * the filter is changed depending on the decimatio ratio used (16/25/32/40) + * int32 cmem_src2_dmic [6] IIR with 2 coefs in the recursive part and 4 coefs + * in the direct part */ #define cmem_src2_dmic /* - * EANC coefficients - * structure of : - * 20 Q6.26 coef for the FIR - * 16 Q6.26 coef for the IIR - * 1 Q6.26 coef for Lambda + * EANC coefficients + * structure of : + * 20 Q6.26 coef for the FIR + * 16 Q6.26 coef for the IIR + * 1 Q6.26 coef for Lambda */ #define cmem_eanc_coef_fir #define cmem_eanc_coef_iir #define cmem_eanc_coef_lambda /* - * EQUALIZERS - SDT - COEF AREA - * int24 cmem_equ(x) [8x2+1] + * EQUALIZERS - SDT - COEF AREA + * int24 cmem_equ(x) [8x2+1] */ -#define cmem_equ1 C_EQU1_data_ADDR -#define cmem_equ2 C_EQU2_data_ADDR -#define cmem_equ3 C_EQU3_data_ADDR -#define cmem_equ4 C_EQU4_data_ADDR -#define cmem_sdt C_SDT_data_ADDR +#define cmem_equ1 C_EQU1_data_ADDR +#define cmem_equ2 C_EQU2_data_ADDR +#define cmem_equ3 C_EQU3_data_ADDR +#define cmem_equ4 C_EQU4_data_ADDR +#define cmem_sdt C_SDT_data_ADDR /* - * APS - COEF AREA - * int24 cmem_aps(x) [16] + * APS - COEF AREA + * int24 cmem_aps(x) [16] */ #define cmem_aps1 #define cmem_aps2 #define cmem_aps3 /* - * DITHER - COEF AREA - * int24 cmem_dither(x) [4] + * DITHER - COEF AREA + * int24 cmem_dither(x) [4] */ #define cmem_dither - -//#ifdef __cplusplus -//} -//#endif diff --git a/sound/soc/omap/abe/abe_ini.c b/sound/soc/omap/abe/abe_ini.c index 0be0570d54e3..50028ae9c01f 100644 --- a/sound/soc/omap/abe/abe_ini.c +++ b/sound/soc/omap/abe/abe_ini.c @@ -1,353 +1,359 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" -#include "abe_dat.h" /* data declaration */ -#include "abe_cof.h" +#include "abe_dm_addr.h" + +short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT]; /* - * initialize the default values for call-backs to subroutines - * - FIFO IRQ call-backs for sequenced tasks - * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols) - * - Remote debugger interface - * - Error monitoring - * - Activity Tracing + * initialize the default values for call-backs to subroutines + * - FIFO IRQ call-backs for sequenced tasks + * - FIFO IRQ call-backs for audio player/recorders (ping-pong protocols) + * - Remote debugger interface + * - Error monitoring + * - Activity Tracing */ -/* - * ABE_HW_CONFIGURATION - * - * Parameter : - * - * Operations : - * - * - * Return value : +/** + * abe_hw_configuration * */ -void abe_hw_configuration() +void abe_hw_configuration () { - abe_uint32 atc_reg; + u32 atc_reg; - /* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */ + /* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */ atc_reg = 0xFF; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4); } -/* - * ABE_BUILD_SCHEDULER_TABLE - * - * Parameter : - * - * Operations : - * - * - * Return value : +/** + * abe_build_scheduler_table * */ -char aUplinkMuxing[D_aUplinkRouting_sizeof]; - -void abe_build_scheduler_table() +void abe_build_scheduler_table () { - short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT]; - abe_uint16 i, n; - abe_uint8 *ptr; - + u16 i, n; + u8 *ptr; + char aUplinkMuxing[16]; +#define ABE_TASK_ID(ID) (D_tasksList_ADDR + sizeof(ABE_STask)*(ID)) /* LOAD OF THE TASKS' MULTIFRAME */ - /* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED IN "abe_init_io_tasks" */ + /* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED + IN "abe_init_io_tasks" */ - for (ptr = (abe_uint8 *)&(MultiFrame[0][0]), i=0; i < sizeof (MultiFrame); i++) + for (ptr = (u8 *)&(MultiFrame[0][0]), i=0; + i < sizeof (MultiFrame); i++) *ptr++ = 0; - //MultiFrame[0][0] = 0; - //MultiFrame[0][1] = 0; - MultiFrame[0][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VX_DL; - //MultiFrame[0][3] = 0; - //MultiFrame[0][4] = 0; - //MultiFrame[0][5] = 0; - MultiFrame[0][6] = 0; - //MultiFrame[0][7] = 0; - //MultiFrame[1][0] = 0; - //MultiFrame[1][1] = 0; + /* MultiFrame[0][0] = 0; */ + /* MultiFrame[0][1] = 0; */ + MultiFrame[0][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_DL); + /* MultiFrame[0][3] = 0; */ + /* MultiFrame[0][4] = 0; */ + /* MultiFrame[0][5] = 0; */ + /* MultiFrame[0][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_MM_DL);*/ + /* MultiFrame[0][7] = 0; */ + + /* MultiFrame[1][0] = 0; */ + /* MultiFrame[1][1] = 0; */ #define TASK_ASRC_VX_DL_SLT 1 #define TASK_ASRC_VX_DL_IDX 2 - MultiFrame[1][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_16; + MultiFrame[1][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_16); #define TASK_VX_DL_SLT 1 #define TASK_VX_DL_IDX 3 - MultiFrame[1][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_16_48; - //MultiFrame[1][4] = 0; - //MultiFrame[1][5] = 0; - MultiFrame[1][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2Mixer; - MultiFrame[1][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VIB_DL; - MultiFrame[2][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1Mixer; - MultiFrame[2][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_SDTMixer; - //MultiFrame[2][2] = 0; - //MultiFrame[2][3] = 0; - //MultiFrame[2][4] = 0; - MultiFrame[2][5] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_DMIC; - //MultiFrame[2][6] = 0; - //MultiFrame[2][7] = 0; - - MultiFrame[3][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_GAIN; - MultiFrame[3][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_EQ; - MultiFrame[3][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EchoMixer; - //MultiFrame[3][3] = 0; - //MultiFrame[3][4] = 0; - //MultiFrame[3][5] = 0; - MultiFrame[3][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_GAIN; - MultiFrame[3][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_APS_EQ; - - MultiFrame[4][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_EQ; - //MultiFrame[4][1] = 0; - MultiFrame[4][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VXRECMixer; - - MultiFrame[4][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VXREC_SPLIT; - //MultiFrame[4][4] = 0; - //MultiFrame[4][5] = 0; - MultiFrame[4][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA1; - MultiFrame[4][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA2; - - MultiFrame[5][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_0SR; - MultiFrame[5][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_LP; - MultiFrame[5][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_UL; - //MultiFrame[5][3] = 0; - //MultiFrame[5][4] = 0; - //MultiFrame[5][5] = 0; - MultiFrame[5][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_EQ; - MultiFrame[5][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA_SPLIT; - - MultiFrame[6][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EARP_48_96_LP; - MultiFrame[6][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_DL; - //MultiFrame[6][2] = 0; - - //MultiFrame[6][3] = 0; - //MultiFrame[6][4] = 0; - //MultiFrame[6][5] = 0; - MultiFrame[6][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_APS_SPLIT; - //MultiFrame[6][7] = 0; - - //MultiFrame[7][0] = 0; - //MultiFrame[7][1] = 0; - MultiFrame[7][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_SPLIT; - MultiFrame[7][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DBG_SYNC; - //MultiFrame[7][4] = 0; - //MultiFrame[7][5] = 0; - MultiFrame[7][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_R_APS_CORE; - MultiFrame[7][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL2_L_APS_CORE; - - //MultiFrame[8][0] = 0; - //MultiFrame[8][1] = 0; - MultiFrame[8][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC1_96_48_LP; - //MultiFrame[8][3] = 0; - MultiFrame[8][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC1_SPLIT; - //MultiFrame[8][5] = 0; - //MultiFrame[8][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_FBK_96_48; - //MultiFrame[8][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_FBK_SPLIT; - - //MultiFrame[9][0] = 0; - //MultiFrame[9][1] = 0; - MultiFrame[9][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC2_96_48_LP; - //MultiFrame[9][3] = 0; - MultiFrame[9][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC2_SPLIT; - //MultiFrame[9][5] = 0; - MultiFrame[9][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_0SR; - MultiFrame[9][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_LP; - - //MultiFrame[10][0] = 0; - //MultiFrame[10][1] = 0; - MultiFrame[10][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC3_96_48_LP; - //MultiFrame[10][3] = 0; - MultiFrame[10][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DMIC3_SPLIT; - //MultiFrame[10][5] = 0; - //MultiFrame[10][6] = 0; // D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_COPY; // NEW: copy EANC coefs to working CMEM areas - MultiFrame[10][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IHF_48_96_LP; - - //MultiFrame[11][0] = 0; - //MultiFrame[11][1] = 0; - MultiFrame[11][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_AMIC_96_48_LP; - //MultiFrame[11][3] = 0; - MultiFrame[11][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_AMIC_SPLIT; - //MultiFrame[11][5] = 0; - //MultiFrame[11][6] = 0; - MultiFrame[11][7] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VIBRA_PACK; - - //MultiFrame[12][0] = 0; - //MultiFrame[12][1] = 0; - MultiFrame[12][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_BT_VX_DL; - MultiFrame[12][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_ROUTING; - MultiFrame[12][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ULMixer; + MultiFrame[1][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_16_48); + /* MultiFrame[1][4] = 0; */ + /* MultiFrame[1][5] = 0; */ + MultiFrame[1][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2Mixer); + MultiFrame[1][7] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VIB_DL); + + MultiFrame[2][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1Mixer); + MultiFrame[2][1] = ABE_TASK_ID(C_ABE_FW_TASK_SDTMixer); + /* MultiFrame[2][2] = 0; */ + /* MultiFrame[2][3] = 0; */ + /* MultiFrame[2][4] = 0; */ + MultiFrame[2][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC); + /* MultiFrame[2][6] = 0; */ + /* MultiFrame[2][7] = 0; */ + + MultiFrame[3][1] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_GAIN); + MultiFrame[3][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_EQ); + MultiFrame[3][2] = ABE_TASK_ID(C_ABE_FW_TASK_EchoMixer); + /* MultiFrame[3][3] = 0; */ + /* MultiFrame[3][4] = 0; */ + /* MultiFrame[3][5] = 0; */ + MultiFrame[3][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_GAIN); + MultiFrame[3][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_APS_EQ); + + MultiFrame[4][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_EQ); + /* MultiFrame[4][1] = 0; */ + MultiFrame[4][2] = ABE_TASK_ID(C_ABE_FW_TASK_VXRECMixer); + MultiFrame[4][3] = ABE_TASK_ID(C_ABE_FW_TASK_VXREC_SPLIT); + /* MultiFrame[4][4] = 0; */ + /* MultiFrame[4][5] = 0; */ + MultiFrame[4][6] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA1); + MultiFrame[4][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA2); + + + MultiFrame[5][0] = 0; + MultiFrame[5][1] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP); + MultiFrame[5][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_UL); + /* MultiFrame[5][3] = 0; */ + /* MultiFrame[5][4] = 0; */ + /* MultiFrame[5][5] = 0; */ + MultiFrame[5][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_EQ); + MultiFrame[5][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_SPLIT); + + MultiFrame[6][0] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP); + /* MultiFrame[6][1] = 0; */ + /* MultiFrame[6][2] = 0; */ + /* MultiFrame[6][3] = 0; */ + /* MultiFrame[6][4] = 0; */ + /* MultiFrame[6][5] = 0; */ + MultiFrame[6][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_APS_SPLIT); + /* MultiFrame[6][7] = 0; */ + + MultiFrame[7][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL); + /* MultiFrame[7][1] = 0; */ + MultiFrame[7][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_SPLIT); + MultiFrame[7][3] = ABE_TASK_ID(C_ABE_FW_TASK_DBG_SYNC); + /* MultiFrame[7][4] = 0; */ + /* MultiFrame[7][5] = 0; */ + MultiFrame[7][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_R_APS_CORE); + MultiFrame[7][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_L_APS_CORE); + + /* MultiFrame[8][0] = 0; */ + /* MultiFrame[8][1] = 0; */ + MultiFrame[8][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_96_48_LP); + /* MultiFrame[8][3] = 0; */ + MultiFrame[8][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_SPLIT); + /* MultiFrame[8][5] = 0; */ + /* MultiFrame[8][6] = 0; */ + /* MultiFrame[8][7] = 0; */ + + /* MultiFrame[9][0] = 0; */ + /* MultiFrame[9][1] = 0; */ + MultiFrame[9][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_96_48_LP); + /* MultiFrame[9][3] = 0; */ + MultiFrame[9][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_SPLIT); + /* MultiFrame[9][5] = 0; */ + MultiFrame[9][6] = 0; + MultiFrame[9][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP); + + /* MultiFrame[10][0] = 0; */ + /* MultiFrame[10][1] = 0; */ + MultiFrame[10][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_96_48_LP); + /* MultiFrame[10][3] = 0; */ + MultiFrame[10][4] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_SPLIT); + /* MultiFrame[10][5] = 0; */ + /* MultiFrame[10][6] = 0; */ + MultiFrame[10][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP); + + /* MultiFrame[11][0] = 0; */ + /* MultiFrame[11][1] = 0; */ + MultiFrame[11][2] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_96_48_LP); + /* MultiFrame[11][3] = 0; */ + MultiFrame[11][4] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_SPLIT); + /* MultiFrame[11][5] = 0; */ + /* MultiFrame[11][6] = 0; */ + MultiFrame[11][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_PACK); + + /* MultiFrame[12][0] = 0; */ + /* MultiFrame[12][1] = 0; */ + /* MultiFrame[12][2] = 0; */ + MultiFrame[12][3] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_ROUTING); + MultiFrame[12][4] = ABE_TASK_ID(C_ABE_FW_TASK_ULMixer); #define TASK_VX_UL_SLT 12 #define TASK_VX_UL_IDX 5 - MultiFrame[12][5] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_16; - //MultiFrame[12][6] = 0; - //MultiFrame[12][7] = 0; - //MultiFrame[13][0] = 0; - //MultiFrame[13][1] = 0; - MultiFrame[13][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_MM_UL2_ROUTING; - MultiFrame[13][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_SideTone; - MultiFrame[13][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_UL; - //MultiFrame[13][5] = 0; - //MultiFrame[13][6] = 0; - //MultiFrame[13][7] = 0; - - //MultiFrame[14][0] = 0; - //MultiFrame[14][1] = 0; - //MultiFrame[14][2] = 0; - MultiFrame[14][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_DMIC; -#define TASK_BT_DL_48_8_SLT 14 -#define TASK_BT_DL_48_8_IDX 4 - MultiFrame[14][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_8; - //MultiFrame[14][5] = 0; -#define TASK_ECHO_SLT 14 -#define TASK_ECHO_IDX 6 - MultiFrame[14][6] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_16; - //MultiFrame[14][7] = 0; - - MultiFrame[15][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_IIR; - MultiFrame[15][1] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DL1_APS_CORE; - //MultiFrame[15][2] = 0; - MultiFrame[15][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_BT_VX_UL; - //MultiFrame[15][4] = 0; - //MultiFrame[15][5] = 0; - //MultiFrame[15][6] = 0; - //MultiFrame[15][7] = 0; - - //MultiFrame[16][0] = 0; - //MultiFrame[16][1] = 0; + MultiFrame[12][5] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16); + /* MultiFrame[12][6] = 0; */ + /* MultiFrame[12][7] = 0; */ + + /* MultiFrame[13][0] = 0; */ + /* MultiFrame[13][1] = 0; */ + MultiFrame[13][2] = ABE_TASK_ID(C_ABE_FW_TASK_MM_UL2_ROUTING); + MultiFrame[13][3] = ABE_TASK_ID(C_ABE_FW_TASK_SideTone); + /* MultiFrame[13][4] = 0; */ + MultiFrame[13][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_DL); + /* MultiFrame[13][6] = 0; */ + /* MultiFrame[13][7] = 0; */ + + /* MultiFrame[14][0] = 0; */ + /* MultiFrame[14][1] = 0; */ + /* MultiFrame[14][2] = 0; */ + MultiFrame[14][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC); +#define TASK_BT_DL_48_8_SLT 14 +#define TASK_BT_DL_48_8_IDX 4 + MultiFrame[14][4] = ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_8); + /* MultiFrame[14][5] = 0; */ + /* MultiFrame[14][6] = 0; */ + /* MultiFrame[14][7] = 0; */ + + MultiFrame[15][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_IIR); + MultiFrame[15][1] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_CORE); + /* MultiFrame[15][2] = 0; */ + MultiFrame[15][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_UL); + /* MultiFrame[15][4] = 0; */ + /* MultiFrame[15][5] = 0; */ + /* MultiFrame[15][6] = 0; */ + /* MultiFrame[15][7] = 0; */ + + /* MultiFrame[16][0] = 0; */ + /* MultiFrame[16][1] = 0; */ #define TASK_ASRC_VX_UL_SLT 16 #define TASK_ASRC_VX_UL_IDX 2 - MultiFrame[16][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_16; - MultiFrame[16][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_VX_UL; // USING ECHO REF MERGED - //MultiFrame[16][4] = 0; - //MultiFrame[16][5] = 0; - //MultiFrame[16][6] = 0; - //MultiFrame[16][7] = 0; - - //MultiFrame[17][0] = 0; - //MultiFrame[17][1] = 0; -#define TASK_BT_UL_8_48_SLT 17 -#define TASK_BT_UL_8_48_IDX 2 - MultiFrame[17][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_8_48; - MultiFrame[17][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_UL2; - //MultiFrame[17][4] = 0; - //MultiFrame[17][5] = 0; - //MultiFrame[17][6] = 0; - //MultiFrame[17][7] = 0; - - MultiFrame[18][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PDM_DL; - //MultiFrame[18][1] = 0; - //MultiFrame[18][2] = 0; - //MultiFrame[18][3] = 0; - //MultiFrame[18][4] = 0; - //MultiFrame[18][5] = 0; - //MultiFrame[18][6] = 0; - //MultiFrame[18][7] = 0; - -#define TASK_IO_MM_DL_SLT 19 + MultiFrame[16][2] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_16); + MultiFrame[16][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_UL); + /* MultiFrame[16][4] = 0; */ + /* MultiFrame[16][5] = 0; */ + /* MultiFrame[16][6] = 0; */ + /* MultiFrame[16][7] = 0; */ + + /* MultiFrame[17][0] = 0; */ + /* MultiFrame[17][1] = 0; */ +#define TASK_BT_UL_8_48_SLT 17 +#define TASK_BT_UL_8_48_IDX 2 + MultiFrame[17][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48); + MultiFrame[17][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL2); + /* MultiFrame[17][4] = 0; */ + /* MultiFrame[17][5] = 0; */ + /* MultiFrame[17][6] = 0; */ + /* MultiFrame[17][7] = 0; */ + +#define TASK_IO_MM_DL_SLT 18 #define TASK_IO_MM_DL_IDX 0 - MultiFrame[19][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL; - //MultiFrame[19][1] = 0 - //MultiFrame[19][2] = 0; - //MultiFrame[19][3] = 0; - //MultiFrame[19][4] = 0; - //MultiFrame[19][5] = 0; - //MultiFrame[19][6] = 0; - //MultiFrame[19][7] = 0; - - MultiFrame[20][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_TONES_DL; - MultiFrame[20][1] = 0; - MultiFrame[20][2] = 0; - //MultiFrame[20][3] = 0; - //MultiFrame[20][4] = 0; - //MultiFrame[20][5] = 0; - //MultiFrame[20][6] = 0; - //MultiFrame[20][7] = 0; - - //MultiFrame[21][0] = 0; - //MultiFrame[21][1] = 0; - //MultiFrame[21][2] = 0; - //MultiFrame[21][3] = 0; - //MultiFrame[21][4] = 0; - //MultiFrame[21][5] = 0; - //MultiFrame[21][6] = 0; - //MultiFrame[21][7] = 0; - - MultiFrame[22][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_DEBUG_IRQFIFO; // MUST STAY ON SLOT 22 - //MultiFrame[22][1] = 0; - MultiFrame[22][2] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_EXT_OUT; - MultiFrame[22][3] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_EXT_IN; - MultiFrame[22][4] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_MM_EXT_IN_SPLIT; - - //MultiFrame[22][5] = 0; - //MultiFrame[22][6] = 0; - //MultiFrame[22][7] = 0; - - MultiFrame[23][0] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_GAIN_UPDATE; - //MultiFrame[23][1] = 0; - //MultiFrame[23][2] = 0; - //MultiFrame[23][3] = 0; - //MultiFrame[23][4] = 0; - //MultiFrame[23][5] = 0; - //MultiFrame[23][6] = 0; - //MultiFrame[23][7] = 0; - - //MultiFrame[24][0] = 0; - //MultiFrame[24][1] = 0; - //MultiFrame[24][2] = 0; - //MultiFrame[24][3] = 0; - //MultiFrame[24][4] = 0; - //MultiFrame[24][5] = 0; - //MultiFrame[24][6] = 0; - //MultiFrame[24][7] = 0; - - abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); - - // EANC Fast Loopback - // dFastLoopback = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_EANC_WRAP2; - // abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_pFastLoopBack_ADDR, (abe_uint32*)&dFastLoopback, sizeof (dFastLoopback)); + MultiFrame[18][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL); + /* MultiFrame[18][1] = 0; */ + /* MultiFrame[18][2] = 0; */ + /* MultiFrame[18][3] = 0; */ + /* MultiFrame[18][4] = 0; */ + /* MultiFrame[18][5] = 0; */ + /* MultiFrame[18][6] = 0; */ + /* MultiFrame[18][7] = 0; */ + + MultiFrame[19][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL); + /* MultiFrame[19][1] = 0 */ + /* MultiFrame[19][2] = 0; */ + /* MultiFrame[19][3] = 0; */ + /* MultiFrame[19][4] = 0; */ + /* MultiFrame[19][5] = 0; */ + /* MM_UL is moved to OPP 100% */ + MultiFrame[19][6] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL); + /* MultiFrame[19][7] = 0; */ + + + MultiFrame[20][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_TONES_DL); + /* MultiFrame[20][1] = 0; */ + /* MultiFrame[20][2] = 0; */ + /* MultiFrame[20][3] = 0; */ + /* MultiFrame[20][4] = 0; */ + /* MultiFrame[20][5] = 0; */ + /* MultiFrame[20][6] = 0; */ + /* MultiFrame[20][7] = 0; */ + + /* MultiFrame[21][0] = 0; */ + MultiFrame[21][1] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs); + MultiFrame[21][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_OUT); + /* MultiFrame[21][3] = 0; */ + /* MultiFrame[21][4] = 0; */ + /* MultiFrame[21][5] = 0; */ + /* MultiFrame[21][6] = 0; */ + /* MultiFrame[21][7] = 0; */ + + /* MUST STAY ON SLOT 22 */ + MultiFrame[22][0] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUG_IRQFIFO); + MultiFrame[22][1] = ABE_TASK_ID(C_ABE_FW_TASK_INIT_FW_MEMORY); + MultiFrame[22][2] = 0; + MultiFrame[22][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN); + MultiFrame[22][4] = ABE_TASK_ID(C_ABE_FW_TASK_MM_EXT_IN_SPLIT); + /* MultiFrame[22][5] = 0; */ + /* MultiFrame[22][6] = 0; */ + /* MultiFrame[22][7] = 0; */ + + MultiFrame[23][0] = ABE_TASK_ID(C_ABE_FW_TASK_GAIN_UPDATE); + /* MultiFrame[23][1] = 0; */ + /* MultiFrame[23][2] = 0; */ + /* MultiFrame[23][3] = 0; */ + /* MultiFrame[23][4] = 0; */ + /* MultiFrame[23][5] = 0; */ + /* MultiFrame[23][6] = 0; */ + /* MultiFrame[23][7] = 0; */ + + /* MultiFrame[24][0] = 0; */ + /* MultiFrame[24][1] = 0; */ + /* MultiFrame[24][2] = 0; */ + /* MultiFrame[24][3] = 0; */ + /* MultiFrame[24][4] = 0; */ + /* MultiFrame[24][5] = 0; */ + /* MultiFrame[24][6] = 0; */ + /* MultiFrame[24][7] = 0; */ + + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, + (u32*)MultiFrame, sizeof (MultiFrame)); /* reset the uplink router */ - n = sizeof(aUplinkMuxing); - for(i = 0; i < n; i++) + n = (D_aUplinkRouting_sizeof)>>1; + for (i = 0; i < n; i++) aUplinkMuxing[i] = ZERO_labelID; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, (abe_uint32 *)aUplinkMuxing, sizeof(aUplinkMuxing)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR, + (u32 *)aUplinkMuxing, sizeof (aUplinkMuxing)); } -/* - * ABE_INIT_ATC - * - * Parameter : - * prot : protocol being used - * - * Operations : - * load the DMEM ATC/AESS descriptors - * - * Return value : +/** + * abe_init_atc + * @id: ABE port ID * + * load the DMEM ATC/AESS descriptors */ -void abe_init_atc(abe_port_id id) +void abe_init_atc (u32 id) { abe_satcdescriptor_aess desc; - abe_uint8 iter; - abe_int32 datasize; + u8 iter; + s32 datasize; - // load default values of the descriptor - desc.rdpt = desc.wrpt = desc.irqdest = desc.cberr = desc.desen = desc.nw =0; + /* load default values of the descriptor */ + desc.rdpt = desc.wrpt = desc.irqdest = desc.cberr = 0; + desc.desen = desc.nw =0; desc.reserved0 = desc.reserved1 = desc.reserved2 = 0; desc.srcid = desc.destid = desc.badd = desc.iter = desc.cbsize = 0; datasize = abe_dma_port_iter_factor (&((abe_port[id]).format)); - iter = (abe_uint8) abe_dma_port_iteration (&((abe_port[id]).format)); - - if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) /* IN from AESS point of view */ + iter = (u8) abe_dma_port_iteration (&((abe_port[id]).format)); + + + /* if the ATC FIFO is too small there will be two ABE firmware + utasks to do the copy this happems on DMIC and MCPDMDL */ + /* VXDL_8kMono = 4 = 2 + 2x1 */ + /* VXDL_16kstereo = 12 = 8 + 2x2 */ + /* MM_DL_1616 = 14 = 12 + 2x1 */ + /* DMIC = 84 = 72 + 2x6 */ + /* VXUL_8kMono = 2 */ + /* VXUL_16kstereo = 4 */ + /* MM_UL2_Stereo = 4 */ + /* PDMDL = 12 */ + + /* IN from AESS point of view */ + if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) if (iter + 2*datasize > 126) desc.wrpt = (iter >>1) + (3*datasize); else @@ -356,167 +362,152 @@ void abe_init_atc(abe_port_id id) desc.wrpt = 0 + 3*datasize; switch ((abe_port[id]).protocol.protocol_switch) { - case SLIMBUS_PORT_PROT: + case SLIMBUS_PORT_PROT : desc.cbdir = (abe_port[id]).protocol.direction; - desc.cbsize = (abe_port[id]).protocol.p.prot_slimbus.buf_size; + desc.cbsize = (abe_port[id]). + protocol.p.prot_slimbus.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4; desc.iter = (abe_port[id]).protocol.p.prot_slimbus.iter; - desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.prot_slimbus.desc_addr1 >> 3]; + desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p. + prot_slimbus.desc_addr1 >> 3]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, (abe_port[id]).protocol.p.prot_slimbus.desc_addr1, - (abe_uint32*)&desc, sizeof(desc)); + (u32*)&desc, sizeof (desc)); desc.badd = (abe_port[id]).protocol.p.prot_slimbus.buf_addr2; - desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.prot_slimbus.desc_addr2 >> 3]; + desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p. + prot_slimbus.desc_addr2 >> 3]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, (abe_port[id]).protocol.p.prot_slimbus.desc_addr2, - (abe_uint32*)&desc, sizeof(desc)); + (u32*)&desc, sizeof (desc)); break; - case SERIAL_PORT_PROT: + case SERIAL_PORT_PROT : desc.cbdir = (abe_port[id]).protocol.direction; desc.cbsize = (abe_port[id]).protocol.p.prot_serial.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4; desc.iter = (abe_port[id]).protocol.p.prot_serial.iter; - desc.srcid = abe_atc_srcid[(abe_port[id]).protocol.p.prot_serial.desc_addr >> 3]; - desc.destid = abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.desc_addr >> 3]; + desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p. + prot_serial.desc_addr >> 3]; + desc.destid = abe_atc_dstid [(abe_port[id]).protocol.p. + prot_serial.desc_addr >> 3]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, (abe_port[id]).protocol.p.prot_serial.desc_addr, - (abe_uint32*)&desc, sizeof(desc)); + (u32*)&desc, sizeof (desc)); break; - case DMIC_PORT_PROT: + case DMIC_PORT_PROT : desc.cbdir = ABE_ATC_DIRECTION_IN; desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4; desc.iter = DMIC_ITER; - desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ]; + desc.srcid = abe_atc_srcid [ABE_ATC_DMIC_DMA_REQ]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - ABE_ATC_DMIC_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + ABE_ATC_DMIC_DMA_REQ * ATC_SIZE, (u32*)&desc, + sizeof (desc)); break; - case MCPDMDL_PORT_PROT: - abe_global_mcpdm_control = abe_port[id].protocol.p.prot_mcpdmdl.control; /* Control allowed on McPDM DL */ + case MCPDMDL_PORT_PROT : desc.cbdir = ABE_ATC_DIRECTION_OUT; desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmdl.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4; desc.iter = MCPDM_DL_ITER; - desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ]; + desc.destid = abe_atc_dstid [ABE_ATC_MCPDMDL_DMA_REQ]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - ABE_ATC_MCPDMDL_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + ABE_ATC_MCPDMDL_DMA_REQ * ATC_SIZE, (u32*)&desc, + sizeof (desc)); break; - case MCPDMUL_PORT_PROT: + case MCPDMUL_PORT_PROT : desc.cbdir = ABE_ATC_DIRECTION_IN; desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmul.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4; desc.iter = MCPDM_UL_ITER; - desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ]; + desc.srcid = abe_atc_srcid [ABE_ATC_MCPDMUL_DMA_REQ]; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - ABE_ATC_MCPDMUL_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof(desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + ABE_ATC_MCPDMUL_DMA_REQ * ATC_SIZE, (u32*)&desc, + sizeof (desc)); break; case PINGPONG_PORT_PROT: /* software protocol, nothing to do on ATC */ break; - case DMAREQ_PORT_PROT: + case DMAREQ_PORT_PROT : desc.cbdir = (abe_port[id]).protocol.direction; desc.cbsize = (abe_port[id]).protocol.p.prot_dmareq.buf_size; desc.badd = ((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4; - desc.iter = 1; /* CBPr needs ITER=1. this is the eDMA job to do the iterations */ + + /* CBPr needs ITER=1. this is the eDMA job to do the iterations */ + desc.iter = 1; + /* input from ABE point of view */ if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) { - desc.rdpt = 127; - desc.wrpt = 0; - desc.srcid = abe_atc_srcid[(abe_port[id]).protocol.p.prot_dmareq.desc_addr >> 3]; + + /* desc.rdpt = 127; */ + /* desc.wrpt = 0; */ + desc.srcid = abe_atc_srcid + [(abe_port[id]).protocol.p. + prot_dmareq.desc_addr >> 3]; } else { - desc.rdpt = 0; - desc.wrpt = 127; - desc.destid = abe_atc_dstid[(abe_port[id]).protocol.p.prot_dmareq.desc_addr >> 3]; + + /* desc.rdpt = 0; */ + /* desc.wrpt = 127; */ + desc.destid = abe_atc_dstid + [(abe_port[id]).protocol.p. + prot_dmareq.desc_addr >> 3]; } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - (abe_port[id]).protocol.p.prot_dmareq.desc_addr, (abe_uint32*)&desc, sizeof (desc)); - break; - default: + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p. + prot_dmareq.desc_addr, + (u32*)&desc, sizeof (desc)); break; } } -/* - * ABE_RESET_ATC - * - * Parameter: - * prot : protocol being used - * - * Operations: - * reset R/W pointers of a FIFO - * - * Return value: +/** + * abe_init_dma_t + * @ id: ABE port ID + * @ prot: protocol being used * + * load the dma_t with physical information from AE memory mapping */ -void abe_reset_atc(abe_uint32 atc_index) -{ - abe_satcdescriptor_aess desc; - - desc.rdpt = desc.wrpt = desc.irqdest = desc.cberr = desc.desen = desc.nw =0; - desc.reserved0 = desc.reserved1 = desc.reserved2 = 0; - desc.srcid = desc.destid = desc.badd = desc.iter = desc.cbsize = 0; - - desc.cbdir = ABE_ATC_DIRECTION_IN; - desc.cbsize = 4; - desc.badd = 448 >> 4; - desc.iter = 1; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - ABE_ATC_DMIC_DMA_REQ * ATC_SIZE, (abe_uint32*)&desc, sizeof (desc)); -} - -/* - * - * ABE_INIT_DMA_T - * Parameter : - * prot : protocol being used - * - * Operations : - * load the dma_t with physical information from AE memory mapping - * - * Return value : - * - */ -void abe_init_dma_t(abe_port_id id, abe_port_protocol_t *prot) +void abe_init_dma_t (u32 id, abe_port_protocol_t *prot) { abe_dma_t_offset dma; - abe_uint32 idx; + u32 idx; - dma.data = 0; /* default dma_t points to address 0000... */ + /* default dma_t points to address 0000... */ + dma.data = 0; dma.iter = 0; switch (prot->protocol_switch) { case PINGPONG_PORT_PROT: for (idx = 0; idx < 32; idx++) { - if (((prot->p).prot_pingpong.irq_data) == (abe_uint32)(1 << idx)) + if (((prot->p).prot_pingpong.irq_data) == (u32)(1 << idx)) break; } (prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE; + /* translate byte address/size in DMEM words */ dma.data = (prot->p).prot_pingpong.buf_addr >> 2; dma.iter = (prot->p).prot_pingpong.buf_size >> 2; break; - case DMAREQ_PORT_PROT: + case DMAREQ_PORT_PROT : for (idx = 0; idx < 32; idx++) { - if (((prot->p).prot_dmareq.dma_data) == (abe_uint32)(1 << idx)) + if (((prot->p).prot_dmareq.dma_data) == (u32)(1 << idx)) break; } dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + idx*4); dma.iter = (prot->p).prot_dmareq.iter; (prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE; break; - case SLIMBUS_PORT_PROT: - case SERIAL_PORT_PROT: - case DMIC_PORT_PROT: - case MCPDMDL_PORT_PROT: - case MCPDMUL_PORT_PROT: - default: + case SLIMBUS_PORT_PROT : + case SERIAL_PORT_PROT : + case DMIC_PORT_PROT : + case MCPDMDL_PORT_PROT : + case MCPDMUL_PORT_PROT : + default : break; } @@ -524,188 +515,206 @@ void abe_init_dma_t(abe_port_id id, abe_port_protocol_t *prot) abe_port [id].dma = dma; } -/* - * ABE_DISENABLE_DMA_REQUEST +/** + * abe_disenable_dma_request * Parameter: * Operations: * Return value: */ -void abe_disable_enable_dma_request(abe_port_id id, abe_uint32 on_off) +void abe_disable_enable_dma_request (u32 id, u32 on_off) { ABE_SIODescriptor desc; ABE_SPingPongDescriptor desc_pp; - abe_uint8 desc_third_word[4], irq_dmareq_field; - abe_uint32 sio_desc_address; - abe_uint32 struct_offset; + u8 desc_third_word[4], irq_dmareq_field; + u32 sio_desc_address; + u32 struct_offset; if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) { - irq_dmareq_field = (abe_uint8)(on_off * abe_port[id].protocol.p.prot_pingpong.irq_data); + irq_dmareq_field = (u8)(on_off * abe_port[id].protocol.p.prot_pingpong.irq_data); sio_desc_address = D_PingPongDesc_ADDR; - struct_offset = (abe_uint32)&(desc_pp.data_size) - (abe_uint32)&(desc_pp); - - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address + struct_offset, (abe_uint32 *)desc_third_word, 4); - desc_third_word[2] = irq_dmareq_field; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address + struct_offset, (abe_uint32 *)desc_third_word, 4); + struct_offset = (u32)&(desc_pp.data_size) - (u32)&(desc_pp); + + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_desc_address + struct_offset, + (u32 *)desc_third_word, 4); + desc_third_word [2] = irq_dmareq_field; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address + struct_offset, + (u32 *)desc_third_word, 4); } else { - sio_desc_address = dmem_port_descriptors + (id * sizeof(ABE_SIODescriptor)); - abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address, (abe_uint32*)&desc, sizeof (desc)); + sio_desc_address = dmem_port_descriptors + ( + id * sizeof(ABE_SIODescriptor)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + sio_desc_address, (u32*)&desc, + sizeof (desc)); if (on_off) { - desc.atc_irq_data = (abe_uint8) abe_port[id].protocol.p.prot_dmareq.dma_data; + desc.atc_irq_data = (u8) abe_port[id].protocol.p. + prot_dmareq.dma_data; desc.on_off = 0x80; } else { desc.atc_irq_data = 0; desc.on_off = 0; } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc, sizeof (desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32*)&desc, sizeof (desc)); } } -void abe_enable_dma_request(abe_port_id id) +void abe_enable_dma_request (u32 id) { - abe_disable_enable_dma_request(id, 1); + abe_disable_enable_dma_request (id, 1); } -/* - * ABE_DISABLE_DMA_REQUEST +/** + * abe_disable_dma_request * * Parameter: * Operations: * Return value: * */ -void abe_disable_dma_request(abe_port_id id) +void abe_disable_dma_request (u32 id) { - abe_disable_enable_dma_request(id, 0); + abe_disable_enable_dma_request (id, 0); } - -/* - * ABE_ENABLE_ATC +/** + * abe_enable_atc * Parameter: * Operations: * Return value: */ -void abe_enable_atc(abe_port_id id) +void abe_enable_atc (u32 id) { - just_to_avoid_the_many_warnings = (abe_port_id)id; -#if 0 - abe_satcdescriptor_aess desc; - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, - (abe_port[id]).protocol.p.prot_dmareq.desc_addr, - (abe_uint32*)&desc, sizeof (desc)); - desc.desen = 1; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - (abe_port[id]).protocol.p.prot_dmareq.desc_addr, - (abe_uint32*)&desc, sizeof (desc)); -#endif } -/* - * ABE_DISABLE_ATC +/** + * abe_disable_atc * Parameter: * Operations: * Return value: */ -void abe_disable_atc(abe_port_id id) +void abe_disable_atc (u32 id) { abe_satcdescriptor_aess desc; - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, - (abe_port[id]).protocol.p.prot_dmareq.desc_addr, - (abe_uint32*)&desc, sizeof (desc)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32*)&desc, sizeof (desc)); desc.desen = 0; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - (abe_port[id]).protocol.p.prot_dmareq.desc_addr, - (abe_uint32*)&desc, sizeof (desc)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (abe_port[id]).protocol.p.prot_dmareq.desc_addr, + (u32*)&desc, sizeof (desc)); } -/* - * ABE_INIT_IO_TASKS +/** + * abe_init_io_tasks + * @prot : protocol being used * - * Parameter : - * prot : protocol being used - * - * Operations : - * load the micro-task parameters doing to DMEM <==> SMEM data moves - * - * I/O descriptors input parameters : - * For Read from DMEM usually THR1/THR2 = X+1/X-1 - * For Write to DMEM usually THR1/THR2 = 2/0 - * UP_1/2 =X+1/X-1 - * - * Return value : + * load the micro-task parameters doing to DMEM <==> SMEM data moves * + * I/O descriptors input parameters : + * For Read from DMEM usually THR1/THR2 = X+1/X-1 + * For Write to DMEM usually THR1/THR2 = 2/0 + * UP_1/2 =X+1/X-1 */ -void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_protocol_t *prot) +void abe_init_io_tasks (u32 id, abe_data_format_t *format, abe_port_protocol_t *prot) { ABE_SIODescriptor desc; ABE_SPingPongDescriptor desc_pp; - abe_uint32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id; - abe_uint32 copy_func_index, before_func_index, after_func_index; - abe_uint32 dmareq_addr, dmareq_field; - abe_uint32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32; - abe_uint32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1; - abe_uint32 copy_func_index2, atc_desc_address1, atc_desc_address2; - short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT]; + u32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id; + u32 copy_func_index, before_func_index, after_func_index; + u32 dmareq_addr, dmareq_field; + u32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32; + u32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1; + u32 copy_func_index2, atc_desc_address1, atc_desc_address2; if (prot->protocol_switch == PINGPONG_PORT_PROT) { + + /* MM_DL managed in ping-pong */ if (MM_DL_PORT == id) { - // @@@@ reset local memory - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, - D_multiFrame_ADDR, - (abe_uint32*)MultiFrame, - sizeof (MultiFrame)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, + (u32*)MultiFrame, + sizeof (MultiFrame)); MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_PING_PONG; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, - sizeof (MultiFrame)); + ABE_TASK_ID(C_ABE_FW_TASK_IO_PING_PONG); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); } else { abe_dbg_param |= ERR_API; abe_dbg_error_log (ABE_PARAMETER_ERROR); } - smem1 = (abe_uint8) abe_port[id].smem_buffer1; - copy_func_index = (abe_uint8) abe_dma_port_copy_subroutine_id (id); - dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr; + /* set the SMEM buffer -- programming sequence */ + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, + &dOppMode32, sizeof (u32)); + if (dOppMode32 == DOPPMODE32_OPP100) + /* ASRC input buffer, size 40 */ + smem1 = smem_mm_dl_opp100; + else + /* at OPP 25/50 or without ASRC */ + smem1 = smem_mm_dl_opp25; + + copy_func_index = (u8) abe_dma_port_copy_subroutine_id (id); + dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr; dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data; datasize = abe_dma_port_iter_factor (format); + + /* number of "samples" either mono or stereo */ iter = abe_dma_port_iteration (format); - iter_samples = (iter / datasize); /* number of "samples" either mono or stereo */ + iter_samples = (iter / datasize); /* load the IO descriptor */ - desc_pp.drift_ASRC = 0; /* no drift */ - desc_pp.drift_io = 0; /* no drift */ - desc_pp.hw_ctrl_addr = (abe_uint16) dmareq_addr; - desc_pp.copy_func_index = (abe_uint8) copy_func_index; - desc_pp.smem_addr = (abe_uint8) smem1; - desc_pp.atc_irq_data = (abe_uint8) dmareq_field; /* DMA req 0 is used for CBPr0 */ - desc_pp.x_io = (abe_uint8) iter_samples; /* size of block transfer */ - desc_pp.data_size = (abe_uint8) datasize; - desc_pp.workbuff_BaseAddr = (abe_uint16) (abe_base_address_pingpong [0]); /* address comunicated in Bytes */ - desc_pp.workbuff_Samples = (abe_uint16) iter_samples; /* size comunicated in XIO sample */ - desc_pp.nextbuff0_BaseAddr = (abe_uint16) (abe_base_address_pingpong [0]); - desc_pp.nextbuff0_Samples = (abe_uint16) ((abe_size_pingpong >> 2)/datasize); - desc_pp.nextbuff1_BaseAddr = (abe_uint16) (abe_base_address_pingpong [1]); - desc_pp.nextbuff1_Samples = (abe_uint16) ((abe_size_pingpong >> 2)/datasize); + + /* no drift */ + desc_pp.drift_ASRC = 0; + + /* no drift */ + desc_pp.drift_io = 0; + desc_pp.hw_ctrl_addr = (u16) dmareq_addr; + desc_pp.copy_func_index = (u8) copy_func_index; + desc_pp.smem_addr = (u8) smem1; + + /* DMA req 0 is used for CBPr0 */ + desc_pp.atc_irq_data = (u8) dmareq_field; + + /* size of block transfer */ + desc_pp.x_io = (u8) iter_samples; + desc_pp.data_size = (u8) datasize; + + /* address comunicated in Bytes */ + desc_pp.workbuff_BaseAddr = (u16) (abe_base_address_pingpong [1]); + + /* size comunicated in XIO sample */ + desc_pp.workbuff_Samples = (u16) iter_samples; + + desc_pp.nextbuff0_BaseAddr = (u16) (abe_base_address_pingpong [0]); + desc_pp.nextbuff0_Samples = (u16) ((abe_size_pingpong >> 2)/datasize); + desc_pp.nextbuff1_BaseAddr = (u16) (abe_base_address_pingpong [1]); + desc_pp.nextbuff1_Samples = (u16) ((abe_size_pingpong >> 2)/datasize); + + /* next buffer to send is B1, first IRQ fills B0 */ desc_pp.counter = 1; /* send a DMA req to fill B0 with N samples - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW, &(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */ + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW, + &(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */ sio_desc_address = D_PingPongDesc_ADDR; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, - (abe_uint32*)&desc_pp, sizeof (desc_pp)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address, + (u32*)&desc_pp, sizeof (desc_pp)); } else { io_sub_id = dmareq_addr = ABE_DMASTATUS_RAW; dmareq_field = 0; atc_desc_address1 = atc_desc_address2 = 0; - datasize2=datasize = abe_dma_port_iter_factor(format); - x_io = (abe_uint8) abe_dma_port_iteration(format); + datasize2=datasize = abe_dma_port_iter_factor (format); + x_io = (u8) abe_dma_port_iteration (format); nsamp = (x_io / datasize); atc_ptr_saved2=atc_ptr_saved = DMIC_ATC_PTR_labelID + id; @@ -713,74 +722,82 @@ void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_proto smem1 = abe_port[id].smem_buffer1; smem3 = smem2 = abe_port[id].smem_buffer2; - copy_func_index1 = (abe_uint8) abe_dma_port_copy_subroutine_id(id); - before_func_index = after_func_index = copy_func_index2 = NULL_COPY_CFPID; + copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id (id); + before_func_index = after_func_index = + copy_func_index2 = NULL_COPY_CFPID; /* MM_DL managed in non-ping-pong mode */ if (MM_DL_PORT == id) { - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, - (abe_uint32*)MultiFrame, sizeof (MultiFrame)); - MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = D_tasksList_ADDR + - sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL; - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, - (abe_uint32 *)MultiFrame, sizeof (MultiFrame)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, + (u32*)MultiFrame, + sizeof (MultiFrame)); + MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = + D_tasksList_ADDR + + sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, + (u32*)MultiFrame, sizeof (MultiFrame)); } switch (prot->protocol_switch) { - case DMIC_PORT_PROT: + case DMIC_PORT_PROT : /* DMIC port is read in two steps */ x_io = x_io >> 1; nsamp = nsamp >> 1; atc_desc_address1 = ABE_ATC_DMIC_DMA_REQ*ATC_SIZE; io_sub_id = IO_IP_CFPID; break; - case MCPDMDL_PORT_PROT: - /* PDMDL port is written to in two steps */ + case MCPDMDL_PORT_PROT : + /* PDMDL port is written to in two steps */ x_io = x_io >> 1; atc_desc_address1 = ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE; io_sub_id = IO_IP_CFPID; break; - case MCPDMUL_PORT_PROT: + case MCPDMUL_PORT_PROT : atc_desc_address1 = ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE; io_sub_id = IO_IP_CFPID; break; - case SLIMBUS_PORT_PROT: - atc_desc_address1 = abe_port[id].protocol.p.prot_slimbus.desc_addr1; - atc_desc_address2 = abe_port[id].protocol.p.prot_slimbus.desc_addr2; + case SLIMBUS_PORT_PROT : + atc_desc_address1 = abe_port[id].protocol.p. + prot_slimbus.desc_addr1; + atc_desc_address2 = abe_port[id].protocol.p. + prot_slimbus.desc_addr2; copy_func_index2 = NULL_COPY_CFPID; -/* @@@@@@ -#define SPLIT_SMEM_CFPID 9 -#define MERGE_SMEM_CFPID 10 -#define SPLIT_TDM_12_CFPID 11 -#define MERGE_TDM_12_CFPID 12 -*/ - io_sub_id = IO_IP_CFPID; - case SERIAL_PORT_PROT: /* McBSP/McASP */ - atc_desc_address1 = (abe_int16) abe_port[id].protocol.p.prot_serial.desc_addr; - io_sub_id = IO_IP_CFPID; + /* @@@@@@ + #define SPLIT_SMEM_CFPID 9 + #define MERGE_SMEM_CFPID 10 + #define SPLIT_TDM_12_CFPID 11 + #define MERGE_TDM_12_CFPID 12 + */ + io_sub_id = IO_IP_CFPID; break; - case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */ - dmareq_addr = abe_port[id].protocol.p.prot_dmareq.dma_addr; - dmareq_field = 0; - atc_desc_address1 = abe_port[id].protocol.p.prot_dmareq.desc_addr; - io_sub_id = IO_DMAREQ_CFPID; + case SERIAL_PORT_PROT : /* McBSP/McASP */ + atc_desc_address1 = (s16) abe_port[id].protocol.p. + prot_serial.desc_addr; + io_sub_id = IO_IP_CFPID; break; - default: + case DMAREQ_PORT_PROT : /* DMA w/wo CBPr */ + dmareq_addr = abe_port[id].protocol.p. + prot_dmareq.dma_addr; + dmareq_field = 0; + atc_desc_address1 = abe_port[id].protocol.p. + prot_dmareq.desc_addr; + io_sub_id = IO_IP_CFPID; break; } /* special situation of the PING_PONG protocol which has its own SIO descriptor format */ - /* Sequence of operations on ping-pong buffers B0/B1 - * ---------- time --------------------------------------------->>>> - * Host Application is ready to send data from DDR to B0 - * SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0 - * ABE HAL init FW to B0 - * send DMAreq to fill B0 - * FIRMWARE starts sending B1 data, sends DMAreq v - * continue with B0, sends DMAreq v continue with B1 - * DMAreq v (direct access from HAL to AESS regs) - * v (from ABE_FW) v (from ABE_FW) - * SDMA | fills B0 | fills B1...| fills B0... + /* + Sequence of operations on ping-pong buffers B0/B1 + + ----------------------------------------------------------------- time --------------------------------------------->>>> + Host Application is ready to send data from DDR to B0 + SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0 + + FIRMWARE starts with #12 B1 data, sends IRQ/DMAreq sens #pong B1 data sends IRQ/DMAreq sends #ping B0 v sends B1 samples + ARM / SDMA | fills B0 | fills B1 ... | fills B0 ... + Counter 0 1 2 3 */ if (MM_UL_PORT == id) { @@ -791,202 +808,203 @@ void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_proto /* check for 8kHz/16kHz */ if (VX_DL_PORT == id) { abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); if (abe_port[id].format.f == 8000) { MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_8; + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8); MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_8_48; - smem1 = IO_VX_DL_ASRC_labelID; /*Voice_8k_DL_labelID*/ + ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48); + + /*Voice_8k_DL_labelID*/ + smem1 = IO_VX_DL_ASRC_labelID; } else { - MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_DL_16; - MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_DL_16_48; - smem1 = IO_VX_DL_ASRC_labelID; /* Voice_16k_DL_labelID */ + MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_16); + MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_16_48); + + /* Voice_16k_DL_labelID */ + smem1 = IO_VX_DL_ASRC_labelID; } abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); } /* check for 8kHz/16kHz */ if (VX_UL_PORT == id) { abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); if (abe_port[id].format.f == 8000) { MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_8; + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8); MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_8; + ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8); /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_8; */ + ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_8); */ smem1 = Voice_8k_UL_labelID; } else { MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ASRC_VX_UL_16; + ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_16); MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_VX_UL_48_16; + ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16); /* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_ECHO_REF_48_16; */ + ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_16); */ smem1 = Voice_16k_UL_labelID; } abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); } /* check for 8kHz/16kHz */ if (BT_VX_DL_PORT == id) { - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, - (abe_uint32*)MultiFrame, - sizeof (MultiFrame)); + (u32*)MultiFrame, sizeof (MultiFrame)); if (abe_port[id].format.f == 8000) { MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_8; + ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_8); smem1 = BT_DL_8k_labelID; } else { MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_DL_48_16; + ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_16); smem1 = BT_DL_16k_labelID; } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, - sizeof (MultiFrame)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); } /* check for 8kHz/16kHz */ if (BT_VX_UL_PORT == id) { - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, - (abe_uint32*)MultiFrame, sizeof (MultiFrame)); + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, + (u32*)MultiFrame, sizeof (MultiFrame)); if (abe_port[id].format.f == 8000) { MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_8_48; + ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48); smem1 = BT_UL_8k_labelID; } else { MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] = - D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_BT_UL_16_48; + ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_16_48); smem1 = BT_UL_16k_labelID; } - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - D_multiFrame_ADDR, (abe_uint32*)MultiFrame, - sizeof (MultiFrame)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); } if (MM_DL_PORT == id) { - //@@@ abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); - //@@@ MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = D_tasksList_ADDR + sizeof(ABE_STask)*C_ABE_FW_TASK_IO2_MM_DL; - //@@@ abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR, (abe_uint32*)MultiFrame, sizeof (MultiFrame)); - /* set the SMEM buffer @@@@@ programming sequence : OPP must be set before channel is defined */ - abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(abe_uint32)); + /* check for CBPr / serial_port / Ping-pong access */ + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); + MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] = + ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + D_multiFrame_ADDR, (u32*)MultiFrame, + sizeof (MultiFrame)); + + /* set the SMEM buffer -- programming sequence */ + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, + D_maxTaskBytesInSlot_ADDR, &dOppMode32, + sizeof (u32)); + if (dOppMode32 == DOPPMODE32_OPP100) - smem1 = smem_mm_dl_opp100; /* ASRC input buffer, size 40 */ + /* ASRC input buffer, size 40 */ + smem1 = smem_mm_dl_opp100; else - smem1 = smem_mm_dl_opp25; /* at OPP 25/50 or without ASRC */ + /* at OPP 25/50 or without ASRC */ + smem1 = smem_mm_dl_opp25; } if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) direction = 0; else - direction = 3; /* offset of the write pointer in the ATC descriptor */ + /* offset of the write pointer in the ATC descriptor */ + direction = 3; desc.drift_ASRC = 0; desc.drift_io = 0; - desc.io_type_idx = (abe_uint8) io_sub_id; - desc.samp_size = (abe_uint8) datasize; - //desc.unused1 = (abe_uint8)0; - //desc.unused2 = (abe_uint8)0; - - desc.hw_ctrl_addr = (abe_uint16) (dmareq_addr << 2); - desc.atc_irq_data = (abe_uint8) dmareq_field; - desc.flow_counter = (abe_uint16) 0; - - desc.direction_rw = (abe_uint8) direction; - desc.nsamp = (abe_uint8) nsamp; - desc.x_io = (abe_uint8) x_io; - desc.on_off = 0x80; // set ATC ON - - desc.split_addr1 = (abe_uint16) smem1; - desc.split_addr2 = (abe_uint16) smem2; - desc.split_addr3 = (abe_uint16) smem3; - desc.before_f_index = (abe_uint8) before_func_index; - desc.after_f_index = (abe_uint8) after_func_index; - - desc.smem_addr1 = (abe_uint16) smem1; - desc.atc_address1 = (abe_uint16) atc_desc_address1; - desc.atc_pointer_saved1 = (abe_uint16) atc_ptr_saved; - desc.data_size1 = (abe_uint8) datasize; - desc.copy_f_index1 = (abe_uint8) copy_func_index1; - - desc.smem_addr2 = (abe_uint16) smem2; - desc.atc_address2 = (abe_uint16) atc_desc_address2; - desc.atc_pointer_saved2 = (abe_uint16) atc_ptr_saved2; - desc.data_size2 = (abe_uint8) datasize2; - desc.copy_f_index2 = (abe_uint8) copy_func_index2; - - sio_desc_address = dmem_port_descriptors + (id * sizeof(ABE_SIODescriptor)); - abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, - sio_desc_address, (abe_uint32*)&desc, sizeof(desc)); + desc.io_type_idx = (u8) io_sub_id; + desc.samp_size = (u8) datasize; + + desc.hw_ctrl_addr = (u16) (dmareq_addr << 2); + desc.atc_irq_data = (u8) dmareq_field; + desc.flow_counter = (u16) 0; + + desc.direction_rw = (u8) direction; + desc.nsamp = (u8) nsamp; + desc.x_io = (u8) x_io; + desc.on_off = 0x80; /* set ATC ON */ + + desc.split_addr1 = (u16) smem1; + desc.split_addr2 = (u16) smem2; + desc.split_addr3 = (u16) smem3; + desc.before_f_index = (u8) before_func_index; + desc.after_f_index = (u8) after_func_index; + + desc.smem_addr1 = (u16) smem1; + desc.atc_address1 = (u16) atc_desc_address1; + desc.atc_pointer_saved1 = (u16) atc_ptr_saved; + desc.data_size1 = (u8) datasize; + desc.copy_f_index1 = (u8) copy_func_index1; + + desc.smem_addr2 = (u16) smem2; + desc.atc_address2 = (u16) atc_desc_address2; + desc.atc_pointer_saved2 = (u16) atc_ptr_saved2; + desc.data_size2 = (u8) datasize2; + desc.copy_f_index2 = (u8) copy_func_index2; + + sio_desc_address = dmem_port_descriptors + (id * + sizeof(ABE_SIODescriptor)); + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, + sio_desc_address, + (u32*)&desc, sizeof (desc)); } } -/* - * ABE_INIT_DMIC - * - * Parameter : - * x : d - * - * Operations : +/** + * abe_init_dmic + * @x: d * * - * Return value : - * */ -void abe_init_dmic(abe_uint32 x) +void abe_init_dmic (u32 x) { - just_to_avoid_the_many_warnings = x; + } -/* - * ABE_INIT_MCPDM - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : +/** + * abe_init_mcpdm + * @x: d * */ -void abe_init_mcpdm(abe_uint32 x) +void abe_init_mcpdm (u32 x) { - just_to_avoid_the_many_warnings = x; + } -/* - * ABE_RESET_FEATURE - * - * Parameter : - * x : index of the feature to be initialized - * - * Operations : - * reload the configuration - * - * Return value : +/** + * abe_reset_feature + * @x: index of the feature to be initialized * + * reload the configuration */ -void abe_reset_one_feature(abe_uint32 x) +void abe_reset_one_feature (u32 x) { - all_feature[x] = all_feature_init[x]; /* load default fields */ - /* abe_call_subroutine ((all_feature[x]).disable_feature, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER); */ + all_feature [x] = all_feature_init [x]; /* load default fields */ + /* abe_call_subroutine ((all_feature[x]).disable_feature, NOPARAMETER, + NOPARAMETER, NOPARAMETER, NOPARAMETER); */ } -/* - * ABE_RESET_ALL_FEATURE +/** + * abe_reset_all_feature * - * Parameter : - * none - * - * Operations : - * load default configuration for all features - * struct { + * load default configuration for all features + * struct { * uint16 load_default_data; * uint16 read_parameter; * uint16 write_parameter; @@ -997,194 +1015,932 @@ void abe_reset_one_feature(abe_uint32 x) * uint16 fw_scheduler_subslot_position; * uint16 min_opp; * char name[NBCHARFEATURENAME]; - * } abe_feature_t; - * - * Return value : - * + * } abe_feature_t; */ -void abe_reset_all_features(void) +void abe_reset_all_features (void) { - abe_uint16 i; + u16 i; - //for (i = 0; i < FEAT_GAINS_DMIC1; i++) - for (i = 0; i < LAST_PORT_ID; i++) - abe_reset_one_feature(i); + for (i = 0; i < MAXNBFEATURE; i++) + abe_reset_one_feature (i); } -/* - * ABE_RESET_ALL_PORTS - * - * Parameter : - * none - * - * Operations : - * load default configuration for all features - * - * Return value : +/** + * abe_reset_all_ports * + * load default configuration for all features */ -void abe_reset_all_ports(void) +void abe_reset_all_ports (void) { - abe_uint16 i; + u16 i; for (i = 0; i < LAST_PORT_ID; i++) - abe_reset_port (i); + abe_reset_port (i); /* mixers' configuration */ - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES); - - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, GAIN_0dB , RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER); - - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES); - abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_100MS, MIX_AUDUL_INPUT_UPLINK); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL); - - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL); - - abe_write_gain(GAINS_DMIC1,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC1,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DMIC2,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC2,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DMIC3,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC3,GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_AMIC,GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - - abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - //abe_write_gain(GAINS_EANC ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); - //abe_write_gain(GAINS_EANC, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES); + + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2); + + abe_write_mixer (MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER); + abe_write_mixer (MIXSDT, GAIN_0dB , RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER); + + abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL); + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES); + abe_write_mixer (MIXAUDUL, GAIN_0dB , RAMP_100MS, MIX_AUDUL_INPUT_UPLINK); + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL); + + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL); + + abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_AMIC ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_AMIC, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + + abe_write_gain(GAINS_SPLIT ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_SPLIT, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); /*@@@Gain set to -6dB due to McPDM Limitation*/ - /* cf CDDS 00635*/ - abe_write_gain(GAINS_DL1, GAIN_M6dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DL1, GAIN_M6dB, RAMP_100MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DL2, GAIN_M6dB, RAMP_100MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DL2, GAIN_M6dB, RAMP_100MS, GAIN_RIGHT_OFFSET); + /* cf CDDS 00635*/ + abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); + abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET); + abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET); } -/* - * ABE_CLEAN_TEMPORARY_BUFFERS - * - * Parameter : - * none - * - * Operations : - * clear temporary buffers - * - * Return value : +/** + * abe_clean_temporay buffers * + * clear temporary buffers */ -void abe_clean_temporary_buffers(abe_port_id id) +void abe_clean_temporary_buffers (u32 id) { switch (id) { - case DMIC_PORT: - abe_reset_mem(ABE_DMEM, D_DMIC_UL_FIFO_ADDR,D_DMIC_UL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3, S_DMIC0_96_48_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3); - abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+dmic1_gains_offset) << 2, 6 << 2); /* reset current gains */ - abe_reset_mem(ABE_SMEM, (S_GCurrent_ADDR+dmic1_gains_offset) << 3, 6 << 3); + case DMIC_PORT: + abe_reset_mem (ABE_DMEM, D_DMIC_UL_FIFO_ADDR, + D_DMIC_UL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3, + S_DMIC0_96_48_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3, + S_DMIC1_96_48_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, + S_DMIC1_96_48_data_sizeof << 3); + abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+dmic1_gains_offset) << 2, + 6 << 2); /* reset current gains */ + abe_reset_mem (ABE_SMEM, (S_GCurrent_ADDR+dmic1_gains_offset) << 3, + 6 << 3); break; - case PDM_UL_PORT: - abe_reset_mem(ABE_DMEM, D_McPDM_UL_FIFO_ADDR, D_McPDM_UL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_AMIC_96_48_data_ADDR << 3, S_AMIC_96_48_data_sizeof << 3); - abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+amic_gains_offset) << 2, 2 << 2); /* reset current gains */ - abe_reset_mem(ABE_SMEM, (S_GCurrent_ADDR+amic_gains_offset) << 3, 6 << 3); + case PDM_UL_PORT: + abe_reset_mem (ABE_DMEM, D_McPDM_UL_FIFO_ADDR, + D_McPDM_UL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3, + S_BT_UL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_AMIC_96_48_data_ADDR << 3, + S_AMIC_96_48_data_sizeof << 3); + abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+amic_gains_offset) << 2, + 2 << 2); /* reset current gains */ + abe_reset_mem (ABE_SMEM, (S_GCurrent_ADDR+amic_gains_offset) << 3, + 6 << 3); break; - case BT_VX_UL_PORT: // ABE <-- BT (8/16kHz) - abe_reset_mem(ABE_DMEM, D_BT_UL_FIFO_ADDR, D_BT_UL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_HP_data_ADDR << 3, - S_BT_UL_8_48_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_LP_data_ADDR << 3, - S_BT_UL_8_48_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_HP_data_ADDR << 3, - S_BT_UL_16_48_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_LP_data_ADDR << 3, - S_BT_UL_16_48_LP_data_sizeof << 3); + case BT_VX_UL_PORT: + abe_reset_mem (ABE_DMEM, D_BT_UL_FIFO_ADDR, + D_BT_UL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3, + S_BT_UL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3, + S_BT_UL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_UL_8_48_HP_data_ADDR << 3, + S_BT_UL_8_48_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_UL_8_48_LP_data_ADDR << 3, + S_BT_UL_8_48_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_UL_16_48_HP_data_ADDR << 3, + S_BT_UL_16_48_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_UL_16_48_LP_data_ADDR << 3, + S_BT_UL_16_48_LP_data_sizeof << 3); break; - case MM_UL_PORT: - abe_reset_mem(ABE_DMEM, D_MM_UL_FIFO_ADDR, D_MM_UL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_MM_UL_ADDR << 3, S_MM_UL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, D_MM_UL2_FIFO_sizeof << 3); + case MM_UL_PORT: + abe_reset_mem (ABE_DMEM, D_MM_UL_FIFO_ADDR, + D_MM_UL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_MM_UL_ADDR << 3, + S_MM_UL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_MM_UL2_ADDR << 3, + D_MM_UL2_FIFO_sizeof << 3); break; - case MM_UL2_PORT: - abe_reset_mem(ABE_DMEM, D_MM_UL2_FIFO_ADDR, D_MM_UL2_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3, S_MM_UL2_sizeof << 3); + case MM_UL2_PORT: + abe_reset_mem (ABE_DMEM, D_MM_UL2_FIFO_ADDR, + D_MM_UL2_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_MM_UL2_ADDR << 3, + S_MM_UL2_sizeof << 3); break; - case VX_UL_PORT: - abe_reset_mem(ABE_DMEM, D_VX_UL_FIFO_ADDR, D_VX_UL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_VX_UL_ADDR << 3, S_VX_UL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_HP_data_ADDR << 3, S_VX_UL_48_8_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3, S_VX_UL_48_8_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3, S_VX_UL_48_16_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3, S_VX_UL_48_16_LP_data_sizeof << 3); + case VX_UL_PORT: + abe_reset_mem (ABE_DMEM, D_VX_UL_FIFO_ADDR, + D_VX_UL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_VX_UL_ADDR << 3, + S_VX_UL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_UL_48_8_HP_data_ADDR << 3, + S_VX_UL_48_8_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3, + S_VX_UL_48_8_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3, + S_VX_UL_48_16_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3, + S_VX_UL_48_16_LP_data_sizeof << 3); break; - case MM_DL_PORT: - abe_reset_mem(ABE_DMEM, D_MM_DL_FIFO_ADDR, D_MM_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_MM_DL_ADDR << 3, S_MM_DL_sizeof << 3); + case MM_DL_PORT: + abe_reset_mem (ABE_DMEM, D_MM_DL_FIFO_ADDR, + D_MM_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_MM_DL_ADDR << 3, + S_MM_DL_sizeof << 3); break; - case VX_DL_PORT: - abe_reset_mem(ABE_DMEM, D_VX_DL_FIFO_ADDR, D_VX_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_VX_DL_ADDR << 3, S_VX_DL_sizeof << 3); - abe_reset_mem (ABE_SMEM, S_VX_DL_8_48_HP_data_ADDR << 3, S_VX_DL_8_48_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3, S_VX_DL_8_48_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3, S_VX_DL_16_48_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3, S_VX_DL_16_48_LP_data_sizeof << 3); + case VX_DL_PORT: + abe_reset_mem (ABE_DMEM, D_VX_DL_FIFO_ADDR, + D_VX_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_VX_DL_ADDR << 3, + S_VX_DL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_DL_8_48_HP_data_ADDR << 3, + S_VX_DL_8_48_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3, + S_VX_DL_8_48_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3, + S_VX_DL_16_48_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3, + S_VX_DL_16_48_LP_data_sizeof << 3); break; - case TONES_DL_PORT: - abe_reset_mem(ABE_DMEM, D_TONES_DL_FIFO_ADDR, D_TONES_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_Tones_ADDR << 3, S_Tones_sizeof << 3); + case TONES_DL_PORT: + abe_reset_mem (ABE_DMEM, D_TONES_DL_FIFO_ADDR, + D_TONES_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_Tones_ADDR << 3, + S_Tones_sizeof << 3); break; - case VIB_DL_PORT: - abe_reset_mem(ABE_DMEM, D_VIB_DL_FIFO_ADDR, D_VIB_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_VIBRA_ADDR << 3, S_VIBRA_sizeof << 3); + case VIB_DL_PORT: + abe_reset_mem (ABE_DMEM, D_VIB_DL_FIFO_ADDR, + D_VIB_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_VIBRA_ADDR << 3, + S_VIBRA_sizeof << 3); break; - case BT_VX_DL_PORT:// ABE --> BT (8/16kHz) - abe_reset_mem(ABE_DMEM, D_BT_DL_FIFO_ADDR, D_BT_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_BT_DL_ADDR << 3, S_BT_DL_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_HP_data_ADDR << 3, S_BT_DL_48_8_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_LP_data_ADDR << 3, S_BT_DL_48_8_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_HP_data_ADDR << 3, S_BT_DL_48_16_HP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_LP_data_ADDR << 3, S_BT_DL_48_16_LP_data_sizeof << 3); + case BT_VX_DL_PORT: + abe_reset_mem (ABE_DMEM, D_BT_DL_FIFO_ADDR, + D_BT_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_BT_DL_ADDR << 3, + S_BT_DL_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_DL_48_8_HP_data_ADDR << 3, + S_BT_DL_48_8_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_DL_48_8_LP_data_ADDR << 3, + S_BT_DL_48_8_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_DL_48_16_HP_data_ADDR << 3, + S_BT_DL_48_16_HP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_BT_DL_48_16_LP_data_ADDR << 3, + S_BT_DL_48_16_LP_data_sizeof << 3); break; - case PDM_DL_PORT: - abe_reset_mem(ABE_DMEM, D_McPDM_DL_FIFO_ADDR, D_McPDM_DL_FIFO_sizeof); - abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, S_DMIC1_96_48_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3, S_DL2_M_LR_EQ_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3, S_DL1_M_EQ_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3, S_EARP_48_96_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3, S_IHF_48_96_LP_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3, S_APS_DL1_EQ_data_sizeof << 3); - abe_reset_mem(ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3, S_APS_DL2_EQ_data_sizeof << 3); - break; - case MM_EXT_OUT_PORT: - abe_reset_mem(ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR, D_MM_EXT_OUT_FIFO_sizeof); + case PDM_DL_PORT: + abe_reset_mem (ABE_DMEM, D_McPDM_DL_FIFO_ADDR, + D_McPDM_DL_FIFO_sizeof); + abe_reset_mem (ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3, + S_DMIC1_96_48_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3, + S_DL2_M_LR_EQ_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3, + S_DL1_M_EQ_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3, + S_EARP_48_96_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3, + S_IHF_48_96_LP_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3, + S_APS_DL1_EQ_data_sizeof << 3); + abe_reset_mem (ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3, + S_APS_DL2_EQ_data_sizeof << 3); break; - case MM_EXT_IN_PORT: - abe_reset_mem(ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR, D_MM_EXT_IN_FIFO_sizeof); + case MM_EXT_OUT_PORT: + abe_reset_mem (ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR, + D_MM_EXT_OUT_FIFO_sizeof); break; - default: + case MM_EXT_IN_PORT: + abe_reset_mem (ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR, + D_MM_EXT_IN_FIFO_sizeof); break; } + +} + +/** + * abe_init_asrc_vx_dl + * + * Initialize the following ASRC VX_DL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_DL_VX_Coefs pointer + * 10. CMEM for ASRC_DL_VX_Coefs pointer + * ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + * C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_DL_VX pointer + * 12. CMEM for XinASRC_DL_VX pointer + * XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 + * 13. SMEM for IO_VX_DL_ASRC pointer + * 14. CMEM for IO_VX_DL_ASRC pointer + * IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_vx_dl ( s32 dppm) +{ + s32 el[45]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + + temp0 = 0; + temp1 = 1; + + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + 1*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i+1] = 1; + adppm = dppm; + } else { + el[i+1] = -1; + adppm = (-1*dppm); + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L); + + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + 2*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + 3*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = dtemp<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + 4*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = (-dtemp)<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_VX_ADDR + 5*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0x00400000; + } else { + el[i+1] = (0x00100000-(dtemp/2))<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_DL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x00000020; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_DL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x003fffe0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + VX_DL_PORT*sizeof(ABE_SIODescriptor) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 9. SMEM for ASRC_DL_VX_Coefs pointer */ + /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0 + /1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_DL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = C_CoefASRC16_VX_ADDR; + el[i+1] = (el[i+1]<<8) + C_CoefASRC16_VX_sizeof; + + el[i+2] = C_CoefASRC15_VX_ADDR; + el[i+2] = (el[i+2]<<8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + + + /* 10. CMEM for ASRC_DL_VX_Coefs pointer */ + /* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/ + 1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_DL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 11. SMEM for XinASRC_DL_VX pointer */ + /* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_DL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_DL_VX_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_VX_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 12. CMEM for XinASRC_DL_VX pointer */ + /* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_DL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 13. SMEM for IO_VX_DL_ASRC pointer */ + /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ + ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = IO_VX_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_DL_VX_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_VX_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 14. CMEM for IO_VX_DL_ASRC pointer */ + /* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ + ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = IO_VX_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = ((ASRC_DL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12) + + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + + + abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR,(u32 *) &el[0], 42); + +} + +/** + * abe_init_asrc_vx_ul + * + * Initialize the following ASRC VX_UL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_UL_VX_Coefs pointer + * 10. CMEM for ASRC_UL_VX_Coefs pointer + * ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof + * /0/1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 + * 11. SMEM for XinASRC_UL_VX pointer + * 12. CMEM for XinASRC_UL_VX pointer + * XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 + * 13. SMEM for UL_48_8_DEC pointer + * 14. CMEM for UL_48_8_DEC pointer + * UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + * 15. SMEM for UL_48_16_DEC pointer + * 16. CMEM for UL_48_16_DEC pointer + * UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + * ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 + */ +void abe_init_asrc_vx_ul ( s32 dppm) +{ + s32 el[51]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + + temp0 = 0; + temp1 = 1; + + + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + 1*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i+1] = 1; + adppm = dppm; + } else { + el[i+1] = -1; + adppm = (-1*dppm); + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L); + + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + 2*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + 3*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = dtemp<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + 4*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = (-dtemp)<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_UL_VX_ADDR + 5*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0x00400000; + } else { + el[i+1] = (0x00100000-(dtemp/2))<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_UL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x00000020; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_UL_VX_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x003fffe0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + VX_UL_PORT*sizeof(ABE_SIODescriptor) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 9. SMEM for ASRC_UL_VX_Coefs pointer */ + /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_UL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = C_CoefASRC16_VX_ADDR; + el[i+1] = (el[i+1]<<8) + C_CoefASRC16_VX_sizeof; + + el[i+2] = C_CoefASRC15_VX_ADDR; + el[i+2] = (el[i+2]<<8) + C_CoefASRC15_VX_sizeof; + i = i + 3; + + + /* 10. CMEM for ASRC_UL_VX_Coefs pointer */ + /* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/ + C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_UL_VX_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 11. SMEM for XinASRC_UL_VX pointer */ + /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_UL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_UL_VX_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 12. CMEM for XinASRC_UL_VX pointer */ + /* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_UL_VX_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 13. SMEM for UL_48_8_DEC pointer */ + /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = UL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_UL_VX_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 14. CMEM for UL_48_8_DEC pointer */ + /* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = UL_48_8_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = ((ASRC_UL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12) + + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 15. SMEM for UL_48_16_DEC pointer */ + /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = UL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_UL_VX_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 16. CMEM for UL_48_16_DEC pointer */ + /* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/ + ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = UL_48_16_DEC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = ((ASRC_UL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12) + + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + + + abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *)&el[0], 48); + +} + +/** + * abe_init_asrc_mm_dl + * + * Initialize the following ASRC MM_DL parameters : + * 1. DriftSign = D_AsrcVars[1] = 1 or -1 + * 2. Subblock = D_AsrcVars[2] = 0 + * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 4. MinusDeltaAlpha = D_AsrcVars[4] = (-round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2 + * 5. OneMinusEpsilon = D_AsrcVars[5] = 1 - DeltaAlpha/2 + * 6. AlphaCurrent = 0x000020 (CMEM), initial value of Alpha parameter + * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter + * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2) + * 8. drift_ASRC = 0 & drift_io = 0 + * 9. SMEM for ASRC_DL_MM_Coefs pointer + * 10. CMEM for ASRC_DL_MM_Coefs pointer + * ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof/ + * 0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1 + * 11. SMEM for XinASRC_DL_MM pointer + * 12. CMEM for XinASRC_DL_MM pointer + * XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0 + * 13. SMEM for IO_MM_DL_ASRC pointer + * 14. CMEM for IO_MM_DL_ASRC pointer + * IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/ + * ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 + */ +void abe_init_asrc_mm_dl ( s32 dppm) +{ + s32 el[45]; + s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr; + u32 i = 0; + + temp0 = 0; + temp1 = 1; + + /* 1. DriftSign = D_AsrcVars[1] = 1 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_MM_ADDR + 1*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm >= 0) { + el[i+1] = 1; + adppm = dppm; + } else { + el[i+1] = -1; + adppm = (-1*dppm); + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L); + + /* 2. Subblock = D_AsrcVars[2] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_MM_ADDR + 2*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 3. DeltaAlpha = D_AsrcVars[3] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_MM_ADDR + 3*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = dtemp<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_MM_ADDR + 4*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0; + } else { + el[i+1] = (-dtemp)<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */ + mem_tag = ABE_DMEM; + mem_addr = D_AsrcVars_DL_MM_ADDR + 5*sizeof(s32); + el[i] = (mem_tag << 16) + mem_addr; + if (dppm == 0) { + el[i+1] = 0x00400000; + } else { + el[i+1] = (0x00100000-(dtemp/2))<<2; + } + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 6. AlphaCurrent = 0x000020 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_AlphaCurrent_DL_MM_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x00000020; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 7. BetaCurrent = 0x3fffe0 (CMEM) */ + mem_tag = ABE_CMEM; + mem_addr = C_BetaCurrent_DL_MM_ADDR; + el[i] = (mem_tag << 16) + (mem_addr << 2); + el[i+1] = 0x003fffe0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 8. drift_ASRC = 0 & drift_io = 0 */ + mem_tag = ABE_DMEM; + mem_addr = D_IOdescr_ADDR + MM_DL_PORT*sizeof(ABE_SIODescriptor) + + drift_asrc_; + el[i] = (mem_tag << 16) + mem_addr; + el[i+1] = temp0; + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 9. SMEM for ASRC_DL_MM_Coefs pointer */ + /* ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof + /0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1 */ + mem_tag = ABE_SMEM; + mem_addr = ASRC_DL_MM_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = C_CoefASRC16_DL_MM_ADDR; + el[i+1] = (el[i+1]<<8) + C_CoefASRC16_DL_MM_sizeof; + + el[i+2] = C_CoefASRC15_DL_MM_ADDR; + el[i+2] = (el[i+2]<<8) + C_CoefASRC15_DL_MM_sizeof; + i = i + 3; + + + /*10. 11. CMEM for ASRC_DL_MM_Coefs pointer */ + /* ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof + /0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1 */ + mem_tag = ABE_CMEM; + mem_addr = ASRC_DL_MM_Coefs_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 11. SMEM for XinASRC_DL_MM pointer */ + /* XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = XinASRC_DL_MM_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_DL_MM_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_MM_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + + /* 12. CMEM for XinASRC_DL_MM pointer */ + /* XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = XinASRC_DL_MM_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + i = i + 3; + + + /* 13. SMEM for IO_MM_DL_ASRC pointer */ + /* IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/ + ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */ + mem_tag = ABE_SMEM; + mem_addr = IO_MM_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + el[i+1] = S_XinASRC_DL_MM_ADDR; + el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_MM_sizeof; + + el[i+2] = temp0; + i = i + 3; + + + /* 14. CMEM for IO_MM_DL_ASRC pointer */ + /* IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/ + ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */ + mem_tag = ABE_CMEM; + mem_addr = IO_MM_DL_ASRC_labelID; + el[i] = (mem_tag << 16) + (mem_addr << 2); + + /* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */ + el[i+1] = ((ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k)<<16) + + (temp1<<12) + (temp0<<4) + temp0; + + /* dummy field */ + el[i+2] = temp0; + + + abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *)&el[0], 42); + } diff --git a/sound/soc/omap/abe/abe_initxxx_labels.h b/sound/soc/omap/abe/abe_initxxx_labels.h index 4408a952e8d3..5057be313abf 100644 --- a/sound/soc/omap/abe/abe_initxxx_labels.h +++ b/sound/soc/omap/abe/abe_initxxx_labels.h @@ -1,313 +1,328 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== */ - #ifndef _ABE_INITXXX_LABELS_H_ #define _ABE_INITXXX_LABELS_H_ -#define Dummy_Regs_labelID 0 -#define Dummy_AM_labelID 1 -#define Voice_8k_UL_labelID 2 -#define Voice_8k_DL_labelID 3 -#define ECHO_REF_8K_labelID 4 -#define Voice_16k_UL_labelID 5 -#define Voice_16k_DL_labelID 6 -#define ECHO_REF_16K_labelID 7 -#define MM_DL_labelID 8 -#define IO_VX_DL_ASRC_labelID 9 -#define IO_MM_DL_ASRC_labelID 10 -#define IO_VIBRA_DL_labelID 11 -#define ZERO_labelID 12 -#define GTarget_labelID 13 -#define GCurrent_labelID 14 -#define Gr_1_labelID 15 -#define Gr_2_labelID 16 -#define Gr_Regs_labelID 17 -#define DMIC0_Gain_labelID 18 -#define DMIC1_Gain_labelID 19 -#define DMIC2_Gain_labelID 20 -#define DMIC3_Gain_labelID 21 -#define AMIC_Gain_labelID 22 -#define MIXDL1_Gain_labelID 23 -#define MIXDL2_Gain_labelID 24 -#define DEFAULT_Gain_labelID 25 -#define DL1_M_G_Tones_labelID 26 -#define DL2_M_G_Tones_labelID 27 -#define Echo_M_G_labelID 28 -#define SDT_M_G_labelID 29 -#define VXREC_M_G_VX_DL_labelID 30 -#define UL_M_G_VX_DL_labelID 31 -#define DL1_M_labelID 32 -#define DL2_M_labelID 33 -#define MM_UL2_labelID 34 -#define VX_DL_labelID 35 -#define Tones_labelID 36 -#define DL_M_MM_UL2_VX_DL_labelID 37 -#define Echo_M_labelID 38 -#define VX_UL_labelID 39 -#define VX_UL_M_labelID 40 -#define SDT_F_labelID 41 -#define SDT_F_data_labelID 42 -#define SDT_Coef_labelID 43 -#define SDT_Regs_labelID 44 -#define SDT_M_labelID 45 -#define DL1_EQ_labelID 46 -#define DL2_EQ_labelID 47 -#define DL1_GAIN_out_labelID 48 -#define DL2_GAIN_out_labelID 49 -#define DMIC1_labelID 50 -#define DMIC1_L_labelID 51 -#define DMIC1_R_labelID 52 -#define DMIC2_labelID 53 -#define DMIC2_L_labelID 54 -#define DMIC2_R_labelID 55 -#define DMIC3_labelID 56 -#define DMIC3_L_labelID 57 -#define DMIC3_R_labelID 58 -#define MIC4_labelID 59 -#define MIC4_L_labelID 60 -#define MIC4_R_labelID 61 -#define BT_UL_L_labelID 62 -#define BT_UL_R_labelID 63 -#define AMIC_labelID 64 -#define AMIC_L_labelID 65 -#define AMIC_R_labelID 66 -#define EANC_FBK_In_labelID 67 -#define EANC_FBK_Out_labelID 68 -#define EANC_FBK_L_labelID 69 -#define EANC_FBK_R_labelID 70 -#define EchoRef_L_labelID 71 -#define EchoRef_R_labelID 72 -#define MM_DL_L_labelID 73 -#define MM_DL_R_labelID 74 -#define MM_UL_labelID 75 -#define AMIC_96_labelID 76 -#define DMIC0_96_labelID 77 -#define DMIC1_96_labelID 78 -#define DMIC2_96_labelID 79 -#define DMIC_desc_labelID 80 -#define UL_MIC_48K_labelID 81 -#define EQ_DL_48K_labelID 82 -#define EQ_48K_labelID 83 -#define McPDM_Out1_labelID 84 -#define McPDM_Out2_labelID 85 -#define McPDM_Out3_labelID 86 -#define VX_UL_MUX_labelID 87 -#define MM_UL2_MUX_labelID 88 -#define MM_UL_MUX_labelID 89 -#define XinASRC_DL_VX_labelID 90 -#define ASRC_DL_VX_Coefs_labelID 91 -#define ASRC_DL_VX_Alpha_labelID 92 -#define ASRC_DL_VX_VarsBeta_labelID 93 -#define ASRC_DL_VX_8k_Regs_labelID 94 -#define XinASRC_UL_VX_labelID 95 -#define ASRC_UL_VX_Coefs_labelID 96 -#define ASRC_UL_VX_Alpha_labelID 97 -#define ASRC_UL_VX_VarsBeta_labelID 98 -#define ASRC_UL_VX_8k_Regs_labelID 99 -#define UL_48_8_DEC_labelID 100 -#define ASRC_DL_VX_16k_Regs_labelID 101 -#define ASRC_UL_VX_16k_Regs_labelID 102 -#define UL_48_16_DEC_labelID 103 -#define XinASRC_DL_MM_labelID 104 -#define ASRC_DL_MM_Coefs_labelID 105 -#define ASRC_DL_MM_Alpha_labelID 106 -#define ASRC_DL_MM_VarsBeta_labelID 107 -#define ASRC_DL_MM_Regs_labelID 108 -#define VX_REC_labelID 109 -#define VXREC_UL_M_Tones_VX_UL_labelID 110 -#define VX_REC_L_labelID 111 -#define VX_REC_R_labelID 112 -#define DL2_M_L_labelID 113 -#define DL2_M_R_labelID 114 -#define DL1_M_data_labelID 115 -#define DL1_M_Coefs_labelID 116 -#define DL2_M_LR_data_labelID 117 -#define DL2_M_LR_Coefs_labelID 118 -#define SRC_6_LP_COEFS_labelID 119 -#define SRC_6_LP_GAIN_COEFS_labelID 120 -#define SRC_6_HP_COEFS_labelID 121 -#define SRC_3_LP_COEFS_labelID 122 -#define SRC_3_LP_GAIN_COEFS_labelID 123 -#define SRC_3_HP_COEFS_labelID 124 -#define VX_DL_8_48_LP_DATA_labelID 125 -#define VX_DL_8_48_HP_DATA_labelID 126 -#define VX_DL_16_48_LP_DATA_labelID 127 -#define VX_DL_16_48_HP_DATA_labelID 128 -#define VX_UL_48_8_LP_DATA_labelID 129 -#define VX_UL_48_8_HP_DATA_labelID 130 -#define VX_UL_48_16_LP_DATA_labelID 131 -#define VX_UL_48_16_HP_DATA_labelID 132 -#define BT_UL_8_48_LP_DATA_labelID 133 -#define BT_UL_8_48_HP_DATA_labelID 134 -#define BT_UL_16_48_LP_DATA_labelID 135 -#define BT_UL_16_48_HP_DATA_labelID 136 -#define BT_DL_48_8_LP_DATA_labelID 137 -#define BT_DL_48_8_HP_DATA_labelID 138 -#define BT_DL_48_16_LP_DATA_labelID 139 -#define BT_DL_48_16_HP_DATA_labelID 140 -#define ECHO_REF_48_16_LP_DATA_labelID 141 -#define ECHO_REF_48_16_HP_DATA_labelID 142 -#define ECHO_REF_48_8_LP_DATA_labelID 143 -#define ECHO_REF_48_8_HP_DATA_labelID 144 -#define ECHO_REF_DEC_labelID 145 -#define VX_UL_8_TEMP_labelID 146 -#define VX_UL_16_TEMP_labelID 147 -#define UP_DOWN_8_48_labelID 148 -#define UP_DOWN_16_48_labelID 149 -#define SRC_6_LP_48k_labelID 150 -#define SRC_6_HP_labelID 151 -#define SRC_3_LP_48k_labelID 152 -#define SRC_3_HP_labelID 153 -#define EARP_48_96_LP_DATA_labelID 154 -#define SRC_48_96_LP_labelID 155 -#define IHF_48_96_LP_DATA_labelID 156 -#define EQ_VX_UL_16K_labelID 157 -#define pAPS_iir1_p23_labelID 158 -#define pAPS_iir1_p45_labelID 159 -#define APS_IIR_Regs_labelID 160 -#define pAPS_core_DL1_p1_labelID 161 -#define pAPS_core_DL1_p23_labelID 162 -#define pAPS_core_DL1_p45_labelID 163 -#define pAPS_core_DL1_r_labelID 164 -#define pAPS_DL2L_core_r_labelID 165 -#define pAPS_DL2R_core_r_labelID 166 -#define pAPS_COIL_core_DL1_p1_labelID 167 -#define pAPS_COIL_core_DL1_p23_labelID 168 -#define pAPS_COIL_core_DL1_p45_labelID 169 -#define pAPS_COIL_core_DL1_r_labelID 170 -#define DL2_L_APS_IIR_p23_labelID 171 -#define DL2_R_APS_IIR_p23_labelID 172 -#define DL2_L_APS_IIR_p45_labelID 173 -#define DL2_R_APS_IIR_p45_labelID 174 -#define DL2_L_APS_CORE_p1_labelID 175 -#define DL2_L_APS_CORE_p23_labelID 176 -#define DL2_L_APS_CORE_p45_labelID 177 -#define DL2_R_APS_CORE_p1_labelID 178 -#define DL2_R_APS_CORE_p23_labelID 179 -#define DL2_R_APS_CORE_p45_labelID 180 -#define DL2_L_APS_COIL_CORE_p1_labelID 181 -#define DL2_L_APS_COIL_CORE_p23_labelID 182 -#define DL2_L_APS_COIL_CORE_p45_labelID 183 -#define pAPS_COIL_DL2L_core_r_labelID 184 -#define DL2_R_APS_COIL_CORE_p1_labelID 185 -#define DL2_R_APS_COIL_CORE_p23_labelID 186 -#define DL2_R_APS_COIL_CORE_p45_labelID 187 -#define pAPS_COIL_DL2R_core_r_labelID 188 -#define DL1_APS_labelID 189 -#define DL2_L_APS_labelID 190 -#define DL2_R_APS_labelID 191 -#define pEANC_p0_labelID 192 -#define pEANC_p1_labelID 193 -#define pEANC_p23_labelID 194 -#define pEANC_p45_labelID 195 -#define pEANC_reg1_labelID 196 -#define pEANC_reg2_labelID 197 -#define pEANC_reg3_labelID 198 -#define pEANC_r_labelID 199 -#define DL1_APS_EQ_p23_labelID 200 -#define DL1_APS_EQ_p45_labelID 201 -#define DL2_APS_EQ_p23_labelID 202 -#define DL2_APS_EQ_p45_labelID 203 -#define pDC_EANC_p23_labelID 204 -#define pDC_EANC_r_labelID 205 -#define pVIBRA1_p0_labelID 206 -#define pVIBRA1_p1_labelID 207 -#define pVIBRA1_p23_labelID 208 -#define pVIBRA1_p45_labelID 209 -#define pVibra1_pR1_labelID 210 -#define pVibra1_pR2_labelID 211 -#define pVibra1_pR3_labelID 212 -#define pVIBRA1_r_labelID 213 -#define pVIBRA2_p0_labelID 214 -#define pVIBRA2_p1_labelID 215 -#define pVIBRA2_p23_labelID 216 -#define pVIBRA2_p45_labelID 217 -#define pCtrl_p67_labelID 218 -#define pVIBRA2_r_labelID 219 -#define VIBRA_labelID 220 -#define PING_labelID 221 -#define PING_Regs_labelID 222 -#define UP_48_96_LP_COEFS_labelID 223 -#define AMIC_96_48_data_labelID 224 -#define DOWN_96_48_Coefs_labelID 225 -#define DOWN_96_48_Regs_labelID 226 -#define DMIC0_96_48_data_labelID 227 -#define DMIC1_96_48_data_labelID 228 -#define DMIC2_96_48_data_labelID 229 -#define EANC_FBK_96_48_data_labelID 230 -#define pDC_EANC_r2_labelID 231 -#define SIO_DMIC_labelID 232 -#define SIO_PDM_UL_labelID 233 -#define SIO_BT_VX_UL_labelID 234 -#define SIO_MM_UL_labelID 235 -#define SIO_MM_UL2_labelID 236 -#define SIO_VX_UL_labelID 237 -#define SIO_MM_DL_labelID 238 -#define SIO_VX_DL_labelID 239 -#define SIO_TONES_DL_labelID 240 -#define SIO_VIB_DL_labelID 241 -#define SIO_BT_VX_DL_labelID 242 -#define SIO_PDM_DL_labelID 243 -#define SIO_MM_EXT_OUT_labelID 244 -#define SIO_MM_EXT_IN_labelID 245 -#define SIO_TDM_OUT_labelID 246 -#define SIO_TDM_IN_labelID 247 -#define DMIC_ATC_PTR_labelID 248 -#define MCPDM_UL_ATC_PTR_labelID 249 -#define BT_VX_UL_ATC_PTR_labelID 250 -#define MM_UL_ATC_PTR_labelID 251 -#define MM_UL2_ATC_PTR_labelID 252 -#define VX_UL_ATC_PTR_labelID 253 -#define MM_DL_ATC_PTR_labelID 254 -#define VX_DL_ATC_PTR_labelID 255 -#define TONES_DL_ATC_PTR_labelID 256 -#define VIB_DL_ATC_PTR_labelID 257 -#define BT_VX_DL_ATC_PTR_labelID 258 -#define PDM_DL_ATC_PTR_labelID 259 -#define MM_EXT_OUT_ATC_PTR_labelID 260 -#define MM_EXT_IN_ATC_PTR_labelID 261 -#define TDM_OUT_ATC_PTR_labelID 262 -#define TDM_IN_ATC_PTR_labelID 263 -#define MCU_IRQ_FIFO_ptr_labelID 264 -#define DEBUG_IRQ_FIFO_reg_labelID 265 -#define UP_DOWN_48_96_labelID 266 -#define OSR96_2_labelID 267 -#define DEBUG_GAINS_labelID 268 -#define DBG_8K_PATTERN_labelID 269 -#define DBG_16K_PATTERN_labelID 270 -#define DBG_24K_PATTERN_labelID 271 -#define DBG_48K_PATTERN_labelID 272 -#define DBG_96K_PATTERN_labelID 273 -#define UL_VX_UL_48_8K_labelID 274 -#define UL_VX_UL_48_16K_labelID 275 -#define BT_DL_labelID 276 -#define BT_UL_labelID 277 -#define BT_DL_8k_labelID 278 -#define BT_DL_16k_labelID 279 -#define BT_UL_8k_labelID 280 -#define BT_UL_16k_labelID 281 -#define MM_EXT_IN_labelID 282 -#define MM_EXT_IN_L_labelID 283 -#define MM_EXT_IN_R_labelID 284 -#define ECHO_REF_48_16_WRAP_labelID 285 -#define ECHO_REF_48_8_WRAP_labelID 286 -#define BT_UL_16_48_WRAP_labelID 287 -#define BT_UL_8_48_WRAP_labelID 288 -#define BT_DL_48_16_WRAP_labelID 289 -#define BT_DL_48_8_WRAP_labelID 290 -#define VX_DL_16_48_WRAP_labelID 291 -#define VX_DL_8_48_WRAP_labelID 292 -#define VX_UL_48_16_WRAP_labelID 293 -#define VX_UL_48_8_WRAP_labelID 294 -#define APS_DL1_IRQs_WRAP_labelID 295 -#define APS_DL2_L_IRQs_WRAP_labelID 296 -#define APS_DL2_R_IRQs_WRAP_labelID 297 +#define Dummy_Regs_labelID 0 +#define Dummy_AM_labelID 1 +#define Voice_8k_UL_labelID 2 +#define Voice_8k_DL_labelID 3 +#define ECHO_REF_8K_labelID 4 +#define Voice_16k_UL_labelID 5 +#define Voice_16k_DL_labelID 6 +#define ECHO_REF_16K_labelID 7 +#define MM_DL_labelID 8 +#define IO_VX_DL_ASRC_labelID 9 +#define IO_MM_DL_ASRC_labelID 10 +#define IO_VIBRA_DL_labelID 11 +#define ZERO_labelID 12 +#define GTarget_labelID 13 +#define GCurrent_labelID 14 +#define Gr_1_labelID 15 +#define Gr_2_labelID 16 +#define Gr_Regs_labelID 17 +#define DMIC0_Gain_labelID 18 +#define DMIC1_Gain_labelID 19 +#define DMIC2_Gain_labelID 20 +#define DMIC3_Gain_labelID 21 +#define AMIC_Gain_labelID 22 +#define MIXDL1_Gain_labelID 23 +#define MIXDL2_Gain_labelID 24 +#define DEFAULT_Gain_labelID 25 +#define DL1_M_G_Tones_labelID 26 +#define DL2_M_G_Tones_labelID 27 +#define Echo_M_G_labelID 28 +#define SDT_M_G_labelID 29 +#define VXREC_M_G_VX_DL_labelID 30 +#define UL_M_G_VX_DL_labelID 31 +#define DL1_M_labelID 32 +#define DL2_M_labelID 33 +#define MM_UL2_labelID 34 +#define VX_DL_labelID 35 +#define Tones_labelID 36 +#define DL_M_MM_UL2_VX_DL_labelID 37 +#define Echo_M_labelID 38 +#define VX_UL_labelID 39 +#define VX_UL_M_labelID 40 +#define SDT_F_labelID 41 +#define SDT_F_data_labelID 42 +#define SDT_Coef_labelID 43 +#define SDT_Regs_labelID 44 +#define SDT_M_labelID 45 +#define DL1_EQ_labelID 46 +#define DL2_EQ_labelID 47 +#define DL1_GAIN_out_labelID 48 +#define DL2_GAIN_out_labelID 49 +#define DMIC1_labelID 50 +#define DMIC1_L_labelID 51 +#define DMIC1_R_labelID 52 +#define DMIC2_labelID 53 +#define DMIC2_L_labelID 54 +#define DMIC2_R_labelID 55 +#define DMIC3_labelID 56 +#define DMIC3_L_labelID 57 +#define DMIC3_R_labelID 58 +#define MIC4_labelID 59 +#define MIC4_L_labelID 60 +#define MIC4_R_labelID 61 +#define BT_UL_L_labelID 62 +#define BT_UL_R_labelID 63 +#define AMIC_labelID 64 +#define AMIC_L_labelID 65 +#define AMIC_R_labelID 66 +#define EANC_FBK_In_labelID 67 +#define EANC_FBK_Out_labelID 68 +#define EANC_FBK_L_labelID 69 +#define EANC_FBK_R_labelID 70 +#define EchoRef_L_labelID 71 +#define EchoRef_R_labelID 72 +#define MM_DL_L_labelID 73 +#define MM_DL_R_labelID 74 +#define MM_UL_labelID 75 +#define AMIC_96_labelID 76 +#define DMIC0_96_labelID 77 +#define DMIC1_96_labelID 78 +#define DMIC2_96_labelID 79 +#define DMIC_desc_labelID 80 +#define UL_MIC_48K_labelID 81 +#define EQ_DL_48K_labelID 82 +#define EQ_48K_labelID 83 +#define McPDM_Out1_labelID 84 +#define McPDM_Out2_labelID 85 +#define McPDM_Out3_labelID 86 +#define VX_UL_MUX_labelID 87 +#define MM_UL2_MUX_labelID 88 +#define MM_UL_MUX_labelID 89 +#define XinASRC_DL_VX_labelID 90 +#define ASRC_DL_VX_Coefs_labelID 91 +#define ASRC_DL_VX_Alpha_labelID 92 +#define ASRC_DL_VX_VarsBeta_labelID 93 +#define ASRC_DL_VX_8k_Regs_labelID 94 +#define XinASRC_UL_VX_labelID 95 +#define ASRC_UL_VX_Coefs_labelID 96 +#define ASRC_UL_VX_Alpha_labelID 97 +#define ASRC_UL_VX_VarsBeta_labelID 98 +#define ASRC_UL_VX_8k_Regs_labelID 99 +#define UL_48_8_DEC_labelID 100 +#define ASRC_DL_VX_16k_Regs_labelID 101 +#define ASRC_UL_VX_16k_Regs_labelID 102 +#define UL_48_16_DEC_labelID 103 +#define XinASRC_DL_MM_labelID 104 +#define ASRC_DL_MM_Coefs_labelID 105 +#define ASRC_DL_MM_Alpha_labelID 106 +#define ASRC_DL_MM_VarsBeta_labelID 107 +#define ASRC_DL_MM_Regs_labelID 108 +#define VX_REC_labelID 109 +#define VXREC_UL_M_Tones_VX_UL_labelID 110 +#define VX_REC_L_labelID 111 +#define VX_REC_R_labelID 112 +#define DL2_M_L_labelID 113 +#define DL2_M_R_labelID 114 +#define DL1_M_data_labelID 115 +#define DL1_M_Coefs_labelID 116 +#define DL2_M_LR_data_labelID 117 +#define DL2_M_LR_Coefs_labelID 118 +#define SRC_6_LP_COEFS_labelID 119 +#define SRC_6_LP_GAIN_COEFS_labelID 120 +#define SRC_6_HP_COEFS_labelID 121 +#define SRC_3_LP_COEFS_labelID 122 +#define SRC_3_LP_GAIN_COEFS_labelID 123 +#define SRC_3_HP_COEFS_labelID 124 +#define VX_DL_8_48_LP_DATA_labelID 125 +#define VX_DL_8_48_HP_DATA_labelID 126 +#define VX_DL_16_48_LP_DATA_labelID 127 +#define VX_DL_16_48_HP_DATA_labelID 128 +#define VX_UL_48_8_LP_DATA_labelID 129 +#define VX_UL_48_8_HP_DATA_labelID 130 +#define VX_UL_48_16_LP_DATA_labelID 131 +#define VX_UL_48_16_HP_DATA_labelID 132 +#define BT_UL_8_48_LP_DATA_labelID 133 +#define BT_UL_8_48_HP_DATA_labelID 134 +#define BT_UL_16_48_LP_DATA_labelID 135 +#define BT_UL_16_48_HP_DATA_labelID 136 +#define BT_DL_48_8_LP_DATA_labelID 137 +#define BT_DL_48_8_HP_DATA_labelID 138 +#define BT_DL_48_16_LP_DATA_labelID 139 +#define BT_DL_48_16_HP_DATA_labelID 140 +#define ECHO_REF_48_16_LP_DATA_labelID 141 +#define ECHO_REF_48_16_HP_DATA_labelID 142 +#define ECHO_REF_48_8_LP_DATA_labelID 143 +#define ECHO_REF_48_8_HP_DATA_labelID 144 +#define ECHO_REF_DEC_labelID 145 +#define VX_UL_8_TEMP_labelID 146 +#define VX_UL_16_TEMP_labelID 147 +#define UP_DOWN_8_48_labelID 148 +#define UP_DOWN_16_48_labelID 149 +#define SRC_6_LP_48k_labelID 150 +#define SRC_6_HP_labelID 151 +#define SRC_3_LP_48k_labelID 152 +#define SRC_3_HP_labelID 153 +#define EARP_48_96_LP_DATA_labelID 154 +#define SRC_48_96_LP_labelID 155 +#define IHF_48_96_LP_DATA_labelID 156 +#define EQ_VX_UL_16K_labelID 157 +#define pAPS_iir1_p23_labelID 158 +#define pAPS_iir1_p45_labelID 159 +#define APS_IIR_Regs_labelID 160 +#define pAPS_core_DL1_p1_labelID 161 +#define pAPS_core_DL1_p23_labelID 162 +#define pAPS_core_DL1_p45_labelID 163 +#define pAPS_core_DL1_r_labelID 164 +#define pAPS_DL2L_core_r_labelID 165 +#define pAPS_DL2R_core_r_labelID 166 +#define pAPS_COIL_core_DL1_p1_labelID 167 +#define pAPS_COIL_core_DL1_p23_labelID 168 +#define pAPS_COIL_core_DL1_p45_labelID 169 +#define pAPS_COIL_core_DL1_r_labelID 170 +#define DL2_L_APS_IIR_p23_labelID 171 +#define DL2_R_APS_IIR_p23_labelID 172 +#define DL2_L_APS_IIR_p45_labelID 173 +#define DL2_R_APS_IIR_p45_labelID 174 +#define DL2_L_APS_CORE_p1_labelID 175 +#define DL2_L_APS_CORE_p23_labelID 176 +#define DL2_L_APS_CORE_p45_labelID 177 +#define DL2_R_APS_CORE_p1_labelID 178 +#define DL2_R_APS_CORE_p23_labelID 179 +#define DL2_R_APS_CORE_p45_labelID 180 +#define DL2_L_APS_COIL_CORE_p1_labelID 181 +#define DL2_L_APS_COIL_CORE_p23_labelID 182 +#define DL2_L_APS_COIL_CORE_p45_labelID 183 +#define pAPS_COIL_DL2L_core_r_labelID 184 +#define DL2_R_APS_COIL_CORE_p1_labelID 185 +#define DL2_R_APS_COIL_CORE_p23_labelID 186 +#define DL2_R_APS_COIL_CORE_p45_labelID 187 +#define pAPS_COIL_DL2R_core_r_labelID 188 +#define DL1_APS_labelID 189 +#define DL2_L_APS_labelID 190 +#define DL2_R_APS_labelID 191 +#define pEANC_p0_labelID 192 +#define pEANC_p1_labelID 193 +#define pEANC_p23_labelID 194 +#define pEANC_p45_labelID 195 +#define pEANC_reg1_labelID 196 +#define pEANC_reg2_labelID 197 +#define pEANC_reg3_labelID 198 +#define pEANC_r_labelID 199 +#define DL1_APS_EQ_p23_labelID 200 +#define DL1_APS_EQ_p45_labelID 201 +#define DL2_APS_EQ_p23_labelID 202 +#define DL2_APS_EQ_p45_labelID 203 +#define pDC_EANC_p23_labelID 204 +#define pDC_EANC_r_labelID 205 +#define pVIBRA1_p0_labelID 206 +#define pVIBRA1_p1_labelID 207 +#define pVIBRA1_p23_labelID 208 +#define pVIBRA1_p45_labelID 209 +#define pVibra1_pR1_labelID 210 +#define pVibra1_pR2_labelID 211 +#define pVibra1_pR3_labelID 212 +#define pVIBRA1_r_labelID 213 +#define pVIBRA2_p0_labelID 214 +#define pVIBRA2_p1_labelID 215 +#define pVIBRA2_p23_labelID 216 +#define pVIBRA2_p45_labelID 217 +#define pCtrl_p67_labelID 218 +#define pVIBRA2_r_labelID 219 +#define VIBRA_labelID 220 +#define PING_labelID 221 +#define PING_Regs_labelID 222 +#define UP_48_96_LP_COEFS_labelID 223 +#define AMIC_96_48_data_labelID 224 +#define DOWN_96_48_Coefs_labelID 225 +#define DOWN_96_48_Regs_labelID 226 +#define DMIC0_96_48_data_labelID 227 +#define DMIC1_96_48_data_labelID 228 +#define DMIC2_96_48_data_labelID 229 +#define EANC_FBK_96_48_data_labelID 230 +#define pDC_EANC_r2_labelID 231 +#define SIO_DMIC_labelID 232 +#define SIO_PDM_UL_labelID 233 +#define SIO_BT_VX_UL_labelID 234 +#define SIO_MM_UL_labelID 235 +#define SIO_MM_UL2_labelID 236 +#define SIO_VX_UL_labelID 237 +#define SIO_MM_DL_labelID 238 +#define SIO_VX_DL_labelID 239 +#define SIO_TONES_DL_labelID 240 +#define SIO_VIB_DL_labelID 241 +#define SIO_BT_VX_DL_labelID 242 +#define SIO_PDM_DL_labelID 243 +#define SIO_MM_EXT_OUT_labelID 244 +#define SIO_MM_EXT_IN_labelID 245 +#define SIO_TDM_OUT_labelID 246 +#define SIO_TDM_IN_labelID 247 +#define DMIC_ATC_PTR_labelID 248 +#define MCPDM_UL_ATC_PTR_labelID 249 +#define BT_VX_UL_ATC_PTR_labelID 250 +#define MM_UL_ATC_PTR_labelID 251 +#define MM_UL2_ATC_PTR_labelID 252 +#define VX_UL_ATC_PTR_labelID 253 +#define MM_DL_ATC_PTR_labelID 254 +#define VX_DL_ATC_PTR_labelID 255 +#define TONES_DL_ATC_PTR_labelID 256 +#define VIB_DL_ATC_PTR_labelID 257 +#define BT_VX_DL_ATC_PTR_labelID 258 +#define PDM_DL_ATC_PTR_labelID 259 +#define MM_EXT_OUT_ATC_PTR_labelID 260 +#define MM_EXT_IN_ATC_PTR_labelID 261 +#define TDM_OUT_ATC_PTR_labelID 262 +#define TDM_IN_ATC_PTR_labelID 263 +#define MCU_IRQ_FIFO_ptr_labelID 264 +#define DEBUG_IRQ_FIFO_reg_labelID 265 +#define UP_DOWN_48_96_labelID 266 +#define OSR96_2_labelID 267 +#define DEBUG_GAINS_labelID 268 +#define DBG_8K_PATTERN_labelID 269 +#define DBG_16K_PATTERN_labelID 270 +#define DBG_24K_PATTERN_labelID 271 +#define DBG_48K_PATTERN_labelID 272 +#define DBG_96K_PATTERN_labelID 273 +#define UL_VX_UL_48_8K_labelID 274 +#define UL_VX_UL_48_16K_labelID 275 +#define BT_DL_labelID 276 +#define BT_UL_labelID 277 +#define BT_DL_8k_labelID 278 +#define BT_DL_16k_labelID 279 +#define BT_UL_8k_labelID 280 +#define BT_UL_16k_labelID 281 +#define MM_EXT_IN_labelID 282 +#define MM_EXT_IN_L_labelID 283 +#define MM_EXT_IN_R_labelID 284 +#define ECHO_REF_48_16_WRAP_labelID 285 +#define ECHO_REF_48_8_WRAP_labelID 286 +#define BT_UL_16_48_WRAP_labelID 287 +#define BT_UL_8_48_WRAP_labelID 288 +#define BT_DL_48_16_WRAP_labelID 289 +#define BT_DL_48_8_WRAP_labelID 290 +#define VX_DL_16_48_WRAP_labelID 291 +#define VX_DL_8_48_WRAP_labelID 292 +#define VX_UL_48_16_WRAP_labelID 293 +#define VX_UL_48_8_WRAP_labelID 294 +#define APS_DL1_IRQs_WRAP_labelID 295 +#define APS_DL2_L_IRQs_WRAP_labelID 296 +#define APS_DL2_R_IRQs_WRAP_labelID 297 +#define ATC_NULL_BUFFER_labelID 298 +#define MEM_INIT_hal_mem_labelID 299 +#define MEM_INIT_write_mem_labelID 300 +#define MEM_INIT_regs_labelID 301 +#define GAIN_0DB_labelID 302 -#endif /* _ABE_INITXXXX_LABELS_H_ */ +#endif /* _ABE_INITXXXX_LABELS_H_ */ diff --git a/sound/soc/omap/abe/abe_irq.c b/sound/soc/omap/abe/abe_irq.c index 61bd1263c0da..1a8efa599e52 100644 --- a/sound/soc/omap/abe/abe_irq.c +++ b/sound/soc/omap/abe/abe_irq.c @@ -1,11 +1,22 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" @@ -19,53 +30,38 @@ * - Activity Tracing */ -/* - * ABE_IRQ_PING_PONG - * Parameter : - * No parameter +/** + * abe_irq_ping_pong * - * Operations : * Call the respective subroutine depending on the IRQ FIFO content: * APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], loopCounter to [15:0] * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0] * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0] - * Check for ping-pong subroutines (low-power players) - * - * Return value : - * None. */ -void abe_irq_ping_pong(void) +void abe_irq_ping_pong (void) { - abe_call_subroutine(abe_irq_pingpong_player_id, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER); + abe_call_subroutine (abe_irq_pingpong_player_id, NOPARAMETER, NOPARAMETER, + NOPARAMETER, NOPARAMETER); } -/* - * ABE_IRQ_CHECK_FOR_SEQUENCES - * Parameter : - * No parameter +/** + * abe_irq_check_for_sequences +* @i: sequence ID * - * Operations : * check the active sequence list * - * Return value : - * None. */ -void abe_irq_check_for_sequences(abe_uint32 i) +void abe_irq_check_for_sequences (u32 i) { } -/* - * ABE_IRQ_APS - * Parameter : - * No parameter +/** + * abe_irq_aps * - * Operations : * call the application subroutines that updates the acoustics protection filters - * - * Return value : - * None. */ -void abe_irq_aps(abe_uint32 aps_info) +void abe_irq_aps (u32 aps_info) { - abe_call_subroutine(abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER, NOPARAMETER, NOPARAMETER); + abe_call_subroutine (abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER, + NOPARAMETER, NOPARAMETER); } diff --git a/sound/soc/omap/abe/abe_lib.c b/sound/soc/omap/abe/abe_lib.c index f27b1485c548..dde165abeac1 100644 --- a/sound/soc/omap/abe/abe_lib.c +++ b/sound/soc/omap/abe/abe_lib.c @@ -1,22 +1,27 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ -#include "abe_main.h" -#include <linux/io.h> - -void __iomem *io_base; -void abe_init_mem(void __iomem *_io_base) -{ - io_base = _io_base; -} +#include "abe_main.h" +#include "abe_ext.h" #define ABE_PMEM_BASE_OFFSET_MPU 0xe0000 #define ABE_CMEM_BASE_OFFSET_MPU 0xa0000 @@ -24,416 +29,159 @@ void abe_init_mem(void __iomem *_io_base) #define ABE_DMEM_BASE_OFFSET_MPU 0x80000 #define ABE_ATC_BASE_OFFSET_MPU 0xf1000 -#if 0 -/* - * ABE_TRANSLATE_TO_XMEM_FORMAT +void __iomem *io_base; + +/** + * abe_init_mem - Allocate Kernel space memory map for ABE * - * Parameter : - * Operations : - * translates a floating point data to the cmem/smem/dmem data format - * Return value : - * None. + * Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM */ -void abe_translate_to_xmem_format(abe_int32 memory_bank, abe_float fc, abe_uint32 *c) +void abe_init_mem(void __iomem *_io_base) { - abe_int32 l; - abe_float afc; - - l = 0; - afc = absolute(fc); + io_base = _io_base; +} - switch (memory_bank) { - case ABE_CMEM: - if (afc >= 1.0 && afc < 32.0) { - /* ALU post shifter +6 */ - l = (abe_int32)(fc * (1 << 16)); - l = (l << 2) + 2; - } else if (afc >= 0.5 && afc < 1.0) { - /* ALU post shifter +1 */ - l = (abe_int32)(fc * (1 << 21)); - l = (l << 2) + 1; - } else if (afc >= 0.25 && afc < 0.5) { - /* ALU post shifter 0 */ - l = (abe_int32)(fc * (1 << 22)); - l = (l << 2) + 0; - } else if (afc < 0.25) { - /* ALU post shifter -6 */ - l = (abe_int32)(fc * (1 << 28)); - l = (l << 2) + 3; - } - break; - case ABE_SMEM: - /* Q23 data format */ - l = (abe_int32)(fc * (1 << 23)); - break; - case ABE_DMEM: - /* Q31 data format (1<<31)=0 */ - l = (abe_int32)(fc * 2* (1 << 30)); - break; - default: /* ABE_PMEM */ - /* Q31 data format */ - l = (abe_int32)(2 * fc * 2* (1 << 30)); - break; - } +#if PC_SIMULATION +#include <stdlib.h> +#endif - *c = l; -} +/** +* abe_fprintf +* @line: character line to be printed +* +* Print ABE debug messages. +*/ -/* - * ABE_TRANSLATE_GAIN_FORMAT - * - * Parameter : - * Operations : - * f: original format name for gain or frequency. - * 1=linear ABE => decibels - * 2=decibels => linear ABE firmware format +/** + * abe_read_feature_from_port + * @x: d * - * lin = power(2, decibel/602); lin = [0.0001 .. 30.0] - * decibel = 6.02 * log2(lin), decibel = [-70 .. +30] + * TBD * - * g1: pointer to the original data - * g2: pointer to the translated gain data - * - * Return value : - * None. */ -void abe_translate_gain_format(abe_uint32 f, abe_float g1, abe_float *g2) +void abe_read_feature_from_port (u32 x) { - abe_float g, frac_part, gg1, gg2; - abe_int32 int_part, i; - - #define C_20LOG2 ((abe_float)6.020599913) - - gg1 = (g1); - int_part = 0; - frac_part = gg2 = 0; - - switch (f) { - case DECIBELS_TO_LINABE: - g = gg1 / C_20LOG2; - int_part = (abe_int32) g; - frac_part = g - int_part; - - gg2 = abe_power_of_two(frac_part); - - if (int_part > 0) - gg2 = gg2 * (1 << int_part); - else - gg2 = gg2 / (1 << (-int_part)); - - break; - case LINABE_TO_DECIBELS: - if (gg1 == 1.0) { - gg2 = 0.0; - return; - } - - /* find the power of 2 by iteration */ - if (gg1 > 1.0) { - for (i = 0; i < 63; i++) { - if ((1 << i) > gg1) { - int_part = (i-1); - frac_part = gg1 / (1 << int_part); - break; - } - } - gg2 = C_20LOG2 * (int_part + abe_log_of_two(frac_part)); - } else { - for (i = 0; i < 63; i++) { - if (((1 << i) * gg1) > 1) { - int_part = i; - frac_part = gg1 * (1 << int_part); - break; - } - } - /* compute the dB using polynomial - * interpolation in the [1..2] range - */ - gg2 = C_20LOG2 * (((-1)*int_part) + abe_log_of_two(frac_part));} - break; - } - - *g2 = gg2; - } +} -/* - * ABE_TRANSLATE_RAMP_FORMAT +/** + * abe_write_feature_to_port + * @x: d * - * Parameter : - * Operations : - * f: original format name for gain or frequency. - * 1=ABE IIR coef => microseconds - * 2=microseconds => ABE IIR coef + * TBD * - * g1: pointer to the original data - * g2: pointer to the translated gain data - * - * Return value : - * None. */ -void abe_translate_ramp_format(abe_float ramp, abe_float *ramp_iir1) +void abe_write_feature_to_port (u32 x) { - *ramp_iir1 = 0.125; } -/* - * ABE_TRANSLATE_EQU_FORMAT - * - * Parameter : - * Operations : - * Translate +/** + * abe_read_fifo + * @x: d * - * Return value : - * None. + * TBD */ -void abe_translate_equ_format(abe_equ_t *p, abe_float *iir, abe_uint32 n) +void abe_read_fifo (u32 x) { -#if 0 - switch (p->type -typedef struct { - abe_iir_t equ_param1; /* type of filter */ - abe_uint32 equ_param2; /* filter length */ - union { /* parameters are the direct and recursive coefficients in */ - abe_int32 type1 [NBEQ1]; /* Q6.26 integer fixed-point format. */ - struct { - abe_int32 freq [NBEQ2]; /* parameters are the frequency (type "freq") and Q factors */ - abe_int32 gain [NBEQ2]; /* (type "gain") of each band. */ - } type2; - } coef; - abe_int32 equ_param3; - } abe_equ_t; - - Fs = 48000; - f0 = 19000; - Q = sqrt(0.5) - dBgain = -40 - - - A = sqrt (power (10, dBgain/20)); - w0 = 2*pi*f0/Fs - alpha = sin(w0) / (2*Q); - - %PeakingEQ ========================================== - b_peak = print_ABE_data ([1+alpha*A -2*cos(w0) 1-alpha*A],3); - a_peak = print_ABE_data ([1+alpha/A -2*cos(w0) 1-alpha/A],3); - -#endif } -#endif -/* - * ABE_FPRINTF +/** + * abe_write_fifo + * @mem_bank: currently only ABE_DMEM supported + * @addr: FIFO descriptor address ( descriptor fields : READ ptr, WRITE ptr, + * FIFO START_ADDR, FIFO END_ADDR) + * @data: data to write to FIFO + * @number: number of 32-bit words to write to DMEM FIFO * - * Parameter : - * character line to be printed - * - * Operations : - * - * Return value : - * None. + * write DMEM FIFO and update FIFO descriptor, it is assumed that FIFO descriptor + * is located in DMEM */ -#if 0 -void abe_fprintf(char *line) +void abe_write_fifo (u32 memory_bank, u32 descr_addr, u32 *data, u32 nb_data32) { - switch (abe_dbg_output) { - case NO_OUTPUT: - break; - case TERMINAL_OUTPUT: - break; - case LINE_OUTPUT: - break; - case DEBUG_TRACE_OUTPUT: + u32 fifo_addr[4]; + u32 i; + + /* read FIFO descriptor from DMEM */ + abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, descr_addr, + &fifo_addr[0], 4*sizeof(u32)); + + /* WRITE ptr < FIFO start address */ + if ( fifo_addr[1] < fifo_addr[2]) + abe_dbg_error_log (ABE_FW_FIFO_WRITE_PTR_ERR); + + /* WRITE ptr > FIFO end address */ + if ( fifo_addr[1] > fifo_addr[3]) + abe_dbg_error_log (ABE_FW_FIFO_WRITE_PTR_ERR); + + switch ( memory_bank ) { + case ABE_DMEM : + for (i=0; i<nb_data32; i++) { + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, + (s32) fifo_addr[1], (u32*) (data+i), 4); + + /* increment WRITE pointer */ + fifo_addr[1] = fifo_addr[1] + 4; + if (fifo_addr[1] > fifo_addr[3]) + fifo_addr[1] = fifo_addr[2]; + if (fifo_addr[1] == fifo_addr[0]) + abe_dbg_error_log (ABE_FW_FIFO_WRITE_PTR_ERR); + } + /* update WRITE pointer in DMEM */ + abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, descr_addr+ + sizeof(u32), &fifo_addr[1], 4); break; - default: + default : + /* printf("currently only DMEM FIFO write supported ERROR\n"); */ break; } -} -#endif - -/* - * ABE_READ_FEATURE_FROM_PORT - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : - * - */ -void abe_read_feature_from_port(abe_uint32 x) -{ - just_to_avoid_the_many_warnings = x; -} - -/* - * ABE_WRITE_FEATURE_TO_PORT - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : - * - */ -void abe_write_feature_to_port(abe_uint32 x) -{ - just_to_avoid_the_many_warnings = x; -} -/* - * ABE_READ_FIFO - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : - * - */ -void abe_read_fifo(abe_uint32 x) -{ - just_to_avoid_the_many_warnings = x; -} -/* - * ABE_WRITE_FIFO - * - * Parameter : - * x : d - * - * Operations : - * - * - * Return value : - * - */ -void abe_write_fifo(abe_uint32 x) -{ - just_to_avoid_the_many_warnings = x; } -/* - * ABE_BLOCK_COPY +/** + * abe_block_copy + * @direction: direction of the data move (Read/Write) + * @memory_bamk:memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO + * @address: address of the memory copy (byte addressing) + * @data: pointer to the data to transfer + * @nb_bytes: number of data to move * - * Parameter : - * direction of the data move (Read/Write) - * memory bank among PMEM, DMEM, CMEM, SMEM, ATC/IO - * address of the memory copy (byte addressing) - * long pointer to the data - * number of data to move - * - * Operations : - * block data move - * - * Return value : - * none + * Memory transfer to/from ABE to MPU */ -void abe_block_copy(abe_int32 direction, abe_int32 memory_bank, abe_int32 address, abe_uint32 *data, abe_uint32 nb_bytes) +void abe_block_copy (u32 direction, u32 memory_bank, u32 address, + u32 *data, u32 nb_bytes) { -#if PC_SIMULATION - abe_uint32 *smem_tmp, smem_offset, smem_base, nb_words48; - - if (direction == COPY_FROM_HOST_TO_ABE) { - switch (memory_bank) { - case ABE_PMEM: - target_server_write_pmem(address/4, data, nb_bytes/4); - break; - case ABE_CMEM: - target_server_write_cmem(address/4, data, nb_bytes/4); - break; - case ABE_ATC: - target_server_write_atc(address/4, data, nb_bytes/4); - break; - case ABE_SMEM: - nb_words48 = (nb_bytes +7)>>3; - /* temporary buffer manages the OCP access to 32bits boundaries */ - smem_tmp = malloc(nb_bytes + 64); - /* address is on SMEM 48bits lines boundary */ - smem_base = address - (address & 7); - target_server_read_smem(smem_base/8, smem_tmp, 2 + nb_words48); - smem_offset = address & 7; - memcpy(&(smem_tmp[smem_offset>>2]), data, nb_bytes); - target_server_write_smem(smem_base/8, smem_tmp, 2 + nb_words48); - free(smem_tmp); - break; - case ABE_DMEM: - target_server_write_dmem(address, data, nb_bytes); - break; - default: - abe_dbg_param |= ERR_LIB; - abe_dbg_error_log(ABE_BLOCK_COPY_ERR); - break; - } - } else { - switch (memory_bank) { - case ABE_PMEM: - target_server_read_pmem(address/4, data, nb_bytes/4); - break; - case ABE_CMEM: - target_server_read_cmem(address/4, data, nb_bytes/4); - break; - case ABE_ATC: - target_server_read_atc(address/4, data, nb_bytes/4); - break; - case ABE_SMEM: - nb_words48 = (nb_bytes +7)>>3; - /* temporary buffer manages the OCP access to 32bits boundaries */ - smem_tmp = malloc(nb_bytes + 64); - /* address is on SMEM 48bits lines boundary */ - smem_base = address - (address & 7); - target_server_read_smem(smem_base/8, smem_tmp, 2 + nb_words48); - smem_offset = address & 7; - memcpy(data, &(smem_tmp[smem_offset>>2]), nb_bytes); - free(smem_tmp); - break; - case ABE_DMEM: - target_server_read_dmem(address, data, nb_bytes); - break; - default: - abe_dbg_param |= ERR_LIB; - abe_dbg_error_log(ABE_BLOCK_COPY_ERR); - break; - } - } -#else - abe_uint32 i; - abe_uint32 base_address = 0, *src_ptr, *dst_ptr, n; + u32 i; + u32 base_address = 0, *src_ptr, *dst_ptr, n; switch (memory_bank) { case ABE_PMEM: - base_address = (abe_uint32) io_base + ABE_PMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_PMEM_BASE_OFFSET_MPU; break; case ABE_CMEM: - base_address = (abe_uint32) io_base + ABE_CMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_CMEM_BASE_OFFSET_MPU; break; case ABE_SMEM: - base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; break; case ABE_DMEM: - base_address = (abe_uint32) io_base + ABE_DMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_DMEM_BASE_OFFSET_MPU; break; case ABE_ATC: - base_address = (abe_uint32) io_base + ABE_ATC_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_ATC_BASE_OFFSET_MPU; break; default: - base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; abe_dbg_param |= ERR_LIB; abe_dbg_error_log(ABE_BLOCK_COPY_ERR); break; } if (direction == COPY_FROM_HOST_TO_ABE) { - dst_ptr = (abe_uint32 *)(base_address + address); - src_ptr = (abe_uint32 *)data; + dst_ptr = (u32 *)(base_address + address); + src_ptr = (u32 *)data; } else { - dst_ptr = (abe_uint32 *)data; - src_ptr = (abe_uint32 *)(base_address + address); + dst_ptr = (u32 *)data; + src_ptr = (u32 *)(base_address + address); } n = (nb_bytes/4); @@ -441,130 +189,125 @@ void abe_block_copy(abe_int32 direction, abe_int32 memory_bank, abe_int32 addres for (i = 0; i < n; i++) *dst_ptr++ = *src_ptr++; -#endif } + + +#if 0 /* - * ABE_RESET_MEM + * ABE_SINGLE_COPY * - * Parameter : - * memory bank among DMEM, SMEM - * address of the memory copy (byte addressing) - * number of data to move + * Parameter : + * address of the memory copy (byte addressing) + * long pointer to the data + * number of data to move * - * Operations : - * reset memory + * Operations : + * 32bits data move * - * Return value : - * none + * Return value : + * none */ -void abe_reset_mem(abe_int32 memory_bank, abe_int32 address, abe_uint32 nb_bytes) -{ -#if PC_SIMULATION - extern void target_server_write_smem(abe_uint32 address_48bits, abe_uint32 *data, abe_uint32 nb_words_48bits); - extern void target_server_write_dmem(abe_uint32 address_byte, abe_uint32 *data, abe_uint32 nb_byte); - - abe_uint32 *smem_tmp, *data, smem_offset, smem_base, nb_words48; +void abe_write_dmem (u32 address, u32 *data, u32 nb_bytes) +void abe_read_dmem (u32 address, u32 *data, u32 nb_bytes) +void abe_write_cmem (u32 address, u32 *data, u32 nb_bytes) +void abe_read_cmem (u32 address, u32 *data, u32 nb_bytes) +void abe_write_smem (u32 address, u32 *data, u32 nb_bytes) +void abe_read_smem (u32 address, u32 *data, u32 nb_bytes) +void abe_write_atc (u32 address, u32 *data, u32 nb_bytes) +void abe_read_atc (u32 address, u32 *data, u32 nb_bytes) +#endif - data = calloc(nb_bytes, 1); - switch (memory_bank) { - case ABE_SMEM: - nb_words48 = (nb_bytes +7)>>3; - /* temporary buffer manages the OCP access to 32bits boundaries */ - smem_tmp = malloc (nb_bytes + 64); - /* address is on SMEM 48bits lines boundary */ - smem_base = address - (address & 7); - target_server_read_smem (smem_base/8, smem_tmp, 2 + nb_words48); - smem_offset = address & 7; - memcpy (&(smem_tmp[smem_offset>>2]), data, nb_bytes); - target_server_write_smem (smem_base/8, smem_tmp, 2 + nb_words48); - free (smem_tmp); - break; - case ABE_DMEM: - target_server_write_dmem(address, data, nb_bytes); - break; - default: - abe_dbg_param |= ERR_LIB; - abe_dbg_error_log(ABE_BLOCK_COPY_ERR); - } - free(data); -#else - abe_uint32 i; - abe_uint32 *dst_ptr, n; - abe_uint32 base_address = 0; +/** + * abe_reset_mem + * + * @memory_bank: memory bank among DMEM, SMEM + * @address: address of the memory copy (byte addressing) + * @nb_bytes: number of data to move + * + * Reset ABE memory + */ +void abe_reset_mem (u32 memory_bank, u32 address, u32 nb_bytes) +{ + u32 i; + u32 *dst_ptr, n; + u32 base_address = 0; switch (memory_bank) { case ABE_SMEM: - base_address = (abe_uint32) io_base + ABE_SMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU; break; case ABE_DMEM: - base_address = (abe_uint32) io_base + ABE_DMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_DMEM_BASE_OFFSET_MPU; break; case ABE_CMEM: - base_address = (abe_uint32) io_base + ABE_CMEM_BASE_OFFSET_MPU; + base_address = (u32) io_base + ABE_CMEM_BASE_OFFSET_MPU; break; } - dst_ptr = (abe_uint32 *) (base_address + address); + dst_ptr = (u32 *) (base_address + address); n = (nb_bytes/4); for (i = 0; i < n; i++) *dst_ptr++ = 0; -#endif } -/* - * ABE_MONITORING - * - * Parameter : +/** + * abe_monitoring * - * Operations : - * checks the internal status of ABE and HAL - * - * Return value : - * Call Backs on Errors + * checks the internal status of ABE and HAL */ -void abe_monitoring(void) +void abe_monitoring (void) { abe_dbg_param = 0; } -/* - * ABE_FORMAT_SWITCH - * - * Parameter : +/** + * abe_format_switch + * @f: port format + * @iter: port iteration + * @mulfac: multiplication factor * - * Operations : - * translates the sampling and data length to ITER number for the DMA - * and the multiplier factor to apply during data move with DMEM + * translates the sampling and data length to ITER number for the DMA + * and the multiplier factor to apply during data move with DMEM * - * Return value : - * Call Backs on Errors */ -void abe_format_switch(abe_data_format_t *f, abe_uint32 *iter, abe_uint32 *mulfac) +void abe_format_switch (abe_data_format_t *f, u32 *iter, u32 *mulfac) { - abe_uint32 n_freq; + u32 n_freq; #if FW_SCHED_LOOP_FREQ==4000 switch (f->f) { - /* nb of samples processed by scheduling loop */ - case 8000: n_freq = 2; break; - case 16000: n_freq = 4; break; - case 24000: n_freq = 6; break; - case 44100: n_freq = 12; break; - case 96000: n_freq = 24; break; - default /*case 48000*/: n_freq = 12; break; + + /* nb of samples processed by scheduling loop */ + case 8000: + n_freq = 2; + break; + case 16000: + n_freq = 4; + break; + case 24000: + n_freq = 6; + break; + case 44100: + n_freq = 12; + break; + case 96000: + n_freq = 24; + break; + default /*case 48000*/: + n_freq = 12; + break; } #else - n_freq = 0; /* erroneous cases */ + /* erroneous cases */ + n_freq = 0; #endif switch (f->samp_format) { case MONO_MSB: case MONO_RSHIFTED_16: - *mulfac = 1; - break; case STEREO_16_16: *mulfac = 1; break; @@ -597,64 +340,50 @@ void abe_format_switch(abe_data_format_t *f, abe_uint32 *iter, abe_uint32 *mulfa *mulfac = 1; break; } - *iter = (n_freq * (*mulfac)); } -/* - * ABE_DMA_PORT_ITERATION +/** + * abe_dma_port_iteration + * @f: port format * - * Parameter : - * - * Operations : - * translates the sampling and data length to ITER number for the DMA - * - * Return value : - * Call Backs on Errors + * translates the sampling and data length to ITER number for the DMA */ -abe_uint32 abe_dma_port_iteration(abe_data_format_t *f) +u32 abe_dma_port_iteration (abe_data_format_t *f) { - abe_uint32 iter, mulfac; + u32 iter, mulfac; - abe_format_switch(f, &iter, &mulfac); + abe_format_switch (f, &iter, &mulfac); return iter; } -/* - * ABE_DMA_PORT_ITER_FACTOR +/** + * abe_dma_port_iter_factor + * @f: port format * - * Parameter : - * - * Operations : - * returns the multiplier factor to apply during data move with DMEM - * - * Return value : - * Call Backs on Errors + * returns the multiplier factor to apply during data move with DMEM */ -abe_uint32 abe_dma_port_iter_factor(abe_data_format_t *f) +u32 abe_dma_port_iter_factor (abe_data_format_t *f) { - abe_uint32 iter, mulfac; + u32 iter, mulfac; - abe_format_switch(f, &iter, &mulfac); + abe_format_switch (f, &iter, &mulfac); return mulfac; } -/* - * ABE_DMA_PORT_COPY_SUBROUTINE_ID +/** + * abe_dma_port_copy_subroutine_id * - * Parameter : + * @port_id: ABE port ID * - * Operations : - * returns the index of the function doing the copy in I/O tasks - * - * Return value : - * Call Backs on Errors + * returns the index of the function doing the copy in I/O tasks */ -abe_uint32 abe_dma_port_copy_subroutine_id(abe_port_id port_id) +u32 abe_dma_port_copy_subroutine_id (u32 port_id) { - abe_uint32 sub_id; + u32 sub_id; + if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) { switch (abe_port[port_id].format.samp_format) { case MONO_MSB: diff --git a/sound/soc/omap/abe/abe_lib.h b/sound/soc/omap/abe/abe_lib.h index e7e6b6cee759..8dc219e69229 100644 --- a/sound/soc/omap/abe/abe_lib.h +++ b/sound/soc/omap/abe/abe_lib.h @@ -1,33 +1,36 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== - */ - -#ifdef __cplusplus -extern "C" { -#endif - -void abe_init_mem(void __iomem *io_base); -void abe_translate_gain_format(abe_uint32 f, abe_float g1, abe_float *g2); -void abe_translate_ramp_format(abe_float g1, abe_float *g2); - -/* - * ABE_FPRINTF + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> * - * Parameter : - * character line to be printed + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. * - * Operations : + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. * - * Return value : - * None. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ -void abe_fprintf(char *line); +void abe_init_mem(void __iomem *io_base); +/** + * abe_fprintf + * + * Parameter : + * character line to be printed + * + * Operations : + * + * Return value : + * None. + */ +void abe_fprintf (char *line); /* * ABE_READ_FEATURE_FROM_PORT @@ -41,7 +44,7 @@ void abe_fprintf(char *line); * Return value : * */ -void abe_read_feature_from_port(abe_uint32 x); +void abe_read_feature_from_port (u32 x); /* * ABE_WRITE_FEATURE_TO_PORT @@ -55,7 +58,7 @@ void abe_read_feature_from_port(abe_uint32 x); * Return value : * */ -void abe_write_feature_to_port(abe_uint32 x); +void abe_write_feature_to_port (u32 x); /* * ABE_READ_FIFO @@ -69,21 +72,27 @@ void abe_write_feature_to_port(abe_uint32 x); * Return value : * */ -void abe_read_fifo(abe_uint32 x); +void abe_read_fifo (u32 x); /* * ABE_WRITE_FIFO * * Parameter : - * x : d + * mem_bank : currently only ABE_DMEM supported + * addr : FIFO descriptor address ( descriptor fields : READ ptr, + * WRITE ptr, FIFO START_ADDR, FIFO END_ADDR) + * data to write to FIFO + * number of 32-bit words to write to DMEM FIFO * * Operations : - * + * write DMEM FIFO and update FIFO descriptor, it is assumed that FIFO + * descriptor is located in DMEM * * Return value : - * + * none */ -void abe_write_fifo(abe_uint32 x); +void abe_write_fifo (u32 mem_bank, u32 addr, u32 *data, u32 nb_data32); + /* * ABE_BLOCK_COPY @@ -101,24 +110,23 @@ void abe_write_fifo(abe_uint32 x); * Return value : * none */ -void abe_block_copy(abe_int32 direction, abe_int32 memory_bank, abe_int32 address, abe_uint32 *data, abe_uint32 nb); +void abe_block_copy (u32 direction, u32 memory_bank, u32 address, u32 *data, + u32 nb); /* - * ABE_RESET_MEM + * ABE_RESET_MEM * - *Parameter: - * memory bank among DMEM, SMEM - * address of the memory copy (byte addressing) - * number of data to move + * Parameter : + * memory bank among DMEM, SMEM + * address of the memory copy (byte addressing) + * number of data to move * - * Operations: - * reset memory + * Operations : + * reset memory * - * Return value: - * none + * Return value : + * none */ -void abe_reset_mem(abe_int32 memory_bank, abe_int32 address, abe_uint32 nb_bytes); +void abe_reset_mem (u32 memory_bank, u32 address, u32 nb_bytes); + -#ifdef __cplusplus -} -#endif diff --git a/sound/soc/omap/abe/abe_main.c b/sound/soc/omap/abe/abe_main.c index 3423fe62e50a..51c5997b360f 100644 --- a/sound/soc/omap/abe/abe_main.c +++ b/sound/soc/omap/abe/abe_main.c @@ -1,26 +1,23 @@ -/* ============================================================================= -* Texas Instruments OMAP(TM) Platform Software -* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. -* -* Use of this software is controlled by the terms and conditions found -* in the license agreement under which this software has been supplied. -* =========================================================================== */ -/** - * @file ABE_MAIN.C +/* + * ALSA SoC OMAP ABE driver + * + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. * - * 'ABEMAIN.C' dummy main of the HAL + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * @path - * @rev 01.00 */ -/* ---------------------------------------------------------------------------- -*! -*! Revision History -*! =================================== -*! 27-Nov-2008 Original (LLF) -*! 05-Jun-2009 V05 release -* =========================================================================== */ - #if !PC_SIMULATION @@ -31,69 +28,250 @@ void main (void) { - abe_dma_t dma_sink, dma_source; - abe_data_format_t format; - abe_uint32 base_address; + abe_dma_t dma_sink, dma_source; + abe_data_format_t format; + abe_uint32 base_address; - abe_auto_check_data_format_translation(); - abe_reset_hal(); - abe_check_opp(); - abe_check_dma(); + abe_auto_check_data_format_translation (); + abe_reset_hal (); + abe_check_opp (); + abe_check_dma (); - /* - To be added here : - Device driver initialization: - McPDM_DL : threshold=1, 6 slots activated - DMIC : threshold=1, 6 microphones activated - McPDM_UL : threshold=1, two microphones activated - */ + /* + To be added here : + Device driver initialization: + McPDM_DL : threshold=1, 6 slots activated + DMIC : threshold=1, 6 microphones activated + McPDM_UL : threshold=1, two microphones activated + */ - /* MM_DL INIT - connect a DMA channel to MM_DL port (ATC FIFO) + /* MM_DL INIT + connect a DMA channel to MM_DL port (ATC FIFO) format.f = 48000; format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); + abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - connect a Ping-Pong SDMA protocol to MM_DL port with Ping-Pong 576 stereo samples + connect a Ping-Pong SDMA protocol to MM_DL port with Ping-Pong 576 stereo samples format.f = 48000; format.samp_format = STEREO_MSB; - abe_connect_dmareq_ping_pong_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, (576 * 4), &dma_sink); + abe_connect_dmareq_ping_pong_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, (576 * 4), &dma_sink); - connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate - */ - abe_add_subroutine(&abe_irq_pingpong_player_id, - (abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0 ); - format.f = 48000; - format.samp_format = STEREO_MSB; -/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ -#define N_SAMPLES ((int)(48000 * 0.020)) - abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, abe_irq_pingpong_player_id, - N_SAMPLES, &base_address, PING_PONG_WITH_MCU_IRQ); - - /* VX_DL INIT - connect a DMA channel to VX_DL port (ATC FIFO) - */ + connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate + */ + abe_add_subroutine (&abe_irq_pingpong_player_id, +(abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0 ); + format.f = 48000; +format.samp_format = STEREO_MSB; + /* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */ + #define N_SAMPLES ((int)(48000 * 0.020)) + abe_connect_irq_ping_pong_port (MM_DL_PORT, &format, abe_irq_pingpong_player_id, +N_SAMPLES, &base_address, PING_PONG_WITH_MCU_IRQ); + + /* VX_DL INIT + connect a DMA channel to VX_DL port (ATC FIFO) + */ format.f = 8000; format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); + abe_connect_cbpr_dmareq_port (VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - /* VX_UL INIT - connect a DMA channel to VX_UL port (ATC FIFO) - */ + /* VX_UL INIT + connect a DMA channel to VX_UL port (ATC FIFO) + */ format.f = 8000; format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_source); + abe_connect_cbpr_dmareq_port (VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_source); + + /* make the AE waking event to be the McPDM DMA requests */ + abe_write_event_generator (EVENT_MCPDM); + + abe_enable_data_transfer (MM_DL_PORT ); + abe_enable_data_transfer (VX_DL_PORT ); + abe_enable_data_transfer (VX_UL_PORT ); + abe_enable_data_transfer (PDM_UL_PORT); + abe_enable_data_transfer (PDM_DL1_PORT); + +} + +#endif + + +/* ========================================================================== */ +/** +* @fn ABE_AUTO_CHECK_DATA_FORMAT_TRANSLATION() +*/ +/* ========================================================================= */ + + +void abe_auto_check_data_format_translation (void) +{ +#if 0 + abe_float test, f_decibel, f_linear, max_error; + abe_uint32 data_mem; +#define C_20LOG2 ((abe_float)6.020599913) + + for (max_error = 0, f_decibel = -70; f_decibel < 30; f_decibel += 0.1) { + f_linear = 0; + abe_translate_gain_format (DECIBELS_TO_LINABE, f_decibel, &f_linear); + abe_translate_to_xmem_format (ABE_CMEM, f_linear, &data_mem); + abe_translate_to_xmem_format (ABE_SMEM, f_linear, &data_mem); + abe_translate_to_xmem_format (ABE_DMEM, f_linear, &data_mem); + + test = (abe_float) pow (2, f_decibel/C_20LOG2); + if ( (absolute(f_linear - test) / 1) > max_error) + max_error = (absolute(f_linear - test) / 1); + + abe_translate_gain_format (LINABE_TO_DECIBELS, f_linear, &f_decibel); + test = (abe_float) (C_20LOG2 * log(f_linear) / log(2)); + + if ( (absolute(f_decibel - test) / 1) > max_error) + max_error = (absolute(f_decibel - test) / 1); + + /* the observed max gain error is 0.0001 decibel (0.002%) */ + } + + #if 0 + { + FILE *outf; + outf = fopen("buff.txt", "wt"); + for (f_decibel = -120; f_decibel < 31; f_decibel += 1) { + f_linear = 0; + abe_translate_gain_format (DECIBELS_TO_LINABE, f_decibel, &f_linear); + abe_translate_to_xmem_format (ABE_CMEM, f_linear, &data_mem); + + + fprintf (outf, "\n 0x%08lX, /* CMEM coding of %4d dB */", data_mem, (short)(f_decibel)); + } + fclose (outf); + } + #endif + #if 1 + { + FILE *outf; + outf = fopen("buff.txt", "wt"); + for (f_decibel = -120; f_decibel < 31; f_decibel += 1) { + //f_linear = 0; + //abe_translate_gain_format (DECIBELS_TO_LINABE, f_decibel, &f_linear); + //abe_translate_to_xmem_format (ABE_SMEM, f_linear, &data_mem); + + + + fprintf (outf, "\n 0x%08lX, /* SMEM coding of %4d dB */", (long)(0x40000L * pow(10, f_decibel/20.0)), (short)(f_decibel)); + //fprintf (outf, "\n 0x%08lX, /* SMEM coding of %4d dB */", data_mem, (short)(f_decibel)); + } + fclose (outf); + } + #endif +#endif +} + +#if 0 + +/* ========================================================================== */ +/** +* @fn ABE_AUTO_CHECK_DATA_FORMAT_TRANSLATION() +*/ +/* ========================================================================= */ + +void abe_check_opp (void) +{ +#if PC_SIMULATION + abe_use_case_id UC[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, 0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + abe_read_hardware_configuration (UC, &OPP, &CONFIG); /* check HW config and OPP config */ +#endif +} + +/* ========================================================================== */ +/** +* @fn ABE_AUTO_CHECK_DATA_FORMAT_TRANSLATION() +*/ +/* ========================================================================= */ + +void abe_check_dma (void) +{ +#if PC_SIMULATION + abe_port_id id; + abe_data_format_t format; + abe_uint32 d; + abe_dma_t dma_sink; + + + /* check abe_read_port_address () */ + id = VX_UL_PORT; + abe_read_port_address (id, &dma_sink); + + format.f = 8000; + format.samp_format = STEREO_MSB; + d = abe_dma_port_iter_factor (&format); + d = abe_dma_port_iteration (&format); + abe_connect_cbpr_dmareq_port (VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); + abe_read_port_address (id, &dma_sink); +#endif +} - /* make the AE waking event to be the McPDM DMA requests */ - abe_write_event_generator(EVENT_MCPDM); - abe_enable_data_transfer(MM_DL_PORT ); - abe_enable_data_transfer(VX_DL_PORT ); - abe_enable_data_transfer(VX_UL_PORT ); - abe_enable_data_transfer(PDM_UL_PORT); - abe_enable_data_transfer(PDM_DL1_PORT); +/* ========================================================================== */ +/** +* @fn ABE_CHECK_MIXERS_GAIN_UPDATE() +*/ +/* ========================================================================= */ +void abe_check_mixers_gain_update (void) +{ +#if PC_SIMULATION + abe_write_mixer (MIXDL1, GAIN_12dB, RAMP_0MS, MIX_DL1_INPUT_TONES); + abe_write_mixer (MIXDL1, GAIN_12dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, GAIN_M12dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_5MS, MIX_DL1_INPUT_MM_UL2); +#endif } +void abe_debug_and_non_regression (void) +{ +#if PC_SIMULATION + abe_uint32 i, j; + abe_dma_t d; + + + abe_set_ping_pong_buffer (MM_DL_PORT, 4); //bug 23 & 24 + abe_read_next_ping_pong_buffer (MM_DL_PORT, &i, &j); + + abe_read_port_address (6, &d); + +#endif +} + +void abe_debug_check_mem (void) +{ +#if 1 + abe_uint32 pmem[512], i; + for (i = 0; i < 512; i++) { + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_PMEM, i *4 , &(pmem[i]), 4); + } + i = 0; +#endif +#if 0 + abe_uint32 cmem[512], i; + for (i = 0; i < 512; i++) { + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_CMEM, i *4 , &(cmem[i]), 4); + } + i = 0; +#endif +#if 0 + static int flag; + + if (flag == 0) { + abe_uint32 data[4] = {0x11111111L, 0x22222222L, 0x33333333L, 0x44444444L}; + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, 0xf00, data, 8); // @ = 0xF00/3 0x3C0 0X11111111 + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0x2000, data, 8); // @ = 0x2000/4 0x800 0x111111 + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0x1100, data, 8); // @ = 0x1100/8 0x220 0x2222221111111 + abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0x5000, data, 8); // @ = 0x5000(B) 0x1111 + + flag = 0; + } +#endif +} #endif diff --git a/sound/soc/omap/abe/abe_main.h b/sound/soc/omap/abe/abe_main.h index 213c38a57cf3..8ef0dd830fe7 100644 --- a/sound/soc/omap/abe/abe_main.h +++ b/sound/soc/omap/abe/abe_main.h @@ -1,48 +1,63 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #ifndef _ABE_MAIN_H_ #define _ABE_MAIN_H_ +#ifdef __cplusplus + +extern "C" { +#endif + +#include <linux/io.h> + #include "abe_dm_addr.h" +#include "abe_sm_addr.h" #include "abe_cm_addr.h" + #include "abe_def.h" #include "abe_typ.h" -#include "abe_dbg.h" #include "abe_ext.h" +#include "abe_dbg.h" #include "abe_lib.h" #include "abe_ref.h" #include "abe_api.h" -//#include "ABE_DAT.h" + + #include "abe_typedef.h" -#include "abe_functionsId.h" -#include "abe_taskId.h" -#include "abe_dm_addr.h" -#include "abe_sm_addr.h" -#include "abe_cm_addr.h" +#include "abe_functionsid.h" +#include "abe_taskid.h" #include "abe_initxxx_labels.h" #include "abe_fw.h" -#ifdef __cplusplus -extern "C" { -#endif +/* pipe connection to the TARGET simulator */ +#define ABE_DEBUG_CHECKERS 0 -#define ABE_HAL_VERSION 0x00000002L -#define ABE_FW_VERSION 0x00000000L -#define ABE_HW_VERSION 0x00000000L +/* simulator data extracted from a text-file */ +#define ABE_DEBUG_HWFILE 0 -#define ABE_DEBUG_CHECKERS 0 /* pipe connection to the TARGET simulator */ -#define ABE_DEBUG_HWFILE 0 /* simulator data extracted from a text-file */ -#define ABE_DEBUG_LL_LOG 0 /* low-level log files */ +/* low-level log files */ +#define ABE_DEBUG_LL_LOG 0 #define ABE_DEBUG (ABE_DEBUG_CHECKERS | ABE_DEBUG_HWFILE | ABE_DEBUG_LL_LOG) @@ -50,4 +65,4 @@ extern "C" { } #endif -#endif /* _ABE_MAIN_H_ */ +#endif /* _ABE_MAIN_H_ */ diff --git a/sound/soc/omap/abe/abe_ref.h b/sound/soc/omap/abe/abe_ref.h index cc69b8770dce..c215750e8a01 100644 --- a/sound/soc/omap/abe/abe_ref.h +++ b/sound/soc/omap/abe/abe_ref.h @@ -1,22 +1,29 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ - #ifndef _ABE_REF_H_ #define _ABE_REF_H_ /* - * 'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ... + * 'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ... */ -#ifdef __cplusplus -extern "C" { -#endif /* * HAL EXTERNAL API @@ -25,124 +32,131 @@ extern "C" { /* * HAL INTERNAL API */ -void abe_load_embedded_patterns(void); -void abe_build_scheduler_table(void); -void abe_reset_all_features(void); -void abe_reset_one_port(abe_uint32 x); -void abe_reset_all_ports(void); -void abe_reset_all_fifo(void); -void abe_reset_all_sequence(void); -abe_uint32 abe_dma_port_iteration(abe_data_format_t *format); -void abe_read_sys_clock(abe_micros_t *time); -void abe_enable_dma_request(abe_port_id id); -void abe_disable_dma_request(abe_port_id id); -void abe_enable_atc(abe_port_id id); -void abe_disable_atc(abe_port_id id); -void abe_init_atc(abe_port_id id); -void abe_init_io_tasks(abe_port_id id, abe_data_format_t *format, abe_port_protocol_t *prot); -void abe_init_dma_t(abe_port_id id, abe_port_protocol_t *prot); -abe_uint32 abe_dma_port_iter_factor(abe_data_format_t *f); -abe_uint32 abe_dma_port_copy_subroutine_id(abe_port_id i); -void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint32 p3, abe_uint32 p4); -void abe_monitoring(void); -void abe_lock_execution(void); -void abe_unlock_execution(void); -void abe_hw_configuration(void); -void abe_add_subroutine(abe_uint32 *id, abe_subroutine2 f, - abe_uint32 nparam, abe_uint32* params); -void abe_read_next_ping_pong_buffer(abe_port_id port, - abe_uint32 *p, abe_uint32 *n); -void abe_irq_ping_pong(void); -void abe_irq_check_for_sequences(abe_uint32 seq_info); +void abe_load_embeddded_patterns (void); +void abe_build_scheduler_table (void); +void abe_reset_one_feature (u32 x); +void abe_reset_all_features (void); +void abe_reset_all_ports (void); +void abe_reset_all_fifo (void); +void abe_reset_all_sequence (void); +u32 abe_dma_port_iteration (abe_data_format_t *format); +void abe_read_sys_clock (u32 *time); +void abe_enable_dma_request (u32 id); +void abe_disable_dma_request (u32 id); +void abe_enable_atc (u32 id); +void abe_disable_atc (u32 id); +void abe_init_atc (u32 id); +void abe_init_io_tasks (u32 id, abe_data_format_t *format, + abe_port_protocol_t *prot); +void abe_init_dma_t (u32 id, abe_port_protocol_t *prot); +u32 abe_dma_port_iter_factor (abe_data_format_t *f); +u32 abe_dma_port_copy_subroutine_id (u32 i); +void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4); +void abe_monitoring (void); +void abe_lock_execution (void); +void abe_unlock_execution (void); +void abe_hw_configuration (void); +void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam, + u32* params); +abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n); +void abe_irq_ping_pong (void); +void abe_irq_check_for_sequences (u32 seq_info); void abe_default_irq_pingpong_player(void); -void abe_default_irq_pingping_player_32bits(void); +void abe_default_irq_pingpong_player_32bits(void); void abe_default_irq_aps_adaptation(void); -void abe_read_hardware_configuration(abe_use_case_id *u, - abe_opp_t *o, abe_hw_config_init_t *hw); -void abe_irq_aps(abe_uint32 aps_info); -void abe_clean_temporary_buffers(abe_port_id id); -void abe_reset_atc(abe_uint32 atc_index); -void abe_dbg_log(abe_uint32 x, abe_uint32 y, abe_uint32 z, abe_uint32 t); -void abe_dbg_error_log(abe_uint32 x); - - -void abe_translate_to_xmem_format(abe_int32 memory_bank, - float fc, abe_uint32 *c); +void abe_irq_aps (u32 aps_info); +void abe_clean_temporary_buffers (u32 id); +void abe_dbg_log (u32 x, u32 y, u32 z, u32 t); +void abe_dbg_error_log (u32 x); +void abe_init_asrc_vx_dl ( s32 dppm); +void abe_init_asrc_vx_ul ( s32 dppm); +void abe_init_asrc_mm_dl ( s32 dppm); +//u8 *memmove(u8 *dst, u8 *src, u32 n); +//u32 __get_unaligned_memmove32(void *p); +//void __put_unaligned_memmove32(u32 val, void *p); /* * HAL INTERNAL DATA */ - +extern const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE]; +extern u32 abe_firmware_version_number; +extern const u32 abe_atc_srcid []; +extern const u32 abe_atc_dstid []; extern abe_port_t abe_port[]; -extern abe_feature_t feature[]; -extern abe_subroutine2 callbacks[]; +extern abe_feature_t feature []; -extern abe_port_t abe_port[]; -extern const abe_port_t abe_port_init[]; +extern const abe_port_t abe_port_init []; -extern abe_feature_t all_feature[]; -extern const abe_feature_t all_feature_init[]; +extern abe_feature_t all_feature []; +extern const abe_feature_t all_feature_init []; -extern abe_seq_t all_sequence[]; +extern abe_seq_t all_sequence []; extern const abe_seq_t all_sequence_init[]; -extern const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL]; -extern abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL]; +extern const abe_router_t abe_router_ul_table_preset +[NBROUTE_CONFIG][NBROUTE_UL]; +extern abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL]; -extern abe_uint32 abe_dbg_output; -extern abe_uint32 abe_dbg_mask; -extern abe_uint32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof]; -extern abe_uint32 abe_dbg_activity_log_write_pointer; -extern abe_uint32 abe_dbg_param; +extern u32 abe_dbg_output; +extern u32 abe_dbg_mask; +extern u32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof]; +extern u32 abe_dbg_activity_log_write_pointer; +extern u32 abe_dbg_param; -extern abe_uint32 abe_global_mcpdm_control; -extern abe_event_id abe_current_event_id; +extern u32 abe_current_event_id; extern const abe_sequence_t seq_null; -extern abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE]; /* table of new subroutines called in the sequence */ -extern abe_uint32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE]; /* number of parameters per calls */ -extern abe_uint32 abe_subroutine_id[MAXNBSUBROUTINE]; -extern abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE]; -extern abe_uint32 abe_subroutine_write_pointer; -extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; /* table of all sequences */ -extern abe_uint32 abe_sequence_write_pointer; -extern abe_uint32 abe_nb_pending_sequences; /* current number of pending sequences (avoids to look in the table) */ -extern abe_uint32 abe_pending_sequences[MAXNBSEQUENCE]; /* pending sequences due to ressource collision */ -extern abe_uint32 abe_global_sequence_mask; /* mask of unsharable ressources among other sequences */ -extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS]; /* table of active sequences */ -extern abe_uint32 abe_irq_pingpong_player_id; /* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */ -extern abe_uint32 abe_irq_aps_adaptation_id; -extern abe_uint32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS]; /* base addresses of the ping pong buffers */ -extern abe_uint32 abe_size_pingpong; /* size of each ping/pong buffers */ -extern abe_uint32 abe_nb_pingpong; /* number of ping/pong buffer being used */ - -extern abe_uint32 abe_irq_dbg_read_ptr; - -extern volatile abe_uint32 just_to_avoid_the_many_warnings; -extern volatile abe_gain_t just_to_avoid_the_many_warnings_abe_gain_t; -extern volatile abe_ramp_t just_to_avoid_the_many_warnings_abe_ramp_t; -extern volatile abe_dma_t just_to_avoid_the_many_warnings_abe_dma_t; -extern volatile abe_port_id just_to_avoid_the_many_warnings_abe_port_id; -extern volatile abe_millis_t just_to_avoid_the_many_warnings_abe_millis_t; -extern volatile abe_micros_t just_to_avoid_the_many_warnings_abe_micros_t; -extern volatile abe_patch_rev just_to_avoid_the_many_warnings_abe_patch_rev; -extern volatile abe_sequence_t just_to_avoid_the_many_warnings_abe_sequence_t; -extern volatile abe_ana_port_id just_to_avoid_the_many_warnings_abe_ana_port_id; -extern volatile abe_time_stamp_t just_to_avoid_the_many_warnings_abe_time_stamp_t; -extern volatile abe_data_format_t just_to_avoid_the_many_warnings_abe_data_format_t; -extern volatile abe_port_protocol_t just_to_avoid_the_many_warnings_abe_port_protocol_t; -extern volatile abe_router_t just_to_avoid_the_many_warnings_abe_router_t; -extern volatile abe_router_id just_to_avoid_the_many_warnings_abe_router_id; - -extern const abe_int32 abe_dmic_40[C_98_48_LP_Coefs_sizeof]; -extern const abe_int32 abe_dmic_32[C_98_48_LP_Coefs_sizeof]; -extern const abe_int32 abe_dmic_25[C_98_48_LP_Coefs_sizeof]; -extern const abe_int32 abe_dmic_16[C_98_48_LP_Coefs_sizeof]; - -extern const abe_uint32 abe_db2lin_table []; - -#ifdef __cplusplus -} -#endif + +/* table of new subroutines called in the sequence */ +extern abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE]; + +/* number of parameters per calls */ +extern u32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE]; +extern u32 abe_subroutine_id [MAXNBSUBROUTINE]; +extern u32* abe_all_subroutine_params[MAXNBSUBROUTINE]; +extern u32 abe_subroutine_write_pointer; + + +extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE]; +extern u32 abe_sequence_write_pointer; + +/* current number of pending sequences (avoids to look in the table) */ +extern u32 abe_nb_pending_sequences; + +/* pending sequences due to ressource collision */ +extern u32 abe_pending_sequences [MAXNBSEQUENCE]; + +/* mask of unsharable ressources among other sequences */ +extern u32 abe_global_sequence_mask; + +/* table of active sequences */ +extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS]; + +/* index of the plugged subroutine doing ping-pong cache-flush + DMEM accesses */ +extern u32 abe_irq_pingpong_player_id; +extern u32 abe_irq_aps_adaptation_id; + +/* base addresses of the ping pong buffers */ +extern u32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS]; + +/* size of each ping/pong buffers */ +extern u32 abe_size_pingpong; + +/* number of ping/pong buffer being used */ +extern u32 abe_nb_pingpong; + +/* circular read pointer to IRQ/DBG DMEM buffer */ +extern u32 abe_irq_dbg_read_ptr; + +extern const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof]; +extern const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof]; + +extern const u32 abe_db2lin_table []; +extern const u32 abe_alpha_iir [64]; +extern const u32 abe_1_alpha_iir [64]; + #endif /* _ABE_REF_H_ */ diff --git a/sound/soc/omap/abe/abe_seq.c b/sound/soc/omap/abe/abe_seq.c index e042fb317eec..9f7e1e96fcdb 100644 --- a/sound/soc/omap/abe/abe_seq.c +++ b/sound/soc/omap/abe/abe_seq.c @@ -1,105 +1,103 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_main.h" -/* - * SEQUENCES - * struct { - * micros_t time; Waiting time before executing next line - * seq_code_t code Subroutine index interpreted in the HAL and translated to - * FW subroutine codes in case of ABE tasks - * int32 param[2] Two parameters - * char param_tag[2] Flags used for parameters when launching the sequences - * } seq_t - * - */ -/* - * ABE_NULL_SUBROUTINE +/** + * abe_null_subroutine * - * Operations : nothing */ -void abe_null_subroutine_0(void) { } -void abe_null_subroutine_2 (abe_uint32 a, abe_uint32 b) { - just_to_avoid_the_many_warnings = a; - just_to_avoid_the_many_warnings = b; +void abe_null_subroutine_0 (void) { } +void abe_null_subroutine_2 (u32 a, u32 b) +{ } -void abe_null_subroutine_4 (abe_uint32 a, abe_uint32 b, abe_uint32 c, abe_uint32 d) { - just_to_avoid_the_many_warnings = a; - just_to_avoid_the_many_warnings = b; - just_to_avoid_the_many_warnings = c; - just_to_avoid_the_many_warnings = d; +void abe_null_subroutine_4 (u32 a, u32 b, u32 c, u32 d) +{ } -/* - * abe_init_subroutine_table - * - * parameter : - * none - * - * operations : - * initializes the default table of pointers to subroutines + +/** + * abe_init_subroutine_table - initializes the default table of pointers + * to subroutines * - * return value : + * initializes the default table of pointers to subroutines * */ -void abe_init_subroutine_table(void) +void abe_init_subroutine_table (void) { - abe_uint32 id; + u32 id; /* reset the table's pointers */ abe_subroutine_write_pointer = 0; + /* the first index is the NULL task */ - abe_add_subroutine(&id,(abe_subroutine2) abe_null_subroutine_2, SUB_0_PARAM, (abe_uint32*)0); - /* write mixer has 3 parameters @@@ TBD*/ - abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]), (abe_subroutine2) abe_write_mixer, SUB_4_PARAM, (abe_uint32*)0); + abe_add_subroutine(&id,(abe_subroutine2) abe_null_subroutine_2, + SUB_0_PARAM, (u32*)0); + + /* write mixer has 4 parameters */ + abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]), + (abe_subroutine2) abe_write_mixer, SUB_4_PARAM, (u32*)0); + /* ping-pong player IRQ */ - abe_add_subroutine(&abe_irq_pingpong_player_id,(abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM, (abe_uint32*)0); - abe_add_subroutine(&abe_irq_aps_adaptation_id,(abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (abe_uint32*)0); + abe_add_subroutine(&abe_irq_pingpong_player_id, + (abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM, (u32*)0); + abe_add_subroutine (&abe_irq_aps_adaptation_id, + (abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (u32*)0); } -/* - * ABE_ADD_SUBROUTINE - * - * Parameter : - * port id - * pointer to the subroutines - * number of parameters to push on the stack before call - * - * Operations : - * add one function pointer more and returns the index to it - * - * Return value : +/** + * abe_add_subroutine + * @id: ABE port id + * @f: pointer to the subroutines + * @nparam: number of parameters + * @params: pointer to the psrameters * + * add one function pointer more and returns the index to it */ -void abe_add_subroutine (abe_uint32 *id, abe_subroutine2 f, abe_uint32 nparam, abe_uint32* params) +void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam, u32* params) { - abe_uint32 i, i_found; + u32 i, i_found; - if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) || ((abe_uint32)f == 0)) { + if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) || + ((u32)f == 0)) { abe_dbg_param |= ERR_SEQ; - abe_dbg_error_log(ABE_PARAMETER_OVERFLOW); + abe_dbg_error_log (ABE_PARAMETER_OVERFLOW); } else { /* search if this subroutine address was not already * declared, then return the previous index */ - for (i_found = abe_subroutine_write_pointer, i = 0; i < abe_subroutine_write_pointer; i++) { + for (i_found = abe_subroutine_write_pointer, i = 0; + i < abe_subroutine_write_pointer; i++) { if (f == abe_all_subsubroutine[i]) i_found = i; } if (i_found == abe_subroutine_write_pointer) { *id = abe_subroutine_write_pointer; - abe_all_subsubroutine[abe_subroutine_write_pointer] = (f); - abe_all_subroutine_params[abe_subroutine_write_pointer] = params; - abe_all_subsubroutine_nparam[abe_subroutine_write_pointer] = nparam; + abe_all_subsubroutine + [abe_subroutine_write_pointer] = (f); + abe_all_subroutine_params + [abe_subroutine_write_pointer] = params; + abe_all_subsubroutine_nparam + [abe_subroutine_write_pointer] = nparam; abe_subroutine_write_pointer++; } else { abe_all_subroutine_params[i_found] = params; @@ -108,39 +106,38 @@ void abe_add_subroutine (abe_uint32 *id, abe_subroutine2 f, abe_uint32 nparam, a } } -/* - * ABE_ADD_SEQUENCE - * - * Parameter : - * Id: returned sequence index after pluging a new sequence (index in the tables) - * s : sequence to be inserted +/** + * abe_add_sequence + * @id: returned sequence index after pluging a new sequence (index in the tables) + * @s: sequence to be inserted * - * Operations : - * Load a time-sequenced operations. - * - * Return value : - * None. + * Load a time-sequenced operations. */ - -void abe_add_sequence(abe_uint32 *id, abe_sequence_t *s) +void abe_add_sequence (u32 *id, abe_sequence_t *s) { abe_seq_t *seq_src, *seq_dst; - abe_uint32 i, no_end_of_sequence_found; + u32 i, no_end_of_sequence_found; seq_src = &(s->seq1); - seq_dst = &((abe_all_sequence[abe_sequence_write_pointer]).seq1); + seq_dst = &((abe_all_sequence [abe_sequence_write_pointer]).seq1); - if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((abe_uint32)s == 0)) { + if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((u32)s == 0)) { abe_dbg_param |= ERR_SEQ; - abe_dbg_error_log(ABE_PARAMETER_OVERFLOW); + abe_dbg_error_log (ABE_PARAMETER_OVERFLOW); } else { *id = abe_subroutine_write_pointer; - (abe_all_sequence[abe_sequence_write_pointer]).mask = s->mask; /* copy the mask */ + + /* copy the mask */ + (abe_all_sequence [abe_sequence_write_pointer]).mask = s->mask; - for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS; i++, seq_src++, seq_dst++) { - (*seq_dst) = (*seq_src); /* sequence copied line by line */ + for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS; + i++, seq_src++, seq_dst++) { + + /* sequence copied line by line */ + (*seq_dst) = (*seq_src); - if ((*(abe_int32 *)seq_src) == -1) { + /* stop when the line start with time=(-1) */ + if ((*(s32 *)seq_src) == (-1)) { /* stop when the line start with time=(-1) */ no_end_of_sequence_found = 0; break; @@ -149,117 +146,103 @@ void abe_add_sequence(abe_uint32 *id, abe_sequence_t *s) abe_subroutine_write_pointer++; if (no_end_of_sequence_found) - abe_dbg_error_log(ABE_SEQTOOLONG); + abe_dbg_error_log (ABE_SEQTOOLONG); } } -/* - * ABE_RESET_ONE_SEQUENCE - * - * Parameter : - * sequence ID - * - * Operations : - * load default configuration for that sequence - * kill running activities - * - * Return value : +/** + * abe_reset_one_sequence + * @id: sequence ID * + * load default configuration for that sequence + * kill running activities */ -void abe_reset_one_sequence(abe_uint32 id) +void abe_reset_one_sequence (u32 id) { - just_to_avoid_the_many_warnings = id; } -/* - * ABE_RESET_ALL_SEQUENCE - * - * Parameter : - * none - * - * Operations : - * load default configuration for all sequences - * kill any running activities - * - * Return value : +/** + * abe_reset_all_sequence * + * load default configuration for all sequences + * kill any running activities */ -void abe_reset_all_sequence(void) +void abe_reset_all_sequence (void) { - abe_uint32 i; + u32 i; - abe_init_subroutine_table(); + abe_init_subroutine_table (); - /* arrange to have the first sequence index=0 to the NULL operation sequence */ - abe_add_sequence(&i, (abe_sequence_t *)&seq_null); + /* arrange to have the first sequence index=0 to the NULL operation + sequence */ + abe_add_sequence (&i, (abe_sequence_t *)&seq_null); /* reset the the collision protection mask */ abe_global_sequence_mask = 0; /* reset the pending sequences list */ for (abe_nb_pending_sequences = i = 0; i < MAXNBSEQUENCE; i++) - abe_pending_sequences[i] = 0; + abe_pending_sequences [i] = 0; } -/* - * ABE_CALL_SUBROUTINE - * - * Parameter : - * index to the table of all registered Call-backs and subroutines +/** + * abe_call_subroutine + * @idx: index to the table of all registered Call-backs and subroutines * - * Operations : - * run and log a subroutine - * - * Return value : - * None. + * run and log a subroutine */ -void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint32 p3, abe_uint32 p4) +void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4) { abe_subroutine0 f0; abe_subroutine1 f1; abe_subroutine2 f2; abe_subroutine3 f3; abe_subroutine4 f4; - abe_uint32* params; + u32* params; - if (idx >= MAXNBSUBROUTINE) - return; + if (idx > MAXNBSUBROUTINE) + return; switch (idx) { + /* call the subroutines defined at compilation time + (const .. sequences) */ #if 0 - /* call the subroutines defined at compilation time (const .. sequences) */ case SUB_WRITE_MIXER_DL1 : - /@@@@ abe_write_mixer_dl1 (p1, p2, p3) - abe_fprintf ("write_mixer"); - break; + abe_write_mixer_dl1 (p1, p2, p3) + abe_fprintf ("write_mixer"); + break; #endif - /* call the subroutines defined at execution time (dynamic sequences) */ + /* call the subroutines defined at execution time + (dynamic sequences) */ default : - switch(abe_all_subsubroutine_nparam[idx]) { + switch (abe_all_subsubroutine_nparam [idx]) { case SUB_0_PARAM: - f0 = (abe_subroutine0)abe_all_subsubroutine[idx]; - (*f0)(); + f0 = (abe_subroutine0) abe_all_subsubroutine [idx]; + (*f0) (); break; case SUB_1_PARAM: - f1 = (abe_subroutine1) abe_all_subsubroutine[idx]; - params = abe_all_subroutine_params[abe_irq_pingpong_player_id]; - if (params != (abe_uint32*)0) + f1 = (abe_subroutine1) abe_all_subsubroutine [idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32*)0) p1 = params[0]; (*f1) (p1); break; case SUB_2_PARAM: - f2 = abe_all_subsubroutine[idx]; - params = abe_all_subroutine_params[abe_irq_pingpong_player_id]; - if (params != (abe_uint32*)0) { + f2 = abe_all_subsubroutine [idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32*)0) { p1 = params[0]; p2 = params[1]; } (*f2) (p1, p2); break; case SUB_3_PARAM: - f3 = (abe_subroutine3) abe_all_subsubroutine[idx]; - params = abe_all_subroutine_params[abe_irq_pingpong_player_id]; - if (params != (abe_uint32*)0) { + f3 = (abe_subroutine3) abe_all_subsubroutine [idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32*)0) { p1 = params[0]; p2 = params[1]; p3 = params[2]; @@ -267,9 +250,10 @@ void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint3 (*f3) (p1, p2, p3); break; case SUB_4_PARAM: - f4 = (abe_subroutine4) abe_all_subsubroutine[idx]; - params = abe_all_subroutine_params[abe_irq_pingpong_player_id]; - if (params != (abe_uint32*)0) { + f4 = (abe_subroutine4) abe_all_subsubroutine [idx]; + params = abe_all_subroutine_params + [abe_irq_pingpong_player_id]; + if (params != (u32*)0) { p1 = params[0]; p2 = params[1]; p3 = params[2]; @@ -277,6 +261,7 @@ void abe_call_subroutine(abe_uint32 idx, abe_uint32 p1, abe_uint32 p2, abe_uint3 } (*f4) (p1, p2, p3, p4); break; + default: break; } diff --git a/sound/soc/omap/abe/abe_seq.h b/sound/soc/omap/abe/abe_seq.h index 6e15531e920e..3c690d77501e 100644 --- a/sound/soc/omap/abe/abe_seq.h +++ b/sound/soc/omap/abe/abe_seq.h @@ -1,32 +1,49 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. - * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== +/* ============================================================================= +* Texas Instruments OMAP(TM) Platform Software +* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. +* +* Use of this software is controlled by the terms and conditions found +* in the license agreement under which this software has been supplied. +* =========================================================================== */ +/** + * @file ABE_SEQ.H + * + * 'ABE_SEQ.H' time-sequenced activations + * + * @path + * @rev 01.00 */ +/* ---------------------------------------------------------------------------- +*! +*! Revision History +*! =================================== +*! 27-Nov-2008 Original (LLF) +*! 05-Jun-2009 V05 release +* =========================================================================== */ + + +void abe_init_subroutine_table (void); + + -void abe_init_subroutine_table(void); /* * Register Programming Examples * * 1. Power on sequence * - * The modules HSLDO, NCP, LSLDO, LPPLL are enabled/disabled automatically by the TWL6040 power state machine after pin AUDPWRON transitions from 0 ' 1. No register writes are necessary. - * - * For the purposes of test it is possible to bypass the power state machine and manually enable these modules in the same order as described in Fig 2-XX. This can be done after VIO comes up and I2C register writes are possible. + * The modules HSLDO, NCP, LSLDO, LPPLL are enabled/disabled automatically by the TWL6040 power state machine after pin AUDPWRON transitions from 0 ' 1. No register writes are necessary. * + * For the purposes of test it is possible to bypass the power state machine and manually enable these modules in the same order as described in Fig 2-XX. This can be done after VIO comes up and I2C register writes are possible. + * * The manual sequence could be as follows * LDOCTL = 0x04 (Enable HSLDO) * NCPCTL = 0x03 (Enable NCP in auto mode) * LDOCTL = 0x05 (Enable LSLDO) - * LPPLLCTL = 0x09 (Enable LPPLL with output frequency = 19.2MHz) - * + * LPPLLCTL = 0x09 (Enable LPPLL with output frequency = 19.2MHz) + * * Please see Fig 2-64 for details on details to be maintained between successive I2C register writes. - * + * * Further if the system MCLK is active the HPPLL could be enabled instead of the LPPLL. * (a) For a square wave where slicer is not required * HPPLLCTL = 0x11 (Select HPPLL output, Enable HPPLL) @@ -34,7 +51,7 @@ void abe_init_subroutine_table(void); * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL) * */ - + /* * 2. Setting up a stereo UPLINK path through MICAMPL, MICAMPR input amplifiers * AMICBCTL = 0x10 @@ -42,13 +59,13 @@ void abe_init_subroutine_table(void); * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL) * MICLCTL = 0x0D (Select MMIC input, Enable ADC) * MICRCTL = 0x0D (Select SMIC input, Enable ADC) - * + * */ /* * 3. Setting up a stereo headset MP3 playback DNLINK path * Please see section 2.3.1.1 for details - * + * * (b) HP * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers) * HSLCTL = 0x01 (Enable HSDAC L, HP mode) @@ -59,9 +76,9 @@ void abe_init_subroutine_table(void); * Wait 2ms * HSLCTL = 0x25 (Close HSDACL switch) * HSRCTL = 0x25 (Close HSDACR switch) - * + * */ - + /* * (a) LP * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers) @@ -73,9 +90,9 @@ void abe_init_subroutine_table(void); * Wait 2ms * HSLCTL = 0x2F (Close HSDACL switch) * HSRCTL = 0x2F (Close HSDACR switch) - * + * */ - + /* * 4. Setting up a stereo FM playback path on headset * (a) HP @@ -86,12 +103,12 @@ void abe_init_subroutine_table(void); * HSLCTL = 0x04 (Enable HSLDRV in HP mode) * HSRCTL = 0x04 (Enable HSRDRV in HP mode) * Wait 2ms - * HSLCTL = 0x44 (Close FMLOOP switch) + * HSLCTL = 0x44 (Close FMLOOP switch) * HSRCTL = 0x44 (Close FMLOOP switch) - * - * + * + * */ - + /* * (b) LP * LINEGAIN = 0x1B (0dB gain on L and R inputs) @@ -101,25 +118,25 @@ void abe_init_subroutine_table(void); * HSLCTL = 0x0C (Enable HSLDRV in LP mode) * HSRCTL = 0x0C (Enable HSRDRV in LP mode) * Wait 2ms - * HSLCTL = 0x4C (Close FMLOOP switch) + * HSLCTL = 0x4C (Close FMLOOP switch) * HSRCTL = 0x4C (Close FMLOOP switch) - * + * */ - - + + /* * 5. Setting up a handset call - * + * * UPLINK - * + * * AMICBCTL = 0x10 * MICGAIN = 0x0F (Gain to 24 dB for L and R) * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL) * MICLCTL = 0x0D (Select MMIC input, Enable ADC) * MICRCTL = 0x0D (Select SMIC input, Enable ADC) - * + * * DNLINK - * + * * HSLCTL = 0x01 (Enable HSDACL, HP mode) * Wait 80us * EARCTL = 0x03 (Enable EAR, Gain = min, by default enabling EAR connects HSDACL output to EAR) diff --git a/sound/soc/omap/abe/abe_sm_addr.h b/sound/soc/omap/abe/abe_sm_addr.h index ee761187d0c1..fe445d5b0753 100644 --- a/sound/soc/omap/abe/abe_sm_addr.h +++ b/sound/soc/omap/abe/abe_sm_addr.h @@ -1,674 +1,685 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== */ - #ifndef _ABE_SM_ADDR_H_ #define _ABE_SM_ADDR_H_ -#define init_SM_ADDR 0 -#define init_SM_ADDR_END 304 -#define init_SM_sizeof 305 +#define init_SM_ADDR 0 +#define init_SM_ADDR_END 303 +#define init_SM_sizeof 304 + +#define S_Data0_ADDR 304 +#define S_Data0_ADDR_END 304 +#define S_Data0_sizeof 1 -#define S_Data0_ADDR 305 -#define S_Data0_ADDR_END 305 -#define S_Data0_sizeof 1 +#define S_Temp_ADDR 305 +#define S_Temp_ADDR_END 305 +#define S_Temp_sizeof 1 -#define S_Temp_ADDR 306 -#define S_Temp_ADDR_END 306 -#define S_Temp_sizeof 1 +#define S_PhoenixOffset_ADDR 306 +#define S_PhoenixOffset_ADDR_END 306 +#define S_PhoenixOffset_sizeof 1 -#define S_PhoenixOffset_ADDR 307 -#define S_PhoenixOffset_ADDR_END 307 -#define S_PhoenixOffset_sizeof 1 +#define S_GTarget1_ADDR 307 +#define S_GTarget1_ADDR_END 313 +#define S_GTarget1_sizeof 7 -#define S_GTarget1_ADDR 308 -#define S_GTarget1_ADDR_END 314 -#define S_GTarget1_sizeof 7 +#define S_Gtarget_DL1_ADDR 314 +#define S_Gtarget_DL1_ADDR_END 315 +#define S_Gtarget_DL1_sizeof 2 -#define S_Gtarget_DL1_ADDR 315 -#define S_Gtarget_DL1_ADDR_END 316 -#define S_Gtarget_DL1_sizeof 2 +#define S_Gtarget_DL2_ADDR 316 +#define S_Gtarget_DL2_ADDR_END 317 +#define S_Gtarget_DL2_sizeof 2 -#define S_Gtarget_DL2_ADDR 317 -#define S_Gtarget_DL2_ADDR_END 318 -#define S_Gtarget_DL2_sizeof 2 +#define S_Gtarget_Echo_ADDR 318 +#define S_Gtarget_Echo_ADDR_END 318 +#define S_Gtarget_Echo_sizeof 1 -#define S_Gtarget_Echo_ADDR 319 -#define S_Gtarget_Echo_ADDR_END 319 -#define S_Gtarget_Echo_sizeof 1 +#define S_Gtarget_SDT_ADDR 319 +#define S_Gtarget_SDT_ADDR_END 319 +#define S_Gtarget_SDT_sizeof 1 -#define S_Gtarget_SDT_ADDR 320 -#define S_Gtarget_SDT_ADDR_END 320 -#define S_Gtarget_SDT_sizeof 1 +#define S_Gtarget_VxRec_ADDR 320 +#define S_Gtarget_VxRec_ADDR_END 321 +#define S_Gtarget_VxRec_sizeof 2 -#define S_Gtarget_VxRec_ADDR 321 -#define S_Gtarget_VxRec_ADDR_END 322 -#define S_Gtarget_VxRec_sizeof 2 +#define S_Gtarget_UL_ADDR 322 +#define S_Gtarget_UL_ADDR_END 323 +#define S_Gtarget_UL_sizeof 2 -#define S_Gtarget_UL_ADDR 323 -#define S_Gtarget_UL_ADDR_END 324 -#define S_Gtarget_UL_sizeof 2 +#define S_Gtarget_unused_ADDR 324 +#define S_Gtarget_unused_ADDR_END 324 +#define S_Gtarget_unused_sizeof 1 -#define S_Gtarget_unused_ADDR 325 -#define S_Gtarget_unused_ADDR_END 325 -#define S_Gtarget_unused_sizeof 1 +#define S_GCurrent_ADDR 325 +#define S_GCurrent_ADDR_END 342 +#define S_GCurrent_sizeof 18 -#define S_GCurrent_ADDR 326 -#define S_GCurrent_ADDR_END 343 -#define S_GCurrent_sizeof 18 +#define S_GAIN_ONE_ADDR 343 +#define S_GAIN_ONE_ADDR_END 343 +#define S_GAIN_ONE_sizeof 1 -#define S_GAIN_ONE_ADDR 344 -#define S_GAIN_ONE_ADDR_END 344 -#define S_GAIN_ONE_sizeof 1 +#define S_Tones_ADDR 344 +#define S_Tones_ADDR_END 355 +#define S_Tones_sizeof 12 -#define S_Tones_ADDR 345 -#define S_Tones_ADDR_END 356 -#define S_Tones_sizeof 12 +#define S_VX_DL_ADDR 356 +#define S_VX_DL_ADDR_END 367 +#define S_VX_DL_sizeof 12 -#define S_VX_DL_ADDR 357 -#define S_VX_DL_ADDR_END 368 -#define S_VX_DL_sizeof 12 +#define S_MM_UL2_ADDR 368 +#define S_MM_UL2_ADDR_END 379 +#define S_MM_UL2_sizeof 12 -#define S_MM_UL2_ADDR 369 -#define S_MM_UL2_ADDR_END 380 -#define S_MM_UL2_sizeof 12 +#define S_MM_DL_ADDR 380 +#define S_MM_DL_ADDR_END 391 +#define S_MM_DL_sizeof 12 -#define S_MM_DL_ADDR 381 -#define S_MM_DL_ADDR_END 392 -#define S_MM_DL_sizeof 12 +#define S_DL1_M_Out_ADDR 392 +#define S_DL1_M_Out_ADDR_END 403 +#define S_DL1_M_Out_sizeof 12 -#define S_DL1_M_Out_ADDR 393 -#define S_DL1_M_Out_ADDR_END 404 -#define S_DL1_M_Out_sizeof 12 +#define S_DL2_M_Out_ADDR 404 +#define S_DL2_M_Out_ADDR_END 415 +#define S_DL2_M_Out_sizeof 12 -#define S_DL2_M_Out_ADDR 405 -#define S_DL2_M_Out_ADDR_END 416 -#define S_DL2_M_Out_sizeof 12 +#define S_Echo_M_Out_ADDR 416 +#define S_Echo_M_Out_ADDR_END 427 +#define S_Echo_M_Out_sizeof 12 -#define S_Echo_M_Out_ADDR 417 -#define S_Echo_M_Out_ADDR_END 428 -#define S_Echo_M_Out_sizeof 12 +#define S_SDT_M_Out_ADDR 428 +#define S_SDT_M_Out_ADDR_END 439 +#define S_SDT_M_Out_sizeof 12 -#define S_SDT_M_Out_ADDR 429 -#define S_SDT_M_Out_ADDR_END 440 -#define S_SDT_M_Out_sizeof 12 +#define S_VX_UL_ADDR 440 +#define S_VX_UL_ADDR_END 451 +#define S_VX_UL_sizeof 12 -#define S_VX_UL_ADDR 441 -#define S_VX_UL_ADDR_END 452 -#define S_VX_UL_sizeof 12 +#define S_VX_UL_M_ADDR 452 +#define S_VX_UL_M_ADDR_END 463 +#define S_VX_UL_M_sizeof 12 -#define S_VX_UL_M_ADDR 453 -#define S_VX_UL_M_ADDR_END 464 -#define S_VX_UL_M_sizeof 12 +#define S_BT_DL_ADDR 464 +#define S_BT_DL_ADDR_END 475 +#define S_BT_DL_sizeof 12 -#define S_BT_DL_ADDR 465 -#define S_BT_DL_ADDR_END 476 -#define S_BT_DL_sizeof 12 +#define S_BT_UL_ADDR 476 +#define S_BT_UL_ADDR_END 487 +#define S_BT_UL_sizeof 12 -#define S_BT_UL_ADDR 477 -#define S_BT_UL_ADDR_END 488 -#define S_BT_UL_sizeof 12 +#define S_BT_DL_8k_ADDR 488 +#define S_BT_DL_8k_ADDR_END 489 +#define S_BT_DL_8k_sizeof 2 -#define S_BT_DL_8k_ADDR 489 -#define S_BT_DL_8k_ADDR_END 490 -#define S_BT_DL_8k_sizeof 2 +#define S_BT_DL_16k_ADDR 490 +#define S_BT_DL_16k_ADDR_END 493 +#define S_BT_DL_16k_sizeof 4 -#define S_BT_DL_16k_ADDR 491 -#define S_BT_DL_16k_ADDR_END 494 -#define S_BT_DL_16k_sizeof 4 +#define S_BT_UL_8k_ADDR 494 +#define S_BT_UL_8k_ADDR_END 495 +#define S_BT_UL_8k_sizeof 2 -#define S_BT_UL_8k_ADDR 495 -#define S_BT_UL_8k_ADDR_END 496 -#define S_BT_UL_8k_sizeof 2 +#define S_BT_UL_16k_ADDR 496 +#define S_BT_UL_16k_ADDR_END 499 +#define S_BT_UL_16k_sizeof 4 -#define S_BT_UL_16k_ADDR 497 -#define S_BT_UL_16k_ADDR_END 500 -#define S_BT_UL_16k_sizeof 4 +#define S_SDT_F_ADDR 500 +#define S_SDT_F_ADDR_END 511 +#define S_SDT_F_sizeof 12 -#define S_SDT_F_ADDR 501 -#define S_SDT_F_ADDR_END 512 -#define S_SDT_F_sizeof 12 +#define S_SDT_F_data_ADDR 512 +#define S_SDT_F_data_ADDR_END 520 +#define S_SDT_F_data_sizeof 9 -#define S_SDT_F_data_ADDR 513 -#define S_SDT_F_data_ADDR_END 521 -#define S_SDT_F_data_sizeof 9 +#define S_MM_DL_OSR_ADDR 521 +#define S_MM_DL_OSR_ADDR_END 544 +#define S_MM_DL_OSR_sizeof 24 -#define S_MM_DL_OSR_ADDR 522 -#define S_MM_DL_OSR_ADDR_END 545 -#define S_MM_DL_OSR_sizeof 24 +#define S_24_zeros_ADDR 545 +#define S_24_zeros_ADDR_END 568 +#define S_24_zeros_sizeof 24 -#define S_24_zeros_ADDR 546 -#define S_24_zeros_ADDR_END 569 -#define S_24_zeros_sizeof 24 +#define S_DMIC1_ADDR 569 +#define S_DMIC1_ADDR_END 580 +#define S_DMIC1_sizeof 12 -#define S_DMIC1_ADDR 570 -#define S_DMIC1_ADDR_END 581 -#define S_DMIC1_sizeof 12 +#define S_DMIC2_ADDR 581 +#define S_DMIC2_ADDR_END 592 +#define S_DMIC2_sizeof 12 -#define S_DMIC2_ADDR 582 -#define S_DMIC2_ADDR_END 593 -#define S_DMIC2_sizeof 12 +#define S_DMIC3_ADDR 593 +#define S_DMIC3_ADDR_END 604 +#define S_DMIC3_sizeof 12 -#define S_DMIC3_ADDR 594 -#define S_DMIC3_ADDR_END 605 -#define S_DMIC3_sizeof 12 +#define S_AMIC_ADDR 605 +#define S_AMIC_ADDR_END 616 +#define S_AMIC_sizeof 12 -#define S_AMIC_ADDR 606 -#define S_AMIC_ADDR_END 617 -#define S_AMIC_sizeof 12 +#define S_EANC_FBK_in_ADDR 617 +#define S_EANC_FBK_in_ADDR_END 640 +#define S_EANC_FBK_in_sizeof 24 -#define S_EANC_FBK_in_ADDR 618 -#define S_EANC_FBK_in_ADDR_END 641 -#define S_EANC_FBK_in_sizeof 24 +#define S_EANC_FBK_out_ADDR 641 +#define S_EANC_FBK_out_ADDR_END 652 +#define S_EANC_FBK_out_sizeof 12 -#define S_EANC_FBK_out_ADDR 642 -#define S_EANC_FBK_out_ADDR_END 653 -#define S_EANC_FBK_out_sizeof 12 +#define S_DMIC1_L_ADDR 653 +#define S_DMIC1_L_ADDR_END 664 +#define S_DMIC1_L_sizeof 12 -#define S_DMIC1_L_ADDR 654 -#define S_DMIC1_L_ADDR_END 665 -#define S_DMIC1_L_sizeof 12 +#define S_DMIC1_R_ADDR 665 +#define S_DMIC1_R_ADDR_END 676 +#define S_DMIC1_R_sizeof 12 -#define S_DMIC1_R_ADDR 666 -#define S_DMIC1_R_ADDR_END 677 -#define S_DMIC1_R_sizeof 12 +#define S_DMIC2_L_ADDR 677 +#define S_DMIC2_L_ADDR_END 688 +#define S_DMIC2_L_sizeof 12 -#define S_DMIC2_L_ADDR 678 -#define S_DMIC2_L_ADDR_END 689 -#define S_DMIC2_L_sizeof 12 +#define S_DMIC2_R_ADDR 689 +#define S_DMIC2_R_ADDR_END 700 +#define S_DMIC2_R_sizeof 12 -#define S_DMIC2_R_ADDR 690 -#define S_DMIC2_R_ADDR_END 701 -#define S_DMIC2_R_sizeof 12 +#define S_DMIC3_L_ADDR 701 +#define S_DMIC3_L_ADDR_END 712 +#define S_DMIC3_L_sizeof 12 -#define S_DMIC3_L_ADDR 702 -#define S_DMIC3_L_ADDR_END 713 -#define S_DMIC3_L_sizeof 12 +#define S_DMIC3_R_ADDR 713 +#define S_DMIC3_R_ADDR_END 724 +#define S_DMIC3_R_sizeof 12 -#define S_DMIC3_R_ADDR 714 -#define S_DMIC3_R_ADDR_END 725 -#define S_DMIC3_R_sizeof 12 +#define S_BT_UL_L_ADDR 725 +#define S_BT_UL_L_ADDR_END 736 +#define S_BT_UL_L_sizeof 12 -#define S_BT_UL_L_ADDR 726 -#define S_BT_UL_L_ADDR_END 737 -#define S_BT_UL_L_sizeof 12 +#define S_BT_UL_R_ADDR 737 +#define S_BT_UL_R_ADDR_END 748 +#define S_BT_UL_R_sizeof 12 -#define S_BT_UL_R_ADDR 738 -#define S_BT_UL_R_ADDR_END 749 -#define S_BT_UL_R_sizeof 12 +#define S_AMIC_L_ADDR 749 +#define S_AMIC_L_ADDR_END 760 +#define S_AMIC_L_sizeof 12 -#define S_AMIC_L_ADDR 750 -#define S_AMIC_L_ADDR_END 761 -#define S_AMIC_L_sizeof 12 +#define S_AMIC_R_ADDR 761 +#define S_AMIC_R_ADDR_END 772 +#define S_AMIC_R_sizeof 12 -#define S_AMIC_R_ADDR 762 -#define S_AMIC_R_ADDR_END 773 -#define S_AMIC_R_sizeof 12 +#define S_EANC_FBK_L_ADDR 773 +#define S_EANC_FBK_L_ADDR_END 784 +#define S_EANC_FBK_L_sizeof 12 -#define S_EANC_FBK_L_ADDR 774 -#define S_EANC_FBK_L_ADDR_END 785 -#define S_EANC_FBK_L_sizeof 12 +#define S_EANC_FBK_R_ADDR 785 +#define S_EANC_FBK_R_ADDR_END 796 +#define S_EANC_FBK_R_sizeof 12 -#define S_EANC_FBK_R_ADDR 786 -#define S_EANC_FBK_R_ADDR_END 797 -#define S_EANC_FBK_R_sizeof 12 +#define S_EchoRef_L_ADDR 797 +#define S_EchoRef_L_ADDR_END 808 +#define S_EchoRef_L_sizeof 12 -#define S_EchoRef_L_ADDR 798 -#define S_EchoRef_L_ADDR_END 809 -#define S_EchoRef_L_sizeof 12 +#define S_EchoRef_R_ADDR 809 +#define S_EchoRef_R_ADDR_END 820 +#define S_EchoRef_R_sizeof 12 -#define S_EchoRef_R_ADDR 810 -#define S_EchoRef_R_ADDR_END 821 -#define S_EchoRef_R_sizeof 12 +#define S_MM_DL_L_ADDR 821 +#define S_MM_DL_L_ADDR_END 832 +#define S_MM_DL_L_sizeof 12 -#define S_MM_DL_L_ADDR 822 -#define S_MM_DL_L_ADDR_END 833 -#define S_MM_DL_L_sizeof 12 +#define S_MM_DL_R_ADDR 833 +#define S_MM_DL_R_ADDR_END 844 +#define S_MM_DL_R_sizeof 12 -#define S_MM_DL_R_ADDR 834 -#define S_MM_DL_R_ADDR_END 845 -#define S_MM_DL_R_sizeof 12 +#define S_MM_UL_ADDR 845 +#define S_MM_UL_ADDR_END 964 +#define S_MM_UL_sizeof 120 -#define S_MM_UL_ADDR 846 -#define S_MM_UL_ADDR_END 965 -#define S_MM_UL_sizeof 120 +#define S_AMIC_96k_ADDR 965 +#define S_AMIC_96k_ADDR_END 988 +#define S_AMIC_96k_sizeof 24 -#define S_AMIC_96k_ADDR 966 -#define S_AMIC_96k_ADDR_END 989 -#define S_AMIC_96k_sizeof 24 +#define S_DMIC0_96k_ADDR 989 +#define S_DMIC0_96k_ADDR_END 1012 +#define S_DMIC0_96k_sizeof 24 -#define S_DMIC0_96k_ADDR 990 -#define S_DMIC0_96k_ADDR_END 1013 -#define S_DMIC0_96k_sizeof 24 +#define S_DMIC1_96k_ADDR 1013 +#define S_DMIC1_96k_ADDR_END 1036 +#define S_DMIC1_96k_sizeof 24 -#define S_DMIC1_96k_ADDR 1014 -#define S_DMIC1_96k_ADDR_END 1037 -#define S_DMIC1_96k_sizeof 24 +#define S_DMIC2_96k_ADDR 1037 +#define S_DMIC2_96k_ADDR_END 1060 +#define S_DMIC2_96k_sizeof 24 -#define S_DMIC2_96k_ADDR 1038 -#define S_DMIC2_96k_ADDR_END 1061 -#define S_DMIC2_96k_sizeof 24 +#define S_UL_VX_UL_48_8K_ADDR 1061 +#define S_UL_VX_UL_48_8K_ADDR_END 1072 +#define S_UL_VX_UL_48_8K_sizeof 12 -#define S_UL_VX_UL_48_8K_ADDR 1062 -#define S_UL_VX_UL_48_8K_ADDR_END 1073 -#define S_UL_VX_UL_48_8K_sizeof 12 +#define S_UL_VX_UL_48_16K_ADDR 1073 +#define S_UL_VX_UL_48_16K_ADDR_END 1084 +#define S_UL_VX_UL_48_16K_sizeof 12 -#define S_UL_VX_UL_48_16K_ADDR 1074 -#define S_UL_VX_UL_48_16K_ADDR_END 1085 -#define S_UL_VX_UL_48_16K_sizeof 12 +#define S_UL_MIC_48K_ADDR 1085 +#define S_UL_MIC_48K_ADDR_END 1096 +#define S_UL_MIC_48K_sizeof 12 -#define S_UL_MIC_48K_ADDR 1086 -#define S_UL_MIC_48K_ADDR_END 1097 -#define S_UL_MIC_48K_sizeof 12 +#define S_Voice_8k_UL_ADDR 1097 +#define S_Voice_8k_UL_ADDR_END 1099 +#define S_Voice_8k_UL_sizeof 3 -#define S_Voice_8k_UL_ADDR 1098 -#define S_Voice_8k_UL_ADDR_END 1100 -#define S_Voice_8k_UL_sizeof 3 +#define S_Voice_8k_DL_ADDR 1100 +#define S_Voice_8k_DL_ADDR_END 1101 +#define S_Voice_8k_DL_sizeof 2 -#define S_Voice_8k_DL_ADDR 1101 -#define S_Voice_8k_DL_ADDR_END 1102 -#define S_Voice_8k_DL_sizeof 2 +#define S_McPDM_Out1_ADDR 1102 +#define S_McPDM_Out1_ADDR_END 1125 +#define S_McPDM_Out1_sizeof 24 -#define S_McPDM_Out1_ADDR 1103 -#define S_McPDM_Out1_ADDR_END 1126 -#define S_McPDM_Out1_sizeof 24 +#define S_McPDM_Out2_ADDR 1126 +#define S_McPDM_Out2_ADDR_END 1149 +#define S_McPDM_Out2_sizeof 24 -#define S_McPDM_Out2_ADDR 1127 -#define S_McPDM_Out2_ADDR_END 1150 -#define S_McPDM_Out2_sizeof 24 +#define S_McPDM_Out3_ADDR 1150 +#define S_McPDM_Out3_ADDR_END 1173 +#define S_McPDM_Out3_sizeof 24 -#define S_McPDM_Out3_ADDR 1151 -#define S_McPDM_Out3_ADDR_END 1174 -#define S_McPDM_Out3_sizeof 24 +#define S_Voice_16k_UL_ADDR 1174 +#define S_Voice_16k_UL_ADDR_END 1178 +#define S_Voice_16k_UL_sizeof 5 -#define S_Voice_16k_UL_ADDR 1175 -#define S_Voice_16k_UL_ADDR_END 1179 -#define S_Voice_16k_UL_sizeof 5 +#define S_Voice_16k_DL_ADDR 1179 +#define S_Voice_16k_DL_ADDR_END 1182 +#define S_Voice_16k_DL_sizeof 4 -#define S_Voice_16k_DL_ADDR 1180 -#define S_Voice_16k_DL_ADDR_END 1183 -#define S_Voice_16k_DL_sizeof 4 +#define S_XinASRC_DL_VX_ADDR 1183 +#define S_XinASRC_DL_VX_ADDR_END 1222 +#define S_XinASRC_DL_VX_sizeof 40 -#define S_XinASRC_DL_VX_ADDR 1184 -#define S_XinASRC_DL_VX_ADDR_END 1223 -#define S_XinASRC_DL_VX_sizeof 40 +#define S_XinASRC_UL_VX_ADDR 1223 +#define S_XinASRC_UL_VX_ADDR_END 1262 +#define S_XinASRC_UL_VX_sizeof 40 -#define S_XinASRC_UL_VX_ADDR 1224 -#define S_XinASRC_UL_VX_ADDR_END 1263 -#define S_XinASRC_UL_VX_sizeof 40 +#define S_XinASRC_DL_MM_ADDR 1263 +#define S_XinASRC_DL_MM_ADDR_END 1302 +#define S_XinASRC_DL_MM_sizeof 40 -#define S_XinASRC_DL_MM_ADDR 1264 -#define S_XinASRC_DL_MM_ADDR_END 1303 -#define S_XinASRC_DL_MM_sizeof 40 +#define S_VX_REC_ADDR 1303 +#define S_VX_REC_ADDR_END 1314 +#define S_VX_REC_sizeof 12 -#define S_VX_REC_ADDR 1304 -#define S_VX_REC_ADDR_END 1315 -#define S_VX_REC_sizeof 12 +#define S_VX_REC_L_ADDR 1315 +#define S_VX_REC_L_ADDR_END 1326 +#define S_VX_REC_L_sizeof 12 -#define S_VX_REC_L_ADDR 1316 -#define S_VX_REC_L_ADDR_END 1327 -#define S_VX_REC_L_sizeof 12 +#define S_VX_REC_R_ADDR 1327 +#define S_VX_REC_R_ADDR_END 1338 +#define S_VX_REC_R_sizeof 12 -#define S_VX_REC_R_ADDR 1328 -#define S_VX_REC_R_ADDR_END 1339 -#define S_VX_REC_R_sizeof 12 +#define S_DL2_M_L_ADDR 1339 +#define S_DL2_M_L_ADDR_END 1350 +#define S_DL2_M_L_sizeof 12 -#define S_DL2_M_L_ADDR 1340 -#define S_DL2_M_L_ADDR_END 1351 -#define S_DL2_M_L_sizeof 12 +#define S_DL2_M_R_ADDR 1351 +#define S_DL2_M_R_ADDR_END 1362 +#define S_DL2_M_R_sizeof 12 -#define S_DL2_M_R_ADDR 1352 -#define S_DL2_M_R_ADDR_END 1363 -#define S_DL2_M_R_sizeof 12 +#define S_DL2_M_LR_EQ_data_ADDR 1363 +#define S_DL2_M_LR_EQ_data_ADDR_END 1387 +#define S_DL2_M_LR_EQ_data_sizeof 25 -#define S_DL2_M_LR_EQ_data_ADDR 1364 -#define S_DL2_M_LR_EQ_data_ADDR_END 1388 -#define S_DL2_M_LR_EQ_data_sizeof 25 +#define S_DL1_M_EQ_data_ADDR 1388 +#define S_DL1_M_EQ_data_ADDR_END 1412 +#define S_DL1_M_EQ_data_sizeof 25 -#define S_DL1_M_EQ_data_ADDR 1389 -#define S_DL1_M_EQ_data_ADDR_END 1413 -#define S_DL1_M_EQ_data_sizeof 25 +#define S_EARP_48_96_LP_data_ADDR 1413 +#define S_EARP_48_96_LP_data_ADDR_END 1427 +#define S_EARP_48_96_LP_data_sizeof 15 -#define S_EARP_48_96_LP_data_ADDR 1414 -#define S_EARP_48_96_LP_data_ADDR_END 1428 -#define S_EARP_48_96_LP_data_sizeof 15 +#define S_IHF_48_96_LP_data_ADDR 1428 +#define S_IHF_48_96_LP_data_ADDR_END 1442 +#define S_IHF_48_96_LP_data_sizeof 15 -#define S_IHF_48_96_LP_data_ADDR 1429 -#define S_IHF_48_96_LP_data_ADDR_END 1443 -#define S_IHF_48_96_LP_data_sizeof 15 +#define S_VX_UL_8_TEMP_ADDR 1443 +#define S_VX_UL_8_TEMP_ADDR_END 1444 +#define S_VX_UL_8_TEMP_sizeof 2 -#define S_VX_UL_8_TEMP_ADDR 1444 -#define S_VX_UL_8_TEMP_ADDR_END 1445 -#define S_VX_UL_8_TEMP_sizeof 2 +#define S_VX_UL_16_TEMP_ADDR 1445 +#define S_VX_UL_16_TEMP_ADDR_END 1448 +#define S_VX_UL_16_TEMP_sizeof 4 -#define S_VX_UL_16_TEMP_ADDR 1446 -#define S_VX_UL_16_TEMP_ADDR_END 1449 -#define S_VX_UL_16_TEMP_sizeof 4 +#define S_VX_DL_8_48_LP_data_ADDR 1449 +#define S_VX_DL_8_48_LP_data_ADDR_END 1459 +#define S_VX_DL_8_48_LP_data_sizeof 11 -#define S_VX_DL_8_48_LP_data_ADDR 1450 -#define S_VX_DL_8_48_LP_data_ADDR_END 1460 -#define S_VX_DL_8_48_LP_data_sizeof 11 +#define S_VX_DL_8_48_HP_data_ADDR 1460 +#define S_VX_DL_8_48_HP_data_ADDR_END 1466 +#define S_VX_DL_8_48_HP_data_sizeof 7 -#define S_VX_DL_8_48_HP_data_ADDR 1461 -#define S_VX_DL_8_48_HP_data_ADDR_END 1467 -#define S_VX_DL_8_48_HP_data_sizeof 7 +#define S_VX_DL_16_48_LP_data_ADDR 1467 +#define S_VX_DL_16_48_LP_data_ADDR_END 1477 +#define S_VX_DL_16_48_LP_data_sizeof 11 -#define S_VX_DL_16_48_LP_data_ADDR 1468 -#define S_VX_DL_16_48_LP_data_ADDR_END 1478 -#define S_VX_DL_16_48_LP_data_sizeof 11 +#define S_VX_DL_16_48_HP_data_ADDR 1478 +#define S_VX_DL_16_48_HP_data_ADDR_END 1482 +#define S_VX_DL_16_48_HP_data_sizeof 5 -#define S_VX_DL_16_48_HP_data_ADDR 1479 -#define S_VX_DL_16_48_HP_data_ADDR_END 1483 -#define S_VX_DL_16_48_HP_data_sizeof 5 +#define S_VX_UL_48_8_LP_data_ADDR 1483 +#define S_VX_UL_48_8_LP_data_ADDR_END 1493 +#define S_VX_UL_48_8_LP_data_sizeof 11 -#define S_VX_UL_48_8_LP_data_ADDR 1484 -#define S_VX_UL_48_8_LP_data_ADDR_END 1494 -#define S_VX_UL_48_8_LP_data_sizeof 11 +#define S_VX_UL_48_8_HP_data_ADDR 1494 +#define S_VX_UL_48_8_HP_data_ADDR_END 1500 +#define S_VX_UL_48_8_HP_data_sizeof 7 -#define S_VX_UL_48_8_HP_data_ADDR 1495 -#define S_VX_UL_48_8_HP_data_ADDR_END 1501 -#define S_VX_UL_48_8_HP_data_sizeof 7 +#define S_VX_UL_48_16_LP_data_ADDR 1501 +#define S_VX_UL_48_16_LP_data_ADDR_END 1511 +#define S_VX_UL_48_16_LP_data_sizeof 11 -#define S_VX_UL_48_16_LP_data_ADDR 1502 -#define S_VX_UL_48_16_LP_data_ADDR_END 1512 -#define S_VX_UL_48_16_LP_data_sizeof 11 +#define S_VX_UL_48_16_HP_data_ADDR 1512 +#define S_VX_UL_48_16_HP_data_ADDR_END 1518 +#define S_VX_UL_48_16_HP_data_sizeof 7 -#define S_VX_UL_48_16_HP_data_ADDR 1513 -#define S_VX_UL_48_16_HP_data_ADDR_END 1519 -#define S_VX_UL_48_16_HP_data_sizeof 7 +#define S_BT_UL_8_48_LP_data_ADDR 1519 +#define S_BT_UL_8_48_LP_data_ADDR_END 1529 +#define S_BT_UL_8_48_LP_data_sizeof 11 -#define S_BT_UL_8_48_LP_data_ADDR 1520 -#define S_BT_UL_8_48_LP_data_ADDR_END 1530 -#define S_BT_UL_8_48_LP_data_sizeof 11 +#define S_BT_UL_8_48_HP_data_ADDR 1530 +#define S_BT_UL_8_48_HP_data_ADDR_END 1536 +#define S_BT_UL_8_48_HP_data_sizeof 7 -#define S_BT_UL_8_48_HP_data_ADDR 1531 -#define S_BT_UL_8_48_HP_data_ADDR_END 1537 -#define S_BT_UL_8_48_HP_data_sizeof 7 +#define S_BT_UL_16_48_LP_data_ADDR 1537 +#define S_BT_UL_16_48_LP_data_ADDR_END 1547 +#define S_BT_UL_16_48_LP_data_sizeof 11 -#define S_BT_UL_16_48_LP_data_ADDR 1538 -#define S_BT_UL_16_48_LP_data_ADDR_END 1548 -#define S_BT_UL_16_48_LP_data_sizeof 11 +#define S_BT_UL_16_48_HP_data_ADDR 1548 +#define S_BT_UL_16_48_HP_data_ADDR_END 1552 +#define S_BT_UL_16_48_HP_data_sizeof 5 -#define S_BT_UL_16_48_HP_data_ADDR 1549 -#define S_BT_UL_16_48_HP_data_ADDR_END 1553 -#define S_BT_UL_16_48_HP_data_sizeof 5 +#define S_BT_DL_48_8_LP_data_ADDR 1553 +#define S_BT_DL_48_8_LP_data_ADDR_END 1563 +#define S_BT_DL_48_8_LP_data_sizeof 11 -#define S_BT_DL_48_8_LP_data_ADDR 1554 -#define S_BT_DL_48_8_LP_data_ADDR_END 1564 -#define S_BT_DL_48_8_LP_data_sizeof 11 +#define S_BT_DL_48_8_HP_data_ADDR 1564 +#define S_BT_DL_48_8_HP_data_ADDR_END 1570 +#define S_BT_DL_48_8_HP_data_sizeof 7 -#define S_BT_DL_48_8_HP_data_ADDR 1565 -#define S_BT_DL_48_8_HP_data_ADDR_END 1571 -#define S_BT_DL_48_8_HP_data_sizeof 7 +#define S_BT_DL_48_16_LP_data_ADDR 1571 +#define S_BT_DL_48_16_LP_data_ADDR_END 1581 +#define S_BT_DL_48_16_LP_data_sizeof 11 -#define S_BT_DL_48_16_LP_data_ADDR 1572 -#define S_BT_DL_48_16_LP_data_ADDR_END 1582 -#define S_BT_DL_48_16_LP_data_sizeof 11 +#define S_BT_DL_48_16_HP_data_ADDR 1582 +#define S_BT_DL_48_16_HP_data_ADDR_END 1586 +#define S_BT_DL_48_16_HP_data_sizeof 5 -#define S_BT_DL_48_16_HP_data_ADDR 1583 -#define S_BT_DL_48_16_HP_data_ADDR_END 1587 -#define S_BT_DL_48_16_HP_data_sizeof 5 +#define S_ECHO_REF_48_8_LP_data_ADDR 1587 +#define S_ECHO_REF_48_8_LP_data_ADDR_END 1597 +#define S_ECHO_REF_48_8_LP_data_sizeof 11 -#define S_ECHO_REF_48_8_LP_data_ADDR 1588 -#define S_ECHO_REF_48_8_LP_data_ADDR_END 1598 -#define S_ECHO_REF_48_8_LP_data_sizeof 11 +#define S_ECHO_REF_48_8_HP_data_ADDR 1598 +#define S_ECHO_REF_48_8_HP_data_ADDR_END 1604 +#define S_ECHO_REF_48_8_HP_data_sizeof 7 -#define S_ECHO_REF_48_8_HP_data_ADDR 1599 -#define S_ECHO_REF_48_8_HP_data_ADDR_END 1605 -#define S_ECHO_REF_48_8_HP_data_sizeof 7 +#define S_ECHO_REF_48_16_LP_data_ADDR 1605 +#define S_ECHO_REF_48_16_LP_data_ADDR_END 1615 +#define S_ECHO_REF_48_16_LP_data_sizeof 11 -#define S_ECHO_REF_48_16_LP_data_ADDR 1606 -#define S_ECHO_REF_48_16_LP_data_ADDR_END 1616 -#define S_ECHO_REF_48_16_LP_data_sizeof 11 +#define S_ECHO_REF_48_16_HP_data_ADDR 1616 +#define S_ECHO_REF_48_16_HP_data_ADDR_END 1620 +#define S_ECHO_REF_48_16_HP_data_sizeof 5 -#define S_ECHO_REF_48_16_HP_data_ADDR 1617 -#define S_ECHO_REF_48_16_HP_data_ADDR_END 1621 -#define S_ECHO_REF_48_16_HP_data_sizeof 5 +#define S_EANC_IIR_data_ADDR 1621 +#define S_EANC_IIR_data_ADDR_END 1637 +#define S_EANC_IIR_data_sizeof 17 -#define S_EANC_IIR_data_ADDR 1622 -#define S_EANC_IIR_data_ADDR_END 1638 -#define S_EANC_IIR_data_sizeof 17 +#define S_EANC_SignalTemp_ADDR 1638 +#define S_EANC_SignalTemp_ADDR_END 1658 +#define S_EANC_SignalTemp_sizeof 21 -#define S_EANC_SignalTemp_ADDR 1639 -#define S_EANC_SignalTemp_ADDR_END 1659 -#define S_EANC_SignalTemp_sizeof 21 +#define S_EANC_Input_ADDR 1659 +#define S_EANC_Input_ADDR_END 1659 +#define S_EANC_Input_sizeof 1 -#define S_EANC_Input_ADDR 1660 -#define S_EANC_Input_ADDR_END 1660 -#define S_EANC_Input_sizeof 1 +#define S_EANC_Output_ADDR 1660 +#define S_EANC_Output_ADDR_END 1660 +#define S_EANC_Output_sizeof 1 -#define S_EANC_Output_ADDR 1661 -#define S_EANC_Output_ADDR_END 1661 -#define S_EANC_Output_sizeof 1 +#define S_APS_IIRmem1_ADDR 1661 +#define S_APS_IIRmem1_ADDR_END 1669 +#define S_APS_IIRmem1_sizeof 9 -#define S_APS_IIRmem1_ADDR 1662 -#define S_APS_IIRmem1_ADDR_END 1670 -#define S_APS_IIRmem1_sizeof 9 +#define S_APS_M_IIRmem2_ADDR 1670 +#define S_APS_M_IIRmem2_ADDR_END 1672 +#define S_APS_M_IIRmem2_sizeof 3 -#define S_APS_M_IIRmem2_ADDR 1671 -#define S_APS_M_IIRmem2_ADDR_END 1673 -#define S_APS_M_IIRmem2_sizeof 3 +#define S_APS_C_IIRmem2_ADDR 1673 +#define S_APS_C_IIRmem2_ADDR_END 1675 +#define S_APS_C_IIRmem2_sizeof 3 -#define S_APS_C_IIRmem2_ADDR 1674 -#define S_APS_C_IIRmem2_ADDR_END 1676 -#define S_APS_C_IIRmem2_sizeof 3 +#define S_APS_DL1_OutSamples_ADDR 1676 +#define S_APS_DL1_OutSamples_ADDR_END 1677 +#define S_APS_DL1_OutSamples_sizeof 2 -#define S_APS_DL1_OutSamples_ADDR 1677 -#define S_APS_DL1_OutSamples_ADDR_END 1678 -#define S_APS_DL1_OutSamples_sizeof 2 +#define S_APS_DL1_COIL_OutSamples_ADDR 1678 +#define S_APS_DL1_COIL_OutSamples_ADDR_END 1679 +#define S_APS_DL1_COIL_OutSamples_sizeof 2 -#define S_APS_DL1_COIL_OutSamples_ADDR 1679 -#define S_APS_DL1_COIL_OutSamples_ADDR_END 1680 -#define S_APS_DL1_COIL_OutSamples_sizeof 2 +#define S_APS_DL2_L_OutSamples_ADDR 1680 +#define S_APS_DL2_L_OutSamples_ADDR_END 1681 +#define S_APS_DL2_L_OutSamples_sizeof 2 -#define S_APS_DL2_L_OutSamples_ADDR 1681 -#define S_APS_DL2_L_OutSamples_ADDR_END 1682 -#define S_APS_DL2_L_OutSamples_sizeof 2 +#define S_APS_DL2_L_COIL_OutSamples_ADDR 1682 +#define S_APS_DL2_L_COIL_OutSamples_ADDR_END 1683 +#define S_APS_DL2_L_COIL_OutSamples_sizeof 2 -#define S_APS_DL2_L_COIL_OutSamples_ADDR 1683 -#define S_APS_DL2_L_COIL_OutSamples_ADDR_END 1684 -#define S_APS_DL2_L_COIL_OutSamples_sizeof 2 +#define S_APS_DL2_R_OutSamples_ADDR 1684 +#define S_APS_DL2_R_OutSamples_ADDR_END 1685 +#define S_APS_DL2_R_OutSamples_sizeof 2 -#define S_APS_DL2_R_OutSamples_ADDR 1685 -#define S_APS_DL2_R_OutSamples_ADDR_END 1686 -#define S_APS_DL2_R_OutSamples_sizeof 2 +#define S_APS_DL2_R_COIL_OutSamples_ADDR 1686 +#define S_APS_DL2_R_COIL_OutSamples_ADDR_END 1687 +#define S_APS_DL2_R_COIL_OutSamples_sizeof 2 -#define S_APS_DL2_R_COIL_OutSamples_ADDR 1687 -#define S_APS_DL2_R_COIL_OutSamples_ADDR_END 1688 -#define S_APS_DL2_R_COIL_OutSamples_sizeof 2 +#define S_XinASRC_ECHO_REF_ADDR 1688 +#define S_XinASRC_ECHO_REF_ADDR_END 1727 +#define S_XinASRC_ECHO_REF_sizeof 40 -#define S_XinASRC_ECHO_REF_ADDR 1689 -#define S_XinASRC_ECHO_REF_ADDR_END 1728 -#define S_XinASRC_ECHO_REF_sizeof 40 +#define S_ECHO_REF_16K_ADDR 1728 +#define S_ECHO_REF_16K_ADDR_END 1732 +#define S_ECHO_REF_16K_sizeof 5 -#define S_ECHO_REF_16K_ADDR 1729 -#define S_ECHO_REF_16K_ADDR_END 1733 -#define S_ECHO_REF_16K_sizeof 5 +#define S_ECHO_REF_8K_ADDR 1733 +#define S_ECHO_REF_8K_ADDR_END 1735 +#define S_ECHO_REF_8K_sizeof 3 -#define S_ECHO_REF_8K_ADDR 1734 -#define S_ECHO_REF_8K_ADDR_END 1736 -#define S_ECHO_REF_8K_sizeof 3 +#define S_DL1_EQ_ADDR 1736 +#define S_DL1_EQ_ADDR_END 1747 +#define S_DL1_EQ_sizeof 12 -#define S_DL1_EQ_ADDR 1737 -#define S_DL1_EQ_ADDR_END 1748 -#define S_DL1_EQ_sizeof 12 +#define S_DL2_EQ_ADDR 1748 +#define S_DL2_EQ_ADDR_END 1759 +#define S_DL2_EQ_sizeof 12 -#define S_DL2_EQ_ADDR 1749 -#define S_DL2_EQ_ADDR_END 1760 -#define S_DL2_EQ_sizeof 12 +#define S_DL1_GAIN_out_ADDR 1760 +#define S_DL1_GAIN_out_ADDR_END 1771 +#define S_DL1_GAIN_out_sizeof 12 -#define S_DL1_GAIN_out_ADDR 1761 -#define S_DL1_GAIN_out_ADDR_END 1772 -#define S_DL1_GAIN_out_sizeof 12 +#define S_DL2_GAIN_out_ADDR 1772 +#define S_DL2_GAIN_out_ADDR_END 1783 +#define S_DL2_GAIN_out_sizeof 12 -#define S_DL2_GAIN_out_ADDR 1773 -#define S_DL2_GAIN_out_ADDR_END 1784 -#define S_DL2_GAIN_out_sizeof 12 +#define S_APS_DL2_L_IIRmem1_ADDR 1784 +#define S_APS_DL2_L_IIRmem1_ADDR_END 1792 +#define S_APS_DL2_L_IIRmem1_sizeof 9 -#define S_APS_DL2_L_IIRmem1_ADDR 1785 -#define S_APS_DL2_L_IIRmem1_ADDR_END 1793 -#define S_APS_DL2_L_IIRmem1_sizeof 9 +#define S_APS_DL2_R_IIRmem1_ADDR 1793 +#define S_APS_DL2_R_IIRmem1_ADDR_END 1801 +#define S_APS_DL2_R_IIRmem1_sizeof 9 -#define S_APS_DL2_R_IIRmem1_ADDR 1794 -#define S_APS_DL2_R_IIRmem1_ADDR_END 1802 -#define S_APS_DL2_R_IIRmem1_sizeof 9 +#define S_APS_DL2_L_M_IIRmem2_ADDR 1802 +#define S_APS_DL2_L_M_IIRmem2_ADDR_END 1804 +#define S_APS_DL2_L_M_IIRmem2_sizeof 3 -#define S_APS_DL2_L_M_IIRmem2_ADDR 1803 -#define S_APS_DL2_L_M_IIRmem2_ADDR_END 1805 -#define S_APS_DL2_L_M_IIRmem2_sizeof 3 +#define S_APS_DL2_R_M_IIRmem2_ADDR 1805 +#define S_APS_DL2_R_M_IIRmem2_ADDR_END 1807 +#define S_APS_DL2_R_M_IIRmem2_sizeof 3 -#define S_APS_DL2_R_M_IIRmem2_ADDR 1806 -#define S_APS_DL2_R_M_IIRmem2_ADDR_END 1808 -#define S_APS_DL2_R_M_IIRmem2_sizeof 3 +#define S_APS_DL2_L_C_IIRmem2_ADDR 1808 +#define S_APS_DL2_L_C_IIRmem2_ADDR_END 1810 +#define S_APS_DL2_L_C_IIRmem2_sizeof 3 -#define S_APS_DL2_L_C_IIRmem2_ADDR 1809 -#define S_APS_DL2_L_C_IIRmem2_ADDR_END 1811 -#define S_APS_DL2_L_C_IIRmem2_sizeof 3 +#define S_APS_DL2_R_C_IIRmem2_ADDR 1811 +#define S_APS_DL2_R_C_IIRmem2_ADDR_END 1813 +#define S_APS_DL2_R_C_IIRmem2_sizeof 3 -#define S_APS_DL2_R_C_IIRmem2_ADDR 1812 -#define S_APS_DL2_R_C_IIRmem2_ADDR_END 1814 -#define S_APS_DL2_R_C_IIRmem2_sizeof 3 +#define S_DL1_APS_ADDR 1814 +#define S_DL1_APS_ADDR_END 1825 +#define S_DL1_APS_sizeof 12 -#define S_DL1_APS_ADDR 1815 -#define S_DL1_APS_ADDR_END 1826 -#define S_DL1_APS_sizeof 12 +#define S_DL2_L_APS_ADDR 1826 +#define S_DL2_L_APS_ADDR_END 1837 +#define S_DL2_L_APS_sizeof 12 -#define S_DL2_L_APS_ADDR 1827 -#define S_DL2_L_APS_ADDR_END 1838 -#define S_DL2_L_APS_sizeof 12 +#define S_DL2_R_APS_ADDR 1838 +#define S_DL2_R_APS_ADDR_END 1849 +#define S_DL2_R_APS_sizeof 12 -#define S_DL2_R_APS_ADDR 1839 -#define S_DL2_R_APS_ADDR_END 1850 -#define S_DL2_R_APS_sizeof 12 +#define S_APS_DL1_EQ_data_ADDR 1850 +#define S_APS_DL1_EQ_data_ADDR_END 1858 +#define S_APS_DL1_EQ_data_sizeof 9 -#define S_APS_DL1_EQ_data_ADDR 1851 -#define S_APS_DL1_EQ_data_ADDR_END 1859 -#define S_APS_DL1_EQ_data_sizeof 9 +#define S_APS_DL2_EQ_data_ADDR 1859 +#define S_APS_DL2_EQ_data_ADDR_END 1867 +#define S_APS_DL2_EQ_data_sizeof 9 -#define S_APS_DL2_EQ_data_ADDR 1860 -#define S_APS_DL2_EQ_data_ADDR_END 1868 -#define S_APS_DL2_EQ_data_sizeof 9 +#define S_DC_DCvalue_ADDR 1868 +#define S_DC_DCvalue_ADDR_END 1868 +#define S_DC_DCvalue_sizeof 1 -#define S_DC_DCvalue_ADDR 1869 -#define S_DC_DCvalue_ADDR_END 1869 -#define S_DC_DCvalue_sizeof 1 +#define S_VIBRA_ADDR 1869 +#define S_VIBRA_ADDR_END 1874 +#define S_VIBRA_sizeof 6 -#define S_VIBRA_ADDR 1870 -#define S_VIBRA_ADDR_END 1875 -#define S_VIBRA_sizeof 6 +#define S_Vibra2_in_ADDR 1875 +#define S_Vibra2_in_ADDR_END 1880 +#define S_Vibra2_in_sizeof 6 -#define S_Vibra2_in_ADDR 1876 -#define S_Vibra2_in_ADDR_END 1881 -#define S_Vibra2_in_sizeof 6 +#define S_Vibra2_addr_ADDR 1881 +#define S_Vibra2_addr_ADDR_END 1881 +#define S_Vibra2_addr_sizeof 1 -#define S_Vibra2_addr_ADDR 1882 -#define S_Vibra2_addr_ADDR_END 1882 -#define S_Vibra2_addr_sizeof 1 +#define S_VibraCtrl_forRightSM_ADDR 1882 +#define S_VibraCtrl_forRightSM_ADDR_END 1905 +#define S_VibraCtrl_forRightSM_sizeof 24 -#define S_VibraCtrl_forRightSM_ADDR 1883 -#define S_VibraCtrl_forRightSM_ADDR_END 1906 -#define S_VibraCtrl_forRightSM_sizeof 24 +#define S_Rnoise_mem_ADDR 1906 +#define S_Rnoise_mem_ADDR_END 1906 +#define S_Rnoise_mem_sizeof 1 -#define S_Rnoise_mem_ADDR 1907 -#define S_Rnoise_mem_ADDR_END 1907 -#define S_Rnoise_mem_sizeof 1 +#define S_Ctrl_ADDR 1907 +#define S_Ctrl_ADDR_END 1924 +#define S_Ctrl_sizeof 18 -#define S_Ctrl_ADDR 1908 -#define S_Ctrl_ADDR_END 1925 -#define S_Ctrl_sizeof 18 +#define S_Vibra1_in_ADDR 1925 +#define S_Vibra1_in_ADDR_END 1930 +#define S_Vibra1_in_sizeof 6 -#define S_Vibra1_in_ADDR 1926 -#define S_Vibra1_in_ADDR_END 1931 -#define S_Vibra1_in_sizeof 6 +#define S_Vibra1_temp_ADDR 1931 +#define S_Vibra1_temp_ADDR_END 1954 +#define S_Vibra1_temp_sizeof 24 -#define S_Vibra1_temp_ADDR 1932 -#define S_Vibra1_temp_ADDR_END 1955 -#define S_Vibra1_temp_sizeof 24 +#define S_VibraCtrl_forLeftSM_ADDR 1955 +#define S_VibraCtrl_forLeftSM_ADDR_END 1978 +#define S_VibraCtrl_forLeftSM_sizeof 24 -#define S_VibraCtrl_forLeftSM_ADDR 1956 -#define S_VibraCtrl_forLeftSM_ADDR_END 1979 -#define S_VibraCtrl_forLeftSM_sizeof 24 +#define S_Vibra1_mem_ADDR 1979 +#define S_Vibra1_mem_ADDR_END 1989 +#define S_Vibra1_mem_sizeof 11 -#define S_Vibra1_mem_ADDR 1980 -#define S_Vibra1_mem_ADDR_END 1990 -#define S_Vibra1_mem_sizeof 11 +#define S_VibraCtrl_Stereo_ADDR 1990 +#define S_VibraCtrl_Stereo_ADDR_END 2013 +#define S_VibraCtrl_Stereo_sizeof 24 -#define S_VibraCtrl_Stereo_ADDR 1991 -#define S_VibraCtrl_Stereo_ADDR_END 2014 -#define S_VibraCtrl_Stereo_sizeof 24 +#define S_AMIC_96_48_data_ADDR 2014 +#define S_AMIC_96_48_data_ADDR_END 2032 +#define S_AMIC_96_48_data_sizeof 19 -#define S_AMIC_96_48_data_ADDR 2015 -#define S_AMIC_96_48_data_ADDR_END 2033 -#define S_AMIC_96_48_data_sizeof 19 +#define S_DMIC0_96_48_data_ADDR 2033 +#define S_DMIC0_96_48_data_ADDR_END 2051 +#define S_DMIC0_96_48_data_sizeof 19 -#define S_DMIC0_96_48_data_ADDR 2034 -#define S_DMIC0_96_48_data_ADDR_END 2052 -#define S_DMIC0_96_48_data_sizeof 19 +#define S_DMIC1_96_48_data_ADDR 2052 +#define S_DMIC1_96_48_data_ADDR_END 2070 +#define S_DMIC1_96_48_data_sizeof 19 -#define S_DMIC1_96_48_data_ADDR 2053 -#define S_DMIC1_96_48_data_ADDR_END 2071 -#define S_DMIC1_96_48_data_sizeof 19 +#define S_DMIC2_96_48_data_ADDR 2071 +#define S_DMIC2_96_48_data_ADDR_END 2089 +#define S_DMIC2_96_48_data_sizeof 19 -#define S_DMIC2_96_48_data_ADDR 2072 -#define S_DMIC2_96_48_data_ADDR_END 2090 -#define S_DMIC2_96_48_data_sizeof 19 +#define S_EANC_FBK_96_48_data_ADDR 2090 +#define S_EANC_FBK_96_48_data_ADDR_END 2108 +#define S_EANC_FBK_96_48_data_sizeof 19 -#define S_EANC_FBK_96_48_data_ADDR 2091 -#define S_EANC_FBK_96_48_data_ADDR_END 2109 -#define S_EANC_FBK_96_48_data_sizeof 19 +#define S_DBG_8K_PATTERN_ADDR 2109 +#define S_DBG_8K_PATTERN_ADDR_END 2110 +#define S_DBG_8K_PATTERN_sizeof 2 -#define S_DBG_8K_PATTERN_ADDR 2110 -#define S_DBG_8K_PATTERN_ADDR_END 2111 -#define S_DBG_8K_PATTERN_sizeof 2 +#define S_DBG_16K_PATTERN_ADDR 2111 +#define S_DBG_16K_PATTERN_ADDR_END 2114 +#define S_DBG_16K_PATTERN_sizeof 4 -#define S_DBG_16K_PATTERN_ADDR 2112 -#define S_DBG_16K_PATTERN_ADDR_END 2115 -#define S_DBG_16K_PATTERN_sizeof 4 +#define S_DBG_24K_PATTERN_ADDR 2115 +#define S_DBG_24K_PATTERN_ADDR_END 2120 +#define S_DBG_24K_PATTERN_sizeof 6 -#define S_DBG_24K_PATTERN_ADDR 2116 -#define S_DBG_24K_PATTERN_ADDR_END 2121 -#define S_DBG_24K_PATTERN_sizeof 6 +#define S_DBG_48K_PATTERN_ADDR 2121 +#define S_DBG_48K_PATTERN_ADDR_END 2132 +#define S_DBG_48K_PATTERN_sizeof 12 -#define S_DBG_48K_PATTERN_ADDR 2122 -#define S_DBG_48K_PATTERN_ADDR_END 2133 -#define S_DBG_48K_PATTERN_sizeof 12 +#define S_DBG_96K_PATTERN_ADDR 2133 +#define S_DBG_96K_PATTERN_ADDR_END 2156 +#define S_DBG_96K_PATTERN_sizeof 24 -#define S_DBG_96K_PATTERN_ADDR 2134 -#define S_DBG_96K_PATTERN_ADDR_END 2157 -#define S_DBG_96K_PATTERN_sizeof 24 +#define S_MM_EXT_IN_ADDR 2157 +#define S_MM_EXT_IN_ADDR_END 2168 +#define S_MM_EXT_IN_sizeof 12 -#define S_MM_EXT_IN_ADDR 2158 -#define S_MM_EXT_IN_ADDR_END 2169 -#define S_MM_EXT_IN_sizeof 12 +#define S_MM_EXT_IN_L_ADDR 2169 +#define S_MM_EXT_IN_L_ADDR_END 2180 +#define S_MM_EXT_IN_L_sizeof 12 -#define S_MM_EXT_IN_L_ADDR 2170 -#define S_MM_EXT_IN_L_ADDR_END 2181 -#define S_MM_EXT_IN_L_sizeof 12 +#define S_MM_EXT_IN_R_ADDR 2181 +#define S_MM_EXT_IN_R_ADDR_END 2192 +#define S_MM_EXT_IN_R_sizeof 12 -#define S_MM_EXT_IN_R_ADDR 2182 -#define S_MM_EXT_IN_R_ADDR_END 2193 -#define S_MM_EXT_IN_R_sizeof 12 +#define S_MIC4_ADDR 2193 +#define S_MIC4_ADDR_END 2204 +#define S_MIC4_sizeof 12 -#define S_MIC4_ADDR 2194 -#define S_MIC4_ADDR_END 2205 -#define S_MIC4_sizeof 12 +#define S_MIC4_L_ADDR 2205 +#define S_MIC4_L_ADDR_END 2216 +#define S_MIC4_L_sizeof 12 -#define S_MIC4_L_ADDR 2206 -#define S_MIC4_L_ADDR_END 2217 -#define S_MIC4_L_sizeof 12 +#define S_MIC4_R_ADDR 2217 +#define S_MIC4_R_ADDR_END 2228 +#define S_MIC4_R_sizeof 12 -#define S_MIC4_R_ADDR 2218 -#define S_MIC4_R_ADDR_END 2229 -#define S_MIC4_R_sizeof 12 +#define S_HW_TEST_ADDR 2229 +#define S_HW_TEST_ADDR_END 2229 +#define S_HW_TEST_sizeof 1 -#define S_HW_TEST_ADDR 2230 -#define S_HW_TEST_ADDR_END 2230 -#define S_HW_TEST_sizeof 1 #endif /* _ABESM_ADDR_H_ */ diff --git a/sound/soc/omap/abe/abe_sys.h b/sound/soc/omap/abe/abe_sys.h index f4d50d2132ff..f7b3bae9f089 100644 --- a/sound/soc/omap/abe/abe_sys.h +++ b/sound/soc/omap/abe/abe_sys.h @@ -1,9 +1,23 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. +/* ============================================================================= +* Texas Instruments OMAP(TM) Platform Software +* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. +* +* Use of this software is controlled by the terms and conditions found +* in the license agreement under which this software has been supplied. +* =========================================================================== */ +/** + * @file ABE_SYS.H * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Headers for system calls and includes + * + * @path + * @rev 01.00 */ +/* ---------------------------------------------------------------------------- +*! +*! Revision History +*! =================================== +*! 27-Nov-2008 Original (LLF) +*! 05-Jun-2009 V05 release +* =========================================================================== */ + diff --git a/sound/soc/omap/abe/abe_taskId.h b/sound/soc/omap/abe/abe_taskId.h deleted file mode 100644 index 6b53e7393501..000000000000 --- a/sound/soc/omap/abe/abe_taskId.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. - * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== - */ - -#ifndef _ABE_TASKID_H_ -#define _ABE_TASKID_H_ - -#define C_ABE_FW_TASK_DL1_APS_CORE 0 -#define C_ABE_FW_TASK_DL1_APS_COIL_CORE 1 -#define C_ABE_FW_TASK_DL2_L_APS_CORE 2 -#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE 3 -#define C_ABE_FW_TASK_DL2_R_APS_CORE 4 -#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE 5 -#define C_ABE_FW_TASK_ASRC_VX_DL_8 6 -#define C_ABE_FW_TASK_ASRC_VX_DL_16 7 -#define C_ABE_FW_TASK_ASRC_MM_DL 8 -#define C_ABE_FW_TASK_ASRC_VX_UL_8 9 -#define C_ABE_FW_TASK_ASRC_VX_UL_16 10 -#define C_ABE_FW_TASK_DC_REMOVAL 11 -#define C_ABE_FW_TASK_VX_UL_48_8_DEC 12 -#define C_ABE_FW_TASK_VX_UL_48_16_DEC 13 -#define C_ABE_FW_TASK_BT_DL_48_8_DEC 14 -#define C_ABE_FW_TASK_BT_DL_48_16_DEC 15 -#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC 16 -#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC 17 -#define C_ABE_FW_TASK_DL2_EQ 18 -#define C_ABE_FW_TASK_DL2_L_APS_IIR 19 -#define C_ABE_FW_TASK_DL2_R_APS_IIR 20 -#define C_ABE_FW_TASK_DL2_APS_EQ 21 -#define C_ABE_FW_TASK_ECHO_REF_48_16 22 -#define C_ABE_FW_TASK_ECHO_REF_48_8 23 -#define C_ABE_FW_TASK_GAIN_UPDATE 24 -#define C_ABE_FW_TASK_SideTone 25 -#define C_ABE_FW_TASK_VX_DL_8_48_LP 26 -#define C_ABE_FW_TASK_VX_DL_8_48_HP 27 -#define C_ABE_FW_TASK_VX_DL_16_48_LP 28 -#define C_ABE_FW_TASK_VX_DL_16_48_HP 29 -#define C_ABE_FW_TASK_VX_UL_48_8_LP 30 -#define C_ABE_FW_TASK_VX_UL_48_8_HP 31 -#define C_ABE_FW_TASK_VX_UL_48_16_LP 32 -#define C_ABE_FW_TASK_VX_UL_48_16_HP 33 -#define C_ABE_FW_TASK_BT_UL_8_48_LP 34 -#define C_ABE_FW_TASK_BT_UL_8_48_HP 35 -#define C_ABE_FW_TASK_BT_UL_16_48_LP 36 -#define C_ABE_FW_TASK_BT_UL_16_48_HP 37 -#define C_ABE_FW_TASK_BT_DL_48_8_LP 38 -#define C_ABE_FW_TASK_BT_DL_48_8_HP 39 -#define C_ABE_FW_TASK_BT_DL_48_16_LP 40 -#define C_ABE_FW_TASK_BT_DL_48_16_HP 41 -#define C_ABE_FW_TASK_ECHO_REF_48_8_LP 42 -#define C_ABE_FW_TASK_ECHO_REF_48_8_HP 43 -#define C_ABE_FW_TASK_ECHO_REF_48_16_LP 44 -#define C_ABE_FW_TASK_ECHO_REF_48_16_HP 45 -#define C_ABE_FW_TASK_DL1_EQ 46 -#define C_ABE_FW_TASK_DL1_APS_IIR 47 -#define C_ABE_FW_TASK_DL1_APS_EQ 48 -#define C_ABE_FW_TASK_IHF_48_96_LP 49 -#define C_ABE_FW_TASK_EARP_48_96_LP 50 -#define C_ABE_FW_TASK_DL1_GAIN 51 -#define C_ABE_FW_TASK_DL2_GAIN 52 -#define C_ABE_FW_TASK_IO_PING_PONG 53 -#define C_ABE_FW_TASK_IO_DMIC 54 -#define C_ABE_FW_TASK_IO_PDM_UL 55 -#define C_ABE_FW_TASK_IO_BT_VX_UL 56 -#define C_ABE_FW_TASK_IO_MM_UL 57 -#define C_ABE_FW_TASK_IO_MM_UL2 58 -#define C_ABE_FW_TASK_IO_VX_UL 59 -#define C_ABE_FW_TASK_IO_MM_DL 60 -#define C_ABE_FW_TASK_IO_VX_DL 61 -#define C_ABE_FW_TASK_IO_TONES_DL 62 -#define C_ABE_FW_TASK_IO_VIB_DL 63 -#define C_ABE_FW_TASK_IO_BT_VX_DL 64 -#define C_ABE_FW_TASK_IO_PDM_DL 65 -#define C_ABE_FW_TASK_IO_MM_EXT_OUT 66 -#define C_ABE_FW_TASK_IO_MM_EXT_IN 67 -#define C_ABE_FW_TASK_IO_TDM_OUT 68 -#define C_ABE_FW_TASK_IO_TDM_IN 69 -#define C_ABE_FW_TASK_DEBUG_IRQFIFO 70 -#define C_ABE_FW_TASK_EchoMixer 71 -#define C_ABE_FW_TASK_SDTMixer 72 -#define C_ABE_FW_TASK_DL1Mixer 73 -#define C_ABE_FW_TASK_DL2Mixer 74 -#define C_ABE_FW_TASK_VXRECMixer 75 -#define C_ABE_FW_TASK_ULMixer 76 -#define C_ABE_FW_TASK_VIBRA_PACK 77 -#define C_ABE_FW_TASK_VX_DL_8_48_0SR 78 -#define C_ABE_FW_TASK_VX_DL_16_48_0SR 79 -#define C_ABE_FW_TASK_BT_UL_8_48_0SR 80 -#define C_ABE_FW_TASK_BT_UL_16_48_0SR 81 -#define C_ABE_FW_TASK_IHF_48_96_0SR 82 -#define C_ABE_FW_TASK_EARP_48_96_0SR 83 -#define C_ABE_FW_TASK_AMIC_SPLIT 84 -#define C_ABE_FW_TASK_DMIC1_SPLIT 85 -#define C_ABE_FW_TASK_DMIC2_SPLIT 86 -#define C_ABE_FW_TASK_DMIC3_SPLIT 87 -#define C_ABE_FW_TASK_VXREC_SPLIT 88 -#define C_ABE_FW_TASK_BT_UL_SPLIT 89 -#define C_ABE_FW_TASK_MM_SPLIT 90 -#define C_ABE_FW_TASK_DL2_APS_SPLIT 91 -#define C_ABE_FW_TASK_VIBRA_SPLIT 92 -#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT 93 -#define C_ABE_FW_TASK_EANC_FBK_SPLIT 94 -#define C_ABE_FW_TASK_MIC4_SPLIT 95 -#define C_ABE_FW_TASK_VX_UL_ROUTING 96 -#define C_ABE_FW_TASK_MM_UL2_ROUTING 97 -#define C_ABE_FW_TASK_VIBRA1 98 -#define C_ABE_FW_TASK_VIBRA2 99 -#define C_ABE_FW_TASK_BT_UL_16_48 100 -#define C_ABE_FW_TASK_BT_UL_8_48 101 -#define C_ABE_FW_TASK_BT_DL_48_16 102 -#define C_ABE_FW_TASK_BT_DL_48_8 103 -#define C_ABE_FW_TASK_VX_DL_16_48 104 -#define C_ABE_FW_TASK_VX_DL_8_48 105 -#define C_ABE_FW_TASK_VX_UL_48_16 106 -#define C_ABE_FW_TASK_VX_UL_48_8 107 -#define C_ABE_FW_TASK_DBG_SYNC 108 -#define C_ABE_FW_TASK_APS_DL1_IRQs 109 -#define C_ABE_FW_TASK_APS_DL2_L_IRQs 110 -#define C_ABE_FW_TASK_APS_DL2_R_IRQs 111 -#define C_ABE_FW_TASK_AMIC_96_48_LP 112 -#define C_ABE_FW_TASK_DMIC1_96_48_LP 113 -#define C_ABE_FW_TASK_DMIC2_96_48_LP 114 -#define C_ABE_FW_TASK_DMIC3_96_48_LP 115 - -#endif /* _ABE_TASKID_H_ */ diff --git a/sound/soc/omap/abe/abe_taskid.h b/sound/soc/omap/abe/abe_taskid.h new file mode 100644 index 000000000000..be152545e825 --- /dev/null +++ b/sound/soc/omap/abe/abe_taskid.h @@ -0,0 +1,144 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef _ABE_TASKID_H_ +#define _ABE_TASKID_H_ + +#define C_ABE_FW_TASK_DL1_APS_CORE 0 +#define C_ABE_FW_TASK_DL1_APS_COIL_CORE 1 +#define C_ABE_FW_TASK_DL2_L_APS_CORE 2 +#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE 3 +#define C_ABE_FW_TASK_DL2_R_APS_CORE 4 +#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE 5 +#define C_ABE_FW_TASK_ASRC_VX_DL_8 6 +#define C_ABE_FW_TASK_ASRC_VX_DL_16 7 +#define C_ABE_FW_TASK_ASRC_MM_DL 8 +#define C_ABE_FW_TASK_ASRC_VX_UL_8 9 +#define C_ABE_FW_TASK_ASRC_VX_UL_16 10 +#define C_ABE_FW_TASK_DC_REMOVAL 11 +#define C_ABE_FW_TASK_VX_UL_48_8_DEC 12 +#define C_ABE_FW_TASK_VX_UL_48_16_DEC 13 +#define C_ABE_FW_TASK_BT_DL_48_8_DEC 14 +#define C_ABE_FW_TASK_BT_DL_48_16_DEC 15 +#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC 16 +#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC 17 +#define C_ABE_FW_TASK_DL2_EQ 18 +#define C_ABE_FW_TASK_DL2_L_APS_IIR 19 +#define C_ABE_FW_TASK_DL2_R_APS_IIR 20 +#define C_ABE_FW_TASK_DL2_APS_EQ 21 +#define C_ABE_FW_TASK_ECHO_REF_48_16 22 +#define C_ABE_FW_TASK_ECHO_REF_48_8 23 +#define C_ABE_FW_TASK_GAIN_UPDATE 24 +#define C_ABE_FW_TASK_SideTone 25 +#define C_ABE_FW_TASK_VX_DL_8_48_LP 26 +#define C_ABE_FW_TASK_VX_DL_8_48_HP 27 +#define C_ABE_FW_TASK_VX_DL_16_48_LP 28 +#define C_ABE_FW_TASK_VX_DL_16_48_HP 29 +#define C_ABE_FW_TASK_VX_UL_48_8_LP 30 +#define C_ABE_FW_TASK_VX_UL_48_8_HP 31 +#define C_ABE_FW_TASK_VX_UL_48_16_LP 32 +#define C_ABE_FW_TASK_VX_UL_48_16_HP 33 +#define C_ABE_FW_TASK_BT_UL_8_48_LP 34 +#define C_ABE_FW_TASK_BT_UL_8_48_HP 35 +#define C_ABE_FW_TASK_BT_UL_16_48_LP 36 +#define C_ABE_FW_TASK_BT_UL_16_48_HP 37 +#define C_ABE_FW_TASK_BT_DL_48_8_LP 38 +#define C_ABE_FW_TASK_BT_DL_48_8_HP 39 +#define C_ABE_FW_TASK_BT_DL_48_16_LP 40 +#define C_ABE_FW_TASK_BT_DL_48_16_HP 41 +#define C_ABE_FW_TASK_ECHO_REF_48_8_LP 42 +#define C_ABE_FW_TASK_ECHO_REF_48_8_HP 43 +#define C_ABE_FW_TASK_ECHO_REF_48_16_LP 44 +#define C_ABE_FW_TASK_ECHO_REF_48_16_HP 45 +#define C_ABE_FW_TASK_DL1_EQ 46 +#define C_ABE_FW_TASK_DL1_APS_IIR 47 +#define C_ABE_FW_TASK_DL1_APS_EQ 48 +#define C_ABE_FW_TASK_IHF_48_96_LP 49 +#define C_ABE_FW_TASK_EARP_48_96_LP 50 +#define C_ABE_FW_TASK_DL1_GAIN 51 +#define C_ABE_FW_TASK_DL2_GAIN 52 +#define C_ABE_FW_TASK_IO_PING_PONG 53 +#define C_ABE_FW_TASK_IO_DMIC 54 +#define C_ABE_FW_TASK_IO_PDM_UL 55 +#define C_ABE_FW_TASK_IO_BT_VX_UL 56 +#define C_ABE_FW_TASK_IO_MM_UL 57 +#define C_ABE_FW_TASK_IO_MM_UL2 58 +#define C_ABE_FW_TASK_IO_VX_UL 59 +#define C_ABE_FW_TASK_IO_MM_DL 60 +#define C_ABE_FW_TASK_IO_VX_DL 61 +#define C_ABE_FW_TASK_IO_TONES_DL 62 +#define C_ABE_FW_TASK_IO_VIB_DL 63 +#define C_ABE_FW_TASK_IO_BT_VX_DL 64 +#define C_ABE_FW_TASK_IO_PDM_DL 65 +#define C_ABE_FW_TASK_IO_MM_EXT_OUT 66 +#define C_ABE_FW_TASK_IO_MM_EXT_IN 67 +#define C_ABE_FW_TASK_IO_TDM_OUT 68 +#define C_ABE_FW_TASK_IO_TDM_IN 69 +#define C_ABE_FW_TASK_DEBUG_IRQFIFO 70 +#define C_ABE_FW_TASK_EchoMixer 71 +#define C_ABE_FW_TASK_SDTMixer 72 +#define C_ABE_FW_TASK_DL1Mixer 73 +#define C_ABE_FW_TASK_DL2Mixer 74 +#define C_ABE_FW_TASK_VXRECMixer 75 +#define C_ABE_FW_TASK_ULMixer 76 +#define C_ABE_FW_TASK_VIBRA_PACK 77 +#define C_ABE_FW_TASK_VX_DL_8_48_0SR 78 +#define C_ABE_FW_TASK_VX_DL_16_48_0SR 79 +#define C_ABE_FW_TASK_BT_UL_8_48_0SR 80 +#define C_ABE_FW_TASK_BT_UL_16_48_0SR 81 +#define C_ABE_FW_TASK_IHF_48_96_0SR 82 +#define C_ABE_FW_TASK_EARP_48_96_0SR 83 +#define C_ABE_FW_TASK_AMIC_SPLIT 84 +#define C_ABE_FW_TASK_DMIC1_SPLIT 85 +#define C_ABE_FW_TASK_DMIC2_SPLIT 86 +#define C_ABE_FW_TASK_DMIC3_SPLIT 87 +#define C_ABE_FW_TASK_VXREC_SPLIT 88 +#define C_ABE_FW_TASK_BT_UL_SPLIT 89 +#define C_ABE_FW_TASK_MM_SPLIT 90 +#define C_ABE_FW_TASK_DL2_APS_SPLIT 91 +#define C_ABE_FW_TASK_VIBRA_SPLIT 92 +#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT 93 +#define C_ABE_FW_TASK_EANC_FBK_SPLIT 94 +#define C_ABE_FW_TASK_MIC4_SPLIT 95 +#define C_ABE_FW_TASK_VX_UL_ROUTING 96 +#define C_ABE_FW_TASK_MM_UL2_ROUTING 97 +#define C_ABE_FW_TASK_VIBRA1 98 +#define C_ABE_FW_TASK_VIBRA2 99 +#define C_ABE_FW_TASK_BT_UL_16_48 100 +#define C_ABE_FW_TASK_BT_UL_8_48 101 +#define C_ABE_FW_TASK_BT_DL_48_16 102 +#define C_ABE_FW_TASK_BT_DL_48_8 103 +#define C_ABE_FW_TASK_VX_DL_16_48 104 +#define C_ABE_FW_TASK_VX_DL_8_48 105 +#define C_ABE_FW_TASK_VX_UL_48_16 106 +#define C_ABE_FW_TASK_VX_UL_48_8 107 +#define C_ABE_FW_TASK_DBG_SYNC 108 +#define C_ABE_FW_TASK_APS_DL1_IRQs 109 +#define C_ABE_FW_TASK_APS_DL2_L_IRQs 110 +#define C_ABE_FW_TASK_APS_DL2_R_IRQs 111 +#define C_ABE_FW_TASK_AMIC_96_48_LP 112 +#define C_ABE_FW_TASK_DMIC1_96_48_LP 113 +#define C_ABE_FW_TASK_DMIC2_96_48_LP 114 +#define C_ABE_FW_TASK_DMIC3_96_48_LP 115 +#define C_ABE_FW_TASK_INIT_FW_MEMORY 116 +#define C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs 117 + +#endif /* _ABE_TASKID_H_ */ diff --git a/sound/soc/omap/abe/abe_test.c b/sound/soc/omap/abe/abe_test.c index 4c7ea4a338fd..07669694d88e 100644 --- a/sound/soc/omap/abe/abe_test.c +++ b/sound/soc/omap/abe/abe_test.c @@ -1,866 +1,662 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. +/* ============================================================================= + + THIS FILE IS PART OF THE ABE/HAL RELEASE FOR TEST PURPOSE + THIS FILE MUST NOT BE INSERTED IN THE MAKEFILE OF THE FINAL APPLICATION + +* =========================================================================== */ +/** + * @file ABE_API.C * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * All the visible API for the audio drivers + * + * @path + * @rev 01.00 */ +/* ---------------------------------------------------------------------------- +*! +*! Revision History +*! =================================== +*! 27-Nov-2008 Original +*! 05-Jun-2009 V05 release +* =========================================================================== */ + + #include <stdio.h> #include <stdlib.h> #include <math.h> +#include <string.h> + #include "ABE_MAIN.h" #include "ABE_DEF.h" -void abe_test_scenario_1(void); -void abe_test_scenario_2(void); -void abe_test_scenario_3(void); -void abe_test_scenario_4(void); +void abe_test_scenario_1 (void); +void abe_test_scenario_2 (void); +void abe_test_scenario_3 (void); +void abe_test_scenario_4 (void); +void abe_test_scenario_5 (void); +void abe_test_scenario_6 (void); +void abe_test_scenario_7 (void); + -/* +/* ========================================================================== */ +/** * @fn ABE_TEST_SCENARIO() */ -void abe_test_scenario(abe_int32 scenario_id) +/* ========================================================================= */ + +void abe_test_scenario (abe_int32 scenario_id) { - switch (scenario_id) { - case 1: - abe_test_scenario_1(); - break; - case 2: - abe_test_scenario_2(); - break; - case 3: - abe_test_scenario_3(); - break; - case 4: - abe_test_scenario_4(); - break; - } + switch (scenario_id) + { + case 1 : abe_test_scenario_1 (); break; + case 2 : abe_test_scenario_2 (); break; + case 3 : abe_test_scenario_3 (); break; + case 4 : abe_test_scenario_4 (); break; + case 5 : abe_test_scenario_5 (); break; // ASRC + case 6 : abe_test_scenario_6 (); break; // APS + case 7 : abe_test_scenario_7 (); break; // RAMP tests + } } -/* + +/* ========================================================================== */ +/** * @fn abe_test_read_time () */ -abe_uint32 abe_test_read_time(void) +/* ========================================================================= */ +abe_uint32 abe_test_read_time (void) { - abe_uint32 time; - abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_slotCounter_ADDR, - (abe_uint32*)&time, sizeof (time)); - return (time & 0xFFFF); + abe_uint32 time; + abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_slotCounter_ADDR, (abe_uint32*)&time, sizeof (time)); + return (time & 0xFFFF); } -/* +/* ========================================================================== */ +/** +* @fn abe_short_ramps () +*/ +/* ========================================================================= */ +void abe_short_ramps (void) +{ + /* mixers' configuration */ + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_1MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_1MS, MIX_DL1_INPUT_MM_UL2); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_1MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_1MS, MIX_DL1_INPUT_TONES); + + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_1MS, MIX_DL2_INPUT_TONES); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_1MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_1MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_1MS, MIX_DL2_INPUT_MM_UL2); + + abe_write_mixer (MIXSDT, MUTE_GAIN, RAMP_1MS, MIX_SDT_INPUT_UP_MIXER); + abe_write_mixer (MIXSDT, GAIN_0dB , RAMP_1MS, MIX_SDT_INPUT_DL1_MIXER); + + abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_1MS, MIX_AUDUL_INPUT_MM_DL); + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_1MS, MIX_AUDUL_INPUT_TONES); + abe_write_mixer (MIXAUDUL, GAIN_0dB , RAMP_1MS, MIX_AUDUL_INPUT_UPLINK); + abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_1MS, MIX_AUDUL_INPUT_VX_DL); + + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_1MS, MIX_VXREC_INPUT_TONES); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_1MS, MIX_VXREC_INPUT_VX_DL); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_1MS, MIX_VXREC_INPUT_MM_DL); + abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_1MS, MIX_VXREC_INPUT_VX_UL); + + abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + abe_write_gain(GAINS_AMIC ,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_AMIC, GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + + abe_write_gain(GAINS_SPLIT ,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain(GAINS_SPLIT, GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + + abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); + abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_1MS, GAIN_LEFT_OFFSET); + abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_1MS, GAIN_RIGHT_OFFSET); +} + +/* ========================================================================== */ +/** * @fn ABE_TEST_SCENARIO_1 () * -* DMA AUDIO PLAYER + DMA VOICE CALL 16kHz +* DMA AUDIO PLAYER + DMA VOICE CALL 16kHz */ -void abe_test_scenario_1(void) +/* ========================================================================= */ + +void abe_test_scenario_1 (void) { - static abe_int32 time_offset, state; - abe_data_format_t format; - abe_dma_t dma_sink; - abe_uint32 current_time; - abe_use_case_id UC2[] = { - ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, - ABE_RINGER_TONES, - (abe_use_case_id)0 - }; - // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; - abe_opp_t OPP; - abe_hw_config_init_t CONFIG; - - /* Scenario 1- 16kHz first */ - switch (state) { - case 0: - state ++; - time_offset = abe_test_read_time(); - abe_reset_hal(); - abe_load_fw(); - - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC2, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_BT]); - - format.f = 48000; - format.samp_format = SIX_MSB; - abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - /* enable all DMIC aquisition */ - abe_enable_data_transfer(MM_UL_PORT); - /* enable large-band DMIC aquisition */ - abe_enable_data_transfer(MM_UL2_PORT); - abe_enable_data_transfer(VX_UL_PORT); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - format.f = 24000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink); - abe_enable_data_transfer(TONES_DL_PORT); - abe_enable_data_transfer(VX_DL_PORT); - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(VIB_DL_PORT); - - /* SERIAL PORTS TEST */ - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_serial_port(BT_VX_UL_PORT, &format, MCBSP1_RX); - format.f = 8000; - format.samp_format = MONO_RSHIFTED_16; - abe_connect_serial_port(BT_VX_DL_PORT, &format, MCBSP1_TX); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_serial_port(MM_EXT_IN_PORT, &format, MCBSP2_RX); - format.f = 48000; - format.samp_format = MONO_RSHIFTED_16; - abe_connect_serial_port(MM_EXT_OUT_PORT, &format, MCBSP2_TX); - abe_enable_data_transfer(BT_VX_UL_PORT); - abe_enable_data_transfer(BT_VX_DL_PORT); - abe_enable_data_transfer(MM_EXT_IN_PORT); - abe_enable_data_transfer(MM_EXT_OUT_PORT); - - /* DMIC ATC can be enabled even if the DMIC */ - abe_enable_data_transfer(DMIC_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - abe_enable_data_transfer(PDM_UL_PORT); - - /* mixers' configuration = voice on earphone + music on hands-free path */ - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); - - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER); - - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES); - abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL); - - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL); - break; - case 1: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100) - break; - else - state ++; - break; - case 2: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100000) - break; - else - state ++; // Internal buffer analysis - break; - default: - state = 0; - break; - } + static abe_int32 time_offset, state; + abe_data_format_t format; + abe_dma_t dma_sink; + abe_uint32 current_time; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; + // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + //-----------------------------Scenario 1- + switch (state) + { + case 0: + { state ++; + + time_offset = abe_test_read_time(); + + abe_reset_hal (); + abe_load_fw (); + abe_short_ramps (); + abe_set_debug_trace (-1); + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + + #if 0 + { abe_equ_t dl2_eq; + const abe_int32 DL2_COEF [25] = { -7554223, 708210, -708206, 7554225, 0,0,0,0, 0,0,0,0, 0, 0,0,0,0, + 0,0,0,0, 0,6802833, -682266, 731554}; + dl2_eq.equ_length = 25; + memcpy (dl2_eq.coef.type1, DL2_COEF, sizeof(DL2_COEF)); + + abe_write_equalizer (EQ2L, &dl2_eq); + abe_write_equalizer (EQ2R, &dl2_eq); + } + #endif + + abe_set_opp_processing (OPP); + abe_write_event_generator (CONFIG.HAL_EVENT_SELECTION); /* "tick" of the audio engine */ + + abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_AMIC, (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); + //abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_BT, (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_BT]); + + //format.f = 8000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_cbpr_dmareq_port (VX_UL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); + format.f = 8000; format.samp_format = MONO_RSHIFTED_16; abe_connect_serial_port (VX_UL_PORT, &format, MCBSP2_TX); + //format.f = 8000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_cbpr_dmareq_port (VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); + format.f = 8000; format.samp_format = MONO_RSHIFTED_16; abe_connect_serial_port (VX_DL_PORT, &format, MCBSP2_RX); + + format.f = 48000; format.samp_format = MONO_MSB; abe_connect_cbpr_dmareq_port (TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); + format.f = 48000; format.samp_format = SIX_MSB; abe_connect_cbpr_dmareq_port (MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); + format.f = 24000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink); + + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); + //format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_serial_port (MM_DL_PORT, &format, MCBSP3_RX); + + // SERIAL PORTS TEST + // abe_select_main_port (MM_DL_PORT); + + format.f = 16000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (BT_VX_UL_PORT, &format, MCBSP1_RX); + format.f = 16000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (BT_VX_DL_PORT, &format, MCBSP1_TX); + //format.f = 48000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (MM_EXT_IN_PORT, &format, MCBSP3_RX); + //format.f = 48000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (MM_EXT_OUT_PORT, &format, MCBSP3_TX); + abe_enable_data_transfer (BT_VX_UL_PORT); + abe_enable_data_transfer (BT_VX_DL_PORT); + //abe_enable_data_transfer (MM_EXT_IN_PORT); + //abe_enable_data_transfer (MM_EXT_OUT_PORT); + + abe_enable_data_transfer (MM_UL_PORT ); /* enable all DMIC aquisition */ + abe_enable_data_transfer (MM_UL2_PORT ); /* enable large-band DMIC aquisition */ + abe_enable_data_transfer (VX_UL_PORT ); + abe_enable_data_transfer (TONES_DL_PORT); + abe_enable_data_transfer (VX_DL_PORT ); + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + abe_enable_data_transfer (VIB_DL_PORT ); + abe_enable_data_transfer (DMIC_PORT); /* DMIC ATC can be enabled even if the DMIC */ + abe_enable_data_transfer (PDM_DL_PORT); + abe_enable_data_transfer (PDM_UL_PORT); + + /* mixers' configuration = voice on earphone + music on hands-free path */ + abe_write_mixer (MIXDL1, GAIN_M12dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); + abe_write_mixer (MIXDL1, GAIN_M12dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, GAIN_M12dB, RAMP_0MS, MIX_DL1_INPUT_TONES); + + abe_write_mixer (MIXDL2, GAIN_M12dB, RAMP_0MS, MIX_DL2_INPUT_TONES); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer (MIXDL2, GAIN_M12dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); + + //abe_enable_test_pattern (DBG_PATCH_MM_DL_MIXDL1, 1); + //abe_enable_test_pattern (DBG_PATCH_MM_DL_MIXDL2, 1); + + } + break; + case 1: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 1000) break; + else + { state ++; + + + + } + break; + case 2: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 1050) break; + else + { state ++; + + + } + break; + + case 3: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 200000) break; + else + { state ++; + } + + default: state = 0; break; + } } -/* + +/* ========================================================================== */ +/** * @fn ABE_TEST_SCENARIO_2 () * -* DMA AUDIO PLAYER + DMA VOICE CALL 8kHz +* DMA AUDIO PLAYER + DMA VOICE CALL 8kHz */ +/* ========================================================================= */ void abe_test_scenario_2 (void) { - static abe_int32 time_offset, state; - abe_data_format_t format; - abe_dma_t dma_sink; - abe_uint32 current_time; - abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; - abe_opp_t OPP; - abe_hw_config_init_t CONFIG; - - /* Scenario 1- 16kHz first */ - switch (state) - { - case 0: - state ++; - - time_offset = abe_test_read_time(); - abe_reset_hal(); - abe_load_fw(); - - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC2, &OPP, &CONFIG); - abe_set_opp_processing(OPP); /* sets the OPP100 on FW05.xx */ - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - abe_set_router_configuration(UPROUTE, - UPROUTE_CONFIG_AMIC, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - abe_enable_data_transfer(MM_UL_PORT); /* enable all DMIC aquisition */ - abe_enable_data_transfer(MM_UL2_PORT); /* enable large-band DMIC aquisition */ - abe_enable_data_transfer(VX_UL_PORT); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - format.f = 24000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VIB_DL_PORT,&format, ABE_CBPR6_IDX, &dma_sink); - abe_enable_data_transfer(TONES_DL_PORT); - abe_enable_data_transfer(VX_DL_PORT); - abe_enable_data_transfer(MM_DL_PORT); /* enable all the data paths */ - abe_enable_data_transfer(VIB_DL_PORT); - - abe_enable_data_transfer(DMIC_PORT); /* DMIC ATC can be enabled even if the DMIC */ - abe_enable_data_transfer(PDM_DL_PORT); - abe_enable_data_transfer(PDM_UL_PORT); - - /* mixers' configuration = voice on earphone + music on hands-free path */ - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); - - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER); - - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES); - abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL); - - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL); - break; - case 1: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100) - break; - else - state ++; - break; - case 2: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100000) - break; - else - state ++; - break; - default: - state = 0; - break; - } + static abe_int32 time_offset, state; + abe_data_format_t format; + abe_dma_t dma_sink; + abe_uint32 current_time; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; + // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + //-----------------------------Scenario 1- 16kHz first + switch (state) + { + case 0: + { state ++; + + time_offset = abe_test_read_time(); + abe_reset_hal (); + abe_load_fw (); + abe_set_debug_trace (-1); + abe_short_ramps (); + + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + abe_set_opp_processing (OPP); /* sets the OPP100 on FW05.xx */ + abe_write_event_generator (CONFIG.HAL_EVENT_SELECTION); /* "tick" of the audio engine */ + + abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_AMIC, (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); + + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); + format.f = 8000; format.samp_format = MONO_MSB; abe_connect_cbpr_dmareq_port (VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); + abe_enable_data_transfer (MM_UL_PORT ); /* enable all DMIC aquisition */ + abe_enable_data_transfer (MM_UL2_PORT ); /* enable large-band DMIC aquisition */ + abe_enable_data_transfer (VX_UL_PORT ); + + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); + format.f = 8000; format.samp_format = MONO_MSB; abe_connect_cbpr_dmareq_port (VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); + format.f = 24000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink); + abe_enable_data_transfer (TONES_DL_PORT); + abe_enable_data_transfer (VX_DL_PORT ); + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + abe_enable_data_transfer (VIB_DL_PORT ); + + abe_enable_data_transfer (DMIC_PORT); /* DMIC ATC can be enabled even if the DMIC */ + abe_enable_data_transfer (PDM_DL_PORT); + abe_enable_data_transfer (PDM_UL_PORT); + + + /* mixers' configuration = voice on earphone + music on hands-free path */ + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); + abe_write_mixer (MIXDL1, GAIN_M6dB , RAMP_0MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); + + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES); + abe_write_mixer (MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer (MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); + + } + break; + case 1: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 100) break; + else + { state ++; + // Gains switch + } + break; + case 2: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 100000) break; + else + { state ++; + // Internal buffer analysis + } + break; + default: state = 0; break; + } } +/* ========================================================================== */ /** -* @fn ABE_TEST_SCENARIO_3 () +* @fn ABE_TEST_SCENARIO_3 () * -* IRQ AUDIO PLAYER 44100Hz OPP 25% +* IRQ AUDIO PLAYER 44100Hz OPP 25% */ +/* ========================================================================= */ void abe_test_scenario_3 (void) { - static abe_int32 time_offset, state, gain=0x040000, i; - abe_data_format_t format; - abe_uint32 data_sink; - abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; - // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; - abe_opp_t OPP; - abe_hw_config_init_t CONFIG; - - /* Scenario 1- 16kHz first */ - switch (state) { - case 0: - state ++; - time_offset = abe_test_read_time(); - abe_reset_hal(); - abe_load_fw(); - - abe_read_hardware_configuration(UC2, &OPP, &CONFIG); /* check HW config and OPP config */ - abe_set_opp_processing(ABE_OPP25); /* sets the OPP25 on FW05.xx */ - abe_write_event_generator(EVENT_44100); /* "tick" of the audio engine */ - - /* connect a Ping-Pong cache-flush protocol to MM_DL port */ -#define N_SAMPLES_BYTES (25 *8) /* half-buffer size in bytes, 32/32 data format */ - format.f = 44100; - format.samp_format = STEREO_MSB; - abe_add_subroutine(&abe_irq_pingpong_player_id, - (abe_subroutine2) abe_default_irq_pingpong_player_32bits, - SUB_0_PARAM, (abe_uint32*)0); - - abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, - abe_irq_pingpong_player_id, N_SAMPLES_BYTES, - &data_sink, PING_PONG_WITH_MCU_IRQ); - - abe_enable_data_transfer(MM_DL_PORT); /* enable all the data paths */ - abe_enable_data_transfer(PDM_DL_PORT); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_serial_port(MM_EXT_OUT_PORT, &format, MCBSP2_TX); - abe_enable_data_transfer(MM_EXT_OUT_PORT); - - /* mixers' configuration */ - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - break; - } + static abe_int32 time_offset, state, gain=0x040000, i; + abe_data_format_t format; + abe_uint32 data_sink; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + //-----------------------------Scenario 1- 16kHz first + switch (state) + { + case 0: + { state ++; + + time_offset = abe_test_read_time(); + abe_reset_hal (); + abe_load_fw (); + abe_short_ramps (); + + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + abe_set_opp_processing (OPP); + //abe_set_opp_processing (ABE_OPP50); + abe_write_event_generator(EVENT_44100); /* "tick" of the audio engine */ + + /* connect a Ping-Pong cache-flush protocol to MM_DL port */ + #define N_SAMPLES_BYTES (25 *8) /* half-buffer size in bytes, 32/32 data format */ + format.f = 44100; format.samp_format = STEREO_MSB; + abe_add_subroutine (&abe_irq_pingpong_player_id, (abe_subroutine2) abe_default_irq_pingpong_player_32bits, SUB_0_PARAM, (abe_uint32*)0); + +// #define N_SAMPLES_BYTES (25 *4) /* half-buffer size in bytes, 16|16 data format */ +// format.f = 48000; format.samp_format = STEREO_16_16; +// abe_add_subroutine (&abe_irq_pingpong_player_id, (abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0); + + abe_connect_irq_ping_pong_port (MM_DL_PORT, &format, abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ); + + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + abe_enable_data_transfer (PDM_DL_PORT); + + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_serial_port (MM_EXT_OUT_PORT, &format, MCBSP2_TX); + abe_enable_data_transfer (MM_EXT_OUT_PORT); + + /* mixers' configuration */ + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_TONES); + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); + + } + break; + } } + +/* ========================================================================== */ /** * @fn ABE_TEST_SCENARIO_4 () * -* DMA AUDIO PLAYER + DMA VOICE CALL 8kHz OPP 50% +* DMA AUDIO PLAYER + DMA VOICE CALL 8kHz OPP 25% */ +/* ========================================================================= */ void abe_test_scenario_4 (void) { - static abe_int32 time_offset, state; - abe_data_format_t format; - abe_dma_t dma_sink; - abe_uint32 current_time; - abe_use_case_id UC2[] = { - ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, - ABE_RINGER_TONES, - (abe_use_case_id)0 - }; - // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; - abe_opp_t OPP; - abe_hw_config_init_t CONFIG; - - /* Scenario 1- 16kHz first */ - switch (state) { - case 0: - state ++; - time_offset = abe_test_read_time(); - - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC2, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - /* enable all DMIC aquisition */ - abe_enable_data_transfer(MM_UL_PORT); - /* enable large-band DMIC aquisition */ - abe_enable_data_transfer(MM_UL2_PORT); - abe_enable_data_transfer(VX_UL_PORT); - - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - format.f = 24000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink); - abe_enable_data_transfer(TONES_DL_PORT); - abe_enable_data_transfer(VX_DL_PORT); - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(VIB_DL_PORT); - - /* DMIC ATC can be enabled even if the DMIC */ - abe_enable_data_transfer(DMIC_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - abe_enable_data_transfer(PDM_UL_PORT); - - /* mixers' configuration = voice on earphone + music on hands-free path */ - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); - - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER); - - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_TONES); - abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_0MS, MIX_AUDUL_INPUT_UPLINK); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_MM_DL); - abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_0MS, MIX_AUDUL_INPUT_VX_DL); - - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_TONES); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_DL); - abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_0MS, MIX_VXREC_INPUT_MM_DL); - abe_write_mixer(MIXVXREC, GAIN_M6dB, RAMP_0MS, MIX_VXREC_INPUT_VX_UL); - - abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - - abe_write_gain(GAINS_SPLIT , GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - //abe_write_gain(GAINS_EANC , GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - //abe_write_gain(GAINS_EANC, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_0MS, GAIN_LEFT_OFFSET); - abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_0MS, GAIN_RIGHT_OFFSET); - break; - case 1: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100) - break; - else - state ++; /* Gains switch */ - break; - case 2: - current_time = abe_test_read_time(); - if ((current_time - time_offset) < 100000) - break; - else - state ++; /* Internal buffer analysis */ - break; - default: - state = 0; - break; - } + abe_set_debug_trace (-1); + abe_short_ramps (); + } -#if 0 - - /* - * build the default uplink router configurations - */ - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); -#if 0 - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]); - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC2, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC2]); - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC3, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC3]); -#endif - /* meaningful other microphone configuration can be added here */ - /* init hardware components */ - abe_hw_configuration(); - - /* enable the VX_UL path with Analog microphones from Phoenix */ - /* MM_DL INIT - connect a DMA channel to MM_DL port (ATC FIFO) */ - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - - /* VX_DL INIT - connect a DMA channel to VX_DL port (ATC FIFO) */ - format.f = 16000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - - /* VX_UL INIT - connect a DMA channel to VX_UL port (ATC FIFO) */ - format.f = 16000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - - /* MM_UL2 INIT - connect a DMA channel to MM_UL2 port (ATC FIFO) */ - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - - /* MM_UL INIT - connect a DMA channel to MM_UL port (ATC FIFO) */ - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL_PORT, &format, ABE_CBPR3_IDX, &dma_sink); - - /* TONES INIT - connect a DMA channel to TONES port (ATC FIFO) */ - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(TONES_DL_PORT, &format, ABE_CBPR5_IDX, &dma_sink); - - /* VIBRA/HAPTICS INIT - connect a DMA channel to VIBRA/HAPTICS port (ATC FIFO) */ - format.f = 24000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VIB_DL_PORT, &format, ABE_CBPR6_IDX, &dma_sink); - - /* mixers' default configuration = voice on earphone + music on hands-free path */ - case 2: - /* Scenario 2- 8kHz first */ - switch (time10us) { - case 1: - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC2, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - // enables VOICECALL-MMDL-MMUL-8/16kHz-ROUTING - abe_reset_hal(); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL); - - /* enable large-band DMIC aquisition */ - abe_enable_data_transfer(MM_UL2_PORT); - /* enable all DMIC aquisition */ - abe_enable_data_transfer(MM_UL_PORT); - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(VX_DL_PORT); - abe_enable_data_transfer(VX_UL_PORT); - abe_enable_data_transfer(PDM_UL_PORT); - /* DMIC ATC can be enabled even if the DMIC */ - abe_enable_data_transfer(DMIC_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - abe_enable_data_transfer(TONES_DL_PORT); - break; - case 100: - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_1MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, GAIN_M6dB, RAMP_5MS, MIX_DL1_INPUT_MM_UL2); - break; - case 1200: - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]); - break; - case 8000: // end - fcloseall(); - exit(-2); - } - /* case scenario_id ==2 */ - break; - case 3: - /* Scenario 3 PING-PONG DMAreq */ - switch (time10us) { - case 1: - /* Ping-Pong access through MM_DL using Left/Right 16bits/16bits data format */ - /* To be added here : Device driver initialization following - abe_read_hardware_configuration() returned data - McPDM_DL : 6 slots activated (5 + Commands) - DMIC : 6 microphones activated - McPDM_UL : 2 microphones activated (No status) - */ - abe_read_hardware_configuration(UC5, &OPP, &CONFIG); - abe_set_opp_processing(OPP); - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - /* MM_DL INIT (overwrite the previous default initialization made above */ - format.f = 48000; - format.samp_format = MONO_MSB; - - /* connect a Ping-Pong SDMA protocol to MM_DL port with Ping-Pong 12 mono - * samples (12x4 bytes for each ping & pong size)*/ - abe_connect_dmareq_ping_pong_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, (12 * 4), &dma_sink); - - /* mixers' configuration = voice on earphone + music on hands-free path */ - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL); - - /* Here : connect the sDMA to "dma_sink" content */ - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - break; - case 8000: // end - fcloseall(); - exit(-3); +/* ========================================================================== */ +/** +* @fn ABE_TEST_SCENARIO_5 () +* +* ASRC TESTS +*/ +/* ========================================================================= */ +void abe_test_scenario_5 (void) +{ + static abe_int32 time_offset, state; + abe_data_format_t format; + abe_dma_t dma_sink; + abe_uint32 current_time; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; + // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + //-----------------------------Scenario 1- 16kHz first + switch (state) + { + case 0: + { state ++; + abe_reset_hal (); + abe_load_fw (); + abe_set_debug_trace (-1); + abe_short_ramps (); + + time_offset = abe_test_read_time(); + + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + abe_set_opp_processing (OPP); /* sets the OPP100 on FW05.xx */ + abe_write_event_generator (CONFIG.HAL_EVENT_SELECTION); /* "tick" of the audio engine */ + + abe_set_router_configuration (UPROUTE, UPROUTE_CONFIG_AMIC, (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); + + format.f = 8000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (VX_UL_PORT, &format, MCBSP2_TX); + format.f = 8000; format.samp_format = STEREO_RSHIFTED_16; abe_connect_serial_port (VX_DL_PORT, &format, MCBSP2_RX); + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_serial_port (MM_DL_PORT, &format, MCBSP3_RX); + + abe_enable_data_transfer (VX_UL_PORT ); + abe_enable_data_transfer (VX_DL_PORT ); + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + + // SERIAL PORTS TEST + // abe_select_main_port (MM_DL_PORT); + + abe_enable_data_transfer (PDM_DL_PORT); + abe_enable_data_transfer (PDM_UL_PORT); + + /* mixers' configuration = voice on earphone + music on hands-free path */ + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); + abe_write_mixer (MIXDL1, GAIN_M6dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); + abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); + + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL); + abe_write_mixer (MIXDL2, GAIN_M6dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); + abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); + } + break; + case 1: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 34) break; + else + { + state ++; + // Init ASRC(s) + abe_init_asrc_vx_dl (0); + abe_init_asrc_vx_ul (0); + abe_init_asrc_mm_dl (0); + // abe_init_asrc_mm_dl (1250); } - /* case scenario_id ==3 */ - break; - case 40: - /* Scenario 4.0 PING_PONG+ IRQ TO MCU */ - switch (time10us) { - case 1: - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC5, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - /* MM_DL INIT (overwrite the previous default initialization made above */ - format.f = 48000; - format.samp_format = STEREO_16_16; - - /* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */ - abe_add_subroutine(&abe_irq_pingpong_player_id, - (abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0); - - #define N_SAMPLES_BYTES (24 *4) // @@@@ to be tuned - abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, - abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ); - - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER); - - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - break; - case 1200: - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]); - break; - case 2400: // end - fcloseall(); - exit(-4); + break; + case 2: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 10000) break; + else + { + state ++; + // abe_write_asrc (VX_UL_PORT, -1250); + // abe_write_asrc (VX_DL_PORT, -1250); + // abe_write_asrc (MM_DL_PORT, -1250); } - /* case scenario_id ==4 */ - break; - case 41: - /* Scenario 4.1 PING_PONG+ IRQ TO MCU 32BITS */ - switch (time10us) { - case 1: - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC5, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - /* MM_DL INIT(overwrite the previous default initialization made above */ - format.f = 48000; - format.samp_format = STEREO_MSB; - - /* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */ - abe_add_subroutine(&abe_irq_pingpong_player_id, - (abe_subroutine2) abe_default_irq_pingpong_player_32bits, SUB_0_PARAM, (abe_uint32*)0); - - #define N_SAMPLES_BYTES (24 * 4) // @@@@ to be tuned - abe_connect_irq_ping_pong_port(MM_DL_PORT, &format, - abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ); - - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_TONES); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_VX_DL); - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_0MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_0MS, MIX_DL1_INPUT_MM_UL2); - - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_TONES); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_VX_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_0MS, MIX_DL2_INPUT_MM_DL); - abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_0MS, MIX_DL2_INPUT_MM_UL2); - - abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_0MS, MIX_SDT_INPUT_UP_MIXER); - abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_0MS, MIX_SDT_INPUT_DL1_MIXER); - - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT ); - abe_enable_data_transfer(PDM_DL_PORT); - - break; - case 1200: - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]); - break; - - case 2400: // end - fcloseall(); - exit(-4); + break; + case 3: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 100000) break; + else + { state ++; + // abe_set_asrc_drift_control (VX_UL_PORT, FORCED_DRIFT_CONTROL); + abe_write_asrc (VX_UL_PORT, -100); + // abe_set_asrc_drift_control (VX_DL_PORT, FORCED_DRIFT_CONTROL); + abe_write_asrc (VX_DL_PORT, -200); + // abe_set_asrc_drift_control (MM_DL_PORT, FORCED_DRIFT_CONTROL); + abe_write_asrc (MM_DL_PORT, -300); + + } + break; + default: state = 0; break; + } +} + + +/* ========================================================================== */ +/** +* @fn ABE_TEST_SCENARIO_6 () +* +* APS TESTS +*/ +/* ========================================================================= */ +void abe_test_scenario_6 (void) +{ + static abe_int32 time_offset, state; + abe_data_format_t format; + abe_uint32 data_sink; + abe_uint32 current_time; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, ABE_RINGER_TONES, (abe_use_case_id)0}; + // abe_use_case_id UC5[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + //-----------------------------Scenario 1- 16kHz first + switch (state) + { + case 0: + + { state ++; + abe_reset_hal (); + abe_load_fw (); + abe_set_debug_trace (-1); + abe_short_ramps (); + + time_offset = abe_test_read_time(); + + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + abe_set_opp_processing (OPP); /* sets the OPP100 on FW05.xx */ + abe_write_event_generator (CONFIG.HAL_EVENT_SELECTION); /* "tick" of the audio engine */ + + /* connect a Ping-Pong cache-flush protocol to MM_DL port */ + #define N_SAMPLES_BYTES (25 *8) /* half-buffer size in bytes, 32/32 data format */ + format.f = 44100; format.samp_format = STEREO_MSB; + abe_add_subroutine (&abe_irq_pingpong_player_id, (abe_subroutine2) abe_default_irq_pingpong_player_32bits, SUB_0_PARAM, (abe_uint32*)0); + +// #define N_SAMPLES_BYTES (25 *4) /* half-buffer size in bytes, 16|16 data format */ +// format.f = 48000; format.samp_format = STEREO_16_16; +// abe_add_subroutine (&abe_irq_pingpong_player_id, (abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0); + + abe_connect_irq_ping_pong_port (MM_DL_PORT, &format, abe_irq_pingpong_player_id, N_SAMPLES_BYTES, &data_sink, PING_PONG_WITH_MCU_IRQ); + + /* mixers' configuration = voice on earphone + music on hands-free path */ + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL); + abe_write_mixer (MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL); + + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + abe_enable_data_transfer (PDM_DL_PORT); + + /* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */ + abe_add_subroutine (&abe_irq_aps_adaptation_id, (abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (abe_uint32*)0); + } + break; + + case 1: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 100000) break; + else + { state ++; + } + break; + default: state = 0; break; + } +} + +/* ========================================================================== */ +/** +* @fn ABE_TEST_SCENARIO_7 () +* +* GAIN RAMP TESTS +*/ +/* ========================================================================= */ +void abe_test_scenario_7 (void) +{ + static abe_int32 time_offset, state, current_time; + abe_data_format_t format; + abe_dma_t dma_sink; + abe_use_case_id UC2[] = {ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE, (abe_use_case_id)0}; + abe_opp_t OPP; + abe_hw_config_init_t CONFIG; + + switch (state) + { + case 0: + { state ++; + abe_reset_hal (); + abe_load_fw (); + abe_set_debug_trace (-1); + + time_offset = abe_test_read_time(); + + abe_read_hardware_configuration (UC2, &OPP, &CONFIG); /* check HW config and OPP config */ + abe_set_opp_processing (OPP); + abe_write_event_generator (CONFIG.HAL_EVENT_SELECTION); /* "tick" of the audio engine */ + + format.f = 48000; format.samp_format = STEREO_MSB; abe_connect_cbpr_dmareq_port (MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); + abe_enable_data_transfer (MM_DL_PORT ); /* enable all the data paths */ + abe_enable_data_transfer (PDM_DL_PORT); + + /* mixers' configuration = voice on earphone + music on hands-free path */ + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_5MS, MIX_DL1_INPUT_MM_DL); + } + break; + case 1: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 10000) break; + else + { + state ++; + abe_write_mixer (MIXDL1, GAIN_MUTE, RAMP_5MS, MIX_DL1_INPUT_MM_DL); } - /* case scenario_id ==4 */ - break; - - case 5: - /* Scenario 5 CHECK APS ADAPTATION ALGO */ - switch (time10us) { - case 1: - /* check HW config and OPP config */ - abe_read_hardware_configuration(UC5, &OPP, &CONFIG); - /* sets the OPP100 on FW05.xx */ - abe_set_opp_processing(OPP); - /* "tick" of the audio engine */ - abe_write_event_generator(CONFIG.HAL_EVENT_SELECTION); - - /* MM_DL INIT(overwrite the previous default initialization made above */ - format.f = 48000; - format.samp_format = STEREO_16_16; - - /* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */ - abe_add_subroutine(&abe_irq_pingpong_player_id, - (abe_subroutine2) abe_default_irq_pingpong_player, SUB_0_PARAM, (abe_uint32*)0); - - #define N_SAMPLES_BYTES (24 *4) // @@@@ to be tuned - abe_connect_irq_ping_pong_port(MM_DL_PORT, - &format, abe_irq_pingpong_player_id, N_SAMPLES_BYTES, - &data_sink, PING_PONG_WITH_MCU_IRQ); - - /* mixers' configuration = voice on earphone + music on hands-free path */ - abe_write_mixer(MIXDL1, GAIN_0dB, RAMP_2MS, MIX_DL1_INPUT_MM_DL); - abe_write_mixer(MIXDL2, GAIN_0dB, RAMP_50MS, MIX_DL2_INPUT_MM_DL); - - /* enable all the data paths */ - abe_enable_data_transfer(MM_DL_PORT); - abe_enable_data_transfer(PDM_DL_PORT); - - /* connect a Ping-Pong cache-flush protocol to MM_DL port with 50Hz (20ms) rate */ - abe_add_subroutine(&abe_irq_aps_adaptation_id, - (abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (abe_uint32*)0); - break; - } /* case scenario_id ==5 */ - - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_AMIC, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_AMIC]); - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC1, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC1]); - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC2, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC2]); - abe_set_router_configuration(UPROUTE, UPROUTE_CONFIG_DMIC3, - (abe_router_t *) abe_router_ul_table_preset[UPROUTE_CONFIG_DMIC3]); - case UC31_VOICE_CALL_8KMONO: - abe_disable_data_transfer(VX_DL_PORT); - abe_disable_data_transfer(VX_UL_PORT); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 8000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - abe_enable_data_transfer(VX_DL_PORT); - abe_enable_data_transfer(VX_UL_PORT); - case UC32_VOICE_CALL_8KSTEREO: - format.f = 8000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 8000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - case UC33_VOICE_CALL_16KMONO: - format.f = 16000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 16000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - case UC34_VOICE_CALL_16KSTEREO: - format.f = 16000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_DL_PORT, &format, ABE_CBPR1_IDX, &dma_sink); - format.f = 16000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(VX_UL_PORT, &format, ABE_CBPR2_IDX, &dma_sink); - case UC35_MMDL_MONO: - format.f = 48000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - case UC36_MMDL_STEREO: - format.f = 48000; - format.samp_format = STEREO_MSB; - abe_connect_cbpr_dmareq_port(MM_DL_PORT, &format, ABE_CBPR0_IDX, &dma_sink); - case UC37_MMUL2_MONO: - format.f = 48000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - case UC38_MMUL2_STEREO: - format.f = 48000; - format.samp_format = MONO_MSB; - abe_connect_cbpr_dmareq_port(MM_UL2_PORT, &format, ABE_CBPR4_IDX, &dma_sink); - case UC91_ASRC_DRIFT1: - abe_set_asrc_drift_control(VX_UL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(VX_UL_PORT, 100); - abe_set_asrc_drift_control(VX_DL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(VX_DL_PORT, 200); - abe_set_asrc_drift_control(MM_DL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(MM_DL_PORT, 300); - case UC92_ASRC_DRIFT2: - abe_set_asrc_drift_control(VX_UL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(VX_UL_PORT, -100); - abe_set_asrc_drift_control(VX_DL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(VX_DL_PORT, -200); - abe_set_asrc_drift_control(MM_DL_PORT, FORCED_DRIFT_CONTROL); - abe_write_asrc(MM_DL_PORT, -300); -#endif + break; + case 2: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 20000) break; + else + { + state ++; + abe_write_mixer (MIXDL1, GAIN_0dB, RAMP_10MS, MIX_DL1_INPUT_MM_DL); + } + break; + case 3: + current_time = abe_test_read_time(); + if ((current_time - time_offset) < 30000) break; + else state ++; + break; + default: state = 0; break; + } +} + diff --git a/sound/soc/omap/abe/abe_test.h b/sound/soc/omap/abe/abe_test.h index b84ee3dafcde..0cc954841fdc 100644 --- a/sound/soc/omap/abe/abe_test.h +++ b/sound/soc/omap/abe/abe_test.h @@ -1,28 +1,47 @@ -/* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. +/* ============================================================================= +* Texas Instruments OMAP(TM) Platform Software +* (c) Copyright 2009 Texas Instruments Incorporated. All Rights Reserved. +* +* Use of this software is controlled by the terms and conditions found +* in the license agreement under which this software has been supplied. +* =========================================================================== */ +/** + * @file ABE_TEST.H + * + * Variable references * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * @path + * @rev 01.00 */ +/* ---------------------------------------------------------------------------- +*! +*! Revision History +*! =================================== +*! 27-August-2009 Original (LLF) +* =========================================================================== */ -#ifndef _ABE_TEST_H_ -#define _ABE_TEST_H_ + +#ifndef abe_test_def +#define abe_test_def /* - * HAL test API - */ -void abe_auto_check_data_format_translation(void); -void abe_check_opp(void); -void abe_check_dma(void); -void abe_debug_and_non_regression(void); -void abe_check_mixers_gain_update(void); -void abe_test_scenario(abe_int32 scenario_id); - + * ============ HAL test API ============================================================================= + */ +#ifdef __cplusplus +extern "C" { +#endif +void abe_auto_check_data_format_translation (void); +void abe_check_opp (void); +void abe_check_dma (void); +void abe_debug_and_non_regression (void); +void abe_check_mixers_gain_update (void); +void abe_test_scenario (abe_int32 scenario_id); +#ifdef __cplusplus +} +#endif /* - * HAL test DATA - */ + * ============ HAL test DATA ============================================================================= + */ + -#endif /* _ABE_TEST_H_ */ +#endif /* REFDEF */ diff --git a/sound/soc/omap/abe/abe_typ.h b/sound/soc/omap/abe/abe_typ.h index 34368261ae9e..76de2c370675 100644 --- a/sound/soc/omap/abe/abe_typ.h +++ b/sound/soc/omap/abe/abe_typ.h @@ -1,82 +1,78 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #include "abe_def.h" -#include "abe_ext.h" #include "abe_initxxx_labels.h" -#ifndef _ABE_TYP_H_ -#define _ABE_TYP_H_ +#ifndef ABETYP +#define ABETYP -#ifdef __cplusplus -extern "C" { -#endif /* * BASIC TYPES */ - #define MAX_UINT8 ((((1L << 7) -1)<<1) +1) #define MAX_UINT16 ((((1L << 15) -1)<<1) +1) #define MAX_UINT32 ((((1L << 31) -1)<<1) +1) -typedef char abe_flag; -typedef unsigned char abe_uint8; -typedef char abe_int8; -typedef unsigned short abe_uint16; -typedef short abe_int16; -typedef unsigned long abe_uint32; -typedef long abe_int32; -typedef float abe_float; -typedef double abe_double; - -typedef abe_uint32 abe_errc_t; -typedef abe_int32 abe_millibel; +#define s8 char +#define u8 unsigned char +#define s16 short +#define u16 unsigned short +#define s32 int +#define u32 unsigned int -//typedef abe_uint32 abe_millisecond; -//typedef abe_uint32 abe_milliHertz; -//typedef abe_uint32 abe_millimeter; -//typedef abe_uint32 abe_millidegree; -//typedef abe_uint32 abe_permille; -//typedef abe_uint32 abe_microsecond; +/* returned status from HAL APIs */ +#define abehal_status u32 -typedef abe_uint32 abe_result; -typedef abe_millibel abe_gain_t; /* smoothed gain amplitude and ramp */ -typedef abe_uint32 abe_ramp_t; +/* 4 bytes Bit field indicating the type of informations to be traced */ +typedef u32 abe_dbg_mask_t; -typedef abe_uint32 abe_freq_t; /* 4 bytes hertz */ -typedef abe_uint32 abe_millis_t; /* 4 bytes milliseconds */ -typedef abe_uint32 abe_micros_t; /* 4 bytes microseconds */ +/* scheduling task loops (250us / 272us with respectively 48kHz / + 44.1kHz on Phoenix). */ +typedef u32 abe_dbg_t; -typedef abe_uint32 abe_dbg_mask_t; /* 4 bytes bit field indicating the type of informations to be traced */ -typedef abe_uint32 abe_time_stamp_t; /* 4 bytes infinite loop 32bits counter incremented on each firmware loop */ +/* Index to the table of sequences */ +typedef u32 abe_seq_code_t; -/* scheduling task loops (250us / 272us with respectively 48kHz / 44.1kHz on Phoenix). */ -typedef abe_uint32 abe_dbg_t; /* debug filter */ +/* Index to the table of subroutines called in the sequence */ +typedef u32 abe_sub_code_t; -typedef abe_uint32 abe_seq_code_t; /* Index to the table of sequences */ -typedef abe_uint32 abe_sub_code_t; /* Index to the table of subroutines called in the sequence */ +/* subroutine with no parameter */ +typedef void (* abe_subroutine0) (void); -typedef void (* abe_subroutine0)(void); /* subroutine with no parameter */ -typedef void (* abe_subroutine1)(abe_uint32); /* subroutine with one parameter */ -typedef void (* abe_subroutine2)(abe_uint32, abe_uint32); /* subroutine with two parameters */ -typedef void (* abe_subroutine3)(abe_uint32, abe_uint32, abe_uint32); /* subroutine with three parameters */ -typedef void (* abe_subroutine4)(abe_uint32, abe_uint32, abe_uint32, abe_uint32); /* subroutine with four parameters */ +/* subroutine with one parameter */ +typedef void (* abe_subroutine1) (u32); +typedef void (* abe_subroutine2) (u32, u32); +typedef void (* abe_subroutine3) (u32, u32, u32); +typedef void (* abe_subroutine4) (u32, u32, u32, u32); /* * CODE PORTABILITY - FUTURE PATCHES * - * 32bits field for having the code compatible with future revisions of the hardware (audio integration) - * or evolution of the software partitionning. Used for the highest level APIs (launch_sequences) + * 32bits field for having the code compatible with future revisions of + * the hardware (audio integration) or evolution of the software + * partitionning. Used for the highest level APIs (launch_sequences) */ -typedef abe_uint32 abe_patch_rev; +typedef u32 abe_patch_rev; /* * ENUMS @@ -85,129 +81,113 @@ typedef abe_uint32 abe_patch_rev; /* * MEMORY CONFIG TYPE * - * 0: Ultra Lowest power consumption audio player - * 1: OPP 25% (simple multimedia features) - * 2: OPP 50% (multimedia and voice calls) - * 3: OPP100% (EANC, multimedia complex use-cases) - */ -typedef enum { - ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE = 1, - ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER, - ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL, - ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT, - ABE_MULTIMEDIA_AUDIO_RECORDER, - ABE_VIBRATOR_OR_HAPTICS, - ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER, - ABE_RINGER_TONES, - ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER, - - ABE_LAST_USE_CASE -} abe_use_case_id; - -/* - * OPP TYPE - * - * 0: Ultra Lowest power consumption audio player - * 1: OPP 25% (simple multimedia features) - * 2: OPP 50% (multimedia and voice calls) - * 3: OPP100% (EANC, multimedia complex use-cases) + * 0: Ultra Lowest power consumption audio player + * 1: OPP 25% (simple multimedia features) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (multimedia complex use-cases) */ -typedef enum { - ABE_OPP0 = 0, - ABE_OPP25, ABE_OPP50, ABE_OPP100 -} abe_opp_t; + +#define ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE 1 +#define ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER 2 +#define ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL 3 +#define ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT 4 +#define ABE_MULTIMEDIA_AUDIO_RECORDER 5 +#define ABE_VIBRATOR_OR_HAPTICS 6 +#define ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER 7 +#define ABE_RINGER_TONES 8 +#define ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER 9 +#define ABE_LAST_USE_CASE 10 + /* - * IIR TYPE + * OPP TYPE * - * 0: Ultra Lowest power consumption audio player - * 1: OPP 25% (simple multimedia features) + * 0: Ultra Lowest power consumption audio player + * 1: OPP 25% (simple multimedia features) + * 2: OPP 50% (multimedia and voice calls) + * 3: OPP100% (multimedia complex use-cases) */ -typedef enum { - ABE_IIR_TYPE_1 = 0, - ABE_IIR_TYPE_2 -} abe_iir_t; +#define ABE_OPP0 0 +#define ABE_OPP25 1 +#define ABE_OPP50 2 +#define ABE_OPP100 3 /* * DMIC DECIMATION RATIO * */ -typedef enum { - ABE_DEC16 = 16, - ABE_DEC25 = 25, - ABE_DEC32 = 32, - ABE_DEC40 = 40 -} abe_dmic_ratio_t; +#define ABE_DEC16 16 +#define ABE_DEC25 25 +#define ABE_DEC32 32 +#define ABE_DEC40 40 + /* * SAMPLES TYPE * - * mono 16bits sample LSB aligned, 16 MSB bits are unused - * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP TX purpose. - * mono sample MSB aligned (16/24/32bits) + * mono 16bits sample LSB aligned, 16 MSB bits are unused + * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP + * TX purpose. + * mono sample MSB aligned (16/24/32bits) * two successive mono samples in one 32bits container - * Two L/R 16bits samples in a 32bits container, - * Two channels defined with two MSB aligned samples - * Three channels defined with three MSB aligned samples (MIC) - * Four channels defined with four MSB aligned samples (MIC) - * . . . - * Eight channels defined with six MSB aligned samples (MIC) - */ -typedef enum { - MONO_MSB = 1, - MONO_RSHIFTED_16, STEREO_RSHIFTED_16, /* only used for McBSP_TX */ - STEREO_16_16, - STEREO_MSB, THREE_MSB, FOUR_MSB, FIVE_MSB, SIX_MSB, SEVEN_MSB, EIGHT_MSB, NINE_MSB, TEN_MSB, -} abe_samp_t; - -/* - * PORT PROTOCOL TYPE - */ -typedef enum { - SLIMBUS_PORT_PROT = 1, - SERIAL_PORT_PROT, - TDM_SERIAL_PORT_PROT, - DMIC_PORT_PROT, - MCPDMDL_PORT_PROT, - MCPDMUL_PORT_PROT, - PINGPONG_PORT_PROT, - DMAREQ_PORT_PROT, -} abe_port_protocol_switch_id; - -/* - * PORT IDs, this list is aligned with the FW data mapping - */ -typedef enum { - DMIC_PORT = 0, - PDM_UL_PORT, /* analog MICs */ - BT_VX_UL_PORT, /* BT uplink (8/16 kHz)*/ - - /* AE source ports - Uplink */ - MM_UL_PORT, /* up to 5 stereo channels */ - MM_UL2_PORT, /* stereo FM record path (4) */ - VX_UL_PORT, /* stereo FM record path */ - - /* AE sink ports - Downlink */ - MM_DL_PORT, /* multimedia player audio path */ - VX_DL_PORT, - TONES_DL_PORT, /* 8 */ - VIB_DL_PORT, - - /* AE source ports - Downlink */ - BT_VX_DL_PORT, - PDM_DL_PORT, /* ABE --> BT (8/16kHz) */ - MM_EXT_OUT_PORT, /* 12 */ - MM_EXT_IN_PORT, - TDM_DL_PORT, - TDM_UL_PORT, - DEBUG_PORT, /* 16 */ - - LAST_PORT_ID /* dummy port used to declare the other tasks of the scheduler */ -} abe_port_id; - -/* - * Definition for the compatibility with HAL05xx - */ + * Two L/R 16bits samples in a 32bits container, + * Two channels defined with two MSB aligned samples + * Three channels defined with three MSB aligned samples (MIC) + * Four channels defined with four MSB aligned samples (MIC) + . . . + * Eight channels defined with eight MSB aligned samples (MIC) + */ +#define MONO_MSB 1 +#define MONO_RSHIFTED_16 2 +#define STEREO_RSHIFTED_16 3 +#define STEREO_16_16 4 +#define STEREO_MSB 5 +#define THREE_MSB 6 +#define FOUR_MSB 7 +#define FIVE_MSB 8 +#define SIX_MSB 9 +#define SEVEN_MSB 10 +#define EIGHT_MSB 11 +#define NINE_MSB 12 +#define TEN_MSB 13 + +/* + * PORT PROTOCOL TYPE - abe_port_protocol_switch_id + */ +#define SLIMBUS_PORT_PROT 1 +#define SERIAL_PORT_PROT 2 +#define TDM_SERIAL_PORT_PROT 3 +#define DMIC_PORT_PROT 4 +#define MCPDMDL_PORT_PROT 5 +#define MCPDMUL_PORT_PROT 6 +#define PINGPONG_PORT_PROT 7 +#define DMAREQ_PORT_PROT 8 + + +/* + * PORT IDs, this list is aligned with the FW data mapping + */ +#define DMIC_PORT 0 +#define PDM_UL_PORT 1 +#define BT_VX_UL_PORT 2 +#define MM_UL_PORT 3 +#define MM_UL2_PORT 4 +#define VX_UL_PORT 5 +#define MM_DL_PORT 6 +#define VX_DL_PORT 7 +#define TONES_DL_PORT 8 +#define VIB_DL_PORT 9 +#define BT_VX_DL_PORT 10 +#define PDM_DL_PORT 11 +#define MM_EXT_OUT_PORT 12 +#define MM_EXT_IN_PORT 13 +#define TDM_DL_PORT 14 +#define TDM_UL_PORT 15 +#define DEBUG_PORT 16 +#define LAST_PORT_ID 17 + + +/* definitions for the compatibility with HAL05xx */ #define PDM_DL1_PORT PDM_DL_PORT #define PDM_DL2_PORT PDM_DL_PORT #define PDM_VIB_PORT PDM_DL_PORT @@ -219,520 +199,652 @@ typedef enum { * ABE_DL_SRC_ID source of samples */ -typedef enum { - SRC_DL1_MIXER_OUTPUT = DL1_M_labelID, - SRC_SDT_MIXER_OUTPUT = SDT_M_labelID, - SRC_DL1_GAIN_OUTPUT = DL1_GAIN_out_labelID, - SRC_DL1_EQ_OUTPUT = DL1_EQ_labelID, - SRC_DL2_GAIN_OUTPUT = DL2_GAIN_out_labelID, - SRC_DL2_EQ_OUTPUT = DL2_EQ_labelID, - SRC_MM_DL = MM_DL_labelID, - SRC_TONES_DL = Tones_labelID, - SRC_VX_DL = VX_DL_labelID, - SRC_VX_UL = VX_UL_labelID, - SRC_MM_UL2 = MM_UL2_labelID, - SRC_MM_UL = MM_UL_labelID, -} abe_dl_src_id; - - -/* - * ANA_PORT_ID Analog companion audio port - */ -typedef enum { - EAR_PHOENIX = 1, - HS_L, - HS_R, - IHF_L, - IHF_R, - VIBRA1, - VIBRA2 -} abe_ana_port_id ; - -/* - * abe_patched_pattern_id: selection of the audio engine - * signal to replace by a precomputed pattern - */ -typedef enum { - DBG_PATCH_AMIC = 1, - DBG_PATCH_DMIC1, - DBG_PATCH_DMIC2, - DBG_PATCH_DMIC3, - DBG_PATCH_VX_REC, - DBG_PATCH_BT_UL, - DBG_PATCH_MM_DL, - DBG_PATCH_DL2_EQ, - DBG_PATCH_VIBRA, - DBG_PATCH_MM_EXT_IN, - DBG_PATCH_EANC_FBK_Out, - DBG_PATCH_MIC4, - DBG_PATCH_MM_DL_MIXDL1, - DBG_PATCH_MM_DL_MIXDL2, -} abe_patched_pattern_id ; - -typedef abe_int32 headset_offset_t; /* Calibration data from the analog companion */ +#define SRC_DL1_MIXER_OUTPUT DL1_M_labelID +#define SRC_SDT_MIXER_OUTPUT SDT_M_labelID +#define SRC_DL1_GAIN_OUTPUT DL1_GAIN_out_labelID +#define SRC_DL1_EQ_OUTPUT DL1_EQ_labelID +#define SRC_DL2_GAIN_OUTPUT DL2_GAIN_out_labelID +#define SRC_DL2_EQ_OUTPUT DL2_EQ_labelID +#define SRC_MM_DL MM_DL_labelID +#define SRC_TONES_DL Tones_labelID +#define SRC_VX_DL VX_DL_labelID +#define SRC_VX_UL VX_UL_labelID +#define SRC_MM_UL2 MM_UL2_labelID +#define SRC_MM_UL MM_UL_labelID + +/* + * abe_patched_pattern_id selection of the audio engine signal to + * replace by a precomputed pattern + */ + +#define DBG_PATCH_AMIC 1 +#define DBG_PATCH_DMIC1 2 +#define DBG_PATCH_DMIC2 3 +#define DBG_PATCH_DMIC3 4 +#define DBG_PATCH_VX_REC 5 +#define DBG_PATCH_BT_UL 6 +#define DBG_PATCH_MM_DL 7 +#define DBG_PATCH_DL2_EQ 8 +#define DBG_PATCH_VIBRA 9 +#define DBG_PATCH_MM_EXT_IN 10 +#define DBG_PATCH_EANC_FBK_Out 11 +#define DBG_PATCH_MIC4 12 +#define DBG_PATCH_MM_DL_MIXDL1 13 +#define DBG_PATCH_MM_DL_MIXDL2 14 /* * Signal processing module names - EQ APS MIX ROUT */ -#define FEAT_EQ1 1 /* equalizer downlink path headset + earphone */ -#define FEAT_EQ2L FEAT_EQ1+1 /* equalizer downlink path integrated handsfree LEFT */ -#define FEAT_EQ2R FEAT_EQ2L+1 /* equalizer downlink path integrated handsfree RIGHT */ -#define FEAT_EQSDT FEAT_EQ2R+1 /* equalizer downlink path side-tone */ -#define FEAT_EQMIC FEAT_EQSDT+1 /* equalizer uplink path first DMIC pair */ -#define FEAT_APS1 FEAT_EQMIC+1 /* Acoustic protection for headset */ -#define FEAT_APS2 FEAT_APS1+1 /* acoustic protection high-pass filter for handsfree "Left" */ -#define FEAT_APS3 FEAT_APS2+1 /* acoustic protection high-pass filter for handsfree "Right" */ -#define FEAT_ASRC1 FEAT_APS3+1 /* asynchronous sample-rate-converter for the downlink voice path */ -#define FEAT_ASRC2 FEAT_ASRC1+1 /* asynchronous sample-rate-converter for the uplink voice path */ -#define FEAT_ASRC3 FEAT_ASRC2+1 /* asynchronous sample-rate-converter for the multimedia player */ -#define FEAT_ASRC4 FEAT_ASRC3+1 /* asynchronous sample-rate-converter for the echo reference */ -#define FEAT_MIXDL1 FEAT_ASRC4+1 /* mixer of the headset and earphone path */ -#define FEAT_MIXDL2 FEAT_MIXDL1+1 /* mixer of the hands-free path */ -#define FEAT_MIXAUDUL FEAT_MIXDL2+1 /* mixer for audio being sent on the voice_ul path */ -#define FEAT_MIXVXREC FEAT_MIXAUDUL+1 /* mixer for voice communication recording */ -#define FEAT_MIXSDT FEAT_MIXVXREC+1 /* mixer for side-tone */ -#define FEAT_MIXECHO FEAT_MIXSDT+1 /* mixer for echo reference */ -#define FEAT_UPROUTE FEAT_MIXECHO+1 /* router of the uplink path */ -#define FEAT_GAINS FEAT_UPROUTE+1 /* all gains */ -#define FEAT_GAINS_DMIC1 FEAT_GAINS+1 -#define FEAT_GAINS_DMIC2 FEAT_GAINS_DMIC1+1 -#define FEAT_GAINS_DMIC3 FEAT_GAINS_DMIC2+1 -#define FEAT_GAINS_AMIC FEAT_GAINS_DMIC3+1 -#define FEAT_GAINS_SPLIT FEAT_GAINS_AMIC+1 -#define FEAT_GAINS_DL1 FEAT_GAINS_SPLIT+1 -#define FEAT_GAINS_DL2 FEAT_GAINS_DL1+1 -#define FEAT_GAIN_EANC FEAT_GAINS_DL2+1 /* active noise canceller */ -#define FEAT_SEQ FEAT_GAIN_EANC+1 /* sequencing queue of micro tasks */ -#define FEAT_CTL FEAT_SEQ+1 /* Phoenix control queue through McPDM */ - -#define MAXNBFEATURE FEAT_CTL /* list of features of the firmware */ - -typedef enum { - EQ1 = FEAT_EQ1, /* equalizer downlink path headset + earphone */ - EQ2L = FEAT_EQ2L, /* equalizer downlink path integrated handsfree LEFT */ - EQ2R = FEAT_EQ2R, - EQSDT = FEAT_EQSDT, /* equalizer downlink path side-tone */ - EQMIC = FEAT_EQMIC, -} abe_equ_id; - -typedef enum { - APS1 = FEAT_APS1, /* Acoustic protection for headset */ - APS2L = FEAT_APS2, - APS2R = FEAT_APS3 -} abe_aps_id; - -typedef enum { - ASRC1 = FEAT_ASRC1, /* asynchronous sample-rate-converter for the downlink voice path */ - ASRC2 = FEAT_ASRC2, /* asynchronous sample-rate-converter for the uplink voice path */ - ASRC3 = FEAT_ASRC3, /* asynchronous sample-rate-converter for the multimedia player */ - ASRC4 = FEAT_ASRC4, /* asynchronous sample-rate-converter for the voice uplink echo_reference */ -} abe_asrc_id; - -typedef enum { - MIXDL1 = FEAT_MIXDL1, - MIXDL2 = FEAT_MIXDL2, - MIXSDT = FEAT_MIXSDT, - MIXECHO = FEAT_MIXECHO, - MIXEANC = FEAT_GAIN_EANC, - MIXAUDUL = FEAT_MIXAUDUL, - MIXVXREC = FEAT_MIXVXREC, -} abe_mixer_id; - -typedef enum { - UPROUTE = FEAT_UPROUTE, /* there is only one router up to now */ -} abe_router_id; - -typedef enum { - GAINS = FEAT_GAINS, /* Misc tasks of the scheduler */ - SEQUENCE = FEAT_SEQ, - CONTROL = FEAT_CTL -} abe_schd_id; - -/* - * GAIN IDs - */ -typedef enum { - GAINS_DMIC1 = FEAT_GAINS_DMIC1, - GAINS_DMIC2 = FEAT_GAINS_DMIC2, - GAINS_DMIC3 = FEAT_GAINS_DMIC3, - GAINS_AMIC = FEAT_GAINS_AMIC, - GAINS_SPLIT = FEAT_GAINS_SPLIT, - GAINS_DL1 = FEAT_GAINS_DL1, - GAINS_DL2 = FEAT_GAINS_DL2, - GAINS_EANC = FEAT_GAIN_EANC, -} abe_gain_id; - -#if 0 -typedef enum { - VX_DL_IN_GAIN = 1, /* mixer's gain */ - MM_DL_IN_GAIN, - TONES_DL_IN_GAIN, - MM_VX_DL_IN_GAIN, - MM_IHF_DL_IN_GAIN, /* mixer's gain */ - MM_HS_DL_OUT_GAIN, /* Output Left gain */ - MM_IHF_L_DL_OUT_GAIN, /* Output Left gain */ - MM_IHF_R_DL_OUT_GAIN, /* Output Right gain */ - MM_VIB1_DL_GAIN, - MM_VIB2_DL_GAIN, /* no gain in fact */ - DMIC_UL_IN_GAIN_0, - DMIC_UL_IN_GAIN_1, /* today = same GAIN on DMIC pairs */ - DMIC_UL_IN_GAIN_2, - DMIC_UL_IN_GAIN_3, - DMIC_UL_IN_GAIN_4, - DMIC_UL_IN_GAIN_5, - AMIC_UL_IN_GAIN_L, - AMIC_UL_IN_GAIN_R, /* today = same gain on AMIC pair */ - ECHO_REF_GAIN, - BT_VX_DL_OUT_GAIN, - BT_VX_UL_IN_GAIN, -} abe_gain_id; -#endif - -/* - * EVENT GENERATORS - */ -typedef enum { - EVENT_MCPDM = 1, - EVENT_DMIC, EVENT_TIMER, - EVENT_McBSP, EVENT_McASP, EVENT_SLIMBUS, EVENT_44100, EVENT_DEFAULT, -} abe_event_id; - -/* - * SERIAL PORTS IDs - */ -typedef enum { - MCBSP1_TX = MCBSP1_DMA_TX, - MCBSP1_RX = MCBSP1_DMA_RX, - MCBSP2_TX = MCBSP2_DMA_TX, - MCBSP2_RX = MCBSP2_DMA_RX, - MCBSP3_TX = MCBSP3_DMA_TX, - MCBSP3_RX = MCBSP3_DMA_RX, -} abe_mcbsp_id; - -/* - * SERIAL PORTS IDs - */ -typedef enum { - SLIMBUS1_TX0 = SLIMBUS1_DMA_TX0, /* SLIMBUS mod 1 - tx rqst channel 0 */ - SLIMBUS1_TX1 = SLIMBUS1_DMA_TX1, /* SLIMBUS mod 1 - tx rqst channel 1 */ - SLIMBUS1_TX2 = SLIMBUS1_DMA_TX2, /* SLIMBUS mod 1 - tx rqst channel 2 */ - SLIMBUS1_TX3 = SLIMBUS1_DMA_TX3, /* SLIMBUS mod 1 - tx rqst channel 3 */ - SLIMBUS1_TX4 = SLIMBUS1_DMA_TX4, /* SLIMBUS mod 1 - tx rqst channel 4 */ - SLIMBUS1_TX5 = SLIMBUS1_DMA_TX5, /* SLIMBUS mod 1 - tx rqst channel 5 */ - SLIMBUS1_TX6 = SLIMBUS1_DMA_TX6, /* SLIMBUS mod 1 - tx rqst channel 6 */ - SLIMBUS1_TX7 = SLIMBUS1_DMA_TX7, /* SLIMBUS mod 1 - tx rqst channel 7 */ - SLIMBUS1_RX0 = SLIMBUS1_DMA_RX0, /* SLIMBUS mod 1 - rx rqst channel 0 */ - SLIMBUS1_RX1 = SLIMBUS1_DMA_RX1, /* SLIMBUS mod 1 - rx rqst channel 1 */ - SLIMBUS1_RX2 = SLIMBUS1_DMA_RX2, /* SLIMBUS mod 1 - rx rqst channel 2 */ - SLIMBUS1_RX3 = SLIMBUS1_DMA_RX3, /* SLIMBUS mod 1 - rx rqst channel 3 */ - SLIMBUS1_RX4 = SLIMBUS1_DMA_RX4, /* SLIMBUS mod 1 - rx rqst channel 4 */ - SLIMBUS1_RX5 = SLIMBUS1_DMA_RX5, /* SLIMBUS mod 1 - rx rqst channel 5 */ - SLIMBUS1_RX6 = SLIMBUS1_DMA_RX6, /* SLIMBUS mod 1 - rx rqst channel 6 */ - SLIMBUS1_RX7 = SLIMBUS1_DMA_RX7, /* SLIMBUS mod 1 - rx rqst channel 7 */ - SLIMBUS_UNUSED = _DUMMY_FIFO_, -} abe_slimbus_id; - -/* - * TYPES USED FOR APIS - */ - -/* - * HARDWARE CONFIG TYPE + +/* equalizer downlink path headset + earphone */ +#define FEAT_EQ1 1 + +/* equalizer downlink path integrated handsfree LEFT */ +#define FEAT_EQ2L FEAT_EQ1+1 + +/* equalizer downlink path integrated handsfree RIGHT */ +#define FEAT_EQ2R FEAT_EQ2L+1 + +/* equalizer downlink path side-tone */ +#define FEAT_EQSDT FEAT_EQ2R+1 + +/* equalizer uplink path MIC pair */ +#define FEAT_EQMIC FEAT_EQSDT+1 + +/* Acoustic protection for headset */ +#define FEAT_APS1 FEAT_EQMIC+1 + +/* acoustic protection high-pass filter for handsfree "Left" */ +#define FEAT_APS2 FEAT_APS1+1 + +/* acoustic protection high-pass filter for handsfree "Right" */ +#define FEAT_APS3 FEAT_APS2+1 + +/* asynchronous sample-rate-converter for the downlink voice path */ +#define FEAT_ASRC1 FEAT_APS3+1 + +/* asynchronous sample-rate-converter for the uplink voice path */ +#define FEAT_ASRC2 FEAT_ASRC1+1 + +/* asynchronous sample-rate-converter for the multimedia player */ +#define FEAT_ASRC3 FEAT_ASRC2+1 + +/* asynchronous sample-rate-converter for the echo reference */ +#define FEAT_ASRC4 FEAT_ASRC3+1 + +/* mixer of the headset and earphone path */ +#define FEAT_MIXDL1 FEAT_ASRC4+1 + +/* mixer of the hands-free path */ +#define FEAT_MIXDL2 FEAT_MIXDL1+1 + +/* mixer for audio being sent on the voice_ul path */ +#define FEAT_MIXAUDUL FEAT_MIXDL2+1 + +/* mixer for voice communication recording */ +#define FEAT_MIXVXREC FEAT_MIXAUDUL+1 + +/* mixer for side-tone */ +#define FEAT_MIXSDT FEAT_MIXVXREC+1 + +/* mixer for echo reference */ +#define FEAT_MIXECHO FEAT_MIXSDT+1 + +/* router of the uplink path */ +#define FEAT_UPROUTE FEAT_MIXECHO+1 + +/* all gains */ +#define FEAT_GAINS FEAT_UPROUTE+1 +#define FEAT_GAINS_DMIC1 FEAT_GAINS+1 +#define FEAT_GAINS_DMIC2 FEAT_GAINS_DMIC1+1 +#define FEAT_GAINS_DMIC3 FEAT_GAINS_DMIC2+1 +#define FEAT_GAINS_AMIC FEAT_GAINS_DMIC3+1 +#define FEAT_GAINS_SPLIT FEAT_GAINS_AMIC+1 +#define FEAT_GAINS_DL1 FEAT_GAINS_SPLIT+1 +#define FEAT_GAINS_DL2 FEAT_GAINS_DL1+1 +#define FEAT_GAIN_EANC FEAT_GAINS_DL2+1 + +/* sequencing queue of micro tasks */ +#define FEAT_SEQ FEAT_GAIN_EANC+1 + +/* Phoenix control queue through McPDM */ +#define FEAT_CTL FEAT_SEQ+1 + +/* list of features of the firmware -------------------------------*/ +#define MAXNBFEATURE FEAT_CTL + +/* abe_equ_id */ +/* equalizer downlink path headset + earphone */ +#define EQ1 FEAT_EQ1 + +/* equalizer downlink path integrated handsfree LEFT */ +#define EQ2L FEAT_EQ2L +#define EQ2R FEAT_EQ2R + +/* equalizer downlink path side-tone */ +#define EQSDT FEAT_EQSDT +#define EQMIC FEAT_EQMIC + + +/* abe_aps_id */ +/* Acoustic protection for headset */ +#define APS1 FEAT_APS1 +#define APS2L FEAT_APS2 +#define APS2R FEAT_APS3 + +/* abe_asrc_id */ +/* asynchronous sample-rate-converter for the downlink voice path */ +#define ASRC1 FEAT_ASRC1 + +/* asynchronous sample-rate-converter for the uplink voice path */ +#define ASRC2 FEAT_ASRC2 + +/* asynchronous sample-rate-converter for the multimedia player */ +#define ASRC3 FEAT_ASRC3 + +/* asynchronous sample-rate-converter for the voice uplink echo_reference */ +#define ASRC4 FEAT_ASRC4 + + +/* abe_mixer_id */ +#define MIXDL1 FEAT_MIXDL1 +#define MIXDL2 FEAT_MIXDL2 +#define MIXSDT FEAT_MIXSDT +#define MIXECHO FEAT_MIXECHO +#define MIXEANC FEAT_GAIN_EANC +#define MIXAUDUL FEAT_MIXAUDUL +#define MIXVXREC FEAT_MIXVXREC + +/* abe_router_id */ +/* there is only one router up to now */ +#define UPROUTE FEAT_UPROUTE + + +/* + * GAIN IDs */ -typedef struct { - abe_uint32 AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE; /* EVENT_GENERATOR_COUNTER_DEFAULT gives about 96kHz */ - abe_uint32 AESS_EVENT_SOURCE_SELECTION__SELECTION; /* 0: DMAreq, 1:Counter */ - abe_uint32 AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION; /* 5bits DMAreq selection */ - abe_event_id HAL_EVENT_SELECTION; - - abe_uint32 MCPDM_CTRL__DIV_SEL; /* 0: 96kHz 1:192kHz */ - abe_uint32 MCPDM_CTRL__CMD_INT; /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */ - abe_uint32 MCPDM_CTRL__PDMOUTFORMAT; /* 0:MSB aligned 1:LSB aligned */ - abe_uint32 MCPDM_CTRL__PDM_DN5_EN; - abe_uint32 MCPDM_CTRL__PDM_DN4_EN; - abe_uint32 MCPDM_CTRL__PDM_DN3_EN; - abe_uint32 MCPDM_CTRL__PDM_DN2_EN; - abe_uint32 MCPDM_CTRL__PDM_DN1_EN; - abe_uint32 MCPDM_CTRL__PDM_UP3_EN; - abe_uint32 MCPDM_CTRL__PDM_UP2_EN; - abe_uint32 MCPDM_CTRL__PDM_UP1_EN; - abe_uint32 MCPDM_FIFO_CTRL_DN__DN_TRESH; - abe_uint32 MCPDM_FIFO_CTRL_UP__UP_TRESH; - - abe_uint32 DMIC_CTRL__DMIC_CLK_DIV; /* 0:2.4MHz 1:3.84MHz */ - abe_uint32 DMIC_CTRL__DMICOUTFORMAT; /* 0:MSB aligned 1:LSB aligned */ - abe_uint32 DMIC_CTRL__DMIC_UP3_EN; - abe_uint32 DMIC_CTRL__DMIC_UP2_EN; - abe_uint32 DMIC_CTRL__DMIC_UP1_EN; - abe_uint32 DMIC_FIFO_CTRL__DMIC_TRESH; /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ - - abe_uint32 MCBSP_SPCR1_REG__RJUST; /* 1:MSB 2:LSB aligned */ - abe_uint32 MCBSP_THRSH2_REG_REG__XTHRESHOLD; /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, */ - abe_uint32 MCBSP_THRSH1_REG_REG__RTHRESHOLD; /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, */ - abe_uint32 SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD; -} abe_hw_config_init_t; - -/* - * EANC_T - * - * TBD : coefficients of the EANC +#define GAINS_DMIC1 FEAT_GAINS_DMIC1 +#define GAINS_DMIC2 FEAT_GAINS_DMIC2 +#define GAINS_DMIC3 FEAT_GAINS_DMIC3 +#define GAINS_AMIC FEAT_GAINS_AMIC +#define GAINS_SPLIT FEAT_GAINS_SPLIT +#define GAINS_DL1 FEAT_GAINS_DL1 +#define GAINS_DL2 FEAT_GAINS_DL2 +#define GAINS_EANC FEAT_GAIN_EANC + + +/* + * EVENT GENERATORS - abe_event_id */ -typedef struct { - abe_int32 dmic_index; - abe_int32 fir_coef[NBEANC1]; - abe_int32 lambda; - abe_int32 iir_filter[NBEANC2]; - abe_int32 loop_gain; -} abe_eanc_t; +#define EVENT_TIMER 0 +#define EVENT_44100 1 + + +/* + * SERIAL PORTS IDs - abe_mcbsp_id + */ + +#define MCBSP1_TX MCBSP1_DMA_TX +#define MCBSP1_RX MCBSP1_DMA_RX +#define MCBSP2_TX MCBSP2_DMA_TX +#define MCBSP2_RX MCBSP2_DMA_RX +#define MCBSP3_TX MCBSP3_DMA_TX +#define MCBSP3_RX MCBSP3_DMA_RX + + +/* + * SERIAL PORTS IDs - abe_slimbus_id; + */ +#define SLIMBUS1_TX0 SLIMBUS1_DMA_TX0 +#define SLIMBUS1_TX1 SLIMBUS1_DMA_TX1 +#define SLIMBUS1_TX2 SLIMBUS1_DMA_TX2 +#define SLIMBUS1_TX3 SLIMBUS1_DMA_TX3 +#define SLIMBUS1_TX4 SLIMBUS1_DMA_TX4 +#define SLIMBUS1_TX5 SLIMBUS1_DMA_TX5 +#define SLIMBUS1_TX6 SLIMBUS1_DMA_TX6 +#define SLIMBUS1_TX7 SLIMBUS1_DMA_TX7 +#define SLIMBUS1_RX0 SLIMBUS1_DMA_RX0 +#define SLIMBUS1_RX1 SLIMBUS1_DMA_RX1 +#define SLIMBUS1_RX2 SLIMBUS1_DMA_RX2 +#define SLIMBUS1_RX3 SLIMBUS1_DMA_RX3 +#define SLIMBUS1_RX4 SLIMBUS1_DMA_RX4 +#define SLIMBUS1_RX5 SLIMBUS1_DMA_RX5 +#define SLIMBUS1_RX6 SLIMBUS1_DMA_RX6 +#define SLIMBUS1_RX7 SLIMBUS1_DMA_RX7 +#define SLIMBUS_UNUSED _DUMMY_FIFO_ + + +/* + * --------------------------------- TYPES USED FOR APIS --------------- + */ +/* + * HARDWARE CONFIG TYPE + */ +typedef struct { + /* EVENT_GENERATOR_COUNTER_DEFAULT gives about 96kHz */ + u32 AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE; + + /* 0: DMAreq, 1:Counter */ + u32 AESS_EVENT_SOURCE_SELECTION__SELECTION; + + /* 5bits DMAreq selection */ + u32 AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION; + u32 HAL_EVENT_SELECTION; + + /* 0: 96kHz 1:192kHz */ + u32 MCPDM_CTRL__DIV_SEL; + + /* 0: no command in the FIFO, 1: 6 data on each lines (with commands)*/ + u32 MCPDM_CTRL__CMD_INT; + + /* 0:MSB aligned 1:LSB aligned */ + u32 MCPDM_CTRL__PDMOUTFORMAT; + u32 MCPDM_CTRL__PDM_DN5_EN; + u32 MCPDM_CTRL__PDM_DN4_EN; + u32 MCPDM_CTRL__PDM_DN3_EN; + u32 MCPDM_CTRL__PDM_DN2_EN; + u32 MCPDM_CTRL__PDM_DN1_EN; + u32 MCPDM_CTRL__PDM_UP3_EN; + u32 MCPDM_CTRL__PDM_UP2_EN; + u32 MCPDM_CTRL__PDM_UP1_EN; + u32 MCPDM_FIFO_CTRL_DN__DN_TRESH; + u32 MCPDM_FIFO_CTRL_UP__UP_TRESH; + + /* 0:2.4MHz 1:3.84MHz */ + u32 DMIC_CTRL__DMIC_CLK_DIV; + + /* 0:MSB aligned 1:LSB aligned */ + u32 DMIC_CTRL__DMICOUTFORMAT; + u32 DMIC_CTRL__DMIC_UP3_EN; + u32 DMIC_CTRL__DMIC_UP2_EN; + u32 DMIC_CTRL__DMIC_UP1_EN; + + /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */ + u32 DMIC_FIFO_CTRL__DMIC_TRESH; + + /* 1:MSB 2:LSB aligned */ + u32 MCBSP_SPCR1_REG__RJUST; + + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + u32 MCBSP_THRSH2_REG_REG__XTHRESHOLD; + + /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */ + u32 MCBSP_THRSH1_REG_REG__RTHRESHOLD; + + u32 SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD; + +} abe_hw_config_init_t; + /* - * EQU_T + * EQU_T * - * coefficients of the equalizer + * coefficients of the equalizer */ -typedef struct { - abe_iir_t equ_type; /* type of filter */ - abe_uint32 equ_length; /* filter length */ - union { /* parameters are the direct and recursive coefficients in */ - abe_int32 type1[NBEQ1]; /* Q6.26 integer fixed-point format. */ +typedef struct { + /* type of filter */ + u32 equ_type; + + /* filter length */ + u32 equ_length; + union { + /* parameters are the direct and recursive coefficients in */ + + /* Q6.26 integer fixed-point format. */ + s32 type1 [NBEQ1]; struct { - abe_int32 freq [NBEQ2]; /* center frequency of the band [Hz] */ - abe_int32 gain [NBEQ2]; /* gain of each band. [dB]*/ - abe_int32 q [NBEQ2]; /* Q factor of this band [dB] */ + /* center frequency of the band [Hz] */ + s32 freq [NBEQ2]; + + /* gain of each band. [dB]*/ + s32 gain [NBEQ2]; + + /* Q factor of this band [dB] */ + s32 q [NBEQ2]; } type2; } coef; - abe_int32 equ_param3; -} abe_equ_t; + s32 equ_param3; +} abe_equ_t ; /* - * APS_T + * APS_T * - * coefficients of the Acoustics Protection and Safety + * coefficients of the Acoustics Protection and Safety */ -typedef struct { - abe_int32 coef1[NBAPS1]; - abe_int32 coef2[NBAPS2]; +typedef struct { + s32 coef1 [NBAPS1]; + s32 coef2 [NBAPS2]; } abe_aps_t; -typedef struct { - abe_millibel e1; /* structure of two energy_t estimation for coil and membrane */ - abe_millibel e2; +typedef struct { + /* structure of two energy_t estimation for coil and membrane */ + u32 e1; + u32 e2; } abe_aps_energy_t; + + /* - * ROUTER_T + * ROUTER_T * - * table of indexes in unsigned bytes + * table of indexes in unsigned bytes */ -typedef abe_uint16 abe_router_t; +typedef u16 abe_router_t; + /* - * DATA_FORMAT_T + * DATA_FORMAT_T * - * used in port declaration + * used in port declaration */ typedef struct { - abe_freq_t f; /* Sampling frequency of the stream */ - abe_samp_t samp_format; /* Sample format type */ + /* Sampling frequency of the stream */ + u32 f; + + /* Sample format type */ + u32 samp_format; } abe_data_format_t; /* - * PORT_PROTOCOL_T + * PORT_PROTOCOL_T * - * port declaration + * port declaration */ -typedef struct { - abe_uint32 direction; /* Direction=0 means input from AESS point of view */ - abe_port_protocol_switch_id protocol_switch; /* Protocol type (switch) during the data transfers */ +typedef struct { + + /* Direction=0 means input from AESS point of view */ + u32 direction; + + /* Protocol type (switch) during the data transfers */ + u32 protocol_switch; union { - struct { /* Slimbus peripheral connected to ATC */ - abe_uint32 desc_addr1; /* Address of ATC Slimbus descriptor's index */ - abe_uint32 desc_addr2; /* Second ATC index for SlimBus reception (or NULL) */ - abe_uint32 buf_addr1; /* DMEM address 1 in bytes */ - abe_uint32 buf_addr2; /* DMEM address 2 in bytes */ - abe_uint32 buf_size; /* DMEM buffer size size in bytes */ - abe_uint32 iter; /* ITERation on each DMAreq signals */ + /* Slimbus peripheral connected to ATC */ + struct { + /* Address of ATC Slimbus descriptor's index */ + u32 desc_addr1; + + /* Second ATC index for SlimBus reception (or NULL) */ + u32 desc_addr2; + + /* DMEM address 1 in bytes */ + u32 buf_addr1; + + /* DMEM address 2 in bytes */ + u32 buf_addr2; + + /* DMEM buffer size size in bytes */ + u32 buf_size; + + /* ITERation on each DMAreq signals */ + u32 iter; } prot_slimbus; + /* McBSP/McASP peripheral connected to ATC */ struct { - abe_uint32 desc_addr; /* McBSP/McASP peripheral connected to ATC */ - abe_uint32 buf_addr; /* Address of ATC McBSP/McASP descriptor's in bytes */ - abe_uint32 buf_size; /* DMEM address in bytes */ - abe_uint32 iter; /* ITERation on each DMAreq signals */ + + u32 desc_addr; + + /* Address of ATC McBSP/McASP descriptor's in bytes */ + u32 buf_addr; + + /* DMEM address in bytes */ + u32 buf_size; + + /* ITERation on each DMAreq signals */ + u32 iter; } prot_serial; - struct { /* DMIC peripheral connected to ATC */ - abe_uint32 buf_addr; /* DMEM address in bytes */ - abe_uint32 buf_size; /* DMEM buffer size in bytes */ - abe_uint32 nbchan; /* Number of activated DMIC */ + /* DMIC peripheral connected to ATC */ + struct { + /* DMEM address in bytes */ + u32 buf_addr; + + /* DMEM buffer size in bytes */ + u32 buf_size; + + /* Number of activated DMIC */ + u32 nbchan; } prot_dmic; - struct { /* McPDMDL peripheral connected to ATC */ - abe_uint32 buf_addr; /* DMEM address in bytes */ - abe_uint32 buf_size; /* DMEM size in bytes */ - abe_uint32 control; /* Control allowed on McPDM DL */ + /* McPDMDL peripheral connected to ATC */ + struct { + /* DMEM address in bytes */ + u32 buf_addr; + + /* DMEM size in bytes */ + u32 buf_size; + + /* Control allowed on McPDM DL */ + u32 control; } prot_mcpdmdl; - struct { /* McPDMUL peripheral connected to ATC */ - abe_uint32 buf_addr; /* DMEM address size in bytes */ - abe_uint32 buf_size; /* DMEM buffer size size in bytes */ + /* McPDMUL peripheral connected to ATC */ + struct { + /* DMEM address size in bytes */ + u32 buf_addr; + + /* DMEM buffer size size in bytes */ + u32 buf_size; } prot_mcpdmul; - struct { /* Ping-Pong interface to the Host using cache-flush */ - abe_uint32 desc_addr; /* Address of ATC descriptor's */ - abe_uint32 buf_addr; /* DMEM buffer base address in bytes */ - abe_uint32 buf_size; /* DMEM size in bytes for each ping and pong buffers */ - abe_uint32 irq_addr; /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */ - abe_uint32 irq_data; /* IRQ data content loaded in the AESS IRQ register */ - abe_uint32 callback; /* Call-back function upon IRQ reception */ + /* Ping-Pong interface to the Host using cache-flush */ + struct { + /* Address of ATC descriptor's */ + u32 desc_addr; + + /* DMEM buffer base address in bytes */ + u32 buf_addr; + + /* DMEM size in bytes for each ping and pong buffers */ + u32 buf_size; + + /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */ + u32 irq_addr; + + /* IRQ data content loaded in the AESS IRQ register */ + u32 irq_data; + + /* Call-back function upon IRQ reception */ + u32 callback; } prot_pingpong; - struct { /* DMAreq line to CBPr */ - abe_uint32 desc_addr; /* Address of ATC descriptor's */ - abe_uint32 buf_addr; /* DMEM buffer address in bytes */ - abe_uint32 buf_size; /* DMEM buffer size size in bytes */ - abe_uint32 iter; /* ITERation on each DMAreq signals */ - abe_uint32 dma_addr; /* DMAreq address */ - abe_uint32 dma_data; /* DMA/AESS = 1 << #DMA */ + /* DMAreq line to CBPr */ + struct { + /* Address of ATC descriptor's */ + u32 desc_addr; + + /* DMEM buffer address in bytes */ + u32 buf_addr; + + /* DMEM buffer size size in bytes */ + u32 buf_size; + + /* ITERation on each DMAreq signals */ + u32 iter; + + /* DMAreq address */ + u32 dma_addr; + + /* DMA/AESS = 1 << #DMA */ + u32 dma_data; } prot_dmareq; - struct { /* Circular buffer - direct addressing to DMEM */ - abe_uint32 buf_addr; /* DMEM buffer base address in bytes */ - abe_uint32 buf_size; /* DMEM buffer size in bytes */ - abe_uint32 dma_addr; /* DMAreq address */ - abe_uint32 dma_data; /* DMA/AESS = 1 << #DMA */ + /* Circular buffer - direct addressing to DMEM */ + struct { + /* DMEM buffer base address in bytes */ + u32 buf_addr; + + /* DMEM buffer size in bytes */ + u32 buf_size; + + /* DMAreq address */ + u32 dma_addr; + + /* DMA/AESS = 1 << #DMA */ + u32 dma_data; } prot_circular_buffer; - }p; + } p; } abe_port_protocol_t; + + /* - * DMA_T + * DMA_T * - * dma structure for easing programming + * dma structure for easing programming */ -typedef struct { - void *data; /* OCP L3 pointer to the first address of the */ - /* destination buffer (either DMA or Ping-Pong read/write pointers). */ - void *l3_dmem; /* address L3 when addressing the DMEM buffer instead of CBPr */ - void *l4_dmem; /* address L3 translated to L4 the ARM memory space */ - abe_uint32 iter; /* number of iterations for the DMA data moves. */ +typedef struct { + /* OCP L3 pointer to the first address of the */ + void *data; + /* destination buffer (either DMA or Ping-Pong read/write pointers). */ + /* address L3 when addressing the DMEM buffer instead of CBPr */ + void *l3_dmem; + + /* address L3 translated to L4 the ARM memory space */ + void *l4_dmem; + + /* number of iterations for the DMA data moves. */ + u32 iter; } abe_dma_t; -typedef struct { - abe_uint32 data; /* Offset to the first address of the */ - abe_uint32 iter; /* number of iterations for the DMA data moves. */ -} abe_dma_t_offset; +typedef struct { + /* Offset to the first address of the */ + u32 data; + /* number of iterations for the DMA data moves. */ + u32 iter; +} abe_dma_t_offset; /* * SEQ_T * - * struct { - * micros_t time; Waiting time before executing next line - * seq_code_t code Subroutine index interpreted in the HAL and translated to - * FW subroutine codes in case of ABE tasks - * int32 param[2] Two parameters - *} seq_t + * struct { + * micros_t time; Waiting time before executing next line + * seq_code_t code Subroutine index interpreted in the HAL and + * translated to + * FW subroutine codes in case of ABE tasks + * int32 param[2] Two parameters + * } seq_t * */ -typedef struct { - abe_micros_t delta_time; - abe_sub_code_t code; - abe_uint32 param[4]; - abe_uint8 tag; +typedef struct { + u32 delta_time; + u32 code; + u32 param[4]; + u8 tag; } abe_seq_t; -typedef struct { - abe_uint32 mask; +typedef struct { + u32 mask; abe_seq_t seq1; abe_seq_t seq2; } abe_sequence_t; + /* - * DRIFT_T + * DRIFT_T abe_drift_t = s32 * - * ASRC drift parameter in [ppm] value + * ASRC drift parameter in [ppm] value */ -typedef abe_int32 abe_drift_t; /* - * INTERNAL DATA TYPES + * --------------------------------- INTERNAL DATA TYPES --------------------- */ + /* - * ABE_IRQ_DATA_T + * ABE_IRQ_DATA_T * - * IRQ FIFO content declaration - * APS interrupts: - * IRQtag_APS to [31:28], APS_IRQs to [27:16], loopCounter to [15:0] - * SEQ interrupts: - * IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0] - * Ping-Pong Interrupts: - * IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0] - */ -typedef struct { - unsigned int counter: 16; - unsigned int data: 12; - unsigned int tag: 4; + * IRQ FIFO content declaration + * APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], + * loopCounter to [15:0] + * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], + * loopCounter to [15:0] + * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], + * loopCounter to [15:0] + */ +typedef struct { + unsigned int counter:16; + unsigned int data:12; + unsigned int tag:4; } abe_irq_data_t; + /* - * ABE_PORT_T status / format / sampling / protocol(call_back) / features / gain / name .. + * ABE_PORT_T status / format / sampling / protocol(call_back) / features / + * gain / name .. * */ -typedef struct { - abe_uint16 status; /* running / idled */ - abe_data_format_t format; /* Sample format type */ - abe_drift_t drift; /* API : for ASRC */ - abe_uint16 callback; /* optionnal call-back index for errors and ack */ - abe_uint16 smem_buffer1; /* IO tasks buffers */ - abe_uint16 smem_buffer2; + +typedef struct { + /* running / idled */ + u16 status; + + /* Sample format type */ + abe_data_format_t format; + + /* API : for ASRC */ + s32 drift; + + /* optionnal call-back index for errors and ack */ + u16 callback; + + /* IO tasks buffers */ + u16 smem_buffer1; + u16 smem_buffer2; abe_port_protocol_t protocol; - abe_dma_t_offset dma; /* pointer and iteration counter of the xDMA */ - abe_uint16 feature_index [MAXFEATUREPORT]; /* list of features associated to a port (EQ, APS, ... , ends with 0) */ - // abe_millibel gain_calibration; /* gain tuning, default=0dB */ + + /* pointer and iteration counter of the xDMA */ + abe_dma_t_offset dma; + + /* list of features associated to a port (EQ, APS, ... , ends with 0) */ + u16 feature_index [MAXFEATUREPORT]; char name[NBCHARPORTNAME]; } abe_port_t; + + + /* - * ABE_SUBROUTINE_T + * ABE_SUBROUTINE_T * */ -typedef struct { - abe_uint32 sub_id; - abe_int32 param[4]; -} abe_subroutine_t; + +typedef struct { + u32 sub_id; + s32 param[4]; +} abe_subroutine_t ; /* - * ABE_PORT_INFO_T + * ABE_PORT_INFO_T OPP, subroutines to call on reset * - * OPP, subroutines to call on reset */ -typedef struct { - abe_opp_t min_opp; + +typedef struct { + u32 min_opp; abe_subroutine_t sub1; abe_subroutine_t sub2; } abe_port_info_t; /* - * ABE_FEATURE_T + * ABE_FEATURE_T * */ -typedef struct { - abe_uint16 enable_with_default_data; - abe_uint16 disable_feature; - abe_uint16 read_parameter; - abe_uint16 write_parameter; - abe_uint16 running_status; - abe_uint16 fw_input_buffer_address; - abe_uint16 fw_output_buffer_address; - abe_uint16 fw_scheduler_slot_position; - abe_uint16 fw_scheduler_subslot_position; - abe_opp_t min_opp; + +typedef struct { + u16 enable_with_default_data; + u16 disable_feature; + u16 read_parameter; + u16 write_parameter; + u16 running_status; + u16 fw_input_buffer_address; + u16 fw_output_buffer_address; + u16 fw_scheduler_slot_position; + u16 fw_scheduler_subslot_position; + u32 min_opp; char name[NBCHARFEATURENAME]; } abe_feature_t; -#ifdef __cplusplus -} -#endif -#endif /* _ABE_TYP_H_ */ + + +#endif /* ifndef ABETYP */ diff --git a/sound/soc/omap/abe/abe_typedef.h b/sound/soc/omap/abe/abe_typedef.h index ec0a4413b6a4..347145b84b39 100644 --- a/sound/soc/omap/abe/abe_typedef.h +++ b/sound/soc/omap/abe/abe_typedef.h @@ -1,25 +1,32 @@ /* - * ========================================================================== - * Texas Instruments OMAP(TM) Platform Firmware - * (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved. + * ALSA SoC OMAP ABE driver * - * Use of this firmware is controlled by the terms and conditions found - * in the license agreement under which this firmware has been supplied. - * ========================================================================== + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * Liam Girdwood <lrg@slimlogic.co.uk> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA */ #ifndef _ABE_TYPEDEF_H_ #define _ABE_TYPEDEF_H_ -#ifdef __cplusplus -extern "C" { -#endif #include "abe_define.h" - /* * Basic types definition -*/ + */ typedef unsigned char ABE_uchar; typedef char ABE_char; typedef unsigned short ABE_uint16; @@ -34,153 +41,324 @@ typedef ABE_int16* pABE_int16; typedef ABE_int32* pABE_int32; typedef ABE_uint32* pABE_uint32; -/* - * Hard-coded data generated in the XLS sheet (to be removed later@@@@) - */ + #ifdef __chess__ typedef struct abeatcdescTag { unsigned long a; unsigned long b; } ABE_SAtcDescriptor; -typedef void (*pABE_voidFunction)()clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13); -typedef void (*pABE_voidFunctionsList[])()clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13); -typedef void (*pABE_cmdFunction)() clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13); -typedef void (*pABE_cmdFunctionsList[])() clobbers(R0, R1, R2, R3, R4, R5, R6, R7, R13); -typedef void (*pABE_copyFunction)(ABE_uint16 chess_storage(R13))clobbers(R13); -typedef void (*pABE_copyFunctionsList[])(ABE_uint16 chess_storage(R13))clobbers(R13); +typedef void (*pABE_voidFunction)()clobbers(R0, R1, R2, R3, R4, + R5, R6, R7, R13); +typedef void (*pABE_voidFunctionsList[])()clobbers(R0, R1, R2, R3, R4, + R5, R6, R7, R13); +typedef void (*pABE_cmdFunction)() clobbers(R0, R1, R2, R3, R4, + R5, R6, R7, R13); +typedef void (*pABE_cmdFunctionsList[])() clobbers(R0, R1, R2, R3, R4, + R5, R6, R7, R13); +typedef void (*pABE_copyFunction)(ABE_uint16 chess_storage(R13)) + clobbers(R13); +typedef void (*pABE_copyFunctionsList[])(ABE_uint16 chess_storage(R13)) + clobbers(R13); #endif /* * Commonly used structures */ - -typedef struct abetaskTag{ - ABE_uint16 iF; /* 0 Index of called function */ - ABE_uint16 A0; /* 2 for INITPTR of A0 */ - ABE_uint16 A1; /* 4 for INITPTR of A1 */ - ABE_uint16 A2_3; /* 6 for INITPTR of A2 & A3 */ - ABE_uint16 A4_5; /* 8 for INITPTR of A4 & A5 */ - ABE_uint16 R; /* 10 for INITREG of R0, R1, R2, R3 */ - ABE_uint16 misc0; /* 12 */ - ABE_uint16 misc1; /* 14 */ +typedef struct abetaskTag { + /* 0 ... Index of called function */ + ABE_uint16 iF; + + /* 2 ... for INITPTR of A0 */ + ABE_uint16 A0; + + /* 4 ... for INITPTR of A1 */ + ABE_uint16 A1; + + /* 6 ... for INITPTR of A2 & A3 */ + ABE_uint16 A2_3; + + /* 8 ... for INITPTR of A4 & A5 */ + ABE_uint16 A4_5; + + /* 10 ... for INITREG of R0, R1, R2, R3 */ + ABE_uint16 R; + + /* 12 */ + ABE_uint16 misc0; + + /* 14 */ + ABE_uint16 misc1; } ABE_STask; typedef ABE_STask* pABE_STask; typedef ABE_STask** ppABE_STask; typedef struct { - ABE_uint16 drift_ASRC; /* 0 */ - ABE_uint16 drift_io; /* 2 */ - ABE_uchar io_type_idx; /* 4 */ - ABE_uchar samp_size; /* 5 */ - ABE_uint16 flow_counter; /* 6 */ - - ABE_uint16 hw_ctrl_addr; /* 8 */ - ABE_uchar atc_irq_data; /* 10 */ - ABE_uchar direction_rw; /* 11 */ - ABE_uchar unused1; /* 12 */ - ABE_uchar nsamp; /* 13 */ - ABE_uchar x_io; /* 14 */ - ABE_uchar on_off; /* 15 */ - - ABE_uint16 split_addr1; /* 16 */ - ABE_uint16 split_addr2; /* 18 */ - ABE_uint16 split_addr3; /* 20 */ - ABE_uchar before_f_index; /* 22 */ - ABE_uchar after_f_index; /* 23 */ - - ABE_uint16 smem_addr1; /* 24 */ - ABE_uint16 atc_address1; /* 26 */ - ABE_uint16 atc_pointer_saved1; /* 28 */ - ABE_uchar data_size1; /* 30 */ - ABE_uchar copy_f_index1; /* 31 */ - - ABE_uint16 smem_addr2; /* 32 */ - ABE_uint16 atc_address2; /* 34 */ - ABE_uint16 atc_pointer_saved2; /* 36 */ - ABE_uchar data_size2; /* 38 */ - ABE_uchar copy_f_index2; /* 39 */ - -} ABE_SIODescriptor; - - -#define drift_asrc_ 0 /* [w] asrc output used for the next asrc call (+/- 1 / 0) */ -#define drift_io_ 2 /* [w] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */ -#define io_type_idx_ 4 /* address of the IO subroutine */ -#define samp_size_ 5 -#define unused1 6 -#define unused2 7 -#define hw_ctrl_addr_ 8 /* dmareq address or host irq buffer address (atc address) */ -#define atc_irq_data_ 10 /* data content to be loaded to "hw_ctrl_addr" */ -#define direction_rw_ 11 /* read dmem =0, write dmem =3 (atc offset of the access pointer) */ -#define flow_counter_ 6 /* flow error counter */ -#define nsamp_ 13 /* number of samples (either mono stereo...) */ -#define x_io_ 14 /* x number of raw DMEM data moved */ -#define on_off_ 15 - -#define split_addr1_ 16 /* internal smem buffer initptr pointer index */ -#define split_addr2_ 18 /* internal smem buffer initptr pointer index */ -#define split_addr3_ 20 /* internal smem buffer initptr pointer index */ -#define before_f_index_ 22 /* index of the copy subroutine */ -#define after_f_index_ 23 /* index of the copy subroutine */ - -#define minidesc1_ 24 -#define rel_smem_ 0 /* internal smem buffer initptr pointer index */ -#define rel_atc_ 2 /* atc descriptor address (byte address x4) */ -#define rel_atc_saved 4 /* location of the saved ATC pointer (+debug info) */ -#define rel_size_ 6 /* size of each sample (1:mono/1616 2:stereo ) */ -#define rel_f_ 7 /* index of the copy subroutine */ - -#define s_mem_mm_ul 24 -#define s_mm_ul_size 30 - -#define minidesc2_ 32 -#define Struct_Size 40 - -typedef ABE_SIODescriptor* pABE_SIODescriptor; -typedef ABE_SIODescriptor** ppABE_SIODescriptor; - -typedef struct abepingpongdescriptorTag{ - ABE_uint16 drift_ASRC; /* 0 [W] asrc output used for the next ASRC call (+/- 1 / 0)*/ - ABE_uint16 drift_io; /* 2 [W] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */ - ABE_uint16 hw_ctrl_addr; /* 4 DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */ - ABE_uchar copy_func_index; /* 6 index of the copy subroutine */ - ABE_uchar x_io; /* 7 X number of SMEM samples to move */ - ABE_uchar data_size; /* 8 0 for mono data, 1 for stereo data */ - ABE_uchar smem_addr; /* 9 internal SMEM buffer INITPTR pointer index */ - ABE_uchar atc_irq_data; /* 10 data content to be loaded to "hw_ctrl_addr" */ - ABE_uchar counter; /* 11 ping/pong buffer flag */ - ABE_uint16 workbuff_BaseAddr; /* 12 current Base address of the working buffer */ - ABE_uint16 workbuff_Samples; /* 14 samples left in the working buffer */ - ABE_uint16 nextbuff0_BaseAddr; /* 6 Base address of the ping/pong buffer 0 */ - ABE_uint16 nextbuff0_Samples; /* 18 samples available in the ping/pong buffer 0 */ - ABE_uint16 nextbuff1_BaseAddr; /* 20 Base address of the ping/pong buffer 1 */ - ABE_uint16 nextbuff1_Samples; /* 22 samples available in the ping/pong buffer 1 */ + /* 0 */ + ABE_uint16 drift_ASRC; + + /* 2 */ + ABE_uint16 drift_io; + + /* 4 "Function index" of XLS sheet "Functions" */ + ABE_uchar io_type_idx; + + /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */ + ABE_uchar samp_size; + + /* 6 drift "issues" for ASRC */ + ABE_int16 flow_counter; + + /* 8 address for IRQ or DMArequests */ + ABE_uint16 hw_ctrl_addr; + + /* 10 DMA request bit-field or IRQ (DSP/MCU) */ + ABE_uchar atc_irq_data; + + /* 11 0 = Read, 3 = Write */ + ABE_uchar direction_rw; + + /* 12 */ + ABE_uchar unused1; + + /* 13 12 at 48kHz, ... */ + ABE_uchar nsamp; + + /* 14 nsamp x samp_size */ + ABE_uchar x_io; + + /* 15 ON = 0x80, OFF = 0x00 */ + ABE_uchar on_off; + + /* 16 For Slimbus and TDM purpose */ + ABE_uint16 split_addr1; + + /* 18 */ + ABE_uint16 split_addr2; + + /* 20 */ + ABE_uint16 split_addr3; + + /* 22 */ + ABE_uchar before_f_index; + + /* 23 */ + ABE_uchar after_f_index; + + /* 24 SM/CM INITPTR field */ + ABE_uint16 smem_addr1; + + /* 26 in bytes */ + ABE_uint16 atc_address1; + + /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */ + ABE_uint16 atc_pointer_saved1; + + /* 30 samp_size (except in TDM or Slimbus) */ + ABE_uchar data_size1; + + /* 31 "Function index" of XLS sheet "Functions" */ + ABE_uchar copy_f_index1; + + /* 32 For Slimbus and TDM purpose */ + ABE_uint16 smem_addr2; + + /* 34 */ + ABE_uint16 atc_address2; + + /* 36 */ + ABE_uint16 atc_pointer_saved2; + + /* 38 */ + ABE_uchar data_size2; + + /* 39 */ + ABE_uchar copy_f_index2; + +} ABE_SIODescriptor ; + +/* [w] asrc output used for the next asrc call (+/- 1 / 0) */ +#define drift_asrc_ 0 + + /* [w] asrc output used for controlling the number of samples to be + exchanged (+/- 1 / 0) */ +#define drift_io_ 2 + +/* address of the IO subroutine */ +#define io_type_idx_ 4 +#define samp_size_ 5 + +/* flow error counter */ +#define flow_counter_ 6 + +/* dmareq address or host irq buffer address (atc address) */ +#define hw_ctrl_addr_ 8 + +/* data content to be loaded to "hw_ctrl_addr" */ +#define atc_irq_data_ 10 + +/* read dmem =0, write dmem =3 (atc offset of the access pointer) */ +#define direction_rw_ 11 + +/* number of samples (either mono stereo...) */ +#define nsamp_ 13 + +/* x number of raw DMEM data moved */ +#define x_io_ 14 +#define on_off_ 15 + +/* internal smem buffer initptr pointer index */ +#define split_addr1_ 16 + +/* internal smem buffer initptr pointer index */ +#define split_addr2_ 18 + +/* internal smem buffer initptr pointer index */ +#define split_addr3_ 20 + +/* index of the copy subroutine */ +#define before_f_index_ 22 + +/* index of the copy subroutine */ +#define after_f_index_ 23 + +#define minidesc1_ 24 + +/* internal smem buffer initptr pointer index */ +#define rel_smem_ 0 + +/* atc descriptor address (byte address x4) */ +#define rel_atc_ 2 + +/* location of the saved ATC pointer (+debug info) */ +#define rel_atc_saved 4 + +/* size of each sample (1:mono/1616 2:stereo ... ) */ +#define rel_size_ 6 + +/* index of the copy subroutine */ +#define rel_f_ 7 + +#define s_mem_mm_ul 24 +#define s_mm_ul_size 30 + +#define minidesc2_ 32 +#define Struct_Size 40 + +typedef struct { + /* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0)*/ + ABE_uint16 drift_ASRC; + + /* 2: [W] asrc output used for controlling the number of + samples to be exchanged (+/- 1 / 0) */ + ABE_uint16 drift_io; + + /* 4: DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */ + ABE_uint16 hw_ctrl_addr; + + /* 6: index of the copy subroutine */ + ABE_uchar copy_func_index; + + /* 7: X number of SMEM samples to move */ + ABE_uchar x_io; + + /* 8: 0 for mono data, 1 for stereo data */ + ABE_uchar data_size; + + /* 9: internal SMEM buffer INITPTR pointer index */ + ABE_uchar smem_addr; + + /* 10: data content to be loaded to "hw_ctrl_addr" */ + ABE_uchar atc_irq_data; + + /* 11: ping/pong buffer flag */ + ABE_uchar counter; + + /* 12: current Base address of the working buffer */ + ABE_uint16 workbuff_BaseAddr; + + /* 14: samples left in the working buffer */ + ABE_uint16 workbuff_Samples; + + /* 16: Base address of the ping/pong buffer 0 */ + ABE_uint16 nextbuff0_BaseAddr; + + /* 18: samples available in the ping/pong buffer 0 */ + ABE_uint16 nextbuff0_Samples; + + /* 20: Base address of the ping/pong buffer 1 */ + ABE_uint16 nextbuff1_BaseAddr; + + /* 22: samples available in the ping/pong buffer 1 */ + ABE_uint16 nextbuff1_Samples; } ABE_SPingPongDescriptor; -typedef ABE_SPingPongDescriptor* pABE_SPingPongDescriptor; #ifdef __chess__ -#define drift_ASRC 0 /* [W] asrc output used for the next ASRC call (+/- 1 / 0)*/ -#define drift_io 2 /* [W] asrc output used for controlling the number of samples to be exchanged (+/- 1 / 0) */ -#define hw_ctrl_addr 4 /* DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */ -#define copy_func_index 6 /* index of the copy subroutine */ -#define x_io 7 /* X number of SMEM samples to move */ -#define data_size 8 /* 0 for mono data, 1 for stereo data */ -#define smem_addr 9 /* internal SMEM buffer INITPTR pointer index */ -#define atc_irq_data 10 /* data content to be loaded to "hw_ctrl_addr" */ -#define atc_address 11 /* ATC descriptor address */ -#define threshold_1 12 /* THR1; For stereo data, THR1 is provided by HAL as THR1<<1 */ -#define threshold_2 13 /* THR2; For stereo data, THR2 is provided by HAL as THR2<<1 */ -#define update_1 14 /* UP_1; For stereo data, UP_1 is provided by HAL as UP_1<<1 */ -#define update_2 15 /* UP_2; For stereo data, UP_2 is provided by HAL as UP_2<<1 */ -#define flow_counter 16 /* Flow error counter */ -#define direction_rw 17 /* Read DMEM =0, Write DMEM =3 (ATC offset of the access pointer) */ -#define counter 11 /* ping/pong buffer flag */ -#define workbuff_BaseAddr 12 /* current Base address of the working buffer */ -#define workbuff_Samples 14 /* samples left in the working buffer */ -#define nextbuff0_BaseAddr 16 /* Base address of the ping/pong buffer 0 */ -#define nextbuff0_Samples 18 /* samples available in the ping/pong buffer 0 */ -#define nextbuff1_BaseAddr 20 /* Base address of the ping/pong buffer 1 */ -#define nextbuff1_Samples 22 /* samples available in the ping/pong buffer 1 */ +/* [W] asrc output used for the next ASRC call (+/- 1 / 0)*/ +#define drift_ASRC 0 + +/* [W] asrc output used for controlling the number of samples to be + exchanged (+/- 1 / 0) */ +#define drift_io 2 + +/* DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */ +#define hw_ctrl_addr 4 + +/* index of the copy subroutine */ +#define copy_func_index 6 + +/* X number of SMEM samples to move */ +#define x_io 7 + +/* 0 for mono data, 1 for stereo data */ +#define data_size 8 + +/* internal SMEM buffer INITPTR pointer index */ +#define smem_addr 9 + +/* data content to be loaded to "hw_ctrl_addr" */ +#define atc_irq_data 10 + +/* ATC descriptor address */ +#define atc_address 11 + +/* THR1; For stereo data, THR1 is provided by HAL as THR1<<1 */ +#define threshold_1 12 + +/* THR2; For stereo data, THR2 is provided by HAL as THR2<<1 */ +#define threshold_2 13 + +/* UP_1; For stereo data, UP_1 is provided by HAL as UP_1<<1 */ +#define update_1 14 + +/* UP_2; For stereo data, UP_2 is provided by HAL as UP_2<<1 */ +#define update_2 15 + +/* Flow error counter */ +#define flow_counter 16 + +/* Read DMEM =0, Write DMEM =3 (ATC offset of the access pointer) */ +#define direction_rw 17 + +/* ping/pong buffer flag */ +#define counter 11 + +/* current Base address of the working buffer */ +#define workbuff_BaseAddr 12 + +/* samples left in the working buffer */ +#define workbuff_Samples 14 + +/* Base address of the ping/pong buffer 0 */ +#define nextbuff0_BaseAddr 16 + +/* samples available in the ping/pong buffer 0 */ +#define nextbuff0_Samples 18 + +/* samples available in the ping/pong buffer 0 */ +#define nextbuff1_BaseAddr 20 + +/* samples available in the ping/pong buffer 1 */ +#define nextbuff1_Samples 22 #endif -#endif /* _ABE_TYPEDEF_H_ */ +#endif /* _ABE_TYPEDEF_H_ */ diff --git a/sound/soc/omap/abe/C_ABE_FW_SIZE.h b/sound/soc/omap/abe/c_abe_fw_size.h index 99860364394a..bda16787a9ba 100644 --- a/sound/soc/omap/abe/C_ABE_FW_SIZE.h +++ b/sound/soc/omap/abe/c_abe_fw_size.h @@ -1,4 +1,4 @@ -/* +/* FW 05.10 MEMORY SIZES */ #define ABE_DMEM_SIZE_OPTIMIZED 16384 |