diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2010-10-01 15:01:51 +0530 |
|---|---|---|
| committer | Sebastien Jan <s-jan@ti.com> | 2010-11-03 15:57:59 +0100 |
| commit | 3230826aca4ca61616dd40b2eceebd410615bd9f (patch) | |
| tree | e9fd611c823aad55d8c69fb01b13261da5355b64 | |
| parent | 8d0b2154c5dec2c76815298001c8a9432bf1ab71 (diff) | |
RCCR and XCCR register values are modified to enable transfer and
receive by default
RCCR and XCCR register values are modified to disable transfer and receive
in the case of "cancelling the transmission". But these values are maintained
even after disabling the clock and enabling the clock. This prevents the
following test cases executed to disable data transfer.
This fix resets the XDISABLE bit and RDSIABLE bit in XCCR and RCCR register
by default.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
| -rw-r--r-- | arch/arm/mach-omap2/mcbsp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index e8b491c1be49..61c3b74cce01 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c @@ -850,10 +850,10 @@ void omap2_mcbsp_set_srg_cfg_param(unsigned int id, int interface_mode, else if (param->sync_mode == OMAP_MCBSP_SRG_RUNNING) mcbsp_cfg->srgr2 = mcbsp_cfg->srgr2 | (GSYNC); - mcbsp_cfg->xccr = OMAP_MCBSP_READ(mcbsp, XCCR); + mcbsp_cfg->xccr = OMAP_MCBSP_READ(mcbsp, XCCR) & ~(XDISABLE); if (param->dlb) mcbsp_cfg->xccr = mcbsp_cfg->xccr | (DILB); - mcbsp_cfg->rccr = OMAP_MCBSP_READ(mcbsp, RCCR); + mcbsp_cfg->rccr = OMAP_MCBSP_READ(mcbsp, RCCR) & ~(RDISABLE); return; } |