ASoC: ABE DSP: Update to HAL release 08.50

Integrate ABE HAL release 08.50 from clearcase
Update ABE HAL release to 08.50. This release introduces new ABE
features in order to support different OPP mode and McBSP format.

Signed-off-by: sebastien Guiriec <s-guiriec@ti.com>
Signed-off-by: Margarita Olaya Cabrera <magi.olaya@ti.com>

31 files changed, 5473 insertions, 7616 deletions

diff --git a/sound/soc/omap/abe/abe_api.c b/sound/soc/omap/abe/abe_api.c
index 71d5577cdd5d..b26ae6ebfbb2 100644
--- a/sound/soc/omap/abe/abe_api.c
+++ b/sound/soc/omap/abe/abe_api.c
@@ -18,12 +18,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
 #include "abe_typedef.h"
 #include "abe_initxxx_labels.h"
 #include "abe_dbg.h"
-
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/init.h>
@@ -37,13 +35,6 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
-
-struct abe_gain {
-	u32 gain;
-	int mute;
-};
-struct abe_gain *abe_gain_table;
-
 /**
  * abe_reset_hal - reset the ABE/HAL
  * @rdev: regulator source
@@ -55,27 +46,31 @@ struct abe_gain *abe_gain_table;
  */
 abehal_status abe_reset_hal(void)
 {
-  _log(id_reset_hal, 0, 0, 0)
-#ifdef CONFIG_OMAP_ABE_DEBUG
-    abe_dbg_output = TERMINAL_OUTPUT;
-
-  abe_dbg_activity_log_write_pointer = 0;
-
-  /* IRQ & DBG circular read pointer in DMEM */
-  abe_irq_dbg_read_ptr = 0;
-
-  /* set debug mask to "enable all traces" */
-  abe_dbg_mask = (abe_dbg_t) (0);
+#if 0
+	u32 i;
+	_log(id_reset_hal, 0, 0, 0);
+	abe_dbg_output = TERMINAL_OUTPUT;
+	abe_dbg_activity_log_write_pointer = 0;
+	/* IRQ & DBG circular read pointer in DMEM */
+	abe_irq_dbg_read_ptr = 0;
+	/* PDM_DL enable/disable collisions */
+	pdm_dl1_status = 0;
+	pdm_dl2_status = 0;
+	pdm_vib_status = 0;
+	/* default = disable the mixer's adaptive gain control */
+	abe_use_compensated_gain(0);
+	/* reset the default gain values */
+	for (i = 0; i < MAXNBFEATURE; i++)
+		abe_unmuted_desired_gains[i] =
+			abe_unmuted_compensated_gains[i] =
+			abe_muted_gains_indicator[i] = 0;
+	/* set debug mask to "enable all traces" */
+	abe_dbg_mask = (abe_dbg_t) (0);
 #endif
-  abe_hw_configuration();
-	abe_gain_table = kzalloc(sizeof(struct abe_gain)*34, GFP_KERNEL);
-
-
-  return 0;
+	abe_hw_configuration();
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_reset_hal);
-
 /**
  * abe_load_fw_param - Load ABE Firmware memories
  * @PMEM: Pointer of Program memory data
@@ -91,67 +86,59 @@ EXPORT_SYMBOL(abe_reset_hal);
  * generator to let execution start, read the version number returned from
  * this execution.
  */
-abehal_status abe_load_fw_param(u32 * ABE_FW)
+abehal_status abe_load_fw_param(u32 *ABE_FW)
 {
-  static u32 warm_boot;
-  u32 event_gen;
-  u32 pmem_size, dmem_size, smem_size, cmem_size;
-  u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr;
-
-  _log(id_load_fw_param, 0, 0, 0)
+	static u32 warm_boot;
+	u32 event_gen;
+	u32 pmem_size, dmem_size, smem_size, cmem_size;
+	u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr;
+	_log(id_load_fw_param, 0, 0, 0);
 #if PC_SIMULATION
-    /* the code is loaded from the Checkers */
+	/* the code is loaded from the Checkers */
 #else
 #define ABE_FW_OFFSET 5
-    fw_ptr = ABE_FW;
-  abe_firmware_version_number = *fw_ptr++;
-  pmem_size = *fw_ptr++;
-  cmem_size = *fw_ptr++;
-  dmem_size = *fw_ptr++;
-  smem_size = *fw_ptr++;
-
-  pmem_ptr = fw_ptr;
-  cmem_ptr = pmem_ptr + (pmem_size >> 2);
-  dmem_ptr = cmem_ptr + (cmem_size >> 2);
-  smem_ptr = dmem_ptr + (dmem_size >> 2);
-
-  /* do not load PMEM */
-  if (warm_boot) {
-    /* Stop the event Generator */
-    event_gen = 0;
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		   EVENT_GENERATOR_START, &event_gen, 4);
-
-    /* Now we are sure the firmware is stalled */
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr,
-		   cmem_size);
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr,
-		   smem_size);
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr,
-		   dmem_size);
-
-    /* Restore the event Generator status */
-    event_gen = 1;
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		   EVENT_GENERATOR_START, &event_gen, 4);
-  } else {
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, pmem_ptr,
-		   pmem_size);
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr,
-		   cmem_size);
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr,
-		   smem_size);
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr,
-		   dmem_size);
-  }
-
-  warm_boot = 1;
+	fw_ptr = ABE_FW;
+	abe_firmware_version_number = *fw_ptr++;
+	pmem_size = *fw_ptr++;
+	cmem_size = *fw_ptr++;
+	dmem_size = *fw_ptr++;
+	smem_size = *fw_ptr++;
+	pmem_ptr = fw_ptr;
+	cmem_ptr = pmem_ptr + (pmem_size >> 2);
+	dmem_ptr = cmem_ptr + (cmem_size >> 2);
+	smem_ptr = dmem_ptr + (dmem_size >> 2);
+	/* do not load PMEM */
+	if (warm_boot) {
+		/* Stop the event Generator */
+		event_gen = 0;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+			       EVENT_GENERATOR_START, &event_gen, 4);
+		/* Now we are sure the firmware is stalled */
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr,
+			       cmem_size);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr,
+			       smem_size);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr,
+			       dmem_size);
+		/* Restore the event Generator status */
+		event_gen = 1;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+			       EVENT_GENERATOR_START, &event_gen, 4);
+	} else {
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_PMEM, 0, pmem_ptr,
+			       pmem_size);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, 0, cmem_ptr,
+			       cmem_size);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, 0, smem_ptr,
+			       smem_size);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, 0, dmem_ptr,
+			       dmem_size);
+	}
+	warm_boot = 1;
 #endif
-  return 0;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_load_fw_param);
-
 /**
  * abe_load_fw - Load ABE Firmware and initialize memories
  *
@@ -161,27 +148,21 @@ EXPORT_SYMBOL(abe_load_fw_param);
  */
 abehal_status abe_load_fw(void)
 {
-
-  _log(id_load_fw, 0, 0, 0)
-
-    abe_load_fw_param((u32 *) abe_firmware_array);
-
-  abe_reset_all_ports();
-  abe_build_scheduler_table();
-  abe_reset_all_sequence();
-  abe_select_main_port(PDM_DL_PORT);
-  return 0;
+	_log(id_load_fw, 0, 0, 0);
+	abe_load_fw_param((u32 *) abe_firmware_array);
+	abe_reset_all_ports();
+	abe_build_scheduler_table();
+	abe_reset_all_sequence();
+	abe_select_main_port(PDM_DL_PORT);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_load_fw);
-
 /**
  * abe_read_hardware_configuration - Return default HW periferals configuration
  * @u: use-case description list (pointer)
  * @o: opp mode (pointer)
  * @hw: pointer to the output HW structure
  *
-
  * Parameter :
  * U : use-case description list (pointer)
  * H : pointer to the output structure
@@ -191,90 +172,70 @@ EXPORT_SYMBOL(abe_load_fw);
  * will be upgraded in FW06
  * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC
  */
-abehal_status
-abe_read_hardware_configuration(u32 * u, u32 * o, abe_hw_config_init_t * hw)
+abehal_status abe_read_hardware_configuration(u32 *u, u32 *o,
+					      abe_hw_config_init_t *hw)
 {
-
-  _log(id_read_hardware_configuration, (u32) u, (u32) u >> 8,
-       (u32) u >> 16)
-
-    abe_read_use_case_opp(u, o);
-
-  /* 0: 96kHz 1:192kHz */
-  hw->MCPDM_CTRL__DIV_SEL = 0;
-
-  /* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */
-  hw->MCPDM_CTRL__CMD_INT = 1;
-
-  /* 0:MSB aligned 1:LSB aligned */
-  hw->MCPDM_CTRL__PDMOUTFORMAT = 0;
-  hw->MCPDM_CTRL__PDM_DN5_EN = 1;
-  hw->MCPDM_CTRL__PDM_DN4_EN = 1;
-  hw->MCPDM_CTRL__PDM_DN3_EN = 1;
-  hw->MCPDM_CTRL__PDM_DN2_EN = 1;
-  hw->MCPDM_CTRL__PDM_DN1_EN = 1;
-  hw->MCPDM_CTRL__PDM_UP3_EN = 0;
-  hw->MCPDM_CTRL__PDM_UP2_EN = 1;
-  hw->MCPDM_CTRL__PDM_UP1_EN = 1;
-
-  /* All the McPDM_DL FIFOs are enabled simultaneously */
-  hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER / 6;
-
-  /* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels
-     are enabled */
-  hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER / 2;
-
-  /* 0:2.4MHz 1:3.84MHz */
-  hw->DMIC_CTRL__DMIC_CLK_DIV = 0;
-
-  /* 0:MSB aligned 1:LSB aligned */
-  hw->DMIC_CTRL__DMICOUTFORMAT = 0;
-  hw->DMIC_CTRL__DMIC_UP3_EN = 1;
-  hw->DMIC_CTRL__DMIC_UP2_EN = 1;
-  hw->DMIC_CTRL__DMIC_UP1_EN = 1;
-
-  /* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */
-  hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER / 6;
-
-  /* MCBSP SPECIFICATION
-     RJUST = 00 Right justify data and zero fill MSBs in DRR[1,2]
-     RJUST = 01 Right justify data and sign extend it into the MSBs
-     in DRR[1,2]
-     RJUST = 10 Left justify data and zero fill LSBs in DRR[1,2]
-     MCBSPLP_RJUST_MODE_RIGHT_ZERO = 0x0,
-     MCBSPLP_RJUST_MODE_RIGHT_SIGN = 0x1,
-     MCBSPLP_RJUST_MODE_LEFT_ZERO = 0x2,
-     MCBSPLP_RJUST_MODE_MAX = MCBSPLP_RJUST_MODE_LEFT_ZERO
-  */
-  hw->MCBSP_SPCR1_REG__RJUST = 2;
-
-  /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
-  hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1;
-
-  /* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
-  hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1;
-
-  /* Slimbus IP FIFO thresholds */
-  hw->SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD = 1;
-
-  /* 2050 gives about 96kHz */
-  hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE =
-    EVENT_GENERATOR_COUNTER_DEFAULT;
-
-  /* 0: DMAreq, 1:Counter */
-  hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1;
-
-  /* 5bits DMAreq selection */
-  hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION =
-    ABE_ATC_MCPDMDL_DMA_REQ;
-
-  /* THE famous EVENT timer ! */
-  hw->HAL_EVENT_SELECTION = EVENT_TIMER;
-  return 0;
+	_log(id_read_hardware_configuration, (u32);
+	     u, (u32) u >> 8, (u32) u >> 16)
+		abe_read_use_case_opp(u, o);
+	/* 0: 96kHz 1:192kHz */
+	hw->MCPDM_CTRL__DIV_SEL = 0;
+	/* 0: no command in the FIFO, 1: 6 data on each lines (with commands) */
+	hw->MCPDM_CTRL__CMD_INT = 1;
+	/* 0:MSB aligned 1:LSB aligned */
+	hw->MCPDM_CTRL__PDMOUTFORMAT = 0;
+	hw->MCPDM_CTRL__PDM_DN5_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN4_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN3_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN2_EN = 1;
+	hw->MCPDM_CTRL__PDM_DN1_EN = 1;
+	hw->MCPDM_CTRL__PDM_UP3_EN = 0;
+	hw->MCPDM_CTRL__PDM_UP2_EN = 1;
+	hw->MCPDM_CTRL__PDM_UP1_EN = 1;
+	/* All the McPDM_DL FIFOs are enabled simultaneously */
+	hw->MCPDM_FIFO_CTRL_DN__DN_TRESH = MCPDM_DL_ITER / 6;
+	/* number of ATC access upon AMIC DMArequests, 2 the FIFOs channels
+	   are enabled */
+	hw->MCPDM_FIFO_CTRL_UP__UP_TRESH = MCPDM_UL_ITER / 2;
+	/* 0:2.4MHz 1:3.84MHz */
+	hw->DMIC_CTRL__DMIC_CLK_DIV = 0;
+	/* 0:MSB aligned 1:LSB aligned */
+	hw->DMIC_CTRL__DMICOUTFORMAT = 0;
+	hw->DMIC_CTRL__DMIC_UP3_EN = 1;
+	hw->DMIC_CTRL__DMIC_UP2_EN = 1;
+	hw->DMIC_CTRL__DMIC_UP1_EN = 1;
+	/* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */
+	hw->DMIC_FIFO_CTRL__DMIC_TRESH = DMIC_ITER / 6;
+	/* MCBSP SPECIFICATION
+	   RJUST = 00 Right justify data and zero fill MSBs in DRR[1,2]
+	   RJUST = 01 Right justify data and sign extend it into the MSBs
+	   in DRR[1,2]
+	   RJUST = 10 Left justify data and zero fill LSBs in DRR[1,2]
+	   MCBSPLP_RJUST_MODE_RIGHT_ZERO = 0x0,
+	   MCBSPLP_RJUST_MODE_RIGHT_SIGN = 0x1,
+	   MCBSPLP_RJUST_MODE_LEFT_ZERO = 0x2,
+	   MCBSPLP_RJUST_MODE_MAX = MCBSPLP_RJUST_MODE_LEFT_ZERO
+	 */
+	hw->MCBSP_SPCR1_REG__RJUST = 2;
+	/* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
+	hw->MCBSP_THRSH2_REG_REG__XTHRESHOLD = 1;
+	/* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
+	hw->MCBSP_THRSH1_REG_REG__RTHRESHOLD = 1;
+	/* Slimbus IP FIFO thresholds */
+	hw->SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD = 1;
+	/* 2050 gives about 96kHz */
+	hw->AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE =
+		EVENT_GENERATOR_COUNTER_DEFAULT;
+	/* 0: DMAreq, 1:Counter */
+	hw->AESS_EVENT_SOURCE_SELECTION__SELECTION = 1;
+	/* 5bits DMAreq selection */
+	hw->AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION =
+		ABE_ATC_MCPDMDL_DMA_REQ;
+	/* THE famous EVENT timer ! */
+	hw->HAL_EVENT_SELECTION = EVENT_TIMER;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_hardware_configuration);
-
 /**
  * abe_irq_processing - Process ABE interrupt
  *
@@ -284,68 +245,59 @@ EXPORT_SYMBOL(abe_read_hardware_configuration);
  * for the delivery of "end of time sequenced tasks" notifications, some are
  * originated from the Ping-Pong protocols, some are generated from
  * the embedded debugger when the firmware stops on programmable break-points,
- * etc …
+ * etc �
  */
 abehal_status abe_irq_processing(void)
 {
-  u32 clear_abe_irq;
-  u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
-  abe_irq_data_t IRQ_data;
+	u32 clear_abe_irq;
+	u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
+	abe_irq_data_t IRQ_data;
 #define IrqFiFoMask ((D_McuIrqFifo_sizeof >> 2) -1)
-
-  _log(id_irq_processing, 0, 0, 0)
-
-    /* extract the write pointer index from CMEM memory (INITPTR format) */
-    /* CMEM address of the write pointer in bytes */
-    cmem_src = MCU_IRQ_FIFO_ptr_labelID * 4;
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_CMEM, cmem_src,
-		 &sm_cm, sizeof(abe_irq_dbg_write_ptr));
-
-  /* AESS left-pointer index located on MSBs */
-  abe_irq_dbg_write_ptr = sm_cm >> 16;
-  abe_irq_dbg_write_ptr &= 0xFF;
-
-  /* loop on the IRQ FIFO content */
-  for (i = 0; i < D_McuIrqFifo_sizeof; i++) {
-    /* stop when the FIFO is empty */
-    if (abe_irq_dbg_write_ptr == abe_irq_dbg_read_ptr)
-      break;
-    /* read the IRQ/DBG FIFO */
-    abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-		   (D_McuIrqFifo_ADDR +
-		    (abe_irq_dbg_read_ptr << 2)),
-		   (u32 *) & IRQ_data, sizeof(IRQ_data));
-    abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) & IrqFiFoMask;
-
-    /* select the source of the interrupt */
-    switch (IRQ_data.tag) {
-    case IRQtag_APS:
-      _log(id_irq_processing, IRQ_data.data, 0, 1)
-	abe_irq_aps(IRQ_data.data);
-      break;
-    case IRQtag_PP:
-      _log(id_irq_processing, 0, 0, 2)
-	abe_irq_ping_pong();
-      break;
-    case IRQtag_COUNT:
-      _log(id_irq_processing, IRQ_data.data, 0, 3)
-	abe_irq_check_for_sequences(IRQ_data.data);
-      break;
-    default:
-      break;
-    }
-  }
-
-  abe_monitoring();
-
-  clear_abe_irq = 1;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS,
-		 &clear_abe_irq, 4);
-  return 0;
+	_log(id_irq_processing, 0, 0, 0);
+	/* extract the write pointer index from CMEM memory (INITPTR format) */
+	/* CMEM address of the write pointer in bytes */
+	cmem_src = MCU_IRQ_FIFO_ptr_labelID << 2;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_CMEM, cmem_src,
+		       &sm_cm, sizeof(abe_irq_dbg_write_ptr));
+	/* AESS left-pointer index located on MSBs */
+	abe_irq_dbg_write_ptr = sm_cm >> 16;
+	abe_irq_dbg_write_ptr &= 0xFF;
+	/* loop on the IRQ FIFO content */
+	for (i = 0; i < D_McuIrqFifo_sizeof; i++) {
+		/* stop when the FIFO is empty */
+		if (abe_irq_dbg_write_ptr == abe_irq_dbg_read_ptr)
+			break;
+		/* read the IRQ/DBG FIFO */
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+			       (D_McuIrqFifo_ADDR +
+				(abe_irq_dbg_read_ptr << 2)),
+			       (u32 *) &IRQ_data, sizeof(IRQ_data));
+		abe_irq_dbg_read_ptr = (abe_irq_dbg_read_ptr + 1) &IrqFiFoMask;
+		/* select the source of the interrupt */
+		switch (IRQ_data.tag) {
+		case IRQtag_APS:
+			_log(id_irq_processing, IRQ_data.data, 0, 1);
+			abe_irq_aps(IRQ_data.data);
+			break;
+		case IRQtag_PP:
+			_log(id_irq_processing, 0, 0, 2);
+			abe_irq_ping_pong();
+			break;
+		case IRQtag_COUNT:
+			_log(id_irq_processing, IRQ_data.data, 0, 3);
+			abe_irq_check_for_sequences(IRQ_data.data);
+			break;
+		default:
+			break;
+		}
+	}
+	abe_monitoring();
+	clear_abe_irq = 1;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_MCU_IRQSTATUS,
+		       &clear_abe_irq, 4);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_irq_processing);
-
 /**
  * abe_select_main_port - Select stynchronization port for Event generator.
  * @id: audio port name
@@ -355,27 +307,20 @@ EXPORT_SYMBOL(abe_irq_processing);
  */
 abehal_status abe_select_main_port(u32 id)
 {
-  u32 selection;
-
-  _log(id_select_main_port, id, 0, 0)
-
-    /* flow control */
-    selection = D_IOdescr_ADDR + id * sizeof(ABE_SIODescriptor) +
-    flow_counter_;
-
-  /* when the main port is a sink port from AESS point of view
-     the sign the firmware task analysis must be changed  */
-  selection &= 0xFFFFL;
-  if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
-    selection |= 0x80000;
-
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR,
-		 &selection, 4);
-  return 0;
+	u32 selection;
+	_log(id_select_main_port, id, 0, 0);
+	/* flow control */
+	selection = D_IOdescr_ADDR + id * sizeof(ABE_SIODescriptor) +
+		flow_counter_;
+	/* when the main port is a sink port from AESS point of view
+	   the sign the firmware task analysis must be changed  */
+	selection &= 0xFFFFL;
+	if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+		selection |= 0x80000;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_Slot23_ctrl_ADDR,
+		       &selection, 4);
+	return 0;
 }
-
-EXPORT_SYMBOL(abe_select_main_port);
-
 /**
  * abe_write_event_generator - Select event generator source
  * @e: Event Generation Counter, McPDM, DMIC or default.
@@ -393,43 +338,36 @@ EXPORT_SYMBOL(abe_select_main_port);
  */
 abehal_status abe_write_event_generator(u32 e)
 {
-  u32 event, selection, counter, start;
-
-  _log(id_write_event_generator, e, 0, 0)
-
-    counter = EVENT_GENERATOR_COUNTER_DEFAULT;
-  start = EVENT_GENERATOR_ON;
-  abe_current_event_id = e;
-
-  switch (e) {
-  case EVENT_TIMER:
-    selection = EVENT_SOURCE_COUNTER;
-    event = 0;
-    break;
-  case EVENT_44100:
-    selection = EVENT_SOURCE_COUNTER;
-    event = 0;
-    counter = EVENT_GENERATOR_COUNTER_44100;
-    break;
-  default:
-    abe_dbg_param |= ERR_API;
-    abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
-  }
-
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		 EVENT_GENERATOR_COUNTER, &counter, 4);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		 EVENT_SOURCE_SELECTION, &selection, 4);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		 EVENT_GENERATOR_START, &start, 4);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
-		 AUDIO_ENGINE_SCHEDULER, &event, 4);
-
-  return 0;
+	u32 event, selection, counter, start;
+	_log(id_write_event_generator, e, 0, 0);
+	counter = EVENT_GENERATOR_COUNTER_DEFAULT;
+	start = EVENT_GENERATOR_ON;
+	abe_current_event_id = e;
+	switch (e) {
+	case EVENT_TIMER:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		break;
+	case EVENT_44100:
+		selection = EVENT_SOURCE_COUNTER;
+		event = 0;
+		counter = EVENT_GENERATOR_COUNTER_44100;
+		break;
+	default:
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+	}
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+		       EVENT_GENERATOR_COUNTER, &counter, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+		       EVENT_SOURCE_SELECTION, &selection, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+		       EVENT_GENERATOR_START, &start, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC,
+		       AUDIO_ENGINE_SCHEDULER, &event, 4);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_write_event_generator);
-
 /**
  * abe_stop_event_generator - Stop event generator source
  *
@@ -452,78 +390,70 @@ EXPORT_SYMBOL(abe_stop_event_generator);
  *
  * returns the expected min OPP for a given use_case list
  */
-abehal_status abe_read_use_case_opp(u32 * u, u32 * o)
+abehal_status abe_read_use_case_opp(u32 *u, u32 *o)
 {
-  u32 opp, i;
-  u32 *ptr = u;
+	u32 opp, i;
+	u32 *ptr = u;
 #define MAX_READ_USE_CASE_OPP 10
 #define OPP_25 1
 #define OPP_50 2
 #define OPP_100 4
-
-  _log(id_read_use_case_opp, (u32) u, (u32) u >> 8, (u32) u >> 16)
-
-    opp = i = 0;
-  do {
-    /* check for pointer errors */
-    if (i > MAX_READ_USE_CASE_OPP) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_READ_USE_CASE_OPP_ERR);
-      break;
-    }
-
-    /* check for end_of_list */
-    if (*ptr <= 0)
-      break;
-
-    /* OPP selection based on current firmware implementation */
-    switch (*ptr) {
-    case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE:
-      opp |= OPP_25;
-      break;
-    case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER:
-      opp |= OPP_100;
-      break;
-    case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL:
-      opp |= OPP_100;
-      break;
-    case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT:
-      opp |= OPP_50;
-      break;
-    case ABE_MULTIMEDIA_AUDIO_RECORDER:
-      opp |= OPP_50;
-      break;
-    case ABE_VIBRATOR_OR_HAPTICS:
-      opp |= OPP_100;
-      break;
-    case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER:
-      opp |= OPP_100;
-      break;
-    case ABE_RINGER_TONES:
-      opp |= OPP_100;
-      break;
-    case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER:
-      opp |= OPP_100;
-      break;
-    default:
-      break;
-    }
-    i++;
-    ptr++;
-  } while (*ptr != 0);
-
-  if (opp & OPP_100)
-    *o = ABE_OPP100;
-  else if (opp & OPP_50)
-    *o = ABE_OPP50;
-  else
-    *o = ABE_OPP25;
-
-  return 0;
+	_log(id_read_use_case_opp, (u32); u, (u32) u >> 8, (u32) u >> 16)
+		opp = i = 0;
+	do {
+		/* check for pointer errors */
+		if (i > MAX_READ_USE_CASE_OPP) {
+			abe_dbg_param |= ERR_API;
+			abe_dbg_error_log(ABE_READ_USE_CASE_OPP_ERR);
+			break;
+		}
+		/* check for end_of_list */
+		if (*ptr <= 0)
+			break;
+		/* OPP selection based on current firmware implementation */
+		switch (*ptr) {
+		case ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE:
+			opp |= OPP_25;
+			break;
+		case ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER:
+			opp |= OPP_100;
+			break;
+		case ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_ON_HEADSET_OR_EARPHONE_OR_BT:
+			opp |= OPP_50;
+			break;
+		case ABE_MULTIMEDIA_AUDIO_RECORDER:
+			opp |= OPP_50;
+			break;
+		case ABE_VIBRATOR_OR_HAPTICS:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_ON_HANDS_FREE_SPEAKER:
+			opp |= OPP_100;
+			break;
+		case ABE_RINGER_TONES:
+			opp |= OPP_100;
+			break;
+		case ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER:
+			opp |= OPP_100;
+			break;
+		default:
+			break;
+		}
+		i++;
+		ptr++;
+	} while (*ptr != 0);
+	if (opp & OPP_100)
+		*o = ABE_OPP100;
+	else if (opp & OPP_50)
+		*o = ABE_OPP50;
+	else
+		*o = ABE_OPP25;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_use_case_opp);
-
 /**
  * abe_set_opp_processing - Set OPP mode for ABE Firmware
  * @opp: OOPP mode
@@ -541,62 +471,32 @@ EXPORT_SYMBOL(abe_read_use_case_opp);
  */
 abehal_status abe_set_opp_processing(u32 opp)
 {
-  u32 dOppMode32, sio_desc_address, sio_desc_address_pp;
-  ABE_SIODescriptor desc;
-  ABE_SPingPongDescriptor desc_pp;
-
-  _lock_enter;
-  _log(id_set_opp_processing, opp, 0, 0)
-
-    switch (opp) {
-    case ABE_OPP25:
-      /* OPP25% */
-      dOppMode32 = DOPPMODE32_OPP25;
-      break;
-    case ABE_OPP50:
-      /* OPP50% */
-      dOppMode32 = DOPPMODE32_OPP50;
-      break;
-    default:
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
-    case ABE_OPP100:
-      /* OPP100% */
-      dOppMode32 = DOPPMODE32_OPP100;
-      break;
-    }
-
-  /* Write Multiframe inside DMEM */
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-		 D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(u32));
-
-  sio_desc_address = dmem_port_descriptors + (MM_DL_PORT *
-					      sizeof(ABE_SIODescriptor));
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address,
-		 (u32 *) & desc, sizeof(desc));
-
-  sio_desc_address_pp = D_PingPongDesc_ADDR;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address_pp,
-		 (u32 *) & desc_pp, sizeof(desc_pp));
-
-  if (dOppMode32 == DOPPMODE32_OPP100) {
-    /* ASRC input buffer, size 40 */
-    desc.smem_addr1 = smem_mm_dl_opp100;
-    desc_pp.smem_addr = smem_mm_dl_opp100;
-  } else {
-    /* at OPP 25/50 or without ASRC */
-    desc.smem_addr1 = smem_mm_dl_opp25;
-    desc_pp.smem_addr = smem_mm_dl_opp25;
-  }
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
-		 (u32 *) & desc, sizeof(desc));
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address_pp,
-		 (u32 *) & desc_pp, sizeof(desc_pp));
-  return 0;
+	u32 dOppMode32;
+	_lock_enter;
+	_log(id_set_opp_processing, opp, 0, 0);
+	switch (opp) {
+	case ABE_OPP25:
+		/* OPP25% */
+		dOppMode32 = DOPPMODE32_OPP25;
+		break;
+	case ABE_OPP50:
+		/* OPP50% */
+		dOppMode32 = DOPPMODE32_OPP50;
+		break;
+	default:
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
+	case ABE_OPP100:
+		/* OPP100% */
+		dOppMode32 = DOPPMODE32_OPP100;
+		break;
+	}
+	/* Write Multiframe inside DMEM */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		       D_maxTaskBytesInSlot_ADDR, &dOppMode32, sizeof(u32));
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_set_opp_processing);
-
 /**
  * abe_set_ping_pong_buffer
  * @port: ABE port ID
@@ -607,54 +507,44 @@ EXPORT_SYMBOL(abe_set_opp_processing);
  */
 abehal_status abe_set_ping_pong_buffer(u32 port, u32 n_bytes)
 {
-  u32 sio_pp_desc_address, struct_offset, n_samples, datasize,
-    base_and_size, *src;
-  ABE_SPingPongDescriptor desc_pp;
-
-  _log(id_set_ping_pong_buffer, port, n_bytes, n_bytes >> 8)
-
-    /* ping_pong is only supported on MM_DL */
-    if (port != MM_DL_PORT) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_PARAMETER_ERROR);
-    }
-  /* translates the number of bytes in samples */
-  /* data size in DMEM words */
-  datasize = abe_dma_port_iter_factor(&((abe_port[port]).format));
-
-  /* data size in bytes */
-  datasize = datasize << 2;
-  n_samples = n_bytes / datasize;
-
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_PingPongDesc_ADDR,
-		 (u32 *) & desc_pp, sizeof(desc_pp));
-
-  /*
-   * read the port SIO descriptor and extract the current pointer
-   * address after reading the counter
-   */
-  if ((desc_pp.counter & 0x1) == 0) {
-    struct_offset =
-      (u32) & (desc_pp.nextbuff0_BaseAddr) - (u32) & (desc_pp);
-    base_and_size = desc_pp.nextbuff0_BaseAddr;
-  } else {
-    struct_offset =
-      (u32) & (desc_pp.nextbuff1_BaseAddr) - (u32) & (desc_pp);
-    base_and_size = desc_pp.nextbuff1_BaseAddr;
-  }
-
-  base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16);
-
-  sio_pp_desc_address = D_PingPongDesc_ADDR + struct_offset;
-  src = &base_and_size;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_pp_desc_address,
-		 (u32 *) & base_and_size, sizeof(u32));
-
-  return 0;
+	u32 sio_pp_desc_address, struct_offset, n_samples, datasize,
+		base_and_size, *src;
+	ABE_SPingPongDescriptor desc_pp;
+	_log(id_set_ping_pong_buffer, port, n_bytes, n_bytes >> 8);
+	/* ping_pong is only supported on MM_DL */
+	if (port != MM_DL_PORT) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	/* translates the number of bytes in samples */
+	/* data size in DMEM words */
+	datasize = abe_dma_port_iter_factor(&((abe_port[port]).format));
+	/* data size in bytes */
+	datasize = datasize << 2;
+	n_samples = n_bytes / datasize;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_PingPongDesc_ADDR,
+		       (u32 *) &desc_pp, sizeof(desc_pp));
+	/*
+	 * read the port SIO descriptor and extract the current pointer
+	 * address after reading the counter
+	 */
+	if ((desc_pp.counter & 0x1) == 0) {
+		struct_offset = (u32) &(desc_pp.nextbuff0_BaseAddr) -
+			(u32) &(desc_pp);
+		base_and_size = desc_pp.nextbuff0_BaseAddr;
+	} else {
+		struct_offset = (u32) &(desc_pp.nextbuff1_BaseAddr) -
+			(u32) &(desc_pp);
+		base_and_size = desc_pp.nextbuff1_BaseAddr;
+	}
+	base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16);
+	sio_pp_desc_address = D_PingPongDesc_ADDR + struct_offset;
+	src = &base_and_size;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_pp_desc_address,
+		       (u32 *) &base_and_size, sizeof(u32));
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_set_ping_pong_buffer);
-
 /**
  * abe_read_next_ping_pong_buffer
  * @port: ABE portID
@@ -663,81 +553,65 @@ EXPORT_SYMBOL(abe_set_ping_pong_buffer);
  *
  * Tell the next base address of the next ping_pong Buffer and its size
  */
-abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 * p, u32 * n)
+abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n)
 {
-  u32 sio_pp_desc_address;
-  ABE_SPingPongDescriptor desc_pp;
-
-  _log(id_read_next_ping_pong_buffer, port, 0, 0)
-
-    /* ping_pong is only supported on MM_DL */
-    if (port != MM_DL_PORT) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_PARAMETER_ERROR);
-    }
-
-  /* read the port SIO descriptor and extract the current pointer
-     address after reading the counter */
-  sio_pp_desc_address = D_PingPongDesc_ADDR;
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address,
-		 (u32 *) & desc_pp, sizeof(ABE_SPingPongDescriptor));
-
-  if ((desc_pp.counter & 0x1) == 0) {
-    _log(id_read_next_ping_pong_buffer, port, 0, 0)
-      * p = desc_pp.nextbuff0_BaseAddr;
-  } else {
-    _log(id_read_next_ping_pong_buffer, port, 1, 0)
-      * p = desc_pp.nextbuff1_BaseAddr;
-  }
-
-  /* translates the number of samples in bytes */
-  *n = abe_size_pingpong;
-
-  return 0;
+	u32 sio_pp_desc_address;
+	ABE_SPingPongDescriptor desc_pp;
+	_log(id_read_next_ping_pong_buffer, port, 0, 0);
+	/* ping_pong is only supported on MM_DL */
+	if (port != MM_DL_PORT) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	/* read the port SIO descriptor and extract the current pointer
+	   address after reading the counter */
+	sio_pp_desc_address = D_PingPongDesc_ADDR;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address,
+		       (u32 *) &desc_pp, sizeof(ABE_SPingPongDescriptor));
+	if ((desc_pp.counter & 0x1) == 0) {
+		_log(id_read_next_ping_pong_buffer, port, 0, 0);
+		*p = desc_pp.nextbuff0_BaseAddr;
+	} else {
+		_log(id_read_next_ping_pong_buffer, port, 1, 0);
+		*p = desc_pp.nextbuff1_BaseAddr;
+	}
+	/* translates the number of samples in bytes */
+	*n = abe_size_pingpong;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_next_ping_pong_buffer);
-
 /**
  * abe_init_ping_pong_buffer
  * @id: ABE port ID
  * @size_bytes:size of the ping pong
  * @n_buffers:number of buffers (2 = ping/pong)
  * @p:returned address of the ping-pong list of base address (byte offset
- from DMEM start)
+	from DMEM start)
  *
  * Computes the base address of the ping_pong buffers
  */
-abehal_status
-abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers, u32 * p)
+abehal_status abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers,
+					u32 *p)
 {
-  u32 i, dmem_addr;
-
-  _log(id_init_ping_pong_buffer, id, size_bytes, n_buffers)
-
-    /* ping_pong is supported in 2 buffers configuration right now but FW
-       is ready for ping/pong/pung/pang... */
-    if (id != MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_PARAMETER_ERROR);
-    }
-
-  for (i = 0; i < n_buffers; i++) {
-    dmem_addr = dmem_ping_pong_buffer + (i * size_bytes);
-
-    /* base addresses of the ping pong buffers in U8 unit */
-    abe_base_address_pingpong[i] = dmem_addr;
-  }
-
-  /* global data */
-  abe_size_pingpong = size_bytes;
-  *p = (u32) dmem_ping_pong_buffer;
-
-  return 0;
+	u32 i, dmem_addr;
+	_log(id_init_ping_pong_buffer, id, size_bytes, n_buffers);
+	/* ping_pong is supported in 2 buffers configuration right now but FW
+	   is ready for ping/pong/pung/pang... */
+	if (id != MM_DL_PORT || n_buffers > MAX_PINGPONG_BUFFERS) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	for (i = 0; i < n_buffers; i++) {
+		dmem_addr = dmem_ping_pong_buffer + (i * size_bytes);
+		/* base addresses of the ping pong buffers in U8 unit */
+		abe_base_address_pingpong[i] = dmem_addr;
+	}
+	/* global data */
+	abe_size_pingpong = size_bytes;
+	*p = (u32) dmem_ping_pong_buffer;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_init_ping_pong_buffer);
-
 /**
  * abe_plug_subroutine
  * @id: returned sequence index after plugging a new subroutine
@@ -747,16 +621,14 @@ EXPORT_SYMBOL(abe_init_ping_pong_buffer);
  *
  * register a list of subroutines for call-back purpose
  */
-abehal_status
-abe_plug_subroutine(u32 * id, abe_subroutine2 f, u32 n, u32 * params)
+abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n,
+				  u32 *params)
 {
-  _log(id_plug_subroutine, (u32) (*id), (u32) f, n)
-    abe_add_subroutine(id, (abe_subroutine2) f, n, (u32 *) params);
-  return 0;
+	_log(id_plug_subroutine, (u32); (*id), (u32) f, n)
+		abe_add_subroutine(id, (abe_subroutine2) f, n, (u32 *) params);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_plug_subroutine);
-
 /**
  * abe_set_sequence_time_accuracy
  * @fast: fast counter
@@ -765,23 +637,17 @@ EXPORT_SYMBOL(abe_plug_subroutine);
  */
 abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow)
 {
-  u32 data;
-
-  _log(id_set_sequence_time_accuracy, fast, slow, 0)
-
-    data = minimum(MAX_UINT16, fast / FW_SCHED_LOOP_FREQ_DIV1000);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_fastCounter_ADDR,
-		 &data, sizeof(data));
-
-  data = minimum(MAX_UINT16, slow / FW_SCHED_LOOP_FREQ_DIV1000);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_slowCounter_ADDR,
-		 &data, sizeof(data));
-
-  return 0;
+	u32 data;
+	_log(id_set_sequence_time_accuracy, fast, slow, 0);
+	data = minimum(MAX_UINT16, fast / FW_SCHED_LOOP_FREQ_DIV1000);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_fastCounter_ADDR,
+		       &data, sizeof(data));
+	data = minimum(MAX_UINT16, slow / FW_SCHED_LOOP_FREQ_DIV1000);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_slowCounter_ADDR,
+		       &data, sizeof(data));
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_set_sequence_time_accuracy);
-
 /**
  * abe_reset_port
  * @id: ABE port ID
@@ -792,14 +658,11 @@ EXPORT_SYMBOL(abe_set_sequence_time_accuracy);
  */
 abehal_status abe_reset_port(u32 id)
 {
-
-  _log(id_reset_port, id, 0, 0)
-    abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  return 0;
+	_log(id_reset_port, id, 0, 0);
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_reset_port);
-
 /**
  * abe_read_remaining_data
  * @id:	ABE port_ID
@@ -807,27 +670,22 @@ EXPORT_SYMBOL(abe_reset_port);
  *
  * computes the remaining amount of data in the buffer.
  */
-abehal_status abe_read_remaining_data(u32 port, u32 * n)
+abehal_status abe_read_remaining_data(u32 port, u32 *n)
 {
-  u32 sio_pp_desc_address;
-  ABE_SPingPongDescriptor desc_pp;
-
-  _log(id_read_remaining_data, port, 0, 0)
-
-    /*
-     * read the port SIO descriptor and extract the
-     * current pointer address after reading the counter
-     */
-    sio_pp_desc_address = D_PingPongDesc_ADDR;
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address,
-		 (u32 *) & desc_pp, sizeof(ABE_SPingPongDescriptor));
-  *n = desc_pp.workbuff_Samples;
-
-  return 0;
+	u32 sio_pp_desc_address;
+	ABE_SPingPongDescriptor desc_pp;
+	_log(id_read_remaining_data, port, 0, 0);
+	/*
+	 * read the port SIO descriptor and extract the
+	 * current pointer address after reading the counter
+	 */
+	sio_pp_desc_address = D_PingPongDesc_ADDR;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_pp_desc_address,
+		       (u32 *) &desc_pp, sizeof(ABE_SPingPongDescriptor));
+	*n = desc_pp.workbuff_Samples;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_remaining_data);
-
 /**
  * abe_disable_data_transfer
  * @id: ABE port id
@@ -838,23 +696,45 @@ EXPORT_SYMBOL(abe_read_remaining_data);
  */
 abehal_status abe_disable_data_transfer(u32 id)
 {
-  _log(id_disable_data_transfer, id, 0, 0)
-
-    /* local host variable status= "port is running" */
-    abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE;
-
-  /* disable DMA requests */
-  abe_disable_dma_request(id);
-
-  /* disable ATC transfers */
-  abe_init_atc(id);
-  abe_clean_temporary_buffers(id);
-
-  return 0;
+	_log(id_disable_data_transfer, id, 0, 0);
+	/* there is only one PDM_DL physical port shared
+	   with DL1/DL2/VIB. Here is a check for the need to stop
+	   PDM_DL if some activity is already on */
+/*
+	if (id == PDM_DL1_PORT) {
+		pdm_dl1_status = 0;
+		if (pdm_dl2_status || pdm_vib_status)
+			return 0;
+		else
+			id = PDM_DL_PORT;
+	}
+	if (id == PDM_DL2_PORT) {
+		pdm_dl2_status = 0;
+		if (pdm_dl1_status || pdm_vib_status)
+			return 0;
+		else
+			id = PDM_DL_PORT;
+	}
+	if (id == PDM_VIB_PORT) {
+		pdm_vib_status = 0;
+		if (pdm_dl1_status || pdm_dl2_status)
+			return 0;
+		else
+			id = PDM_DL_PORT;
+	}
+*/
+	/* local host variable status= "port is running" */
+	abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE;
+	/* disable DMA requests */
+	abe_disable_dma_request(id);
+	/* disable ATC transfers */
+	abe_init_atc(id);
+	abe_clean_temporary_buffers(id);
+	/* select the main port based on the desactivation of this port */
+	abe_decide_main_port(id);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_disable_data_transfer);
-
 /**
  * abe_enable_data_transfer
  * @ip: ABE port id
@@ -865,96 +745,84 @@ EXPORT_SYMBOL(abe_disable_data_transfer);
  */
 abehal_status abe_enable_data_transfer(u32 id)
 {
-  abe_port_protocol_t *protocol;
-  abe_data_format_t format;
-
-  _log(id_enable_data_transfer, id, 0, 0)
-
-    /* check firmware status bit for this */
-    /*if (abe_port[id].status == OMAP_ABE_PORT_ACTIVITY_RUNNING)
-      return 0; */
-    abe_clean_temporary_buffers(id);
-
-  if (id == PDM_UL_PORT) {
-    /* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */
-    protocol = &(abe_port[PDM_UL_PORT].protocol);
-    format = abe_port[PDM_UL_PORT].format;
-    abe_init_atc(PDM_UL_PORT);
-    abe_init_io_tasks(PDM_UL_PORT, &format, protocol);
-  }
-  if (id == PDM_DL_PORT) {
-    /* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */
-    protocol = &(abe_port[PDM_DL_PORT].protocol);
-    format = abe_port[PDM_DL_PORT].format;
-    abe_init_atc(PDM_DL_PORT);
-    abe_init_io_tasks(PDM_DL_PORT, &format, protocol);
-  }
-  if (id == DMIC_PORT) {
-    /* one DMIC port enabled = all DMICs enabled,
-     * since there is a single DMIC path for all DMICs */
-    protocol = &(abe_port[DMIC_PORT].protocol);
-    format = abe_port[DMIC_PORT].format;
-    abe_init_atc(DMIC_PORT);
-    abe_init_io_tasks(DMIC_PORT, &format, protocol);
-  }
-  if (id == VX_UL_PORT) {
-    /* Init VX_UL ASRC and enable its adaptation */
-    abe_init_asrc_vx_ul(250);
-  }
-  if (id == VX_DL_PORT) {
-    /* Init VX_DL ASRC and enable its adaptation */
-    abe_init_asrc_vx_dl(250);
-  }
-
-  /* local host variable status= "port is running" */
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-  /* enable DMA requests */
-  abe_enable_dma_request(id);
-
-  return 0;
+	abe_port_protocol_t *protocol;
+	abe_data_format_t format;
+	u32 dOppMode32;
+	_log(id_enable_data_transfer, id, 0, 0);
+	/* there is only one PDM_DL physical port shared
+	   with DL1/DL2/VIB. Here is a check for the need to enable
+	   PDM_DL when some activity is already on */
+/*
+	if (id == PDM_DL1_PORT) {
+		id = PDM_DL_PORT;
+		if (pdm_dl1_status == 1)
+			return 0;
+		else
+			pdm_dl1_status = 1;
+	}
+	if (id == PDM_DL2_PORT) {
+		id = PDM_DL_PORT;
+		if (pdm_dl2_status == 1)
+			return 0;
+		else
+			pdm_dl2_status = 1;
+	}
+	if (id == PDM_VIB_PORT) {
+		id = PDM_DL_PORT;
+		if (pdm_vib_status == 1)
+			return 0;
+		else
+			pdm_vib_status = 1;
+	}
+*/
+	abe_clean_temporary_buffers(id);
+	if (id == PDM_UL_PORT) {
+		/* initializes the ABE ATC descriptors in DMEM - MCPDM_UL */
+		protocol = &(abe_port[PDM_UL_PORT].protocol);
+		format = abe_port[PDM_UL_PORT].format;
+		abe_init_atc(PDM_UL_PORT);
+		abe_init_io_tasks(PDM_UL_PORT, &format, protocol);
+	}
+	if (id == PDM_DL_PORT) {
+		/* initializes the ABE ATC descriptors in DMEM - MCPDM_DL */
+		protocol = &(abe_port[PDM_DL_PORT].protocol);
+		format = abe_port[PDM_DL_PORT].format;
+		abe_init_atc(PDM_DL_PORT);
+		abe_init_io_tasks(PDM_DL_PORT, &format, protocol);
+	}
+	if (id == DMIC_PORT) {
+		/* one DMIC port enabled = all DMICs enabled,
+		 * since there is a single DMIC path for all DMICs */
+		protocol = &(abe_port[DMIC_PORT].protocol);
+		format = abe_port[DMIC_PORT].format;
+		abe_init_atc(DMIC_PORT);
+		abe_init_io_tasks(DMIC_PORT, &format, protocol);
+	}
+	if (id == VX_UL_PORT) {
+		/* Init VX_UL ASRC and enable its adaptation */
+		abe_init_asrc_vx_ul(250);
+	}
+	if (id == VX_DL_PORT) {
+		/* Init VX_DL ASRC and enable its adaptation */
+		abe_init_asrc_vx_dl(250);
+	}
+	if (id == MM_EXT_IN_PORT) {
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+			       D_maxTaskBytesInSlot_ADDR, &dOppMode32,
+			       sizeof(u32));
+		if (dOppMode32 == DOPPMODE32_OPP100)
+			/* Init MM_EXT_IN ASRC and enable its adaptation */
+			abe_init_asrc_mm_ext_in(250);
+	}
+	/* local host variable status= "port is running" */
+	abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
+	/* enable DMA requests */
+	abe_enable_dma_request(id);
+	/* select the main port based on the activation of this new port */
+	abe_decide_main_port(id);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_enable_data_transfer);
-
-/**
- * abe_set_dmic_filter
- * @d: DMIC decimation ratio : 16/25/32/40
- *
- * Loads in CMEM a specific list of coefficients depending on the DMIC sampling
- * frequency (2.4MHz or 3.84MHz). This table compensates the DMIC decimator
- * roll-off at 20kHz.
- * The default table is loaded with the DMIC 2.4MHz recommended configuration.
- */
-abehal_status abe_set_dmic_filter(u32 d)
-{
-  s32 *src;
-
-  _log(id_set_dmic_filter, d, 0, 0)
-
-    switch (d) {
-    case ABE_DEC16:
-      src = (s32 *) abe_dmic_16;
-      break;
-    case ABE_DEC25:
-      src = (s32 *) abe_dmic_25;
-      break;
-    case ABE_DEC32:
-      src = (s32 *) abe_dmic_32;
-      break;
-    default:
-    case ABE_DEC40:
-      src = (s32 *) abe_dmic_40;
-      break;
-    }
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM,
-		 C_98_48_LP_Coefs_ADDR,
-		 (u32 *) src, C_98_48_LP_Coefs_sizeof << 2);
-
-  return 0;
-}
-
-EXPORT_SYMBOL(abe_set_dmic_filter);
-
 /**
  * abe_connect_cbpr_dmareq_port
  * @id: port name
@@ -966,41 +834,29 @@ EXPORT_SYMBOL(abe_set_dmic_filter);
  * enables the data echange between a DMA and the ABE through the
  *	CBPr registers of AESS.
  */
-
-abehal_status
-abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t * f, u32 d,
-			     abe_dma_t * returned_dma_t)
+abehal_status abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d,
+					   abe_dma_t *returned_dma_t)
 {
-
-  _log(id_connect_cbpr_dmareq_port, id, f->f, f->samp_format)
-
-    abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  (abe_port[id]).format = (*f);
-  abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
-  abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
-  abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
-  abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the dma_t with physical information from AE memory mapping */
-  abe_init_dma_t(id, &((abe_port[id]).protocol));
-
-  /* load the ATC descriptors - disabled */
-  abe_init_atc(id);
-
-  /* return the dma pointer address */
-  abe_read_port_address(id, returned_dma_t);
-
-  return 0;
+	_log(id_connect_cbpr_dmareq_port, id, f->f, f->samp_format);
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
+	abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
+	abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
+	abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the dma_t with physical information from AE memory mapping */
+	abe_init_dma_t(id, &((abe_port[id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+	/* return the dma pointer address */
+	abe_read_port_address(id, returned_dma_t);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_cbpr_dmareq_port);
-
 /**
  * abe_connect_dmareq_ping_pong_port
  * @id: port name
@@ -1014,52 +870,40 @@ EXPORT_SYMBOL(abe_connect_cbpr_dmareq_port);
  * the DMEM memory of ABE. On each dma_request activation the DMA will exchange
  * "s" bytes and switch to the "pong" buffer for a new buffer exchange.
  */
-abehal_status
-abe_connect_dmareq_ping_pong_port(u32 id, abe_data_format_t * f,
-				  u32 d, u32 s, abe_dma_t * returned_dma_t)
+abehal_status abe_connect_dmareq_ping_pong_port(u32 id, abe_data_format_t *f,
+						u32 d, u32 s,
+						abe_dma_t *returned_dma_t)
 {
-  abe_dma_t dma1;
-
-  _log(id_connect_dmareq_ping_pong_port, id, f->f, f->samp_format)
-
-    /* ping_pong is only supported on MM_DL */
-    if (id != MM_DL_PORT) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_PARAMETER_ERROR);
-    }
-
-  /* declare PP buffer and prepare the returned dma_t */
-  abe_init_ping_pong_buffer(MM_DL_PORT, s, 2,
-			    (u32 *) & (returned_dma_t->data));
-
-  abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-
-  (abe_port[id]).format = (*f);
-  (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
-  (abe_port[id]).protocol.p.prot_pingpong.buf_addr =
-    dmem_ping_pong_buffer;
-  (abe_port[id]).protocol.p.prot_pingpong.buf_size = s;
-  (abe_port[id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW;
-  (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1 << d);
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters DESC_IO_PP */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the dma_t with physical information from AE memory mapping */
-  abe_init_dma_t(id, &((abe_port[id]).protocol));
-
-  dma1.data = (u32 *) (abe_port[id].dma.data + ABE_DMEM_BASE_ADDRESS_L3);
-  dma1.iter = abe_port[id].dma.iter;
-  *returned_dma_t = dma1;
-
-  return 0;
+	abe_dma_t dma1;
+	_log(id_connect_dmareq_ping_pong_port, id, f->f, f->samp_format);
+	/* ping_pong is only supported on MM_DL */
+	if (id != MM_DL_PORT) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	/* declare PP buffer and prepare the returned dma_t */
+	abe_init_ping_pong_buffer(MM_DL_PORT, s, 2,
+				  (u32 *) &(returned_dma_t->data));
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_addr =
+		dmem_ping_pong_buffer;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_size = s;
+	(abe_port[id]).protocol.p.prot_pingpong.irq_addr = ABE_DMASTATUS_RAW;
+	(abe_port[id]).protocol.p.prot_pingpong.irq_data = (1 << d);
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters DESC_IO_PP */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the dma_t with physical information from AE memory mapping */
+	abe_init_dma_t(id, &((abe_port[id]).protocol));
+	dma1.data = (u32 *) (abe_port[id].dma.data + ABE_DMEM_BASE_ADDRESS_L3);
+	dma1.iter = abe_port[id].dma.iter;
+	*returned_dma_t = dma1;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_dmareq_ping_pong_port);
-
 /**
  * abe_connect_irq_ping_pong_port
  * @id: port name
@@ -1075,54 +919,40 @@ EXPORT_SYMBOL(abe_connect_dmareq_ping_pong_port);
  * "abe_set_ping_pong_buffer" to notify the new amount of samples in the
  * pong buffer.
  */
-abehal_status
-abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t * f,
-			       u32 subroutine_id, u32 size,
-			       u32 * sink, u32 dsp_mcu_flag)
+abehal_status abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f,
+					     u32 subroutine_id, u32 size,
+					     u32 *sink, u32 dsp_mcu_flag)
 {
-
-  _log(id_connect_irq_ping_pong_port, id, f->f, f->samp_format)
-
-    /* ping_pong is only supported on MM_DL */
-    if (id != MM_DL_PORT) {
-      abe_dbg_param |= ERR_API;
-      abe_dbg_error_log(ABE_PARAMETER_ERROR);
-    }
-
-  abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  (abe_port[id]).format = (*f);
-  (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
-  (abe_port[id]).protocol.p.prot_pingpong.buf_addr =
-    dmem_ping_pong_buffer;
-  (abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
-  (abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
-
-  abe_init_ping_pong_buffer(MM_DL_PORT, size, 2, sink);
-
-  if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
-    (abe_port[id]).protocol.p.prot_pingpong.irq_addr =
-      ABE_MCU_IRQSTATUS_RAW;
-
-  if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
-    (abe_port[id]).protocol.p.prot_pingpong.irq_addr =
-      ABE_DSP_IRQSTATUS_RAW;
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the ATC descriptors - disabled */
-  abe_init_atc(id);
-
-  *sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr;
-
-  return 0;
+	_log(id_connect_irq_ping_pong_port, id, f->f, f->samp_format);
+	/* ping_pong is only supported on MM_DL */
+	if (id != MM_DL_PORT) {
+		abe_dbg_param |= ERR_API;
+		abe_dbg_error_log(ABE_PARAMETER_ERROR);
+	}
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_addr =
+		dmem_ping_pong_buffer;
+	(abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
+	(abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
+	abe_init_ping_pong_buffer(MM_DL_PORT, size, 2, sink);
+	if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
+		(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
+			ABE_MCU_IRQSTATUS_RAW;
+	if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
+		(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
+			ABE_DSP_IRQSTATUS_RAW;
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+	*sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_irq_ping_pong_port);
-
 /**
  * abe_connect_serial_port()
  * @id: port name
@@ -1134,42 +964,31 @@ EXPORT_SYMBOL(abe_connect_irq_ping_pong_port);
  * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
  * abe_write_port API.
  */
-abehal_status
-abe_connect_serial_port(u32 id, abe_data_format_t * f, u32 mcbsp_id)
+abehal_status abe_connect_serial_port(u32 id, abe_data_format_t *f,
+				      u32 mcbsp_id)
 {
-  u32 UC_NULL[] = { 0 };
-  u32 OPP;
-  abe_hw_config_init_t CONFIG;
-
-  _log(id_connect_serial_port, id, f->samp_format, mcbsp_id)
-
-    abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  (abe_port[id]).format = (*f);
-
-  (abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT;
-
-  /* McBSP peripheral connected to ATC */
-  (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id * ATC_SIZE;
-
-  /* check the iteration of ATC */
-  abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
-
-  (abe_port[id]).protocol.p.prot_serial.iter =
-    abe_dma_port_iter_factor(f);
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the ATC descriptors - disabled */
-  abe_init_atc(id);
-  return 0;
+	u32 UC_NULL[] = { 0 };
+	u32 OPP;
+	abe_hw_config_init_t CONFIG;
+	_log(id_connect_serial_port, id, f->samp_format, mcbsp_id);
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT;
+	/* McBSP peripheral connected to ATC */
+	(abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+	/* check the iteration of ATC */
+	abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
+	(abe_port[id]).protocol.p.prot_serial.iter =
+		abe_dma_port_iter_factor(f);
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_serial_port);
-
 /**
  * abe_connect_slimbus_port
  * @id: port name
@@ -1180,48 +999,37 @@ EXPORT_SYMBOL(abe_connect_serial_port);
  * enables the data echanges between 1/2 SB and an ATC buffers in
  * DMEM.
  */
-abehal_status
-abe_connect_slimbus_port(u32 id, abe_data_format_t * f,
-			 u32 sb_port1, u32 sb_port2)
+abehal_status abe_connect_slimbus_port(u32 id, abe_data_format_t *f,
+				       u32 sb_port1, u32 sb_port2)
 {
-  u32 UC_NULL[] = { 0 };
-  u32 OPP;
-  abe_hw_config_init_t CONFIG;
-  u32 iter;
-
-  _log(id_connect_slimbus_port, id, f->samp_format, sb_port2)
-
-    abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  (abe_port[id]).format = (*f);
-  (abe_port[id]).protocol.protocol_switch = SLIMBUS_PORT_PROT;
-
-  /* SB1 peripheral connected to ATC */
-  (abe_port[id]).protocol.p.prot_slimbus.desc_addr1 = sb_port1 * ATC_SIZE;
-
-  /* SB2 peripheral connected to ATC */
-  (abe_port[id]).protocol.p.prot_slimbus.desc_addr2 = sb_port2 * ATC_SIZE;
-
-  /* check the iteration of ATC */
-  abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
-  iter = CONFIG.SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD;
-
-  /* SLIMBUS iter should be 1 */
-  (abe_port[id]).protocol.p.prot_serial.iter = iter;
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the ATC descriptors - disabled */
-  abe_init_atc(id);
-
-  return 0;
+	u32 UC_NULL[] = {
+		0
+	};
+	u32 OPP;
+	abe_hw_config_init_t CONFIG;
+	u32 iter;
+	_log(id_connect_slimbus_port, id, f->samp_format, sb_port2);
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch = SLIMBUS_PORT_PROT;
+	/* SB1 peripheral connected to ATC */
+	(abe_port[id]).protocol.p.prot_slimbus.desc_addr1 = sb_port1*ATC_SIZE;
+	/* SB2 peripheral connected to ATC */
+	(abe_port[id]).protocol.p.prot_slimbus.desc_addr2 = sb_port2*ATC_SIZE;
+	/* check the iteration of ATC */
+	abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
+	iter = CONFIG.SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD;
+	/* SLIMBUS iter should be 1 */
+	(abe_port[id]).protocol.p.prot_serial.iter = iter;
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_slimbus_port);
-
 /**
  * abe_connect_tdm_port
  * @id: port name
@@ -1232,44 +1040,35 @@ EXPORT_SYMBOL(abe_connect_slimbus_port);
  * enables the data echanges between TDM McBSP ATC buffers in
  * DMEM and 1/2 SMEM buffers
  */
-abehal_status abe_connect_tdm_port(u32 id, abe_data_format_t * f, u32 mcbsp_id)
+abehal_status abe_connect_tdm_port(u32 id, abe_data_format_t *f, u32 mcbsp_id)
 {
-  u32 UC_NULL[] = { 0 };
-  u32 OPP;
-  abe_hw_config_init_t CONFIG;
-  u32 iter;
-
-  _log(id_connect_tdm_port, id, f->samp_format, mcbsp_id)
-
-    abe_port[id] = ((abe_port_t *) abe_port_init)[id];
-  (abe_port[id]).format = (*f);
-  (abe_port[id]).protocol.protocol_switch = TDM_SERIAL_PORT_PROT;
-  /* McBSP peripheral connected to ATC */
-  (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id * ATC_SIZE;
-
-  /* check the iteration of ATC */
-  abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
-  if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
-    iter = CONFIG.MCBSP_THRSH1_REG_REG__RTHRESHOLD;
-  else
-    iter = CONFIG.MCBSP_THRSH2_REG_REG__XTHRESHOLD;
-  /* McBSP iter should be 1 */
-  (abe_port[id]).protocol.p.prot_serial.iter = iter;
-
-  abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
-
-  /* load the micro-task parameters */
-  abe_init_io_tasks(id, &((abe_port[id]).format),
-		    &((abe_port[id]).protocol));
-
-  /* load the ATC descriptors - disabled */
-  abe_init_atc(id);
-
-  return 0;
+	u32 UC_NULL[] = { 0 };
+	u32 OPP;
+	abe_hw_config_init_t CONFIG;
+	u32 iter;
+	_log(id_connect_tdm_port, id, f->samp_format, mcbsp_id);
+	abe_port[id] = ((abe_port_t *) abe_port_init)[id];
+	(abe_port[id]).format = (*f);
+	(abe_port[id]).protocol.protocol_switch = TDM_SERIAL_PORT_PROT;
+	/* McBSP peripheral connected to ATC */
+	(abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+	/* check the iteration of ATC */
+	abe_read_hardware_configuration(UC_NULL, &OPP, &CONFIG);
+	if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
+		iter = CONFIG.MCBSP_THRSH1_REG_REG__RTHRESHOLD;
+	else
+		iter = CONFIG.MCBSP_THRSH2_REG_REG__XTHRESHOLD;
+	/* McBSP iter should be 1 */
+	(abe_port[id]).protocol.p.prot_serial.iter = iter;
+	abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
+	/* load the micro-task parameters */
+	abe_init_io_tasks(id, &((abe_port[id]).format),
+			  &((abe_port[id]).protocol));
+	/* load the ATC descriptors - disabled */
+	abe_init_atc(id);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_tdm_port);
-
 /**
  * abe_read_port_address
  * @dma: output pointer to the DMA iteration and data destination pointer
@@ -1278,44 +1077,77 @@ EXPORT_SYMBOL(abe_connect_tdm_port);
  * Depending on the protocol being used, adds the base address offset L3
  * (DMA) or MPU (ARM)
  */
-abehal_status abe_read_port_address(u32 port, abe_dma_t * dma2)
+abehal_status abe_read_port_address(u32 port, abe_dma_t *dma2)
 {
-  abe_dma_t_offset dma1;
-  u32 protocol_switch;
-
-  _log(id_read_port_address, port, 0, 0)
-
-    dma1 = (abe_port[port]).dma;
-  protocol_switch = abe_port[port].protocol.protocol_switch;
-
-  switch (protocol_switch) {
-  case PINGPONG_PORT_PROT:
-    /* return the base address of the buffer in L3 and L4 spaces */
-    (*dma2).data = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
-    (*dma2).l3_dmem =
-      (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
-    (*dma2).l4_dmem =
-      (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L4);
-    break;
-  case DMAREQ_PORT_PROT:
-    /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
-    (*dma2).data = (void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3);
-    (*dma2).l3_dmem =
-      (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
-	       ABE_DMEM_BASE_ADDRESS_L3);
-    (*dma2).l4_dmem =
-      (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
-	       ABE_DMEM_BASE_ADDRESS_L4);
-    break;
-  default:
-    break;
-  }
-  (*dma2).iter = (dma1.iter);
-  return 0;
+	abe_dma_t_offset dma1;
+	u32 protocol_switch;
+	_log(id_read_port_address, port, 0, 0);
+	dma1 = (abe_port[port]).dma;
+	protocol_switch = abe_port[port].protocol.protocol_switch;
+	switch (protocol_switch) {
+	case PINGPONG_PORT_PROT:
+		/* return the base address of the buffer in L3 and L4 spaces */
+		(*dma2).data = (void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l3_dmem =
+			(void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l4_dmem =
+			(void *)(dma1.data + ABE_DMEM_BASE_ADDRESS_L4);
+		break;
+	case DMAREQ_PORT_PROT:
+		/* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
+		(*dma2).data = (void *)(dma1.data + ABE_ATC_BASE_ADDRESS_L3);
+		(*dma2).l3_dmem =
+			(void *)((abe_port[port]).protocol.p.prot_dmareq.
+				 buf_addr + ABE_DMEM_BASE_ADDRESS_L3);
+		(*dma2).l4_dmem =
+			(void *)((abe_port[port]).protocol.p.prot_dmareq.
+				 buf_addr + ABE_DMEM_BASE_ADDRESS_L4);
+		break;
+	default:
+		break;
+	}
+	(*dma2).iter = (dma1.iter);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_port_address);
-
+/*
+ *  ABE_SELECT_DATA_SOURCE
+ *
+ *  Parameter  :
+ *	port id where data are exchanged
+ *	data_cource_id among:
+ *      SRC_DL1_MIXER_OUTPUT (DL1_M_labelID)
+ *      SRC_SDT_MIXER_OUTPUT (SDT_M_labelID)
+ *      SRC_DL1_GAIN_OUTPUT (DL1_GAIN_out_labelID)
+ *      SRC_DL1_EQ_OUTPUT (DL1_EQ_labelID)
+ *      SRC_DL2_GAIN_OUTPUT (DL2_GAIN_out_labelID)
+ *      SRC_DL2_EQ_OUTPUT (DL2_EQ_labelID)
+ *      SRC_MM_DL (MM_DL_labelID)
+ *      SRC_TONES_DL  (Tones_labelID)
+ *      SRC_VX_DL (VX_DL_labelID)
+ *      SRC_VX_UL (VX_UL_labelID)
+ *      SRC_MM_UL2 (MM_UL2_labelID)
+ *      SRC_MM_UL (MM_UL_labelID)
+ *
+ *  Operations :
+ *
+ *  Return value :
+ *      None.
+ */
+abehal_status abe_select_data_source(u32 port_id, u32 smem_source)
+{
+	ABE_SIODescriptor desc;
+	u32 sio_desc_address;
+	sio_desc_address = dmem_port_descriptors +
+		(port_id * sizeof(ABE_SIODescriptor));
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+		       sio_desc_address, (u32 *) &desc, sizeof(desc));
+	desc.smem_addr1 = (u16) smem_source;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		       sio_desc_address, (u32 *) &desc, sizeof(desc));
+	return 0;
+}
+EXPORT_SYMBOL(abe_select_data_source);
 /**
  * abe_write_equalizer
  * @id: name of the equalizer
@@ -1323,54 +1155,74 @@ EXPORT_SYMBOL(abe_read_port_address);
  *
  * Load the coefficients in CMEM.
  */
-abehal_status abe_write_equalizer(u32 id, abe_equ_t * param)
+abehal_status abe_write_equalizer(u32 id, abe_equ_t *param)
 {
-  u32 eq_offset, length, *src;
-
-  _log(id_write_equalizer, id, 0, 0)
-
-    switch (id) {
-    default:
-    case EQ1:
-      eq_offset = C_DL1_Coefs_ADDR;
-      break;
-    case EQ2L:
-      eq_offset = C_DL2_L_Coefs_ADDR;
-      break;
-    case EQ2R:
-      eq_offset = C_DL2_R_Coefs_ADDR;
-      break;
-    case EQSDT:
-      eq_offset = C_SDT_Coefs_ADDR;
-      break;
-    case EQMIC:
-      eq_offset = C_98_48_LP_Coefs_ADDR;
-      break;
-    case APS1:
-      eq_offset = C_APS_DL1_coeffs1_ADDR;
-      break;
-    case APS2L:
-      eq_offset = C_APS_DL2_L_coeffs1_ADDR;
-      break;
-    case APS2R:
-      eq_offset = C_APS_DL2_R_coeffs1_ADDR;
-      break;
-    }
-  length = param->equ_length;
-  src = (u32 *) ((param->coef).type1);
-
-  /* translate in bytes */
-  eq_offset <<= 2;
-
-  /* translate in bytes */
-  length <<= 2;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, src, length);
-
-  return 0;
+	u32 eq_offset, length, *src, eq_mem, eq_mem_len;
+	_log(id_write_equalizer, id, 0, 0);
+	switch (id) {
+	default:
+	case EQ1:
+		eq_offset = C_DL1_Coefs_ADDR;
+		eq_mem = S_DL1_M_EQ_data_ADDR;
+		eq_mem_len = S_DL1_M_EQ_data_sizeof;
+		break;
+	case EQ2L:
+		eq_offset = C_DL2_L_Coefs_ADDR;
+		eq_mem = S_DL2_M_LR_EQ_data_ADDR;
+		eq_mem_len = S_DL2_M_LR_EQ_data_sizeof;
+		break;
+	case EQ2R:
+		eq_offset = C_DL2_R_Coefs_ADDR;
+		eq_mem = S_DL2_M_LR_EQ_data_ADDR;
+		eq_mem_len = S_DL2_M_LR_EQ_data_sizeof;
+		break;
+	case EQSDT:
+		eq_offset = C_SDT_Coefs_ADDR;
+		eq_mem = S_SDT_F_data_ADDR;
+		eq_mem_len = S_SDT_F_data_sizeof;
+		break;
+	case EQAMIC:
+		eq_offset = C_96_48_AMIC_Coefs_ADDR;
+		eq_mem = S_AMIC_96_48_data_ADDR;
+		eq_mem_len = S_AMIC_96_48_data_sizeof;
+		break;
+	case EQDMIC:
+		eq_offset = C_96_48_DMIC_Coefs_ADDR;
+		eq_mem = S_DMIC0_96_48_data_ADDR;
+		eq_mem_len = S_DMIC0_96_48_data_sizeof;
+		/* three DMIC are clear at the same time DMIC0 DMIC1 DMIC2 */
+		eq_mem_len *= 3;
+		break;
+	case APS1:
+		eq_offset = C_APS_DL1_coeffs1_ADDR;
+		eq_mem = S_APS_IIRmem1_ADDR;
+		eq_mem_len = S_APS_IIRmem1_sizeof;
+		break;
+	case APS2L:
+		eq_offset = C_APS_DL2_L_coeffs1_ADDR;
+		eq_mem = S_APS_M_IIRmem2_ADDR;
+		eq_mem_len = S_APS_M_IIRmem2_sizeof;
+		break;
+	case APS2R:
+		eq_offset = C_APS_DL2_R_coeffs1_ADDR;
+		eq_mem = S_APS_M_IIRmem2_ADDR;
+		eq_mem_len = S_APS_M_IIRmem2_sizeof;
+		break;
+	}
+	length = param->equ_length;
+	src = (u32 *) ((param->coef).type1);
+	/* translate in bytes */
+	eq_offset <<= 2;
+	/* reset SMEM buffers before the coefficients are loaded */
+	abe_reset_mem(ABE_SMEM, eq_mem << 3, eq_mem_len << 3);
+	/* translate in bytes */
+	length <<= 2;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, eq_offset, src, length);
+	/* reset SMEM buffers after the coefficients are loaded */
+	abe_reset_mem(ABE_SMEM, eq_mem << 3, eq_mem_len << 3);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_write_equalizer);
-
 /**
  * abe_write_asrc
  * @id: name of the port
@@ -1385,216 +1237,171 @@ EXPORT_SYMBOL(abe_write_equalizer);
  */
 abehal_status abe_write_asrc(u32 port, s32 dppm)
 {
-  s32 dtempvalue, adppm, drift_sign, drift_sign_addr, alpha_params_addr;
-  s32 alpha_params[3];
-
-  _log(id_write_asrc, port, dppm, dppm >> 8)
-
-    /*
-     * x = ppm
-     *
-     * - 1000000/x must be multiple of 16
-     * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits.
-     *      then shifted by 2bits
-     * - minusdeltaalpha
-     * - oneminusepsilon = 1-deltaalpha/2.
-     *
-     * ppm = 250
-     * - 1000000/250=4000
-     * - deltaalpha = 4194.3 ~ 4195 => 0x00418c
-     */
-    /* examples for -6250 ppm */
-    /* atempvalue32[1] = -1;  d_driftsign */
-    /* atempvalue32[3] = 0x00066668;  d_deltaalpha */
-    /* atempvalue32[4] = 0xfff99998;  d_minusdeltaalpha */
-    /* atempvalue32[5] = 0x003ccccc;  d_oneminusepsilon */
-    /* example for 100 ppm */
-    /* atempvalue32[1] = 1;* d_driftsign */
-    /* atempvalue32[3] = 0x00001a38;  d_deltaalpha */
-    /* atempvalue32[4] = 0xffffe5c8;  d_minusdeltaalpha */
-    /* atempvalue32[5] = 0x003ccccc;  d_oneminusepsilon */
-    /* compute new value for the ppm */
-    if (dppm >= 0) {
-      /* d_driftsign */
-      drift_sign = 1;
-      adppm = dppm;
-    } else {
-      /* d_driftsign */
-      drift_sign = -1;
-      adppm = (-1 * dppm);
-    }
-  if (dppm == 0) {
-    /* delta_alpha */
-    alpha_params[0] = 0;
-
-    /* minusdelta_alpha */
-    alpha_params[1] = 0;
-
-    /* one_minusepsilon */
-    alpha_params[2] = 0x003ffff0;
-  } else {
-    dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
-
-    /* delta_alpha */
-    alpha_params[0] = dtempvalue << 2;
-
-    /* minusdelta_alpha */
-    alpha_params[1] = (-dtempvalue) << 2;
-
-    /* one_minusepsilon */
-    alpha_params[2] = (0x00100000 - (dtempvalue / 2)) << 2;
-  }
-
-  switch (port) {
-
-    /* asynchronous sample-rate-converter for the uplink voice path */
-  case VX_DL_PORT:
-    drift_sign_addr = D_AsrcVars_DL_VX_ADDR + 1 * sizeof(s32);
-    alpha_params_addr = D_AsrcVars_DL_VX_ADDR + 3 * sizeof(s32);
-    break;
-
-    /* asynchronous sample-rate-converter for the downlink voice path */
-  case VX_UL_PORT:
-    drift_sign_addr = D_AsrcVars_UL_VX_ADDR + 1 * sizeof(s32);
-    alpha_params_addr = D_AsrcVars_UL_VX_ADDR + 3 * sizeof(s32);
-    break;
-
-  default:
-
-    /* asynchronous sample-rate-converter for the multimedia player */
-  case MM_DL_PORT:
-    drift_sign_addr = D_AsrcVars_DL_MM_ADDR + 1 * sizeof(s32);
-    alpha_params_addr = D_AsrcVars_DL_MM_ADDR + 3 * sizeof(s32);
-    break;
-  }
-
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, drift_sign_addr,
-		 (u32 *) & drift_sign, 4);
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, alpha_params_addr,
-		 (u32 *) & alpha_params[0], 12);
-
-  return 0;
+	s32 dtempvalue, adppm, drift_sign, drift_sign_addr, alpha_params_addr;
+	s32 alpha_params[3];
+	_log(id_write_asrc, port, dppm, dppm >> 8);
+	/*
+	 * x = ppm
+	 *
+	 * - 1000000/x must be multiple of 16
+	 * - deltaalpha = round(2^20*x*16/1000000)=round(2^18/5^6*x) on 22 bits.
+	 *      then shifted by 2bits
+	 * - minusdeltaalpha
+	 * - oneminusepsilon = 1-deltaalpha/2.
+	 *
+	 * ppm = 250
+	 * - 1000000/250=4000
+	 * - deltaalpha = 4194.3 ~ 4195 => 0x00418c
+	 */
+	/* examples for -6250 ppm */
+	/* atempvalue32[1] = -1;  d_driftsign */
+	/* atempvalue32[3] = 0x00066668;  d_deltaalpha */
+	/* atempvalue32[4] = 0xfff99998;  d_minusdeltaalpha */
+	/* atempvalue32[5] = 0x003ccccc;  d_oneminusepsilon */
+	/* example for 100 ppm */
+	/* atempvalue32[1] = 1;* d_driftsign */
+	/* atempvalue32[3] = 0x00001a38;  d_deltaalpha */
+	/* atempvalue32[4] = 0xffffe5c8;  d_minusdeltaalpha */
+	/* atempvalue32[5] = 0x003ccccc;  d_oneminusepsilon */
+	/* compute new value for the ppm */
+	if (dppm >= 0) {
+		/* d_driftsign */
+		drift_sign = 1;
+		adppm = dppm;
+	} else {
+		/* d_driftsign */
+		drift_sign = -1;
+		adppm = (-1 * dppm);
+	}
+	if (dppm == 0) {
+		/* delta_alpha */
+		alpha_params[0] = 0;
+		/* minusdelta_alpha */
+		alpha_params[1] = 0;
+		/* one_minusepsilon */
+		alpha_params[2] = 0x003ffff0;
+	} else {
+		dtempvalue = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
+		/* delta_alpha */
+		alpha_params[0] = dtempvalue << 2;
+		/* minusdelta_alpha */
+		alpha_params[1] = (-dtempvalue) << 2;
+		/* one_minusepsilon */
+		alpha_params[2] = (0x00100000 - (dtempvalue / 2)) << 2;
+	}
+	switch (port) {
+		/* asynchronous sample-rate-converter for the uplink voice path */
+	case VX_DL_PORT:
+		drift_sign_addr = D_AsrcVars_DL_VX_ADDR + (1 * sizeof(s32));
+		alpha_params_addr = D_AsrcVars_DL_VX_ADDR + (3 * sizeof(s32));
+		break;
+		/* asynchronous sample-rate-converter for the downlink voice path */
+	case VX_UL_PORT:
+		drift_sign_addr = D_AsrcVars_UL_VX_ADDR + (1 * sizeof(s32));
+		alpha_params_addr = D_AsrcVars_UL_VX_ADDR + (3 * sizeof(s32));
+		break;
+		/* asynchronous sample-rate-converter for the multimedia player */
+	default:
+	case MM_EXT_IN_PORT:
+		drift_sign_addr = D_AsrcVars_MM_EXT_IN_ADDR + (1 * sizeof(s32));
+		alpha_params_addr = D_AsrcVars_MM_EXT_IN_ADDR + (3 * sizeof(s32));
+		break;
+	}
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, drift_sign_addr,
+		       (u32 *) &drift_sign, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, alpha_params_addr,
+		       (u32 *) &alpha_params[0], 12);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_write_asrc);
-
 /**
  * abe_write_aps
  * @id: name of the aps filter
  * @param: table of filter coefficients
  *
- * Load the filters and thresholds coefficients in FW memory. This API
+ * Load the filters and thresholds coefficients in FW memory. This AP
  * can be called when the corresponding APS is not activated. After
  * reloading the firmware the default coefficients corresponds to "no APS
  * activated".
  * Loading all the coefficients value with zero disables the feature.
  */
-abehal_status abe_write_aps(u32 id, abe_aps_t * param)
+abehal_status abe_write_aps(u32 id, abe_aps_t *param)
 {
-  _log(id_write_aps, id, 0, 0)
-    return 0;
+	_log(id_write_aps, id, 0, 0);
+	return 0;
 }
 EXPORT_SYMBOL(abe_write_aps);
-
-int abe_get_gain_index(u32 id, u32 p)
+/**
+ * abe_use_compensated_gain
+ * @on_off:
+ *
+ * Selects the automatic Mixer's gain management
+ * on_off = 1 allows the "abe_write_gain" to adjust the overall
+ * gains of the mixer to be tuned not to create saturation
+ */
+abehal_status abe_use_compensated_gain(u32 on_off)
 {
-	int index;
-
-	switch (id) {
-	default:
-	case GAINS_DMIC1:
-		index = 0;
-		break;
-	case GAINS_DMIC2:
-		index = 2;
-		break;
-	case GAINS_DMIC3:
-		index = 4;
-		break;
-	case GAINS_AMIC:
-		index = 6;
-		break;
-	case GAINS_DL1:
-		index = 8;
-		break;
-	case GAINS_DL2:
-		index = 10;
-		break;
-	case GAINS_SPLIT:
-		index = 12;
-		break;
-	case MIXDL1:
-		index = 14;
-		break;
-	case MIXDL2:
-		index = 18;
-		break;
-	case MIXECHO:
-		index = 22;
-		break;
-	case MIXSDT:
-		index = 24;
-		break;
-	case MIXVXREC:
-		index = 26;
-		break;
-	case MIXAUDUL:
-		index = 30;
-		break;
-	}
-	index += p;
-
-	return(index);
-
+	abe_compensated_mixer_gain = on_off;
+	return 0;
 }
-
+EXPORT_SYMBOL(abe_use_compensated_gain);
 /**
  * abe_mute_gain
- * @id: name of the mixer
- * @p: port corresponding to the above gains
+ * Parameters:
+ *	mixer id
+ *	sub-port id
  *
- * Mute ABE gain
  */
 abehal_status abe_mute_gain(u32 id, u32 p)
 {
-	int index;
-
-	index = abe_get_gain_index(id, p);
-
-	if (abe_gain_table[index].mute == 0) {
-		abe_gain_table[index].mute = 1;
-		abe_read_gain(id, &abe_gain_table[index].gain, p);
-		abe_update_gain(id, MUTE_GAIN, RAMP_5MS, p);
-	} else
-		abe_gain_table[index].mute = 1;
+	u32 lin_g, mixer_offset, mixer_target;
+	abe_gain_offset(id, &mixer_offset);
+	abe_muted_gains_indicator[mixer_offset + p] = 1;
+	/* SMEM word32 address */
+	mixer_target = (S_GTarget1_ADDR << 1);
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	/* new muted gain */
+	lin_g = 0;
+	/* load the S_G_Target SMEM table */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target,
+		       (u32 *) &lin_g, sizeof(lin_g));
 	return 0;
-
 }
 EXPORT_SYMBOL(abe_mute_gain);
-
-
 /**
  * abe_unmute_gain
- * @id: name of the mixer
- * @p: port corresponding to the above gains
+ * Parameters:
+ *	mixer id
+ *	sub-port id
  *
- * UnMute ABE gain
  */
 abehal_status abe_unmute_gain(u32 id, u32 p)
 {
-	int index;
-
-	index = abe_get_gain_index(id, p);
-
-	abe_gain_table[index].mute = 0;
-	abe_update_gain(id, abe_gain_table[index].gain, RAMP_5MS, p);
-
+	u32 mixer_offset, mixer_target, lin_g;
+	abe_gain_offset(id, &mixer_offset);
+	/* SMEM word32 address */
+	mixer_target = (S_GTarget1_ADDR << 1);
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	/* unmute gain */
+	if (abe_compensated_mixer_gain)
+		lin_g = abe_unmuted_compensated_gains[mixer_offset + p];
+	else
+		lin_g = abe_unmuted_desired_gains[mixer_offset + p];
+	abe_muted_gains_indicator[mixer_offset + p] = 0;
+	/* load the S_G_Target SMEM table */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target,
+		       (u32 *) &lin_g, sizeof(lin_g));
 	return 0;
 }
 EXPORT_SYMBOL(abe_unmute_gain);
-
 /**
- * abe_update_gain
+ * abe_write_mixer
  * @id: name of the mixer
  * @param: list of input gains of the mixer
  * @p: list of port corresponding to the above gains
@@ -1605,136 +1412,113 @@ EXPORT_SYMBOL(abe_unmute_gain);
  * in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
-abehal_status abe_update_gain(u32 id, u32 f_g, u32 ramp, u32 p)
-{
-  u32 lin_g, mixer_target, mixer_offset;
-  s32 gain_index;
-  u32 alpha, beta;
-  u32 ramp_index;
-
-  _log(id_write_gain, id, f_g, p)
-
-    gain_index = ((f_g - min_mdb) / 100);
-  gain_index = maximum(gain_index, 0);
-  gain_index = minimum(gain_index, sizeof_db2lin_table);
-
-  lin_g = abe_db2lin_table[gain_index];
-
-  switch (id) {
-  default:
-  case GAINS_DMIC1:
-    mixer_offset = dmic1_gains_offset;
-    break;
-  case GAINS_DMIC2:
-    mixer_offset = dmic2_gains_offset;
-    break;
-  case GAINS_DMIC3:
-    mixer_offset = dmic3_gains_offset;
-    break;
-  case GAINS_AMIC:
-    mixer_offset = amic_gains_offset;
-    break;
-  case GAINS_DL1:
-    mixer_offset = dl1_gains_offset;
-    break;
-  case GAINS_DL2:
-    mixer_offset = dl2_gains_offset;
-    break;
-  case GAINS_SPLIT:
-    mixer_offset = splitters_gains_offset;
-    break;
-
-  case MIXDL1:
-    mixer_offset = mixer_dl1_offset;
-    break;
-  case MIXDL2:
-    mixer_offset = mixer_dl2_offset;
-    break;
-  case MIXECHO:
-    mixer_offset = mixer_echo_offset;
-    break;
-  case MIXSDT:
-    mixer_offset = mixer_sdt_offset;
-    break;
-  case MIXVXREC:
-    mixer_offset = mixer_vxrec_offset;
-    break;
-  case MIXAUDUL:
-    mixer_offset = mixer_audul_offset;
-    break;
-  }
-
-  /* SMEM word32 address */
-  mixer_target = (S_GTarget1_ADDR << 1);
-  mixer_target += mixer_offset;
-  mixer_target += p;
-
-  /* translate coef address in Bytes */
-  mixer_target <<= 2;
-
-  /* load the S_G_Target SMEM table */
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target,
-		 (u32 *) & lin_g, sizeof(lin_g));
-
-  ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
-
-  /* ramp data should be interpolated in the table instead */
-  if (ramp < RAMP_5MS)
-    ramp_index = 8;
-  if ((RAMP_5MS <= ramp) && (ramp < RAMP_50MS))
-    ramp_index = 24;
-  if ((RAMP_50MS <= ramp) && (ramp < RAMP_500MS))
-    ramp_index = 36;
-  if (ramp > RAMP_500MS)
-    ramp_index = 48;
-
-  beta = abe_alpha_iir[ramp_index];
-  alpha = abe_1_alpha_iir[ramp_index];
-
-  /* CMEM word32 address */
-  mixer_target = C_1_Alpha_ADDR;
-
-  /* a pair of gains is updated once in the firmware */
-  mixer_target += (p + mixer_offset) >> 1;
-
-  /* translate coef address in Bytes */
-  mixer_target <<= 2;
-
-  /* load the ramp delay data */
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target,
-		 (u32 *) & alpha, sizeof(alpha));
-
-  /* CMEM word32 address */
-  mixer_target = C_Alpha_ADDR;
-
-  /* a pair of gains is updated once in the firmware */
-  mixer_target += (p + mixer_offset) >> 1;
-
-  /* translate coef address in Bytes */
-  mixer_target <<= 2;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target,
-		 (u32 *) & beta, sizeof(beta));
-
-  return 0;
-}
-EXPORT_SYMBOL(abe_update_gain);
-
-abehal_status abe_write_gain (u32 id, u32 f_g, u32 ramp, u32 p)
+abehal_status abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p)
 {
-	int index;
-
-	index = abe_get_gain_index(id, p);
-
-	if (abe_gain_table[index].mute == 0) {
-		abe_gain_table[index].gain = f_g;
-		abe_update_gain(id, f_g,ramp, p);
-	} else
-		abe_gain_table[index].gain = f_g;
-
+	u32 lin_g, mixer_target, mixer_offset, i, mean_gain, mean_exp;
+	s32 gain_index;
+	u32 alpha, beta;
+	u32 ramp_index;
+	_log(id_write_gain, id, f_g, p);
+	gain_index = ((f_g - min_mdb) / 100);
+	gain_index = maximum(gain_index, 0);
+	gain_index = minimum(gain_index, sizeof_db2lin_table);
+	lin_g = abe_db2lin_table[gain_index];
+	abe_gain_offset(id, &mixer_offset);
+	/* SMEM word32 address */
+	mixer_target = (S_GTarget1_ADDR << 1);
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	abe_muted_gains_indicator[mixer_offset + p] = 0;
+	abe_unmuted_desired_gains[mixer_offset + p] = lin_g;
+	if (abe_compensated_mixer_gain) {
+		switch (id) {
+		case MIXDL1:
+		case MIXDL2:
+		case MIXVXREC:
+		case MIXAUDUL:
+			/* compute the sum of the gain of the mixer */
+			for (lin_g = i = 0; i < 4; i++)
+				lin_g += abe_unmuted_desired_gains[mixer_offset
+								   + i];
+			/* lets avoid a division by 0 */
+			if (lin_g == 0)
+				break;
+			/* translate it in Q16 format for the later division */
+			abe_int_2_float16(lin_g, &mean_gain, &mean_exp);
+			mean_exp = 10 - mean_exp;
+			for (i = 0; i < 4; i++) {
+				/* new gain = desired gain divided by sum of gains */
+				abe_unmuted_compensated_gains[mixer_offset +
+							      i] =
+					(abe_unmuted_desired_gains
+					 [mixer_offset + i]
+					 << 8) / mean_gain;
+				abe_unmuted_compensated_gains[mixer_offset +
+							      i] =
+					(mean_exp >
+					 0) ?
+					abe_unmuted_compensated_gains
+					[mixer_offset + i]
+					<< mean_exp :
+					abe_unmuted_compensated_gains
+					[mixer_offset + i]
+					>> mean_exp;
+			}
+			/* load the whole adpated S_G_Target SMEM MIXER table */
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+				       mixer_target - (p << 2),
+				       abe_unmuted_compensated_gains,
+				       (4 * sizeof(lin_g)));
+			break;
+		default:
+		case GAINS_DMIC1:
+		case GAINS_DMIC2:
+		case GAINS_DMIC3:
+		case GAINS_AMIC:
+		case GAINS_DL1:
+		case GAINS_DL2:
+		case MIXECHO:
+		case MIXSDT:
+			break;
+		}
+	} else {
+		/* load the S_G_Target SMEM table */
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       mixer_target, (u32 *) &lin_g, sizeof(lin_g));
+	}
+	ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
+	/* ramp data should be interpolated in the table instead */
+	ramp_index = 8;
+	if ((RAMP_5MS <= ramp) && (ramp < RAMP_50MS))
+		ramp_index = 24;
+	if ((RAMP_50MS <= ramp) && (ramp < RAMP_500MS))
+		ramp_index = 36;
+	if (ramp > RAMP_500MS)
+		ramp_index = 48;
+	beta = abe_alpha_iir[ramp_index];
+	alpha = abe_1_alpha_iir[ramp_index];
+	/* CMEM word32 address */
+	mixer_target = C_1_Alpha_ADDR;
+	/* a pair of gains is updated once in the firmware */
+	mixer_target += (p + mixer_offset) >> 1;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	/* load the ramp delay data */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target,
+		       (u32 *) &alpha, sizeof(alpha));
+	/* CMEM word32 address */
+	mixer_target = C_Alpha_ADDR;
+	/* a pair of gains is updated once in the firmware */
+	mixer_target += (p + mixer_offset) >> 1;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_CMEM, mixer_target,
+		       (u32 *) &beta, sizeof(beta));
 	return 0;
 }
 EXPORT_SYMBOL(abe_write_gain);
-
 /**
  * abe_write_mixer
  * @id: name of the mixer
@@ -1747,16 +1531,13 @@ EXPORT_SYMBOL(abe_write_gain);
  * gain in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
-abehal_status abe_write_mixer(u32 id, u32 f_g, u32 f_ramp, u32 p)
+abehal_status abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p)
 {
-  _log(id_write_mixer, id, f_ramp, p)
-
-    abe_write_gain(id, f_g, f_ramp, p);
-  return 0;
+	_log(id_write_mixer, id, f_ramp, p);
+	abe_write_gain(id, f_g, f_ramp, p);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_write_mixer);
-
 /**
  * abe_read_gain
  * @id: name of the mixer
@@ -1764,83 +1545,32 @@ EXPORT_SYMBOL(abe_write_mixer);
  * @p: list of port corresponding to the above gains
  *
  */
-abehal_status abe_read_gain(u32 id, u32 * f_g, u32 p)
+abehal_status abe_read_gain(u32 id, u32 *f_g, u32 p)
 {
-  u32 mixer_target, mixer_offset;
-       int i;
-
-  _log(id_read_gain, id, (u32) f_g, p)
-
-    switch (id) {
-    default:
-    case GAINS_DMIC1:
-      mixer_offset = dmic1_gains_offset;
-      break;
-    case GAINS_DMIC2:
-      mixer_offset = dmic2_gains_offset;
-      break;
-    case GAINS_DMIC3:
-      mixer_offset = dmic3_gains_offset;
-      break;
-    case GAINS_AMIC:
-      mixer_offset = amic_gains_offset;
-      break;
-    case GAINS_DL1:
-      mixer_offset = dl1_gains_offset;
-      break;
-    case GAINS_DL2:
-      mixer_offset = dl2_gains_offset;
-      break;
-    case GAINS_SPLIT:
-      mixer_offset = splitters_gains_offset;
-      break;
-
-    case MIXDL1:
-      mixer_offset = mixer_dl1_offset;
-      break;
-    case MIXDL2:
-      mixer_offset = mixer_dl2_offset;
-      break;
-    case MIXECHO:
-      mixer_offset = mixer_echo_offset;
-      break;
-    case MIXSDT:
-      mixer_offset = mixer_sdt_offset;
-      break;
-    case MIXVXREC:
-      mixer_offset = mixer_vxrec_offset;
-      break;
-    case MIXAUDUL:
-      mixer_offset = mixer_audul_offset;
-      break;
-    }
-
-  /* SMEM word32 address */
-  mixer_target = (S_GTarget1_ADDR << 1);
-  mixer_target += mixer_offset;
-  mixer_target += p;
-
-  /* translate coef address in Bytes */
-  mixer_target <<= 2;
-
+	u32 mixer_target, mixer_offset;
+	u32 i;
+	_log(id_read_gain, id, (u32); f_g, p)
+		abe_gain_offset(id, &mixer_offset);
+	/* SMEM word32 address */
+	mixer_target = (S_GTarget1_ADDR << 1);
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
 	/* load the S_G_Target SMEM table */
- 	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_SMEM, mixer_target,
-		 (u32 *) f_g, sizeof(*f_g));
-
-       for (i = 0; i < sizeof_db2lin_table; i++) {
-               if (abe_db2lin_table[i] == *f_g)
-                       goto found;
-       }
-       *f_g = 0;
-       return -1;
-
-found:
-       *f_g = (i * 100) + min_mdb;
-
-       return 0;
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_SMEM, mixer_target,
+		       (u32 *) f_g, sizeof(*f_g));
+	for (i = 0; i < sizeof_db2lin_table; i++) {
+		if (abe_db2lin_table[i] == *f_g)
+			goto found;
+	}
+	*f_g = 0;
+	return -1;
+      found:
+	*f_g = (i * 100) + min_mdb;
+	return 0;
 }
 EXPORT_SYMBOL(abe_read_gain);
-
 /**
  * abe_read_mixer
  * @id: name of the mixer
@@ -1853,16 +1583,13 @@ EXPORT_SYMBOL(abe_read_gain);
  * gain in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
-abehal_status abe_read_mixer(u32 id, u32 * f_g, u32 p)
+abehal_status abe_read_mixer(u32 id, u32 *f_g, u32 p)
 {
-  _log(id_read_mixer, id, 0, p)
-
-    abe_read_gain(id, f_g, p);
-  return 0;
+	_log(id_read_mixer, id, 0, p);
+	abe_read_gain(id, f_g, p);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_mixer);
-
 /**
  * abe_set_router_configuration
  * @Id: name of the router
@@ -1873,8 +1600,8 @@ EXPORT_SYMBOL(abe_read_mixer);
  * and PORT1/2 (2 stereo ports). Each sample will be individually stored in
  * an intermediate table of 10 elements.
  *
- * Example of router table parameter for voice uplink with phoenix microphones 
- * 
+ * Example of router table parameter for voice uplink with phoenix microphones
+ *
  * indexes 0 .. 9 = MM_UL description (digital MICs and MMEXTIN)
  *	DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
  *	MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID,
@@ -1886,45 +1613,15 @@ EXPORT_SYMBOL(abe_read_mixer);
  * indexes 14 .. 15 = RESERVED (NULL)
  *	ZERO_labelID, ZERO_labelID,
  */
-abehal_status abe_set_router_configuration(u32 id, u32 k, u16 * param)
+abehal_status abe_set_router_configuration(u32 id, u32 k, u32 *param)
 {
-
-  _log(id_set_router_configuration, id, (u32) param, (u32) param >> 8)
-
-    abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-		   D_aUplinkRouting_ADDR, (u32 *) param,
-		   D_aUplinkRouting_sizeof);
-
-  return 0;
+	_log(id_set_router_configuration, id, (u32); param, (u32) param >> 8)
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       D_aUplinkRouting_ADDR,
+			       param, D_aUplinkRouting_sizeof);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_set_router_configuration);
-
-/**
- * abe_select_data_source
- * @@@
- */
-abehal_status abe_select_data_source(u32 port_id, u32 smem_source)
-{
-  ABE_SIODescriptor desc;
-  u32 sio_desc_address;
-
-  _log(id_select_data_source, port_id, smem_source, smem_source >> 8)
-
-    sio_desc_address = dmem_port_descriptors + (port_id *
-						sizeof
-						(ABE_SIODescriptor));
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, sio_desc_address,
-		 (u32 *) & desc, sizeof(desc));
-  desc.smem_addr1 = (u16) smem_source;
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
-		 (u32 *) & desc, sizeof(desc));
-
-  return 0;
-}
-
-EXPORT_SYMBOL(abe_select_data_source);
-
 /**
  * ABE_READ_DEBUG_TRACE
  *
@@ -1941,14 +1638,12 @@ EXPORT_SYMBOL(abe_select_data_source);
  * Return value :
  *	None.
  */
-abehal_status abe_read_debug_trace(u32 * data, u32 * n)
+abehal_status abe_read_debug_trace(u32 *data, u32 *n)
 {
-  _log(id_select_data_source, 0, 0, 0)
-    return 0;
+	_log(id_select_data_source, 0, 0, 0);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_read_debug_trace);
-
 /**
  * abe_connect_debug_trace
  * @dma2:pointer to the DMEM trace buffer
@@ -1956,25 +1651,19 @@ EXPORT_SYMBOL(abe_read_debug_trace);
  * returns the address and size of the real-time debug trace buffer,
  * the content of which will vary from one firmware release to an other
  */
-abehal_status abe_connect_debug_trace(abe_dma_t * dma2)
+abehal_status abe_connect_debug_trace(abe_dma_t *dma2)
 {
-
-  _log(id_connect_debug_trace, 0, 0, 0)
-
-    /* return the base address of the ping buffer in L3 and L4 spaces */
-    (*dma2).data =
-    (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3);
-  (*dma2).l3_dmem =
-    (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3);
-  (*dma2).l4_dmem =
-    (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L4);
-  (*dma2).iter = D_DEBUG_FIFO_sizeof;
-
-  return 0;
+	_log(id_connect_debug_trace, 0, 0, 0);
+	/* return the base address of the ping buffer in L3 and L4 spaces */
+	(*dma2).data = (void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3);
+	(*dma2).l3_dmem =
+		(void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L3);
+	(*dma2).l4_dmem =
+		(void *)(D_DEBUG_FIFO_ADDR + ABE_DMEM_BASE_ADDRESS_L4);
+	(*dma2).iter = D_DEBUG_FIFO_sizeof;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_connect_debug_trace);
-
 /**
  * abe_set_debug_trace
  * @debug: debug ID from a list to be defined
@@ -1983,149 +1672,132 @@ EXPORT_SYMBOL(abe_connect_debug_trace);
  */
 abehal_status abe_set_debug_trace(abe_dbg_t debug)
 {
-
-  _log(id_set_debug_trace, 0, 0, 0)
-
-    abe_dbg_mask = debug;
-  return 0;
+	_log(id_set_debug_trace, 0, 0, 0);
+	abe_dbg_mask = debug;
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_set_debug_trace);
-
 /**
  * abe_remote_debugger_interface
  *
  * interpretation of the UART stream from the remote debugger commands.
  * The commands consist in setting break points, loading parameter
  */
-abehal_status abe_remote_debugger_interface(u32 n, u8 * p)
+abehal_status abe_remote_debugger_interface(u32 n, u8 *p)
 {
-
-  _log(id_remote_debugger_interface, n, 0, 0)
-    return 0;
+	_log(id_remote_debugger_interface, n, 0, 0);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_remote_debugger_interface);
-
 /**
  * abe_enable_test_pattern
  *
  */
-
 abehal_status abe_enable_test_pattern(u32 smem_id, u32 on_off)
 {
-  u16 dbg_on, dbg_off, idx_patch, task_patch, addr_patch;
-  u32 patch, task32;
-
-  _log(id_enable_test_pattern, on_off, smem_id, smem_id >> 8)
-
-    switch (smem_id) {
-    case DBG_PATCH_AMIC:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = AMIC_labelID;
-      task_patch = C_ABE_FW_TASK_AMIC_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_DMIC1:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = DMIC1_labelID;
-      task_patch = C_ABE_FW_TASK_DMIC1_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_DMIC2:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = DMIC2_labelID;
-      task_patch = C_ABE_FW_TASK_DMIC2_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_DMIC3:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = DMIC3_labelID;
-      task_patch = C_ABE_FW_TASK_DMIC3_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_VX_REC:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = VX_REC_labelID;
-      task_patch = C_ABE_FW_TASK_VXREC_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_BT_UL:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = BT_UL_labelID;
-      task_patch = C_ABE_FW_TASK_BT_UL_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_MM_DL:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = MM_DL_labelID;
-      task_patch = C_ABE_FW_TASK_MM_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_DL2_EQ:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = DL2_EQ_labelID;
-      task_patch = C_ABE_FW_TASK_DL2_APS_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_VIBRA:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = VIBRA_labelID;
-      task_patch = C_ABE_FW_TASK_VIBRA_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_MM_EXT_IN:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = MM_EXT_IN_labelID;
-      task_patch = C_ABE_FW_TASK_MM_EXT_IN_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_EANC_FBK_Out:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = EANC_FBK_Out_labelID;
-      task_patch = C_ABE_FW_TASK_EANC_FBK_SPLIT;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_MIC4:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = MIC4_labelID;
-      task_patch = C_ABE_FW_TASK_MIC4_SPLIT;
-      idx_patch = 1;
-      break;
-
-    case DBG_PATCH_MM_DL_MIXDL1:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = AMIC_labelID;
-      task_patch = C_ABE_FW_TASK_DL1Mixer;
-      idx_patch = 1;
-      break;
-    case DBG_PATCH_MM_DL_MIXDL2:
-      dbg_on = DBG_48K_PATTERN_labelID;
-      dbg_off = AMIC_labelID;
-      task_patch = C_ABE_FW_TASK_DL2Mixer;
-      idx_patch = 1;
-      break;
-    default:
-      return 0;
-    }
-  patch = (on_off != 0) ? dbg_on : dbg_off;
-
-  /* address is on 16bits boundary */
-  addr_patch = D_tasksList_ADDR + 16 * task_patch + 2 * idx_patch;
-
-  /* read on 32bits words' boundary */
-  abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, addr_patch & (~0x03),
-		 &task32, 4);
-
-  if (addr_patch & 0x03)
-    task32 = (0x0000FFFFL & task32) | (patch << 16);
-  else
-    task32 = (0xFFFF0000L & task32) | (0x0000FFFF & patch);
-
-  abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, addr_patch & (~0x03),
-		 &task32, 4);
-
-  return 0;
+	u16 dbg_on, dbg_off, idx_patch, task_patch, addr_patch;
+	u32 patch, task32;
+	_log(id_enable_test_pattern, on_off, smem_id, smem_id >> 8);
+	switch (smem_id) {
+	case DBG_PATCH_AMIC:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = AMIC_labelID;
+		task_patch = C_ABE_FW_TASK_AMIC_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_DMIC1:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = DMIC1_labelID;
+		task_patch = C_ABE_FW_TASK_DMIC1_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_DMIC2:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = DMIC2_labelID;
+		task_patch = C_ABE_FW_TASK_DMIC2_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_DMIC3:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = DMIC3_labelID;
+		task_patch = C_ABE_FW_TASK_DMIC3_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_VX_REC:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = VX_REC_labelID;
+		task_patch = C_ABE_FW_TASK_VXREC_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_BT_UL:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = BT_UL_labelID;
+		task_patch = C_ABE_FW_TASK_BT_UL_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_MM_DL:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = MM_DL_labelID;
+		task_patch = C_ABE_FW_TASK_MM_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_DL2_EQ:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = DL2_EQ_labelID;
+		task_patch = C_ABE_FW_TASK_DL2_APS_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_VIBRA:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = VIBRA_labelID;
+		task_patch = C_ABE_FW_TASK_VIBRA_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_MM_EXT_IN:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = MM_EXT_IN_labelID;
+		task_patch = C_ABE_FW_TASK_MM_EXT_IN_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_EANC_FBK_Out:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = EANC_FBK_Out_labelID;
+		task_patch = C_ABE_FW_TASK_EANC_FBK_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_MIC4:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = MIC4_labelID;
+		task_patch = C_ABE_FW_TASK_MIC4_SPLIT;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_MM_DL_MIXDL1:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = AMIC_labelID;
+		task_patch = C_ABE_FW_TASK_DL1Mixer;
+		idx_patch = 1;
+		break;
+	case DBG_PATCH_MM_DL_MIXDL2:
+		dbg_on = DBG_48K_PATTERN_labelID;
+		dbg_off = AMIC_labelID;
+		task_patch = C_ABE_FW_TASK_DL2Mixer;
+		idx_patch = 1;
+		break;
+	default:
+		return 0;
+	}
+	patch = (on_off != 0) ? dbg_on : dbg_off;
+	/* address is on 16bits boundary */
+	addr_patch = D_tasksList_ADDR + (16 * task_patch) + (2 * idx_patch);
+	/* read on 32bits words' boundary */
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, addr_patch & (~0x03),
+		       &task32, 4);
+	if (addr_patch & 0x03)
+		task32 = (0x0000FFFFL & task32) | (patch << 16);
+	else
+		task32 = (0xFFFF0000L & task32) | (0x0000FFFF & patch);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, addr_patch & (~0x03),
+		       &task32, 4);
+	return 0;
 }
-
 EXPORT_SYMBOL(abe_enable_test_pattern);
diff --git a/sound/soc/omap/abe/abe_api.h b/sound/soc/omap/abe/abe_api.h
index 381245ff7444..f67f228674b7 100644
--- a/sound/soc/omap/abe/abe_api.h
+++ b/sound/soc/omap/abe/abe_api.h
@@ -18,14 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #ifndef _ABE_API_H_
 #define _ABE_API_H_
-
-#include <linux/io.h>
-
-void  abe_init_mem(void __iomem *iomem);
-
 /**
  * abe_reset_hal - reset the ABE/HAL
  * @rdev: regulator source
@@ -35,8 +29,7 @@ void  abe_init_mem(void __iomem *iomem);
  * default AESS registers.
  * Called after a PRCM cold-start reset of ABE
  */
-abehal_status abe_reset_hal (void);
-
+abehal_status abe_reset_hal(void);
 /**
  * abe_load_fw_param - Load ABE Firmware memories
  * @PMEM: Pointer of Program memory data
@@ -52,8 +45,7 @@ abehal_status abe_reset_hal (void);
  * generator to let execution start, read the version number returned from
  * this execution.
  */
-abehal_status abe_load_fw_param (u32 *FW);
-
+abehal_status abe_load_fw_param(u32 *FW);
 /**
  * abe_load_fw - Load ABE Firmware and initialize memories
  *
@@ -61,15 +53,13 @@ abehal_status abe_load_fw_param (u32 *FW);
  * generator to let execution start, read the version number returned from
  * this execution.
  */
-abehal_status abe_load_fw (void);
-
+abehal_status abe_load_fw(void);
 /**
  * abe_read_hardware_configuration - Return default HW periferals configuration
  * @u: use-case description list (pointer)
  * @o: opp mode (pointer)
  * @hw: pointer to the output HW structure
  *
-
  * Parameter :
  * U : use-case description list (pointer)
  * H : pointer to the output structure
@@ -79,8 +69,8 @@ abehal_status abe_load_fw (void);
  * will be upgraded in FW06
  * return a structure with the HW thresholds compatible with the HAL/FW/AESS_ATC
  */
-abehal_status abe_read_hardware_configuration (u32 *u, u32 *o, abe_hw_config_init_t *hw);
-
+abehal_status abe_read_hardware_configuration(u32 *u, u32 *o,
+					      abe_hw_config_init_t *hw);
 /**
  * abe_irq_processing - Process ABE interrupt
  *
@@ -92,8 +82,7 @@ abehal_status abe_read_hardware_configuration (u32 *u, u32 *o, abe_hw_config_ini
  * the embedded debugger when the firmware stops on programmable break-points,
  * etc …
  */
-abehal_status abe_irq_processing (void);
-
+abehal_status abe_irq_processing(void);
 /**
  * abe_select_main_port - Select stynchronization port for Event generator.
  * @id: audio port name
@@ -101,8 +90,7 @@ abehal_status abe_irq_processing (void);
  * tells the FW which is the reference stream for adjusting
  * the processing on 23/24/25 slots
  */
-abehal_status abe_select_main_port (u32 id);
-
+abehal_status abe_select_main_port(u32 id);
 /**
  * abe_write_event_generator - Select event generator source
  * @e: Event Generation Counter, McPDM, DMIC or default.
@@ -118,8 +106,7 @@ abehal_status abe_select_main_port (u32 id);
  * The ratio is (MCLK/96000)+(1<<1) = 2050
  * (1<<1) in order to have the same speed at 50% and 100% OPP (only 15 MSB bits are used at OPP50%)
  */
-abehal_status abe_write_event_generator (u32 e);
-
+abehal_status abe_write_event_generator(u32 e);
 /**
  * abe_stop_event_generator - Stop event generator source
  *
@@ -132,8 +119,7 @@ abehal_status abe_stop_event_generator(void);
  *
  * returns the expected min OPP for a given use_case list
  */
-abehal_status abe_read_use_case_opp (u32 *u, u32 *o);
-
+abehal_status abe_read_use_case_opp(u32 *u, u32 *o);
 /**
  * abe_set_opp_processing - Set OPP mode for ABE Firmware
  * @opp: OOPP mode
@@ -149,8 +135,7 @@ abehal_status abe_read_use_case_opp (u32 *u, u32 *o);
  * this switch.
  *
  */
-abehal_status abe_set_opp_processing (u32 opp);
-
+abehal_status abe_set_opp_processing(u32 opp);
 /**
  * abe_set_ping_pong_buffer
  * @port: ABE port ID
@@ -159,9 +144,7 @@ abehal_status abe_set_opp_processing (u32 opp);
  * Updates the next ping-pong buffer with "size" bytes copied from the
  * host processor. This API notifies the FW that the data transfer is done.
  */
-abehal_status abe_set_ping_pong_buffer (u32 port, u32 n_bytes);
-
-
+abehal_status abe_set_ping_pong_buffer(u32 port, u32 n_bytes);
 /**
  * abe_read_next_ping_pong_buffer
  * @port: ABE portID
@@ -170,8 +153,7 @@ abehal_status abe_set_ping_pong_buffer (u32 port, u32 n_bytes);
  *
  * Tell the next base address of the next ping_pong Buffer and its size
  */
-abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n);
-
+abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
 /**
  * abe_init_ping_pong_buffer
  * @id: ABE port ID
@@ -182,8 +164,8 @@ abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n);
  *
  * Computes the base address of the ping_pong buffers
  */
-abehal_status abe_init_ping_pong_buffer (u32 id, u32 size_bytes, u32 n_buffers, u32 *p);
-
+abehal_status abe_init_ping_pong_buffer(u32 id, u32 size_bytes, u32 n_buffers,
+					u32 *p);
 /**
  * abe_plug_subroutine
  * @id: returned sequence index after plugging a new subroutine
@@ -193,16 +175,15 @@ abehal_status abe_init_ping_pong_buffer (u32 id, u32 size_bytes, u32 n_buffers,
  *
  * register a list of subroutines for call-back purpose
  */
-abehal_status abe_plug_subroutine (u32 *id, abe_subroutine2 f, u32 n, u32* params);
-
+abehal_status abe_plug_subroutine(u32 *id, abe_subroutine2 f, u32 n,
+				  u32 *params);
 /**
  * abe_set_sequence_time_accuracy
  * @fast: fast counter
  * @slow: slow counter
  *
  */
-abehal_status abe_set_sequence_time_accuracy (u32 fast, u32 slow);
-
+abehal_status abe_set_sequence_time_accuracy(u32 fast, u32 slow);
 /**
  * abe_reset_port
  * @id: ABE port ID
@@ -211,8 +192,7 @@ abehal_status abe_set_sequence_time_accuracy (u32 fast, u32 slow);
  * processing features.
  * Clears the internal AE buffers.
  */
-abehal_status abe_reset_port (u32 id);
-
+abehal_status abe_reset_port(u32 id);
 /**
  * abe_read_remaining_data
  * @id:	ABE port_ID
@@ -220,8 +200,7 @@ abehal_status abe_reset_port (u32 id);
  *
  * computes the remaining amount of data in the buffer.
  */
-abehal_status abe_read_remaining_data (u32 port, u32 *n);
-
+abehal_status abe_read_remaining_data(u32 port, u32 *n);
 /**
  * abe_disable_data_transfer
  * @id: ABE port id
@@ -230,8 +209,7 @@ abehal_status abe_read_remaining_data (u32 port, u32 *n);
  * disable the IO task (@f = 0)
  * clear ATC DMEM buffer, ATC enabled
  */
-abehal_status abe_disable_data_transfer (u32 id);
-
+abehal_status abe_disable_data_transfer(u32 id);
 /**
  * abe_enable_data_transfer
  * @ip: ABE port id
@@ -240,8 +218,7 @@ abehal_status abe_disable_data_transfer (u32 id);
  * reset ATC pointers
  * enable the IO task (@f <> 0)
  */
-abehal_status abe_enable_data_transfer (u32 id);
-
+abehal_status abe_enable_data_transfer(u32 id);
 /**
  * abe_set_dmic_filter
  * @d: DMIC decimation ratio : 16/25/32/40
@@ -251,8 +228,7 @@ abehal_status abe_enable_data_transfer (u32 id);
  * roll-off at 20kHz.
  * The default table is loaded with the DMIC 2.4MHz recommended configuration.
  */
-abehal_status abe_set_dmic_filter (u32 d);
-
+abehal_status abe_set_dmic_filter(u32 d);
 /**
  * abe_connect_cbpr_dmareq_port
  * @id: port name
@@ -264,10 +240,8 @@ abehal_status abe_set_dmic_filter (u32 d);
  * enables the data echange between a DMA and the ABE through the
  *	CBPr registers of AESS.
  */
-
-abehal_status abe_connect_cbpr_dmareq_port (u32 id, abe_data_format_t *f, u32 d,
-				   abe_dma_t *returned_dma_t);
-
+abehal_status abe_connect_cbpr_dmareq_port(u32 id, abe_data_format_t *f, u32 d,
+					   abe_dma_t *returned_dma_t);
 /**
  * abe_connect_dmareq_ping_pong_port
  * @id: port name
@@ -281,9 +255,9 @@ abehal_status abe_connect_cbpr_dmareq_port (u32 id, abe_data_format_t *f, u32 d,
  * the DMEM memory of ABE. On each dma_request activation the DMA will exchange
  * "s" bytes and switch to the "pong" buffer for a new buffer exchange.
  */
-abehal_status abe_connect_dmareq_ping_pong_port (u32 id, abe_data_format_t *f,
-					u32 d, u32 s, abe_dma_t *returned_dma_t);
-
+abehal_status abe_connect_dmareq_ping_pong_port(u32 id, abe_data_format_t *f,
+						u32 d, u32 s,
+						abe_dma_t *returned_dma_t);
 /**
  * abe_connect_irq_ping_pong_port
  * @id: port name
@@ -299,10 +273,9 @@ abehal_status abe_connect_dmareq_ping_pong_port (u32 id, abe_data_format_t *f,
  * "abe_set_ping_pong_buffer" to notify the new amount of samples in the
  * pong buffer.
  */
-abehal_status abe_connect_irq_ping_pong_port (u32 id, abe_data_format_t *f,
-				     u32 subroutine_id, u32 size,
-				     u32 *sink, u32 dsp_mcu_flag);
-
+abehal_status abe_connect_irq_ping_pong_port(u32 id, abe_data_format_t *f,
+					     u32 subroutine_id, u32 size,
+					     u32 *sink, u32 dsp_mcu_flag);
 /**
  * abe_connect_serial_port()
  * @id: port name
@@ -314,8 +287,8 @@ abehal_status abe_connect_irq_ping_pong_port (u32 id, abe_data_format_t *f,
  * voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
  * abe_write_port API.
  */
-abehal_status abe_connect_serial_port (u32 id, abe_data_format_t *f, u32 mcbsp_id);
-
+abehal_status abe_connect_serial_port(u32 id, abe_data_format_t *f,
+				      u32 mcbsp_id);
 /**
  * abe_connect_slimbus_port
  * @id: port name
@@ -326,9 +299,8 @@ abehal_status abe_connect_serial_port (u32 id, abe_data_format_t *f, u32 mcbsp_i
  * enables the data echanges between 1/2 SB and an ATC buffers in
  * DMEM.
  */
-abehal_status abe_connect_slimbus_port (u32 id, abe_data_format_t *f,
-			       u32 sb_port1, u32 sb_port2);
-
+abehal_status abe_connect_slimbus_port(u32 id, abe_data_format_t *f,
+				       u32 sb_port1, u32 sb_port2);
 /**
  * abe_connect_tdm_port
  * @id: port name
@@ -339,8 +311,7 @@ abehal_status abe_connect_slimbus_port (u32 id, abe_data_format_t *f,
  * enables the data echanges between TDM McBSP ATC buffers in
  * DMEM and 1/2 SMEM buffers
  */
-abehal_status abe_connect_tdm_port (u32 id, abe_data_format_t *f, u32 mcbsp_id);
-
+abehal_status abe_connect_tdm_port(u32 id, abe_data_format_t *f, u32 mcbsp_id);
 /**
  * abe_read_port_address
  * @dma: output pointer to the DMA iteration and data destination pointer
@@ -349,8 +320,7 @@ abehal_status abe_connect_tdm_port (u32 id, abe_data_format_t *f, u32 mcbsp_id);
  * Depending on the protocol being used, adds the base address offset L3
  * (DMA) or MPU (ARM)
  */
-abehal_status abe_read_port_address (u32 port, abe_dma_t *dma2);
-
+abehal_status abe_read_port_address(u32 port, abe_dma_t *dma2);
 /**
  * abe_write_equalizer
  * @id: name of the equalizer
@@ -358,8 +328,7 @@ abehal_status abe_read_port_address (u32 port, abe_dma_t *dma2);
  *
  * Load the coefficients in CMEM.
  */
-abehal_status abe_write_equalizer (u32 id, abe_equ_t *param);
-
+abehal_status abe_write_equalizer(u32 id, abe_equ_t *param);
 /**
  * abe_write_asrc
  * @id: name of the port
@@ -372,21 +341,19 @@ abehal_status abe_write_equalizer (u32 id, abe_equ_t *param);
  * or vice versa, there will be click in the output signal. Loading the drift
  * value with zero disables the feature.
  */
-abehal_status abe_write_asrc (u32 port, s32 dppm);
-
+abehal_status abe_write_asrc(u32 port, s32 dppm);
 /**
  * abe_write_aps
  * @id: name of the aps filter
  * @param: table of filter coefficients
  *
- * Load the filters and thresholds coefficients in FW memory. This API
+ * Load the filters and thresholds coefficients in FW memory. This AP
  * can be called when the corresponding APS is not activated. After
  * reloading the firmware the default coefficients corresponds to "no APS
  * activated".
  * Loading all the coefficients value with zero disables the feature.
  */
-abehal_status abe_write_aps (u32 id, abe_aps_t *param);
-
+abehal_status abe_write_aps(u32 id, abe_aps_t *param);
 /**
  * abe_write_mixer
  * @id: name of the mixer
@@ -399,11 +366,10 @@ abehal_status abe_write_aps (u32 id, abe_aps_t *param);
  * in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
+abehal_status abe_write_gain(u32 id, s32 f_g, u32 ramp, u32 p);
+abehal_status abe_use_compensated_gain(u32 on_off);
 abehal_status abe_mute_gain(u32 id, u32 p);
 abehal_status abe_unmute_gain(u32 id, u32 p);
-abehal_status abe_update_gain(u32 id, u32 f_g, u32 ramp, u32 p);
-abehal_status abe_write_gain(u32 id, u32 f_g, u32 ramp, u32 p);
-
 /**
  * abe_write_mixer
  * @id: name of the mixer
@@ -416,8 +382,7 @@ abehal_status abe_write_gain(u32 id, u32 f_g, u32 ramp, u32 p);
  * gain in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
-abehal_status abe_write_mixer (u32 id, u32 f_g, u32 f_ramp, u32 p);
-
+abehal_status abe_write_mixer(u32 id, s32 f_g, u32 f_ramp, u32 p);
 /**
  * abe_read_gain
  * @id: name of the mixer
@@ -425,8 +390,7 @@ abehal_status abe_write_mixer (u32 id, u32 f_g, u32 f_ramp, u32 p);
  * @p: list of port corresponding to the above gains
  *
  */
-abehal_status abe_read_gain (u32 id, u32 *f_g, u32 p);
-
+abehal_status abe_read_gain(u32 id, u32 *f_g, u32 p);
 /**
  * abe_read_mixer
  * @id: name of the mixer
@@ -439,7 +403,7 @@ abehal_status abe_read_gain (u32 id, u32 *f_g, u32 p);
  * gain in mute state". A mixer is disabled with a network reconfiguration
  * corresponding to an OPP value.
  */
-abehal_status abe_read_mixer (u32 id, u32 *f_g, u32 p);
+abehal_status abe_read_mixer(u32 id, u32 *f_g, u32 p);
 /**
  * abe_set_router_configuration
  * @Id: name of the router
@@ -452,14 +416,12 @@ abehal_status abe_read_mixer (u32 id, u32 *f_g, u32 p);
  * route the samples to three directions : REC1 mixer, 2 EANC DMIC source of
  * filtering and MM recording audio path.
  */
-abehal_status abe_set_router_configuration (u32 id, u32 k, u16 *param);
-
+abehal_status abe_set_router_configuration(u32 id, u32 k, u32 *param);
 /**
  * abe_select_data_source
  * @@@
  */
-abehal_status abe_select_data_source (u32 port_id, u32 smem_source);
-
+abehal_status abe_select_data_source(u32 port_id, u32 smem_source);
 /**
  * ABE_READ_DEBUG_TRACE
  *
@@ -476,8 +438,7 @@ abehal_status abe_select_data_source (u32 port_id, u32 smem_source);
  * Return value :
  *	None.
  */
-abehal_status abe_read_debug_trace (u32 *data, u32 *n);
-
+abehal_status abe_read_debug_trace(u32 *data, u32 *n);
 /**
  * abe_connect_debug_trace
  * @dma2:pointer to the DMEM trace buffer
@@ -485,29 +446,24 @@ abehal_status abe_read_debug_trace (u32 *data, u32 *n);
  * returns the address and size of the real-time debug trace buffer,
  * the content of which will vary from one firmware release to an other
  */
-abehal_status abe_connect_debug_trace (abe_dma_t *dma2);
-
+abehal_status abe_connect_debug_trace(abe_dma_t *dma2);
 /**
  * abe_set_debug_trace
  * @debug: debug ID from a list to be defined
  *
  * load a mask which filters the debug trace to dedicated types of data
  */
-abehal_status abe_set_debug_trace (abe_dbg_t debug);
-
+abehal_status abe_set_debug_trace(abe_dbg_t debug);
 /**
  * abe_remote_debugger_interface
  *
  * interpretation of the UART stream from the remote debugger commands.
  * The commands consist in setting break points, loading parameter
  */
-abehal_status abe_remote_debugger_interface (u32 n, u8 *p);
-
+abehal_status abe_remote_debugger_interface(u32 n, u8 *p);
 /**
  * abe_enable_test_pattern
  *
  */
-abehal_status abe_enable_test_pattern (u32 smem_id, u32 on_off);
-
-
+abehal_status abe_enable_test_pattern(u32 smem_id, u32 on_off);
 #endif/* _ABE_API_H_ */
diff --git a/sound/soc/omap/abe/abe_cm_addr.h b/sound/soc/omap/abe/abe_cm_addr.h
index 1096e28ab9a8..9130fa7c1501 100644
--- a/sound/soc/omap/abe/abe_cm_addr.h
+++ b/sound/soc/omap/abe/abe_cm_addr.h
@@ -20,354 +20,268 @@
  */
 #ifndef _ABE_CM_ADDR_H_
 #define _ABE_CM_ADDR_H_
-
-#define init_CM_ADDR                                        0 
-#define init_CM_ADDR_END                                    303 
-#define init_CM_sizeof                                      304 
-
-#define C_Data_LSB_2_ADDR                                   304 
-#define C_Data_LSB_2_ADDR_END                               304 
-#define C_Data_LSB_2_sizeof                                 1 
-
-#define C_1_Alpha_ADDR                                      305 
-#define C_1_Alpha_ADDR_END                                  322 
-#define C_1_Alpha_sizeof                                    18 
-
-#define C_Alpha_ADDR                                        323 
-#define C_Alpha_ADDR_END                                    340 
-#define C_Alpha_sizeof                                      18 
-
-#define C_GainsWRamp_ADDR                                   341 
-#define C_GainsWRamp_ADDR_END                               354 
-#define C_GainsWRamp_sizeof                                 14 
-
-#define C_Gains_DL1M_ADDR                                   355 
-#define C_Gains_DL1M_ADDR_END                               358 
-#define C_Gains_DL1M_sizeof                                 4 
-
-#define C_Gains_DL2M_ADDR                                   359 
-#define C_Gains_DL2M_ADDR_END                               362 
-#define C_Gains_DL2M_sizeof                                 4 
-
-#define C_Gains_EchoM_ADDR                                  363 
-#define C_Gains_EchoM_ADDR_END                              364 
-#define C_Gains_EchoM_sizeof                                2 
-
-#define C_Gains_SDTM_ADDR                                   365 
-#define C_Gains_SDTM_ADDR_END                               366 
-#define C_Gains_SDTM_sizeof                                 2 
-
-#define C_Gains_VxRecM_ADDR                                 367 
-#define C_Gains_VxRecM_ADDR_END                             370 
-#define C_Gains_VxRecM_sizeof                               4 
-
-#define C_Gains_ULM_ADDR                                    371 
-#define C_Gains_ULM_ADDR_END                                374 
-#define C_Gains_ULM_sizeof                                  4 
-
-#define C_Gains_unused_ADDR                                 375 
-#define C_Gains_unused_ADDR_END                             376 
-#define C_Gains_unused_sizeof                               2 
-
-#define C_SDT_Coefs_ADDR                                    377 
-#define C_SDT_Coefs_ADDR_END                                385 
-#define C_SDT_Coefs_sizeof                                  9 
-
-#define C_CoefASRC1_VX_ADDR                                 386 
-#define C_CoefASRC1_VX_ADDR_END                             404 
-#define C_CoefASRC1_VX_sizeof                               19 
-
-#define C_CoefASRC2_VX_ADDR                                 405 
-#define C_CoefASRC2_VX_ADDR_END                             423 
-#define C_CoefASRC2_VX_sizeof                               19 
-
-#define C_CoefASRC3_VX_ADDR                                 424 
-#define C_CoefASRC3_VX_ADDR_END                             442 
-#define C_CoefASRC3_VX_sizeof                               19 
-
-#define C_CoefASRC4_VX_ADDR                                 443 
-#define C_CoefASRC4_VX_ADDR_END                             461 
-#define C_CoefASRC4_VX_sizeof                               19 
-
-#define C_CoefASRC5_VX_ADDR                                 462 
-#define C_CoefASRC5_VX_ADDR_END                             480 
-#define C_CoefASRC5_VX_sizeof                               19 
-
-#define C_CoefASRC6_VX_ADDR                                 481 
-#define C_CoefASRC6_VX_ADDR_END                             499 
-#define C_CoefASRC6_VX_sizeof                               19 
-
-#define C_CoefASRC7_VX_ADDR                                 500 
-#define C_CoefASRC7_VX_ADDR_END                             518 
-#define C_CoefASRC7_VX_sizeof                               19 
-
-#define C_CoefASRC8_VX_ADDR                                 519 
-#define C_CoefASRC8_VX_ADDR_END                             537 
-#define C_CoefASRC8_VX_sizeof                               19 
-
-#define C_CoefASRC9_VX_ADDR                                 538 
-#define C_CoefASRC9_VX_ADDR_END                             556 
-#define C_CoefASRC9_VX_sizeof                               19 
-
-#define C_CoefASRC10_VX_ADDR                                557 
-#define C_CoefASRC10_VX_ADDR_END                            575 
-#define C_CoefASRC10_VX_sizeof                              19 
-
-#define C_CoefASRC11_VX_ADDR                                576 
-#define C_CoefASRC11_VX_ADDR_END                            594 
-#define C_CoefASRC11_VX_sizeof                              19 
-
-#define C_CoefASRC12_VX_ADDR                                595 
-#define C_CoefASRC12_VX_ADDR_END                            613 
-#define C_CoefASRC12_VX_sizeof                              19 
-
-#define C_CoefASRC13_VX_ADDR                                614 
-#define C_CoefASRC13_VX_ADDR_END                            632 
-#define C_CoefASRC13_VX_sizeof                              19 
-
-#define C_CoefASRC14_VX_ADDR                                633 
-#define C_CoefASRC14_VX_ADDR_END                            651 
-#define C_CoefASRC14_VX_sizeof                              19 
-
-#define C_CoefASRC15_VX_ADDR                                652 
-#define C_CoefASRC15_VX_ADDR_END                            670 
-#define C_CoefASRC15_VX_sizeof                              19 
-
-#define C_CoefASRC16_VX_ADDR                                671 
-#define C_CoefASRC16_VX_ADDR_END                            689 
-#define C_CoefASRC16_VX_sizeof                              19 
-
-#define C_AlphaCurrent_UL_VX_ADDR                           690 
-#define C_AlphaCurrent_UL_VX_ADDR_END                       690 
-#define C_AlphaCurrent_UL_VX_sizeof                         1 
-
-#define C_BetaCurrent_UL_VX_ADDR                            691 
-#define C_BetaCurrent_UL_VX_ADDR_END                        691 
-#define C_BetaCurrent_UL_VX_sizeof                          1 
-
-#define C_AlphaCurrent_DL_VX_ADDR                           692 
-#define C_AlphaCurrent_DL_VX_ADDR_END                       692 
-#define C_AlphaCurrent_DL_VX_sizeof                         1 
-
-#define C_BetaCurrent_DL_VX_ADDR                            693 
-#define C_BetaCurrent_DL_VX_ADDR_END                        693 
-#define C_BetaCurrent_DL_VX_sizeof                          1 
-
-#define C_CoefASRC1_DL_MM_ADDR                              694 
-#define C_CoefASRC1_DL_MM_ADDR_END                          711 
-#define C_CoefASRC1_DL_MM_sizeof                            18 
-
-#define C_CoefASRC2_DL_MM_ADDR                              712 
-#define C_CoefASRC2_DL_MM_ADDR_END                          729 
-#define C_CoefASRC2_DL_MM_sizeof                            18 
-
-#define C_CoefASRC3_DL_MM_ADDR                              730 
-#define C_CoefASRC3_DL_MM_ADDR_END                          747 
-#define C_CoefASRC3_DL_MM_sizeof                            18 
-
-#define C_CoefASRC4_DL_MM_ADDR                              748 
-#define C_CoefASRC4_DL_MM_ADDR_END                          765 
-#define C_CoefASRC4_DL_MM_sizeof                            18 
-
-#define C_CoefASRC5_DL_MM_ADDR                              766 
-#define C_CoefASRC5_DL_MM_ADDR_END                          783 
-#define C_CoefASRC5_DL_MM_sizeof                            18 
-
-#define C_CoefASRC6_DL_MM_ADDR                              784 
-#define C_CoefASRC6_DL_MM_ADDR_END                          801 
-#define C_CoefASRC6_DL_MM_sizeof                            18 
-
-#define C_CoefASRC7_DL_MM_ADDR                              802 
-#define C_CoefASRC7_DL_MM_ADDR_END                          819 
-#define C_CoefASRC7_DL_MM_sizeof                            18 
-
-#define C_CoefASRC8_DL_MM_ADDR                              820 
-#define C_CoefASRC8_DL_MM_ADDR_END                          837 
-#define C_CoefASRC8_DL_MM_sizeof                            18 
-
-#define C_CoefASRC9_DL_MM_ADDR                              838 
-#define C_CoefASRC9_DL_MM_ADDR_END                          855 
-#define C_CoefASRC9_DL_MM_sizeof                            18 
-
-#define C_CoefASRC10_DL_MM_ADDR                             856 
-#define C_CoefASRC10_DL_MM_ADDR_END                         873 
-#define C_CoefASRC10_DL_MM_sizeof                           18 
-
-#define C_CoefASRC11_DL_MM_ADDR                             874 
-#define C_CoefASRC11_DL_MM_ADDR_END                         891 
-#define C_CoefASRC11_DL_MM_sizeof                           18 
-
-#define C_CoefASRC12_DL_MM_ADDR                             892 
-#define C_CoefASRC12_DL_MM_ADDR_END                         909 
-#define C_CoefASRC12_DL_MM_sizeof                           18 
-
-#define C_CoefASRC13_DL_MM_ADDR                             910 
-#define C_CoefASRC13_DL_MM_ADDR_END                         927 
-#define C_CoefASRC13_DL_MM_sizeof                           18 
-
-#define C_CoefASRC14_DL_MM_ADDR                             928 
-#define C_CoefASRC14_DL_MM_ADDR_END                         945 
-#define C_CoefASRC14_DL_MM_sizeof                           18 
-
-#define C_CoefASRC15_DL_MM_ADDR                             946 
-#define C_CoefASRC15_DL_MM_ADDR_END                         963 
-#define C_CoefASRC15_DL_MM_sizeof                           18 
-
-#define C_CoefASRC16_DL_MM_ADDR                             964 
-#define C_CoefASRC16_DL_MM_ADDR_END                         981 
-#define C_CoefASRC16_DL_MM_sizeof                           18 
-
-#define C_AlphaCurrent_DL_MM_ADDR                           982 
-#define C_AlphaCurrent_DL_MM_ADDR_END                       982 
-#define C_AlphaCurrent_DL_MM_sizeof                         1 
-
-#define C_BetaCurrent_DL_MM_ADDR                            983 
-#define C_BetaCurrent_DL_MM_ADDR_END                        983 
-#define C_BetaCurrent_DL_MM_sizeof                          1 
-
-#define C_DL2_L_Coefs_ADDR                                  984 
-#define C_DL2_L_Coefs_ADDR_END                              1008 
-#define C_DL2_L_Coefs_sizeof                                25 
-
-#define C_DL2_R_Coefs_ADDR                                  1009 
-#define C_DL2_R_Coefs_ADDR_END                              1033 
-#define C_DL2_R_Coefs_sizeof                                25 
-
-#define C_DL1_Coefs_ADDR                                    1034 
-#define C_DL1_Coefs_ADDR_END                                1058 
-#define C_DL1_Coefs_sizeof                                  25 
-
-#define C_SRC_3_LP_Coefs_ADDR                               1059 
-#define C_SRC_3_LP_Coefs_ADDR_END                           1069 
-#define C_SRC_3_LP_Coefs_sizeof                             11 
-
-#define C_SRC_3_LP_GAIN_Coefs_ADDR                          1070 
-#define C_SRC_3_LP_GAIN_Coefs_ADDR_END                      1080 
-#define C_SRC_3_LP_GAIN_Coefs_sizeof                        11 
-
-#define C_SRC_3_HP_Coefs_ADDR                               1081 
-#define C_SRC_3_HP_Coefs_ADDR_END                           1085 
-#define C_SRC_3_HP_Coefs_sizeof                             5 
-
-#define C_SRC_6_LP_Coefs_ADDR                               1086 
-#define C_SRC_6_LP_Coefs_ADDR_END                           1096 
-#define C_SRC_6_LP_Coefs_sizeof                             11 
-
-#define C_SRC_6_LP_GAIN_Coefs_ADDR                          1097 
-#define C_SRC_6_LP_GAIN_Coefs_ADDR_END                      1107 
-#define C_SRC_6_LP_GAIN_Coefs_sizeof                        11 
-
-#define C_SRC_6_HP_Coefs_ADDR                               1108 
-#define C_SRC_6_HP_Coefs_ADDR_END                           1114 
-#define C_SRC_6_HP_Coefs_sizeof                             7 
-
-#define C_EANC_WarpCoeffs_ADDR                              1115 
-#define C_EANC_WarpCoeffs_ADDR_END                          1116 
-#define C_EANC_WarpCoeffs_sizeof                            2 
-
-#define C_EANC_FIRcoeffs_ADDR                               1117 
-#define C_EANC_FIRcoeffs_ADDR_END                           1137 
-#define C_EANC_FIRcoeffs_sizeof                             21 
-
-#define C_EANC_IIRcoeffs_ADDR                               1138 
-#define C_EANC_IIRcoeffs_ADDR_END                           1154 
-#define C_EANC_IIRcoeffs_sizeof                             17 
-
-#define C_EANC_FIRcoeffs_2nd_ADDR                           1155 
-#define C_EANC_FIRcoeffs_2nd_ADDR_END                       1175 
-#define C_EANC_FIRcoeffs_2nd_sizeof                         21 
-
-#define C_EANC_IIRcoeffs_2nd_ADDR                           1176 
-#define C_EANC_IIRcoeffs_2nd_ADDR_END                       1192 
-#define C_EANC_IIRcoeffs_2nd_sizeof                         17 
-
-#define C_APS_DL1_coeffs1_ADDR                              1193 
-#define C_APS_DL1_coeffs1_ADDR_END                          1201 
-#define C_APS_DL1_coeffs1_sizeof                            9 
-
-#define C_APS_DL1_M_coeffs2_ADDR                            1202 
-#define C_APS_DL1_M_coeffs2_ADDR_END                        1204 
-#define C_APS_DL1_M_coeffs2_sizeof                          3 
-
-#define C_APS_DL1_C_coeffs2_ADDR                            1205 
-#define C_APS_DL1_C_coeffs2_ADDR_END                        1207 
-#define C_APS_DL1_C_coeffs2_sizeof                          3 
-
-#define C_APS_DL2_L_coeffs1_ADDR                            1208 
-#define C_APS_DL2_L_coeffs1_ADDR_END                        1216 
-#define C_APS_DL2_L_coeffs1_sizeof                          9 
-
-#define C_APS_DL2_R_coeffs1_ADDR                            1217 
-#define C_APS_DL2_R_coeffs1_ADDR_END                        1225 
-#define C_APS_DL2_R_coeffs1_sizeof                          9 
-
-#define C_APS_DL2_L_M_coeffs2_ADDR                          1226 
-#define C_APS_DL2_L_M_coeffs2_ADDR_END                      1228 
-#define C_APS_DL2_L_M_coeffs2_sizeof                        3 
-
-#define C_APS_DL2_R_M_coeffs2_ADDR                          1229 
-#define C_APS_DL2_R_M_coeffs2_ADDR_END                      1231 
-#define C_APS_DL2_R_M_coeffs2_sizeof                        3 
-
-#define C_APS_DL2_L_C_coeffs2_ADDR                          1232 
-#define C_APS_DL2_L_C_coeffs2_ADDR_END                      1234 
-#define C_APS_DL2_L_C_coeffs2_sizeof                        3 
-
-#define C_APS_DL2_R_C_coeffs2_ADDR                          1235 
-#define C_APS_DL2_R_C_coeffs2_ADDR_END                      1237 
-#define C_APS_DL2_R_C_coeffs2_sizeof                        3 
-
-#define C_AlphaCurrent_ECHO_REF_ADDR                        1238 
-#define C_AlphaCurrent_ECHO_REF_ADDR_END                    1238 
-#define C_AlphaCurrent_ECHO_REF_sizeof                      1 
-
-#define C_BetaCurrent_ECHO_REF_ADDR                         1239 
-#define C_BetaCurrent_ECHO_REF_ADDR_END                     1239 
-#define C_BetaCurrent_ECHO_REF_sizeof                       1 
-
-#define C_APS_DL1_EQ_ADDR                                   1240 
-#define C_APS_DL1_EQ_ADDR_END                               1248 
-#define C_APS_DL1_EQ_sizeof                                 9 
-
-#define C_APS_DL2_L_EQ_ADDR                                 1249 
-#define C_APS_DL2_L_EQ_ADDR_END                             1257 
-#define C_APS_DL2_L_EQ_sizeof                               9 
-
-#define C_APS_DL2_R_EQ_ADDR                                 1258 
-#define C_APS_DL2_R_EQ_ADDR_END                             1266 
-#define C_APS_DL2_R_EQ_sizeof                               9 
-
-#define C_Vibra2_consts_ADDR                                1267 
-#define C_Vibra2_consts_ADDR_END                            1270 
-#define C_Vibra2_consts_sizeof                              4 
-
-#define C_Vibra1_coeffs_ADDR                                1271 
-#define C_Vibra1_coeffs_ADDR_END                            1281 
-#define C_Vibra1_coeffs_sizeof                              11 
-
-#define C_48_96_LP_Coefs_ADDR                               1282 
-#define C_48_96_LP_Coefs_ADDR_END                           1296 
-#define C_48_96_LP_Coefs_sizeof                             15 
-
-#define C_98_48_LP_Coefs_ADDR                               1297 
-#define C_98_48_LP_Coefs_ADDR_END                           1315 
-#define C_98_48_LP_Coefs_sizeof                             19 
-
-#define C_INPUT_SCALE_ADDR                                  1316 
-#define C_INPUT_SCALE_ADDR_END                              1316 
-#define C_INPUT_SCALE_sizeof                                1 
-
-#define C_OUTPUT_SCALE_ADDR                                 1317 
-#define C_OUTPUT_SCALE_ADDR_END                             1317 
-#define C_OUTPUT_SCALE_sizeof                               1 
-
-#define C_MUTE_SCALING_ADDR                                 1318 
-#define C_MUTE_SCALING_ADDR_END                             1318 
-#define C_MUTE_SCALING_sizeof                               1 
-
-#define C_GAINS_0DB_ADDR                                    1319 
-#define C_GAINS_0DB_ADDR_END                                1320 
-#define C_GAINS_0DB_sizeof                                  2 
-
-
-#endif /* _ABECM_ADDR_H_ */
+#define init_CM_ADDR                                        0
+#define init_CM_ADDR_END                                    305
+#define init_CM_sizeof                                      306
+#define C_Data_LSB_2_ADDR                                   306
+#define C_Data_LSB_2_ADDR_END                               306
+#define C_Data_LSB_2_sizeof                                 1
+#define C_1_Alpha_ADDR                                      307
+#define C_1_Alpha_ADDR_END                                  324
+#define C_1_Alpha_sizeof                                    18
+#define C_Alpha_ADDR                                        325
+#define C_Alpha_ADDR_END                                    342
+#define C_Alpha_sizeof                                      18
+#define C_GainsWRamp_ADDR                                   343
+#define C_GainsWRamp_ADDR_END                               356
+#define C_GainsWRamp_sizeof                                 14
+#define C_Gains_DL1M_ADDR                                   357
+#define C_Gains_DL1M_ADDR_END                               360
+#define C_Gains_DL1M_sizeof                                 4
+#define C_Gains_DL2M_ADDR                                   361
+#define C_Gains_DL2M_ADDR_END                               364
+#define C_Gains_DL2M_sizeof                                 4
+#define C_Gains_EchoM_ADDR                                  365
+#define C_Gains_EchoM_ADDR_END                              366
+#define C_Gains_EchoM_sizeof                                2
+#define C_Gains_SDTM_ADDR                                   367
+#define C_Gains_SDTM_ADDR_END                               368
+#define C_Gains_SDTM_sizeof                                 2
+#define C_Gains_VxRecM_ADDR                                 369
+#define C_Gains_VxRecM_ADDR_END                             372
+#define C_Gains_VxRecM_sizeof                               4
+#define C_Gains_ULM_ADDR                                    373
+#define C_Gains_ULM_ADDR_END                                376
+#define C_Gains_ULM_sizeof                                  4
+#define C_Gains_unused_ADDR                                 377
+#define C_Gains_unused_ADDR_END                             378
+#define C_Gains_unused_sizeof                               2
+#define C_SDT_Coefs_ADDR                                    379
+#define C_SDT_Coefs_ADDR_END                                387
+#define C_SDT_Coefs_sizeof                                  9
+#define C_CoefASRC1_VX_ADDR                                 388
+#define C_CoefASRC1_VX_ADDR_END                             406
+#define C_CoefASRC1_VX_sizeof                               19
+#define C_CoefASRC2_VX_ADDR                                 407
+#define C_CoefASRC2_VX_ADDR_END                             425
+#define C_CoefASRC2_VX_sizeof                               19
+#define C_CoefASRC3_VX_ADDR                                 426
+#define C_CoefASRC3_VX_ADDR_END                             444
+#define C_CoefASRC3_VX_sizeof                               19
+#define C_CoefASRC4_VX_ADDR                                 445
+#define C_CoefASRC4_VX_ADDR_END                             463
+#define C_CoefASRC4_VX_sizeof                               19
+#define C_CoefASRC5_VX_ADDR                                 464
+#define C_CoefASRC5_VX_ADDR_END                             482
+#define C_CoefASRC5_VX_sizeof                               19
+#define C_CoefASRC6_VX_ADDR                                 483
+#define C_CoefASRC6_VX_ADDR_END                             501
+#define C_CoefASRC6_VX_sizeof                               19
+#define C_CoefASRC7_VX_ADDR                                 502
+#define C_CoefASRC7_VX_ADDR_END                             520
+#define C_CoefASRC7_VX_sizeof                               19
+#define C_CoefASRC8_VX_ADDR                                 521
+#define C_CoefASRC8_VX_ADDR_END                             539
+#define C_CoefASRC8_VX_sizeof                               19
+#define C_CoefASRC9_VX_ADDR                                 540
+#define C_CoefASRC9_VX_ADDR_END                             558
+#define C_CoefASRC9_VX_sizeof                               19
+#define C_CoefASRC10_VX_ADDR                                559
+#define C_CoefASRC10_VX_ADDR_END                            577
+#define C_CoefASRC10_VX_sizeof                              19
+#define C_CoefASRC11_VX_ADDR                                578
+#define C_CoefASRC11_VX_ADDR_END                            596
+#define C_CoefASRC11_VX_sizeof                              19
+#define C_CoefASRC12_VX_ADDR                                597
+#define C_CoefASRC12_VX_ADDR_END                            615
+#define C_CoefASRC12_VX_sizeof                              19
+#define C_CoefASRC13_VX_ADDR                                616
+#define C_CoefASRC13_VX_ADDR_END                            634
+#define C_CoefASRC13_VX_sizeof                              19
+#define C_CoefASRC14_VX_ADDR                                635
+#define C_CoefASRC14_VX_ADDR_END                            653
+#define C_CoefASRC14_VX_sizeof                              19
+#define C_CoefASRC15_VX_ADDR                                654
+#define C_CoefASRC15_VX_ADDR_END                            672
+#define C_CoefASRC15_VX_sizeof                              19
+#define C_CoefASRC16_VX_ADDR                                673
+#define C_CoefASRC16_VX_ADDR_END                            691
+#define C_CoefASRC16_VX_sizeof                              19
+#define C_AlphaCurrent_UL_VX_ADDR                           692
+#define C_AlphaCurrent_UL_VX_ADDR_END                       692
+#define C_AlphaCurrent_UL_VX_sizeof                         1
+#define C_BetaCurrent_UL_VX_ADDR                            693
+#define C_BetaCurrent_UL_VX_ADDR_END                        693
+#define C_BetaCurrent_UL_VX_sizeof                          1
+#define C_AlphaCurrent_DL_VX_ADDR                           694
+#define C_AlphaCurrent_DL_VX_ADDR_END                       694
+#define C_AlphaCurrent_DL_VX_sizeof                         1
+#define C_BetaCurrent_DL_VX_ADDR                            695
+#define C_BetaCurrent_DL_VX_ADDR_END                        695
+#define C_BetaCurrent_DL_VX_sizeof                          1
+#define C_CoefASRC1_MM_ADDR                                 696
+#define C_CoefASRC1_MM_ADDR_END                             713
+#define C_CoefASRC1_MM_sizeof                               18
+#define C_CoefASRC2_MM_ADDR                                 714
+#define C_CoefASRC2_MM_ADDR_END                             731
+#define C_CoefASRC2_MM_sizeof                               18
+#define C_CoefASRC3_MM_ADDR                                 732
+#define C_CoefASRC3_MM_ADDR_END                             749
+#define C_CoefASRC3_MM_sizeof                               18
+#define C_CoefASRC4_MM_ADDR                                 750
+#define C_CoefASRC4_MM_ADDR_END                             767
+#define C_CoefASRC4_MM_sizeof                               18
+#define C_CoefASRC5_MM_ADDR                                 768
+#define C_CoefASRC5_MM_ADDR_END                             785
+#define C_CoefASRC5_MM_sizeof                               18
+#define C_CoefASRC6_MM_ADDR                                 786
+#define C_CoefASRC6_MM_ADDR_END                             803
+#define C_CoefASRC6_MM_sizeof                               18
+#define C_CoefASRC7_MM_ADDR                                 804
+#define C_CoefASRC7_MM_ADDR_END                             821
+#define C_CoefASRC7_MM_sizeof                               18
+#define C_CoefASRC8_MM_ADDR                                 822
+#define C_CoefASRC8_MM_ADDR_END                             839
+#define C_CoefASRC8_MM_sizeof                               18
+#define C_CoefASRC9_MM_ADDR                                 840
+#define C_CoefASRC9_MM_ADDR_END                             857
+#define C_CoefASRC9_MM_sizeof                               18
+#define C_CoefASRC10_MM_ADDR                                858
+#define C_CoefASRC10_MM_ADDR_END                            875
+#define C_CoefASRC10_MM_sizeof                              18
+#define C_CoefASRC11_MM_ADDR                                876
+#define C_CoefASRC11_MM_ADDR_END                            893
+#define C_CoefASRC11_MM_sizeof                              18
+#define C_CoefASRC12_MM_ADDR                                894
+#define C_CoefASRC12_MM_ADDR_END                            911
+#define C_CoefASRC12_MM_sizeof                              18
+#define C_CoefASRC13_MM_ADDR                                912
+#define C_CoefASRC13_MM_ADDR_END                            929
+#define C_CoefASRC13_MM_sizeof                              18
+#define C_CoefASRC14_MM_ADDR                                930
+#define C_CoefASRC14_MM_ADDR_END                            947
+#define C_CoefASRC14_MM_sizeof                              18
+#define C_CoefASRC15_MM_ADDR                                948
+#define C_CoefASRC15_MM_ADDR_END                            965
+#define C_CoefASRC15_MM_sizeof                              18
+#define C_CoefASRC16_MM_ADDR                                966
+#define C_CoefASRC16_MM_ADDR_END                            983
+#define C_CoefASRC16_MM_sizeof                              18
+#define C_AlphaCurrent_MM_EXT_IN_ADDR                       984
+#define C_AlphaCurrent_MM_EXT_IN_ADDR_END                   984
+#define C_AlphaCurrent_MM_EXT_IN_sizeof                     1
+#define C_BetaCurrent_MM_EXT_IN_ADDR                        985
+#define C_BetaCurrent_MM_EXT_IN_ADDR_END                    985
+#define C_BetaCurrent_MM_EXT_IN_sizeof                      1
+#define C_DL2_L_Coefs_ADDR                                  986
+#define C_DL2_L_Coefs_ADDR_END                              1010
+#define C_DL2_L_Coefs_sizeof                                25
+#define C_DL2_R_Coefs_ADDR                                  1011
+#define C_DL2_R_Coefs_ADDR_END                              1035
+#define C_DL2_R_Coefs_sizeof                                25
+#define C_DL1_Coefs_ADDR                                    1036
+#define C_DL1_Coefs_ADDR_END                                1060
+#define C_DL1_Coefs_sizeof                                  25
+#define C_SRC_3_LP_Coefs_ADDR                               1061
+#define C_SRC_3_LP_Coefs_ADDR_END                           1071
+#define C_SRC_3_LP_Coefs_sizeof                             11
+#define C_SRC_3_LP_GAIN_Coefs_ADDR                          1072
+#define C_SRC_3_LP_GAIN_Coefs_ADDR_END                      1082
+#define C_SRC_3_LP_GAIN_Coefs_sizeof                        11
+#define C_SRC_3_HP_Coefs_ADDR                               1083
+#define C_SRC_3_HP_Coefs_ADDR_END                           1087
+#define C_SRC_3_HP_Coefs_sizeof                             5
+#define C_SRC_6_LP_Coefs_ADDR                               1088
+#define C_SRC_6_LP_Coefs_ADDR_END                           1098
+#define C_SRC_6_LP_Coefs_sizeof                             11
+#define C_SRC_6_LP_GAIN_Coefs_ADDR                          1099
+#define C_SRC_6_LP_GAIN_Coefs_ADDR_END                      1109
+#define C_SRC_6_LP_GAIN_Coefs_sizeof                        11
+#define C_SRC_6_HP_Coefs_ADDR                               1110
+#define C_SRC_6_HP_Coefs_ADDR_END                           1116
+#define C_SRC_6_HP_Coefs_sizeof                             7
+#define C_EANC_WarpCoeffs_ADDR                              1117
+#define C_EANC_WarpCoeffs_ADDR_END                          1118
+#define C_EANC_WarpCoeffs_sizeof                            2
+#define C_EANC_FIRcoeffs_ADDR                               1119
+#define C_EANC_FIRcoeffs_ADDR_END                           1139
+#define C_EANC_FIRcoeffs_sizeof                             21
+#define C_EANC_IIRcoeffs_ADDR                               1140
+#define C_EANC_IIRcoeffs_ADDR_END                           1156
+#define C_EANC_IIRcoeffs_sizeof                             17
+#define C_EANC_FIRcoeffs_2nd_ADDR                           1157
+#define C_EANC_FIRcoeffs_2nd_ADDR_END                       1177
+#define C_EANC_FIRcoeffs_2nd_sizeof                         21
+#define C_EANC_IIRcoeffs_2nd_ADDR                           1178
+#define C_EANC_IIRcoeffs_2nd_ADDR_END                       1194
+#define C_EANC_IIRcoeffs_2nd_sizeof                         17
+#define C_APS_DL1_coeffs1_ADDR                              1195
+#define C_APS_DL1_coeffs1_ADDR_END                          1203
+#define C_APS_DL1_coeffs1_sizeof                            9
+#define C_APS_DL1_M_coeffs2_ADDR                            1204
+#define C_APS_DL1_M_coeffs2_ADDR_END                        1206
+#define C_APS_DL1_M_coeffs2_sizeof                          3
+#define C_APS_DL1_C_coeffs2_ADDR                            1207
+#define C_APS_DL1_C_coeffs2_ADDR_END                        1209
+#define C_APS_DL1_C_coeffs2_sizeof                          3
+#define C_APS_DL2_L_coeffs1_ADDR                            1210
+#define C_APS_DL2_L_coeffs1_ADDR_END                        1218
+#define C_APS_DL2_L_coeffs1_sizeof                          9
+#define C_APS_DL2_R_coeffs1_ADDR                            1219
+#define C_APS_DL2_R_coeffs1_ADDR_END                        1227
+#define C_APS_DL2_R_coeffs1_sizeof                          9
+#define C_APS_DL2_L_M_coeffs2_ADDR                          1228
+#define C_APS_DL2_L_M_coeffs2_ADDR_END                      1230
+#define C_APS_DL2_L_M_coeffs2_sizeof                        3
+#define C_APS_DL2_R_M_coeffs2_ADDR                          1231
+#define C_APS_DL2_R_M_coeffs2_ADDR_END                      1233
+#define C_APS_DL2_R_M_coeffs2_sizeof                        3
+#define C_APS_DL2_L_C_coeffs2_ADDR                          1234
+#define C_APS_DL2_L_C_coeffs2_ADDR_END                      1236
+#define C_APS_DL2_L_C_coeffs2_sizeof                        3
+#define C_APS_DL2_R_C_coeffs2_ADDR                          1237
+#define C_APS_DL2_R_C_coeffs2_ADDR_END                      1239
+#define C_APS_DL2_R_C_coeffs2_sizeof                        3
+#define C_AlphaCurrent_ECHO_REF_ADDR                        1240
+#define C_AlphaCurrent_ECHO_REF_ADDR_END                    1240
+#define C_AlphaCurrent_ECHO_REF_sizeof                      1
+#define C_BetaCurrent_ECHO_REF_ADDR                         1241
+#define C_BetaCurrent_ECHO_REF_ADDR_END                     1241
+#define C_BetaCurrent_ECHO_REF_sizeof                       1
+#define C_APS_DL1_EQ_ADDR                                   1242
+#define C_APS_DL1_EQ_ADDR_END                               1250
+#define C_APS_DL1_EQ_sizeof                                 9
+#define C_APS_DL2_L_EQ_ADDR                                 1251
+#define C_APS_DL2_L_EQ_ADDR_END                             1259
+#define C_APS_DL2_L_EQ_sizeof                               9
+#define C_APS_DL2_R_EQ_ADDR                                 1260
+#define C_APS_DL2_R_EQ_ADDR_END                             1268
+#define C_APS_DL2_R_EQ_sizeof                               9
+#define C_Vibra2_consts_ADDR                                1269
+#define C_Vibra2_consts_ADDR_END                            1272
+#define C_Vibra2_consts_sizeof                              4
+#define C_Vibra1_coeffs_ADDR                                1273
+#define C_Vibra1_coeffs_ADDR_END                            1283
+#define C_Vibra1_coeffs_sizeof                              11
+#define C_48_96_LP_Coefs_ADDR                               1284
+#define C_48_96_LP_Coefs_ADDR_END                           1298
+#define C_48_96_LP_Coefs_sizeof                             15
+#define C_96_48_AMIC_Coefs_ADDR                             1299
+#define C_96_48_AMIC_Coefs_ADDR_END                         1317
+#define C_96_48_AMIC_Coefs_sizeof                           19
+#define C_96_48_DMIC_Coefs_ADDR                             1318
+#define C_96_48_DMIC_Coefs_ADDR_END                         1336
+#define C_96_48_DMIC_Coefs_sizeof                           19
+#define C_INPUT_SCALE_ADDR                                  1337
+#define C_INPUT_SCALE_ADDR_END                              1337
+#define C_INPUT_SCALE_sizeof                                1
+#define C_OUTPUT_SCALE_ADDR                                 1338
+#define C_OUTPUT_SCALE_ADDR_END                             1338
+#define C_OUTPUT_SCALE_sizeof                               1
+#define C_MUTE_SCALING_ADDR                                 1339
+#define C_MUTE_SCALING_ADDR_END                             1339
+#define C_MUTE_SCALING_sizeof                               1
+#define C_GAINS_0DB_ADDR                                    1340
+#define C_GAINS_0DB_ADDR_END                                1341
+#define C_GAINS_0DB_sizeof                                  2
+#endif/* _ABECM_ADDR_H_ */
diff --git a/sound/soc/omap/abe/abe_cof.h b/sound/soc/omap/abe/abe_cof.h
deleted file mode 100644
index 132d0fa2f136..000000000000
--- a/sound/soc/omap/abe/abe_cof.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * ALSA SoC OMAP ABE driver
- *
- * Author:          Laurent Le Faucheur <l-le-faucheur@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-/*
- * ABE CONST AREA FOR DMIC DECIMATION FILTERS
- */
-const abe_int32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 };
-const abe_int32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 };
-const abe_int32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 };
-const abe_int32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { -4119413, -192384, -341428, -348088, -151380, 151380, 348088, 341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 2997698, -3692214, 3406822, -2280190, 1042982 };
-
diff --git a/sound/soc/omap/abe/abe_dat.c b/sound/soc/omap/abe/abe_dat.c
index 9aa2d3b609bd..c029dff4fefb 100644
--- a/sound/soc/omap/abe/abe_dat.c
+++ b/sound/soc/omap/abe/abe_dat.c
@@ -18,469 +18,393 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
 #ifndef abe_dat_c
 #define abe_dat_c
-
-
 const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE] = {
 #include "abe_firmware.c"
 };
-
 u32 abe_firmware_version_number;
-
+/*
+ * automatic gain control of input mixer's gains
+ */
+u32 abe_compensated_mixer_gain;
+u8 abe_muted_gains_indicator[MAX_NBGAIN_CMEM];
+u32 abe_unmuted_desired_gains[MAX_NBGAIN_CMEM];
+u32 abe_unmuted_compensated_gains[MAX_NBGAIN_CMEM];
 /*
  * HAL/FW ports status / format / sampling / protocol(call_back) / features
  *	/ gain / name
  */
-
-abe_port_t abe_port [LAST_PORT_ID]; /* list of ABE ports */
-const abe_port_t abe_port_init [LAST_PORT_ID] = {
-
+u32 pdm_dl1_status;
+u32 pdm_dl2_status;
+u32 pdm_vib_status;
+/*
+ * HAL/FW ports status / format / sampling / protocol(call_back) / features
+ *	/ gain / name
+ */
+abe_port_t abe_port[LAST_PORT_ID];	/* list of ABE ports */
+const abe_port_t abe_port_init[LAST_PORT_ID] = {
 	/* Status Data Format Drift Call-Back Protocol+selector desc_addr;
-	buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features
-	reseted at start Port Name for the debug trace */
+	   buf_addr; buf_size; iter; irq_addr irq_data DMA_T $Features
+	   reseted at start Port Name for the debug trace */
 	/* DMIC */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
-		NODRIFT, NOCALLBACK, 0, 0,
-		{
-			SNK_P, DMIC_PORT_PROT,
-			{{dmem_dmic, dmem_dmic_size, DMIC_ITER}}
-		},
-		{0, 0},
-		{EQMIC, 0}, "DMIC"
-	},
+		    OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
+		    NODRIFT, NOCALLBACK, 0, 0,
+		    {
+		     SNK_P, DMIC_PORT_PROT,
+		     {{dmem_dmic, dmem_dmic_size, DMIC_ITER} }
+		     },
+		    {0, 0},
+		    {EQDMIC, 0}, "DMIC"},
 	/* PDM_UL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_amic, 0,
-		{
-			SNK_P, MCPDMUL_PORT_PROT,
-			{{dmem_amic, dmem_amic_size, MCPDM_UL_ITER}}
-		},
-		{0, 0},
-		{EQMIC, 0},	"PDM_UL"
-	},
-	/* BT_VX_UL*/ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_bt_vx_ul, 0,
-		{
-			SNK_P, SERIAL_PORT_PROT,
-			{{
-				MCBSP1_DMA_TX*ATC_SIZE,
-				dmem_bt_vx_ul,dmem_bt_vx_ul_size,
-				1 * SCHED_LOOP_8kHz
-			}}
-		},
-		{0, 0}, {0},	"BT_VX_UL"
-	},
+		      OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, STEREO_MSB},
+		      NODRIFT, NOCALLBACK, smem_amic, 0,
+		      {
+		       SNK_P, MCPDMUL_PORT_PROT,
+		       {{dmem_amic, dmem_amic_size, MCPDM_UL_ITER} }
+		       },
+		      {0, 0},
+		      {EQAMIC, 0}, "PDM_UL"},
+	/* BT_VX_UL */ {
+			OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, STEREO_MSB},
+			NODRIFT, NOCALLBACK, smem_bt_vx_ul, 0,
+			{
+			 SNK_P, SERIAL_PORT_PROT, {{
+						   (MCBSP1_DMA_TX*ATC_SIZE),
+						   dmem_bt_vx_ul,
+						   dmem_bt_vx_ul_size,
+						   (1*SCHED_LOOP_8kHz)
+						   } }
+			 },
+			{0, 0}, {0}, "BT_VX_UL"},
 	/* MM_UL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_mm_ul, 0,
-		{
-			SRC_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX3*ATC_SIZE,
-				dmem_mm_ul,dmem_mm_ul_size,
-				10 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<3)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__3, 120},
-		{UPROUTE, 0}, "MM_UL"
-	},
+		     OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+		     NODRIFT, NOCALLBACK, smem_mm_ul, 0,
+		     {
+		      SRC_P, DMAREQ_PORT_PROT, {{
+						(CBPr_DMA_RTX3*ATC_SIZE),
+						dmem_mm_ul, dmem_mm_ul_size,
+						(10*SCHED_LOOP_48kHz),
+						ABE_DMASTATUS_RAW, (1 << 3)
+						} }
+		      },
+		     {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120},
+		     {UPROUTE, 0}, "MM_UL"},
 	/* MM_UL2 */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_mm_ul2,0,
-		{
-			SRC_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX4*ATC_SIZE,
-				dmem_mm_ul2,dmem_mm_ul2_size,
-				2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<4)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__4, 24},
-		{UPROUTE, 0}, "MM_UL2"
-	},
+		      OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+		      NODRIFT, NOCALLBACK, smem_mm_ul2, 0,
+		      {
+		       SRC_P, DMAREQ_PORT_PROT, {{
+						 (CBPr_DMA_RTX4*ATC_SIZE),
+						 dmem_mm_ul2, dmem_mm_ul2_size,
+						 (2*SCHED_LOOP_48kHz),
+						 ABE_DMASTATUS_RAW, (1 << 4)
+						 } }
+		       },
+		      {CIRCULAR_BUFFER_PERIPHERAL_R__4, 24},
+		      {UPROUTE, 0}, "MM_UL2"},
 	/* VX_UL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB},
-		NODRIFT, NOCALLBACK, smem_vx_ul, 0,
-		{
-			SRC_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX2*ATC_SIZE,
-				dmem_vx_ul,dmem_vx_ul_size,
-				1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<2)
-			}}
-		}, {
-			CIRCULAR_BUFFER_PERIPHERAL_R__2, 2
-		},
-		{ASRC2, 0}, "VX_UL"
-	},
+		     OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+		     NODRIFT, NOCALLBACK, smem_vx_ul, 0,
+		     {
+		      SRC_P, DMAREQ_PORT_PROT, {{
+						(CBPr_DMA_RTX2*ATC_SIZE),
+						dmem_vx_ul, dmem_vx_ul_size,
+						(1*SCHED_LOOP_8kHz),
+						ABE_DMASTATUS_RAW, (1 << 2)
+						} }
+		      }, {
+			  CIRCULAR_BUFFER_PERIPHERAL_R__2, 2},
+		     {ASRC2, 0}, "VX_UL"},
 	/* MM_DL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_mm_dl_opp100, 0,
-		{
-			SNK_P, PINGPONG_PORT_PROT,
-			{{
-				CBPr_DMA_RTX0*ATC_SIZE,
-				dmem_mm_dl,dmem_mm_dl_size,
-				2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<0)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__0, 24},
-		{ASRC3, 0}, "MM_DL"
-	},
+		     OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+		     NODRIFT, NOCALLBACK, smem_mm_dl, 0,
+		     {
+		      SNK_P, PINGPONG_PORT_PROT, {{
+						  (CBPr_DMA_RTX0*ATC_SIZE),
+						  dmem_mm_dl, dmem_mm_dl_size,
+						  (2*SCHED_LOOP_48kHz),
+						  ABE_DMASTATUS_RAW, (1 << 0)
+						  } }
+		      },
+		     {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24},
+		     {ASRC3, 0}, "MM_DL"},
 	/* VX_DL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB},
-		NODRIFT, NOCALLBACK, smem_vx_dl, 0,
-		{
-			SNK_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX1*ATC_SIZE,
-				dmem_vx_dl,dmem_vx_dl_size,
-				1 * SCHED_LOOP_8kHz, ABE_DMASTATUS_RAW,(1<<1)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__1, 2},
-		{ASRC1, 0}, "VX_DL"
-	},
-	/* TONES_DL*/ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_tones_dl, 0,
-		{
-			SNK_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX5*ATC_SIZE,
-				dmem_tones_dl,dmem_tones_dl_size,
-				2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<5)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__5, 24},
-		{0}, "TONES_DL"
-	},
+		     OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+		     NODRIFT, NOCALLBACK, smem_vx_dl, 0,
+		     {
+		      SNK_P, DMAREQ_PORT_PROT, {{
+						(CBPr_DMA_RTX1*ATC_SIZE),
+						dmem_vx_dl, dmem_vx_dl_size,
+						(1*SCHED_LOOP_8kHz),
+						ABE_DMASTATUS_RAW, (1 << 1)
+						} }
+		      },
+		     {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2},
+		     {ASRC1, 0}, "VX_DL"},
+	/* TONES_DL */ {
+			OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+			NODRIFT, NOCALLBACK, smem_tones_dl, 0,
+			{
+			 SNK_P, DMAREQ_PORT_PROT, {{
+						   (CBPr_DMA_RTX5*ATC_SIZE),
+						   dmem_tones_dl,
+						   dmem_tones_dl_size,
+						   (2*SCHED_LOOP_48kHz),
+						   ABE_DMASTATUS_RAW, (1 << 5)
+						   } }
+			 },
+			{CIRCULAR_BUFFER_PERIPHERAL_R__5, 24},
+			{0}, "TONES_DL"},
 	/* VIB_DL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {24000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_vib, 0,
-		{
-			SNK_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX6*ATC_SIZE,
-				dmem_vib_dl,dmem_vib_dl_size,
-				2 * SCHED_LOOP_24kHz, ABE_DMASTATUS_RAW,(1<<6)
-			}}
-		},
-		{CIRCULAR_BUFFER_PERIPHERAL_R__6, 12},
-		{0}, "VIB_DL"
-	},
-	/* BT_VX_DL*/ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, { 8000, MONO_MSB},
-		NODRIFT, NOCALLBACK, smem_bt_vx_dl, 0,
-		{
-			SRC_P, SERIAL_PORT_PROT,
-			{{
-				MCBSP1_DMA_RX*ATC_SIZE,
-				dmem_bt_vx_dl,dmem_bt_vx_dl_size,
-				1 * SCHED_LOOP_8kHz,
-			}}
-		},
-		{0, 0}, {0}, "BT_VX_DL"
-	},
-
+		      OMAP_ABE_PORT_ACTIVITY_IDLE, {24000, STEREO_MSB},
+		      NODRIFT, NOCALLBACK, smem_vib, 0,
+		      {
+		       SNK_P, DMAREQ_PORT_PROT, {{
+						 (CBPr_DMA_RTX6*ATC_SIZE),
+						 dmem_vib_dl, dmem_vib_dl_size,
+						 (2*SCHED_LOOP_24kHz),
+						 ABE_DMASTATUS_RAW, (1 << 6)
+						 } }
+		       },
+		      {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12},
+		      {0}, "VIB_DL"},
+	/* BT_VX_DL */ {
+			OMAP_ABE_PORT_ACTIVITY_IDLE, {8000, MONO_MSB},
+			NODRIFT, NOCALLBACK, smem_bt_vx_dl, 0,
+			{
+			 SRC_P, SERIAL_PORT_PROT, {{
+						   (MCBSP1_DMA_RX*ATC_SIZE),
+						   dmem_bt_vx_dl,
+						   dmem_bt_vx_dl_size,
+						   (1*SCHED_LOOP_8kHz),
+						   } }
+			 },
+			{0, 0}, {0}, "BT_VX_DL"},
 	/* PDM_DL */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
-		NODRIFT, NOCALLBACK, 0,0,
-		{
-			SRC_P, MCPDMDL_PORT_PROT,
-			{{dmem_mcpdm, dmem_mcpdm_size}}
-		},
-		{0, 0},
-		{MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R,0},
-		"PDM_DL"
-	},
-
-	/* MM_EXT_OUT*/
-	{
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_mm_ext_out, 0,
-		{
-			SRC_P, SERIAL_PORT_PROT,
-			{{
-				MCBSP1_DMA_TX*ATC_SIZE,
-				dmem_mm_ext_out,dmem_mm_ext_out_size,
-				2 * SCHED_LOOP_48kHz
-			}}
-		}, {0, 0}, {0}, "MM_EXT_OUT"
-	},
-
+		      OMAP_ABE_PORT_ACTIVITY_IDLE, {96000, SIX_MSB},
+		      NODRIFT, NOCALLBACK, 0, 0,
+		      {SRC_P, MCPDMDL_PORT_PROT, {{dmem_mcpdm, dmem_mcpdm_size} } },
+		      {0, 0},
+		      {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R, 0},
+		      "PDM_DL"},
+	/* MM_EXT_OUT */
+	{
+	 OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+	 NODRIFT, NOCALLBACK, smem_mm_ext_out, 0,
+	 {
+	  SRC_P, SERIAL_PORT_PROT, {{
+				    (MCBSP1_DMA_TX*ATC_SIZE),
+				    dmem_mm_ext_out, dmem_mm_ext_out_size,
+				    (2*SCHED_LOOP_48kHz)
+				    } }
+	  }, {0, 0}, {0}, "MM_EXT_OUT"},
 	/* MM_EXT_IN */
 	{
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, smem_mm_ext_in, 0,
-		{
-			SNK_P, SERIAL_PORT_PROT,
-			{{
-				MCBSP1_DMA_RX*ATC_SIZE,
-				dmem_mm_ext_in ,dmem_mm_ext_in_size,
-				2 * SCHED_LOOP_48kHz
-			}}
-		},
-		{0, 0}, {0}, "MM_EXT_IN"
-	},
-
+	 OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+	 NODRIFT, NOCALLBACK, smem_mm_ext_in_opp100, 0,
+	 {
+	  SNK_P, SERIAL_PORT_PROT, {{
+				    (MCBSP1_DMA_RX*ATC_SIZE),
+				    dmem_mm_ext_in, dmem_mm_ext_in_size,
+				    (2*SCHED_LOOP_48kHz)
+				    } }
+	  },
+	 {0, 0}, {0}, "MM_EXT_IN"},
 	/* PCM3_TX */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, 0, 0,
-		{
-			SRC_P, TDM_SERIAL_PORT_PROT,
-			{{
-				MCBSP3_DMA_TX*ATC_SIZE,
-				dmem_mm_ext_out,dmem_mm_ext_out_size,
-				2 * SCHED_LOOP_48kHz
-			}}
-		},
-		{0, 0}, {0}, "TDM_OUT"
-	},
-
+		       OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+		       NODRIFT, NOCALLBACK, 0, 0,
+		       {
+			SRC_P, TDM_SERIAL_PORT_PROT, {{
+						      (MCBSP3_DMA_TX *
+						       ATC_SIZE),
+						      dmem_mm_ext_out,
+						      dmem_mm_ext_out_size,
+						      (2*SCHED_LOOP_48kHz)
+						      } }
+			},
+		       {0, 0}, {0}, "TDM_OUT"},
 	/* PCM3_RX */ {
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
-		NODRIFT, NOCALLBACK, 0, 0,
-		{
-			SRC_P, TDM_SERIAL_PORT_PROT,
-			{{
-				MCBSP3_DMA_RX*ATC_SIZE,
-				dmem_mm_ext_in ,dmem_mm_ext_in_size,
-				2 * SCHED_LOOP_48kHz
-			}}
-		},
-		{0, 0}, {0}, "TDM_IN"
-	},
-
-	/* SCHD_DBG_PORT */{
-		OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, MONO_MSB},
-		NODRIFT, NOCALLBACK, 0,0,
-		{
-			SRC_P, DMAREQ_PORT_PROT,
-			{{
-				CBPr_DMA_RTX7*ATC_SIZE,
-				dmem_mm_trace,dmem_mm_trace_size,
-				2 * SCHED_LOOP_48kHz,ABE_DMASTATUS_RAW,(1<<4)
-			}}
-		}, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24},
-		{FEAT_SEQ, FEAT_CTL, FEAT_GAINS, 0}, "SCHD_DBG"
-	},
+		       OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, STEREO_MSB},
+		       NODRIFT, NOCALLBACK, 0, 0,
+		       {
+			SRC_P, TDM_SERIAL_PORT_PROT, {{
+						      (MCBSP3_DMA_RX *
+						       ATC_SIZE),
+						      dmem_mm_ext_in,
+						      dmem_mm_ext_in_size,
+						      (2*SCHED_LOOP_48kHz)
+						      } }
+			},
+		       {0, 0}, {0}, "TDM_IN"},
+	/* SCHD_DBG_PORT */ {
+			     OMAP_ABE_PORT_ACTIVITY_IDLE, {48000, MONO_MSB},
+			     NODRIFT, NOCALLBACK, 0, 0,
+			     {
+			      SRC_P, DMAREQ_PORT_PROT, {{
+							(CBPr_DMA_RTX7 *
+							 ATC_SIZE),
+							dmem_mm_trace,
+							dmem_mm_trace_size,
+							(2*SCHED_LOOP_48kHz),
+							ABE_DMASTATUS_RAW,
+							(1 << 4)
+							} }
+			      }, {CIRCULAR_BUFFER_PERIPHERAL_R__7, 24},
+			     {FEAT_SEQ, FEAT_CTL, FEAT_GAINS, 0}, "SCHD_DBG"},
 };
 /* abe_port_init : smem content for DMIC/PDM must be 0 or Dummy_AM_labelID */
-
 /*
  * Firmware features
  */
-abe_feature_t all_feature [MAXNBFEATURE];
-const abe_feature_t all_feature_init [] = {
+abe_feature_t all_feature[MAXNBFEATURE];
+const abe_feature_t all_feature_init[] = {
 	/* ON_reset OFF READ WRITE STATUS INPUT OUTPUT SLOT/S OPP NAME */
 	/* equalizer downlink path headset + earphone */
 	/* EQ1 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1,
-		c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ1"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1,
+	 c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ1"},
 	/* equalizer downlink path integrated handsfree LEFT */
 	/* EQ2L */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2,
-		c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2L"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2,
+	 c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ2L"},
 	/* equalizer downlink path integrated handsfree RIGHT */
 	/* EQ2R */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ2R"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ2R"},
 	/* equalizer downlink path side-tone */
 	/* EQSDT */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQSDT"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQSDT"},
 	/* SRC+equalizer uplink DMIC 1st pair */
 	/* EQDMIC1 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC1"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC1"},
 	/* SRC+equalizer uplink DMIC 2nd pair */
 	/* EQDMIC2 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC2"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC2"},
 	/* SRC+equalizer uplink DMIC 3rd pair */
 	/* EQDMIC3 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQDMIC3"},
 	/* SRC+equalizer uplink AMIC */
 	/* EQAMIC */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQAMIC"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " EQAMIC"},
 	/* Acoustic protection for headset */
 	/* APS1 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " APS1"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " APS1"},
 	/* acoustic protection high-pass filter for handsfree "Left" */
 	/* APS2 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS2"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " APS2"},
 	/* acoustic protection high-pass filter for handsfree "Right" */
 	/* APS3 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," APS3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " APS3"},
 	/* asynchronous sample-rate-converter for the downlink voice path */
 	/* ASRC1 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXDL"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXDL"},
 	/* asynchronous sample-rate-converter for the uplink voice path */
 	/* ASRC2 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXUL"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_VXUL"},
 	/* asynchronous sample-rate-converter for the multimedia player */
 	/* ASRC3 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," ASRC_MMDL"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " ASRC_MMDL"},
 	/* asynchronous sample-rate-converter for the echo reference */
 	/* ASRC4 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_ECHO"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " ASRC_ECHO"},
 	/* mixer of the headset and earphone path */
 	/* MXDL1 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " MIX_DL1"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " MIX_DL1"},
 	/* mixer of the hands-free path */
 	/* MXDL2 */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," MIX_DL2"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " MIX_DL2"},
 	/* mixer for uplink tone mixer */
 	/* MXAUDUL */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXSAUDUL"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXSAUDUL"},
 	/* mixer for voice recording */
 	/* MXVXREC */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXVXREC"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MXVXREC"},
 	/* mixer for side-tone */
 	/* MXSDT */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_SDT"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_SDT"},
 	/* mixer for echo reference */
 	/* MXECHO */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_ECHO"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " MIX_ECHO"},
 	/* router of the uplink path */
 	/* UPROUTE */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " DLEQ3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, " DLEQ3"},
 	/* all gains */
 	/* GAINS */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"},
 	/* active noise canceller */
 	/* EANC */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP100," DLEQ3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP100, " DLEQ3"},
 	/* sequencing queue of micro tasks */
 	/* SEQ */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"
-	},
-
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"},
 	/* Phoenix control queue through McPDM */
 	/* CTL */
 	{
-		c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
-		0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"
-	},
+	 c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3,
+	 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, " DLEQ3"},
 };
-
-
-
 /*
  * MEMORY MAPPING OF THE DMEM FIFOs
  */
-
 /* DMEM port map */
-u32 abe_map_dmem [LAST_PORT_ID];
-u32 abe_map_dmem_secondary [LAST_PORT_ID];
-
+u32 abe_map_dmem[LAST_PORT_ID];
+u32 abe_map_dmem_secondary[LAST_PORT_ID];
 /* DMEM port buffer sizes */
-u32 abe_map_dmem_size [LAST_PORT_ID];
-
-
+u32 abe_map_dmem_size[LAST_PORT_ID];
 /*
  * AESS/ATC destination and source address translation (except McASPs)
  * from the original 64bits words address
  */
-const u32 abe_atc_dstid [ABE_ATC_DESC_SIZE>>3] = {
+const u32 abe_atc_dstid[ABE_ATC_DESC_SIZE >> 3] = {
 	/* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */
 	0, 0, 12, 0, 1, 0, 2, 0,
 	/* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */
@@ -494,10 +418,10 @@ const u32 abe_atc_dstid [ABE_ATC_DESC_SIZE>>3] = {
 	/* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */
 	0, 0, 0, 0, 0, 0, 0, 0,
 	/* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14
-	CBP_T15 48 .. 63 */
+	   CBP_T15 48 .. 63 */
 	0, 0, 0, 0, 0, 0, 0, 0,
 };
-const u32 abe_atc_srcid [ABE_ATC_DESC_SIZE>>3] = {
+const u32 abe_atc_srcid[ABE_ATC_DESC_SIZE >> 3] = {
 	/* DMA_0 DMIC PDM_DL PDM_UL McB1TX McB1RX McB2TX McB2RX 0 .. 7 */
 	0, 12, 0, 13, 0, 1, 0, 2,
 	/* McB3TX McB3RX SLIMT0 SLIMT1 SLIMT2 SLIMT3 SLIMT4 SLIMT5 8 .. 15 */
@@ -511,455 +435,398 @@ const u32 abe_atc_srcid [ABE_ATC_DESC_SIZE>>3] = {
 	/* CBP_T0 CBP_T1 CBP_T2 CBP_T3 CBP_T4 CBP_T5 CBP_T6 CBP_T7 40 .. 47 */
 	0, 0, 0, 0, 0, 0, 0, 0,
 	/* CBP_T8 CBP_T9 CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14
-	CBP_T15 48 .. 63 */
+	   CBP_T15 48 .. 63 */
 	0, 0, 0, 0, 0, 0, 0, 0,
 };
-
-
 /*
  * preset default routing configurations
  * This is given as implementation EXAMPLES
  * the programmer uses "abe_set_router_configuration" with its own tables
 	*/
-
-const abe_router_t abe_router_ul_table_preset [NBROUTE_CONFIG][NBROUTE_UL] = { {
-
-		/* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */
-
-		/* 0 .. 9 = MM_UL */
-		DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
-		MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID,
-		ZERO_labelID, ZERO_labelID,
-
-		/* 10 .. 11 = MM_UL2 */
-		DMIC3_L_labelID, DMIC3_R_labelID,
-
-		/* 12 .. 13 = VX_UL */
-		AMIC_L_labelID, AMIC_R_labelID,
-
-		/* 14 .. 15 = RESERVED */
-		ZERO_labelID, ZERO_labelID,
-	},
-
-	/* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1*/
-	{
-		/* 0 .. 9 = MM_UL */
-		DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID,
-		DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID,
-		ZERO_labelID, ZERO_labelID,
-
-		/* 10 .. 11 = MM_UL2 */
-		DMIC1_L_labelID, DMIC1_R_labelID,
-
-		/* 12 .. 13 = VX_UL */
-		DMIC1_L_labelID, DMIC1_R_labelID,
-
-		/* 14 .. 15 = RESERVED */
-		ZERO_labelID, ZERO_labelID,
-	},
-
+const abe_router_t abe_router_ul_table_preset[NBROUTE_CONFIG][NBROUTE_UL] = {
+	/* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */
+	{
+	/* 0 .. 9 = MM_UL */
+	 DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+	 MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, AMIC_L_labelID,
+	 AMIC_L_labelID,
+	 ZERO_labelID, ZERO_labelID,
+	/* 10 .. 11 = MM_UL2 */
+	 AMIC_L_labelID, AMIC_L_labelID,
+	/* 12 .. 13 = VX_UL */
+	 AMIC_L_labelID, AMIC_R_labelID,
+	/* 14 .. 15 = RESERVED */
+	 ZERO_labelID, ZERO_labelID,
+	 },
+	/* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1 */
+	{
+	/* 0 .. 9 = MM_UL */
+	 DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID,
+	 DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID,
+	 ZERO_labelID, ZERO_labelID,
+	/* 10 .. 11 = MM_UL2 */
+	 DMIC1_L_labelID, DMIC1_R_labelID,
+	/* 12 .. 13 = VX_UL */
+	 DMIC1_L_labelID, DMIC1_R_labelID,
+	/* 14 .. 15 = RESERVED */
+	 ZERO_labelID, ZERO_labelID,
+	 },
 	/* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */
 	{
-		/* 0 .. 9 = MM_UL */
-		DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
-		DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID,
-		ZERO_labelID, ZERO_labelID,
-
-		/* 10 .. 11 = MM_UL2 */
-		DMIC2_L_labelID, DMIC2_R_labelID,
-
-		/* 12 .. 13 = VX_UL */
-		DMIC2_L_labelID, DMIC2_R_labelID,
-
-		/* 14 .. 15 = RESERVED */
-		ZERO_labelID, ZERO_labelID,
-	},
-
+	/* 0 .. 9 = MM_UL */
+	 DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
+	 DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID,
+	 ZERO_labelID, ZERO_labelID,
+	/* 10 .. 11 = MM_UL2 */
+	 DMIC2_L_labelID, DMIC2_R_labelID,
+	/* 12 .. 13 = VX_UL */
+	 DMIC2_L_labelID, DMIC2_R_labelID,
+	/* 14 .. 15 = RESERVED */
+	 ZERO_labelID, ZERO_labelID,
+	 },
 	/* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */
 	{
-		/* 0 .. 9 = MM_UL */
-		AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
-		DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID,
-		ZERO_labelID, ZERO_labelID,
-
-		/* 10 .. 11 = MM_UL2 */
-		DMIC3_L_labelID, DMIC3_R_labelID,
-
-		/* 12 .. 13 = VX_UL */
-		DMIC3_L_labelID, DMIC3_R_labelID,
-
-		/* 14 .. 15 = RESERVED */
-		ZERO_labelID, ZERO_labelID,
-	},
-
+	/* 0 .. 9 = MM_UL */
+	 AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+	 DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID,
+	 ZERO_labelID, ZERO_labelID,
+	/* 10 .. 11 = MM_UL2 */
+	 DMIC3_L_labelID, DMIC3_R_labelID,
+	/* 12 .. 13 = VX_UL */
+	 DMIC3_L_labelID, DMIC3_R_labelID,
+	/* 14 .. 15 = RESERVED */
+	 ZERO_labelID, ZERO_labelID,
+	 },
 	/* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */
 	{
-		/* 0 .. 9 = MM_UL */
-		BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
-		DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
-		ZERO_labelID, ZERO_labelID,
-
-		/* 10 .. 11 = MM_UL2 */
-		AMIC_L_labelID, AMIC_R_labelID,
-
-		/* 12 .. 13 = VX_UL */
-		BT_UL_L_labelID, BT_UL_R_labelID,
-
-		/* 14 .. 15 = RESERVED */
-		ZERO_labelID, ZERO_labelID,
-	},
+	/* 0 .. 9 = MM_UL */
+	 BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,
+	 DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
+	 ZERO_labelID, ZERO_labelID,
+	/* 10 .. 11 = MM_UL2 */
+	 AMIC_L_labelID, AMIC_R_labelID,
+	/* 12 .. 13 = VX_UL */
+	 BT_UL_L_labelID, BT_UL_R_labelID,
+	/* 14 .. 15 = RESERVED */
+	 ZERO_labelID, ZERO_labelID,
+	 },
 };
-
 /* all default routing configurations */
-abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL];
-
+abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
 /*
  * ABE SUBROUTINES AND SEQUENCES
  */
-
-
 /*
 const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] =
- {{0, 0, 0, 0}, {-1, 0, 0, 0}},
- {{0, 0, 0, 0}, {-1, 0, 0, 0}},
+ {{0, 0, 0, 0}, {-1, 0, 0, 0} },
+ {{0, 0, 0, 0}, {-1, 0, 0, 0} },
 const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1, 0, 0, 0, 0,
  -1, C_CALLBACK1, 0, 0, 0, 0 };
-
 const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] =
  abe_init_atc, 0, 0,
  abe_init_atc, 0, 0,
-
  typedef double (*PtrFun) (double);
 PtrFun pFun;
 pFun = sin;
-y = (* pFun) (x);
-*/ /* mask, { time id param tag1} */
+       y = (* pFun) (x);
+*//* mask, { time id param tag1} */
 const abe_sequence_t seq_null = {
-	NOMASK,
-	{
-		CL_M1,
-		0,
-		{0,0,0,0},
-		0
-	},
-	{
-		CL_M1,
-		0,
-		{0,0,0,0},
-		0
-	},
+	NOMASK, {CL_M1, 0, {0, 0, 0, 0}, 0}, {CL_M1, 0, {0, 0, 0, 0}, 0}
 };
-
 /* table of new subroutines called in the sequence */
-abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE];
-
+abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];
 /* number of parameters per calls */
-u32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE];
-
+u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE];
 /* index of the subroutine */
-u32 abe_subroutine_id [MAXNBSUBROUTINE];
-
+u32 abe_subroutine_id[MAXNBSUBROUTINE];
 /* paramters of the subroutine (if any) */
-u32* abe_all_subroutine_params[MAXNBSUBROUTINE];
+u32 *abe_all_subroutine_params[MAXNBSUBROUTINE];
 u32 abe_subroutine_write_pointer;
-
 /* table of all sequences */
 abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];
 u32 abe_sequence_write_pointer;
-
 /* current number of pending sequences (avoids to look in the table) */
 u32 abe_nb_pending_sequences;
-
 /* pending sequences due to ressource collision */
-u32 abe_pending_sequences [MAXNBSEQUENCE];
-
+u32 abe_pending_sequences[MAXNBSEQUENCE];
 /* mask of unsharable ressources among other sequences */
 u32 abe_global_sequence_mask;
-
 /* table of active sequences */
-abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS];
-
+abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS];
 /* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */
 u32 abe_irq_pingpong_player_id;
-
 /* index of the plugged subroutine doing acoustics protection adaptation */
 u32 abe_irq_aps_adaptation_id;
-
 /* base addresses of the ping pong buffers in bytes addresses */
-u32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS];
-
+u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS];
 /* size of each ping/pong buffers */
 u32 abe_size_pingpong;
-
 /* number of ping/pong buffer being used */
 u32 abe_nb_pingpong;
-
 /* current EVENT */
 u32 abe_current_event_id;
-
 /*
  * ABE CONST AREA FOR PARAMETERS TRANSLATION
  */
-const u32 abe_db2lin_table [sizeof_db2lin_table] = {
-
-	0x00000000, /* SMEM coding of -120 dB */
-	0x00000000, /* SMEM coding of -119 dB */
-	0x00000000, /* SMEM coding of -118 dB */
-	0x00000000, /* SMEM coding of -117 dB */
-	0x00000000, /* SMEM coding of -116 dB */
-	0x00000000, /* SMEM coding of -115 dB */
-	0x00000000, /* SMEM coding of -114 dB */
-	0x00000000, /* SMEM coding of -113 dB */
-	0x00000000, /* SMEM coding of -112 dB */
-	0x00000000, /* SMEM coding of -111 dB */
-	0x00000000, /* SMEM coding of -110 dB */
-	0x00000000, /* SMEM coding of -109 dB */
-	0x00000001, /* SMEM coding of -108 dB */
-	0x00000001, /* SMEM coding of -107 dB */
-	0x00000001, /* SMEM coding of -106 dB */
-	0x00000001, /* SMEM coding of -105 dB */
-	0x00000001, /* SMEM coding of -104 dB */
-	0x00000001, /* SMEM coding of -103 dB */
-	0x00000002, /* SMEM coding of -102 dB */
-	0x00000002, /* SMEM coding of -101 dB */
-	0x00000002, /* SMEM coding of -100 dB */
-	0x00000002, /* SMEM coding of -99 dB */
-	0x00000003, /* SMEM coding of -98 dB */
-	0x00000003, /* SMEM coding of -97 dB */
-	0x00000004, /* SMEM coding of -96 dB */
-	0x00000004, /* SMEM coding of -95 dB */
-	0x00000005, /* SMEM coding of -94 dB */
-	0x00000005, /* SMEM coding of -93 dB */
-	0x00000006, /* SMEM coding of -92 dB */
-	0x00000007, /* SMEM coding of -91 dB */
-	0x00000008, /* SMEM coding of -90 dB */
-	0x00000009, /* SMEM coding of -89 dB */
-	0x0000000A, /* SMEM coding of -88 dB */
-	0x0000000B, /* SMEM coding of -87 dB */
-	0x0000000D, /* SMEM coding of -86 dB */
-	0x0000000E, /* SMEM coding of -85 dB */
-	0x00000010, /* SMEM coding of -84 dB */
-	0x00000012, /* SMEM coding of -83 dB */
-	0x00000014, /* SMEM coding of -82 dB */
-	0x00000017, /* SMEM coding of -81 dB */
-	0x0000001A, /* SMEM coding of -80 dB */
-	0x0000001D, /* SMEM coding of -79 dB */
-	0x00000021, /* SMEM coding of -78 dB */
-	0x00000025, /* SMEM coding of -77 dB */
-	0x00000029, /* SMEM coding of -76 dB */
-	0x0000002E, /* SMEM coding of -75 dB */
-	0x00000034, /* SMEM coding of -74 dB */
-	0x0000003A, /* SMEM coding of -73 dB */
-	0x00000041, /* SMEM coding of -72 dB */
-	0x00000049, /* SMEM coding of -71 dB */
-	0x00000052, /* SMEM coding of -70 dB */
-	0x0000005D, /* SMEM coding of -69 dB */
-	0x00000068, /* SMEM coding of -68 dB */
-	0x00000075, /* SMEM coding of -67 dB */
-	0x00000083, /* SMEM coding of -66 dB */
-	0x00000093, /* SMEM coding of -65 dB */
-	0x000000A5, /* SMEM coding of -64 dB */
-	0x000000B9, /* SMEM coding of -63 dB */
-	0x000000D0, /* SMEM coding of -62 dB */
-	0x000000E9, /* SMEM coding of -61 dB */
-	0x00000106, /* SMEM coding of -60 dB */
-	0x00000126, /* SMEM coding of -59 dB */
-	0x0000014A, /* SMEM coding of -58 dB */
-	0x00000172, /* SMEM coding of -57 dB */
-	0x0000019F, /* SMEM coding of -56 dB */
-	0x000001D2, /* SMEM coding of -55 dB */
-	0x0000020B, /* SMEM coding of -54 dB */
-	0x0000024A, /* SMEM coding of -53 dB */
-	0x00000292, /* SMEM coding of -52 dB */
-	0x000002E2, /* SMEM coding of -51 dB */
-	0x0000033C, /* SMEM coding of -50 dB */
-	0x000003A2, /* SMEM coding of -49 dB */
-	0x00000413, /* SMEM coding of -48 dB */
-	0x00000492, /* SMEM coding of -47 dB */
-	0x00000521, /* SMEM coding of -46 dB */
-	0x000005C2, /* SMEM coding of -45 dB */
-	0x00000676, /* SMEM coding of -44 dB */
-	0x0000073F, /* SMEM coding of -43 dB */
-	0x00000822, /* SMEM coding of -42 dB */
-	0x00000920, /* SMEM coding of -41 dB */
-	0x00000A3D, /* SMEM coding of -40 dB */
-	0x00000B7D, /* SMEM coding of -39 dB */
-	0x00000CE4, /* SMEM coding of -38 dB */
-	0x00000E76, /* SMEM coding of -37 dB */
-	0x0000103A, /* SMEM coding of -36 dB */
-	0x00001235, /* SMEM coding of -35 dB */
-	0x0000146E, /* SMEM coding of -34 dB */
-	0x000016EC, /* SMEM coding of -33 dB */
-	0x000019B8, /* SMEM coding of -32 dB */
-	0x00001CDC, /* SMEM coding of -31 dB */
-	0x00002061, /* SMEM coding of -30 dB */
-	0x00002455, /* SMEM coding of -29 dB */
-	0x000028C4, /* SMEM coding of -28 dB */
-	0x00002DBD, /* SMEM coding of -27 dB */
-	0x00003352, /* SMEM coding of -26 dB */
-	0x00003995, /* SMEM coding of -25 dB */
-	0x0000409C, /* SMEM coding of -24 dB */
-	0x0000487E, /* SMEM coding of -23 dB */
-	0x00005156, /* SMEM coding of -22 dB */
-	0x00005B43, /* SMEM coding of -21 dB */
-	0x00006666, /* SMEM coding of -20 dB */
-	0x000072E5, /* SMEM coding of -19 dB */
-	0x000080E9, /* SMEM coding of -18 dB */
-	0x000090A4, /* SMEM coding of -17 dB */
-	0x0000A24B, /* SMEM coding of -16 dB */
-	0x0000B618, /* SMEM coding of -15 dB */
-	0x0000CC50, /* SMEM coding of -14 dB */
-	0x0000E53E, /* SMEM coding of -13 dB */
-	0x00010137, /* SMEM coding of -12 dB */
-	0x0001209A, /* SMEM coding of -11 dB */
-	0x000143D1, /* SMEM coding of -10 dB */
-	0x00016B54, /* SMEM coding of -9 dB */
-	0x000197A9, /* SMEM coding of -8 dB */
-	0x0001C967, /* SMEM coding of -7 dB */
-	0x00020137, /* SMEM coding of -6 dB */
-	0x00023FD6, /* SMEM coding of -5 dB */
-	0x00028619, /* SMEM coding of -4 dB */
-	0x0002D4EF, /* SMEM coding of -3 dB */
-	0x00032D64, /* SMEM coding of -2 dB */
-	0x000390A4, /* SMEM coding of -1 dB */
-	0x00040000, /* SMEM coding of 0 dB */
-	0x00047CF2, /* SMEM coding of 1 dB */
-	0x00050923, /* SMEM coding of 2 dB */
-	0x0005A670, /* SMEM coding of 3 dB */
-	0x000656EE, /* SMEM coding of 4 dB */
-	0x00071CF5, /* SMEM coding of 5 dB */
-	0x0007FB26, /* SMEM coding of 6 dB */
-	0x0008F473, /* SMEM coding of 7 dB */
-	0x000A0C2B, /* SMEM coding of 8 dB */
-	0x000B4606, /* SMEM coding of 9 dB */
-	0x000CA62C, /* SMEM coding of 10 dB */
-	0x000E314A, /* SMEM coding of 11 dB */
-	0x000FEC9E, /* SMEM coding of 12 dB */
-	0x0011DE0A, /* SMEM coding of 13 dB */
-	0x00140C28, /* SMEM coding of 14 dB */
-	0x00167E60, /* SMEM coding of 15 dB */
-	0x00193D00, /* SMEM coding of 16 dB */
-	0x001C515D, /* SMEM coding of 17 dB */
-	0x001FC5EB, /* SMEM coding of 18 dB */
-	0x0023A668, /* SMEM coding of 19 dB */
-	0x00280000, /* SMEM coding of 20 dB */
-	0x002CE178, /* SMEM coding of 21 dB */
-	0x00325B65, /* SMEM coding of 22 dB */
-	0x00388062, /* SMEM coding of 23 dB */
-	0x003F654E, /* SMEM coding of 24 dB */
-	0x00472194, /* SMEM coding of 25 dB */
-	0x004FCF7C, /* SMEM coding of 26 dB */
-	0x00598C81, /* SMEM coding of 27 dB */
-	0x006479B7, /* SMEM coding of 28 dB */
-	0x0070BC3D, /* SMEM coding of 29 dB */
-	0x007E7DB9, /* SMEM coding of 30 dB */
-
+const u32 abe_db2lin_table[sizeof_db2lin_table] = {
+	0x00000000,		/* SMEM coding of -120 dB */
+	0x00000000,		/* SMEM coding of -119 dB */
+	0x00000000,		/* SMEM coding of -118 dB */
+	0x00000000,		/* SMEM coding of -117 dB */
+	0x00000000,		/* SMEM coding of -116 dB */
+	0x00000000,		/* SMEM coding of -115 dB */
+	0x00000000,		/* SMEM coding of -114 dB */
+	0x00000000,		/* SMEM coding of -113 dB */
+	0x00000000,		/* SMEM coding of -112 dB */
+	0x00000000,		/* SMEM coding of -111 dB */
+	0x00000000,		/* SMEM coding of -110 dB */
+	0x00000000,		/* SMEM coding of -109 dB */
+	0x00000001,		/* SMEM coding of -108 dB */
+	0x00000001,		/* SMEM coding of -107 dB */
+	0x00000001,		/* SMEM coding of -106 dB */
+	0x00000001,		/* SMEM coding of -105 dB */
+	0x00000001,		/* SMEM coding of -104 dB */
+	0x00000001,		/* SMEM coding of -103 dB */
+	0x00000002,		/* SMEM coding of -102 dB */
+	0x00000002,		/* SMEM coding of -101 dB */
+	0x00000002,		/* SMEM coding of -100 dB */
+	0x00000002,		/* SMEM coding of -99 dB */
+	0x00000003,		/* SMEM coding of -98 dB */
+	0x00000003,		/* SMEM coding of -97 dB */
+	0x00000004,		/* SMEM coding of -96 dB */
+	0x00000004,		/* SMEM coding of -95 dB */
+	0x00000005,		/* SMEM coding of -94 dB */
+	0x00000005,		/* SMEM coding of -93 dB */
+	0x00000006,		/* SMEM coding of -92 dB */
+	0x00000007,		/* SMEM coding of -91 dB */
+	0x00000008,		/* SMEM coding of -90 dB */
+	0x00000009,		/* SMEM coding of -89 dB */
+	0x0000000A,		/* SMEM coding of -88 dB */
+	0x0000000B,		/* SMEM coding of -87 dB */
+	0x0000000D,		/* SMEM coding of -86 dB */
+	0x0000000E,		/* SMEM coding of -85 dB */
+	0x00000010,		/* SMEM coding of -84 dB */
+	0x00000012,		/* SMEM coding of -83 dB */
+	0x00000014,		/* SMEM coding of -82 dB */
+	0x00000017,		/* SMEM coding of -81 dB */
+	0x0000001A,		/* SMEM coding of -80 dB */
+	0x0000001D,		/* SMEM coding of -79 dB */
+	0x00000021,		/* SMEM coding of -78 dB */
+	0x00000025,		/* SMEM coding of -77 dB */
+	0x00000029,		/* SMEM coding of -76 dB */
+	0x0000002E,		/* SMEM coding of -75 dB */
+	0x00000034,		/* SMEM coding of -74 dB */
+	0x0000003A,		/* SMEM coding of -73 dB */
+	0x00000041,		/* SMEM coding of -72 dB */
+	0x00000049,		/* SMEM coding of -71 dB */
+	0x00000052,		/* SMEM coding of -70 dB */
+	0x0000005D,		/* SMEM coding of -69 dB */
+	0x00000068,		/* SMEM coding of -68 dB */
+	0x00000075,		/* SMEM coding of -67 dB */
+	0x00000083,		/* SMEM coding of -66 dB */
+	0x00000093,		/* SMEM coding of -65 dB */
+	0x000000A5,		/* SMEM coding of -64 dB */
+	0x000000B9,		/* SMEM coding of -63 dB */
+	0x000000D0,		/* SMEM coding of -62 dB */
+	0x000000E9,		/* SMEM coding of -61 dB */
+	0x00000106,		/* SMEM coding of -60 dB */
+	0x00000126,		/* SMEM coding of -59 dB */
+	0x0000014A,		/* SMEM coding of -58 dB */
+	0x00000172,		/* SMEM coding of -57 dB */
+	0x0000019F,		/* SMEM coding of -56 dB */
+	0x000001D2,		/* SMEM coding of -55 dB */
+	0x0000020B,		/* SMEM coding of -54 dB */
+	0x0000024A,		/* SMEM coding of -53 dB */
+	0x00000292,		/* SMEM coding of -52 dB */
+	0x000002E2,		/* SMEM coding of -51 dB */
+	0x0000033C,		/* SMEM coding of -50 dB */
+	0x000003A2,		/* SMEM coding of -49 dB */
+	0x00000413,		/* SMEM coding of -48 dB */
+	0x00000492,		/* SMEM coding of -47 dB */
+	0x00000521,		/* SMEM coding of -46 dB */
+	0x000005C2,		/* SMEM coding of -45 dB */
+	0x00000676,		/* SMEM coding of -44 dB */
+	0x0000073F,		/* SMEM coding of -43 dB */
+	0x00000822,		/* SMEM coding of -42 dB */
+	0x00000920,		/* SMEM coding of -41 dB */
+	0x00000A3D,		/* SMEM coding of -40 dB */
+	0x00000B7D,		/* SMEM coding of -39 dB */
+	0x00000CE4,		/* SMEM coding of -38 dB */
+	0x00000E76,		/* SMEM coding of -37 dB */
+	0x0000103A,		/* SMEM coding of -36 dB */
+	0x00001235,		/* SMEM coding of -35 dB */
+	0x0000146E,		/* SMEM coding of -34 dB */
+	0x000016EC,		/* SMEM coding of -33 dB */
+	0x000019B8,		/* SMEM coding of -32 dB */
+	0x00001CDC,		/* SMEM coding of -31 dB */
+	0x00002061,		/* SMEM coding of -30 dB */
+	0x00002455,		/* SMEM coding of -29 dB */
+	0x000028C4,		/* SMEM coding of -28 dB */
+	0x00002DBD,		/* SMEM coding of -27 dB */
+	0x00003352,		/* SMEM coding of -26 dB */
+	0x00003995,		/* SMEM coding of -25 dB */
+	0x0000409C,		/* SMEM coding of -24 dB */
+	0x0000487E,		/* SMEM coding of -23 dB */
+	0x00005156,		/* SMEM coding of -22 dB */
+	0x00005B43,		/* SMEM coding of -21 dB */
+	0x00006666,		/* SMEM coding of -20 dB */
+	0x000072E5,		/* SMEM coding of -19 dB */
+	0x000080E9,		/* SMEM coding of -18 dB */
+	0x000090A4,		/* SMEM coding of -17 dB */
+	0x0000A24B,		/* SMEM coding of -16 dB */
+	0x0000B618,		/* SMEM coding of -15 dB */
+	0x0000CC50,		/* SMEM coding of -14 dB */
+	0x0000E53E,		/* SMEM coding of -13 dB */
+	0x00010137,		/* SMEM coding of -12 dB */
+	0x0001209A,		/* SMEM coding of -11 dB */
+	0x000143D1,		/* SMEM coding of -10 dB */
+	0x00016B54,		/* SMEM coding of -9 dB */
+	0x000197A9,		/* SMEM coding of -8 dB */
+	0x0001C967,		/* SMEM coding of -7 dB */
+	0x00020137,		/* SMEM coding of -6 dB */
+	0x00023FD6,		/* SMEM coding of -5 dB */
+	0x00028619,		/* SMEM coding of -4 dB */
+	0x0002D4EF,		/* SMEM coding of -3 dB */
+	0x00032D64,		/* SMEM coding of -2 dB */
+	0x000390A4,		/* SMEM coding of -1 dB */
+	0x00040000,		/* SMEM coding of 0 dB */
+	0x00047CF2,		/* SMEM coding of 1 dB */
+	0x00050923,		/* SMEM coding of 2 dB */
+	0x0005A670,		/* SMEM coding of 3 dB */
+	0x000656EE,		/* SMEM coding of 4 dB */
+	0x00071CF5,		/* SMEM coding of 5 dB */
+	0x0007FB26,		/* SMEM coding of 6 dB */
+	0x0008F473,		/* SMEM coding of 7 dB */
+	0x000A0C2B,		/* SMEM coding of 8 dB */
+	0x000B4606,		/* SMEM coding of 9 dB */
+	0x000CA62C,		/* SMEM coding of 10 dB */
+	0x000E314A,		/* SMEM coding of 11 dB */
+	0x000FEC9E,		/* SMEM coding of 12 dB */
+	0x0011DE0A,		/* SMEM coding of 13 dB */
+	0x00140C28,		/* SMEM coding of 14 dB */
+	0x00167E60,		/* SMEM coding of 15 dB */
+	0x00193D00,		/* SMEM coding of 16 dB */
+	0x001C515D,		/* SMEM coding of 17 dB */
+	0x001FC5EB,		/* SMEM coding of 18 dB */
+	0x0023A668,		/* SMEM coding of 19 dB */
+	0x00280000,		/* SMEM coding of 20 dB */
+	0x002CE178,		/* SMEM coding of 21 dB */
+	0x00325B65,		/* SMEM coding of 22 dB */
+	0x00388062,		/* SMEM coding of 23 dB */
+	0x003F654E,		/* SMEM coding of 24 dB */
+	0x00472194,		/* SMEM coding of 25 dB */
+	0x004FCF7C,		/* SMEM coding of 26 dB */
+	0x00598C81,		/* SMEM coding of 27 dB */
+	0x006479B7,		/* SMEM coding of 28 dB */
+	0x0070BC3D,		/* SMEM coding of 29 dB */
+	0x007E7DB9,		/* SMEM coding of 30 dB */
 };
-
-const u32 abe_1_alpha_iir [64] = {
-	0x040002, 0x040002, 0x040002, 0x040002, /* 0 */
-	0x50E955, 0x48CA65, 0x40E321, 0x72BE78, /* 1 [ms] */
-	0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, /* 2 */
-	0x38A084, 0x308974, 0x297B00, 0x235C7C, /* 4 */
-	0x1E14B0, 0x198AF0, 0x15A800, 0x125660, /* 8 */
-	0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, /* 16 */
-	0x07E054, 0x06A3B8, 0x059844, 0x04B680, /* 32 */
-	0x03F80C, 0x035774, 0x02D018, 0x025E0C, /* 64 */
-	0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, /* 128 */
-	0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, /* 256 */
-	0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, /* 512 */
-	0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, /* 1.024 [s] */
-	0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, /* 2.048 */
-	0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, /* 4.096 */
-	0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, /* 8.192 */
+const u32 abe_1_alpha_iir[64] = {
+	0x040002, 0x040002, 0x040002, 0x040002,	/* 0 */
+	0x50E955, 0x48CA65, 0x40E321, 0x72BE78,	/* 1 [ms] */
+	0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690,	/* 2 */
+	0x38A084, 0x308974, 0x297B00, 0x235C7C,	/* 4 */
+	0x1E14B0, 0x198AF0, 0x15A800, 0x125660,	/* 8 */
+	0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC,	/* 16 */
+	0x07E054, 0x06A3B8, 0x059844, 0x04B680,	/* 32 */
+	0x03F80C, 0x035774, 0x02D018, 0x025E0C,	/* 64 */
+	0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB,	/* 128 */
+	0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF,	/* 256 */
+	0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B,	/* 512 */
+	0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB,	/* 1.024 [s] */
+	0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193,	/* 2.048 */
+	0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7,	/* 4.096 */
+	0x01FFFB, 0x01AE87, 0x016A07, 0x01306F,	/* 8.192 */
 	0x00FFFF, 0x00D743, 0x00B503, 0x009837,
 };
-
-const u32 abe_alpha_iir [64] = {
-	0x000000, 0x000000, 0x000000, 0x000000, /* 0 */
-	0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, /* 1 [ms] */
-	0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, /* 2 */
-	0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, /* 4 */
-	0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, /* 8 */
-	0x783EB1, 0x797251, 0x7A7761, 0x7B549D, /* 16 */
-	0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, /* 32 */
-	0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, /* 64 */
-	0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, /* 128 */
-	0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, /* 256 */
-	0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, /* 512 */
-	0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, /* 1.024 [s] */
-	0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, /* 2.048 */
-	0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, /* 4.096 */
-	0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, /* 8.192 */
+const u32 abe_alpha_iir[64] = {
+	0x000000, 0x000000, 0x000000, 0x000000,	/* 0 */
+	0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5,	/* 1 [ms] */
+	0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9,	/* 2 */
+	0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1,	/* 4 */
+	0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1,	/* 8 */
+	0x783EB1, 0x797251, 0x7A7761, 0x7B549D,	/* 16 */
+	0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1,	/* 32 */
+	0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9,	/* 64 */
+	0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825,	/* 128 */
+	0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD,	/* 256 */
+	0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9,	/* 512 */
+	0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD,	/* 1.024 [s] */
+	0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D,	/* 2.048 */
+	0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41,	/* 4.096 */
+	0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1,	/* 8.192 */
 	0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1,
 };
-
 /*
  * ABE_DEBUG DATA
  */
-
 /*
  * IRQ and trace pointer in DMEM:
  * FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL
  */
 u32 abe_irq_dbg_read_ptr;
-
 /*
  * General circular buffer used to trace APIs calls and AE activity.
  */
-u32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof];
+u32 abe_dbg_activity_log[D_DEBUG_HAL_TASK_sizeof];
 u32 abe_dbg_activity_log_write_pointer;
 u32 abe_dbg_mask;
-
 /*
  * Global variable holding parameter errors
  */
-
 u32 abe_dbg_param;
-
-
 /*
  * Output of messages selector
  */
 u32 abe_dbg_output;
-
 /*
  * last parameters
  */
-
 #define SIZE_PARAM 10
-
 u32 param1[SIZE_PARAM];
 u32 param2[SIZE_PARAM];
 u32 param3[SIZE_PARAM];
 u32 param4[SIZE_PARAM];
 u32 param5[SIZE_PARAM];
-
 /*
- * END ABE_DEBUG DATA
+ * MAIN PORT SELECTION
  */
-
-
-
+const u32 abe_port_priority[LAST_PORT_ID - 1] = {
+	PDM_DL_PORT,
+	PDM_UL_PORT,
+	MM_EXT_OUT_PORT,
+	MM_EXT_IN_PORT,
+	TDM_DL_PORT,
+	TDM_UL_PORT,
+	DMIC_PORT,
+	MM_UL_PORT,
+	MM_UL2_PORT,
+	MM_DL_PORT,
+	TONES_DL_PORT,
+	VX_UL_PORT,
+	VX_DL_PORT,
+	BT_VX_DL_PORT,
+	BT_VX_UL_PORT,
+	VIB_DL_PORT,
+};
 /*
  * ABE CONST AREA FOR DMIC DECIMATION FILTERS
  */
-const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = { 
-	-4119413, -192384, -341428, -348088, -151380, 151380, 348088, 
-	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 
+/* const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380, 348088,
+	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934,
 	2997698, -3692214, 3406822, -2280190, 1042982 };
-const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = { 
-	-4119413, -192384, -341428, -348088, -151380, 151380, 348088, 
-	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 
+const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380, 348088,
+	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934,
 	2997698, -3692214, 3406822, -2280190, 1042982 };
-const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = { 
-	-4119413, -192384, -341428, -348088, -151380, 151380, 348088, 
-	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 
+const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380, 348088,
+	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934,
 	2997698, -3692214, 3406822, -2280190, 1042982 };
-const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = { 
-	-4119413, -192384, -341428, -348088, -151380, 151380, 348088, 
-	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934, 
+const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof] = {
+	-4119413, -192384, -341428, -348088, -151380, 151380, 348088,
+	341428, 192384, 4119415, 1938156, -6935719, 775202, -1801934,
 	2997698, -3692214, 3406822, -2280190, 1042982 };
-
-
-#endif /* abe_dat_c */
+*/
+#endif/* abe_dat_c */
diff --git a/sound/soc/omap/abe/abe_dat.h b/sound/soc/omap/abe/abe_dat.h
deleted file mode 100644
index 352af9bb5677..000000000000
--- a/sound/soc/omap/abe/abe_dat.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * ALSA SoC OMAP ABE driver
- *
- * Author:          Laurent Le Faucheur <l-le-faucheur@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef abe_dat_def
-#define abe_dat_def
-
-	/*
-	 *      Call-backs
-	 */
-
-	abe_subroutine2 callbacks [MAXCALLBACK];                            /* 2 parameters subroutine pointers */
-
-
-
-	/*
-	 *      HAL/FW ports status / format / sampling / protocol(call_back) / features / gain / name
-	 */
-
-	abe_port_t abe_port [LAST_PORT_ID];                    /* list of ABE ports */
-	const   abe_port_t abe_port_init [LAST_PORT_ID] = {
-
-		/* Status    Data Format       Drift     Call-Back                               Protocol+selector            desc_addr;             buf_addr;  buf_size;                iter;                 irq_addr          irq_data                  DMA_T                        $Features reseted at start   Port Name for the debug trace */
-		/*      DMIC    */      { IDLE_P, {96000, SIX_MSB},    NODRIFT, NOCALLBACK, 0, 0,                        {SNK_P, DMIC_PORT_PROT,                            {{dmem_dmic, dmem_dmic_size, DMIC_ITER}}},                                                                   {0, 0},                 {EQMIC, 0},        "DMIC" },
-		/*      PDM_UL  */      { IDLE_P, {96000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_amic,  0,               {SNK_P, MCPDMUL_PORT_PROT,                         {{dmem_amic, dmem_amic_size, MCPDM_UL_ITER}}},                                                               {0, 0},                 {EQMIC, 0},	"PDM_UL" },
-		/*      BT_VX_UL*/      { IDLE_P, { 8000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_bt_vx_ul, 0,            {SNK_P, SERIAL_PORT_PROT,   {{MCBSP1_DMA_TX*ATC_SIZE,dmem_bt_vx_ul,dmem_bt_vx_ul_size,   1 * SCHED_LOOP_8kHz}}},                                                {0, 0},                 {0},		"BT_VX_UL" },
-		/*      MM_UL   */      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ul, 0,               {SRC_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX3*ATC_SIZE,dmem_mm_ul,dmem_mm_ul_size,        10 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<3)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__3, 120},   {UPROUTE, 0},      "MM_UL" },
-		/*      MM_UL2  */      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ul2,0,               {SRC_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX4*ATC_SIZE,dmem_mm_ul2,dmem_mm_ul2_size,       2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<4)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__4,  24},   {UPROUTE, 0},      "MM_UL2" },
-		/*      VX_UL   */      { IDLE_P, { 8000, MONO_MSB},   NODRIFT, NOCALLBACK, smem_vx_ul, 0,               {SRC_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX2*ATC_SIZE,dmem_vx_ul,dmem_vx_ul_size,         1 * SCHED_LOOP_8kHz,  ABE_DMASTATUS_RAW,(1<<2)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__2,  2},    {ASRC2, 0},        "VX_UL" },
-		/*      MM_DL   */      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_dl_opp100, 0,        {SNK_P, PINGPONG_PORT_PROT, {{CBPr_DMA_RTX0*ATC_SIZE,dmem_mm_dl,dmem_mm_dl_size,         2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<0)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__0, 24},    {ASRC3, 0},        "MM_DL" },
-		/*      VX_DL   */      { IDLE_P, { 8000, MONO_MSB},   NODRIFT, NOCALLBACK, smem_vx_dl, 0,               {SNK_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX1*ATC_SIZE,dmem_vx_dl,dmem_vx_dl_size,         1 * SCHED_LOOP_8kHz,  ABE_DMASTATUS_RAW,(1<<1)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__1, 2},     {ASRC1, 0},        "VX_DL" },
-		/*      TONES_DL*/      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_tones_dl, 0,            {SNK_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX5*ATC_SIZE,dmem_tones_dl,dmem_tones_dl_size,   2 * SCHED_LOOP_48kHz, ABE_DMASTATUS_RAW,(1<<5)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__5, 24},    {0},               "TONES_DL" },
-		/*      VIB_DL  */      { IDLE_P, {24000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_vib, 0,                 {SNK_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX6*ATC_SIZE,dmem_vib_dl,dmem_vib_dl_size,       2 * SCHED_LOOP_24kHz, ABE_DMASTATUS_RAW,(1<<6)}}},   {CIRCULAR_BUFFER_PERIPHERAL_R__6, 12},    {0},               "VIB_DL" },
-		/*      BT_VX_DL*/      { IDLE_P, { 8000, MONO_MSB},   NODRIFT, NOCALLBACK, smem_bt_vx_dl, 0,            {SRC_P, SERIAL_PORT_PROT,   {{MCBSP1_DMA_RX*ATC_SIZE,dmem_bt_vx_dl,dmem_bt_vx_dl_size,   1 * SCHED_LOOP_8kHz,}}},                                               {0, 0},                                   {0},               "BT_VX_DL" },
-		/*      PDM_DL  */      { IDLE_P, {96000, SIX_MSB},    NODRIFT, NOCALLBACK, 0,0,                         {SRC_P, MCPDMDL_PORT_PROT,                         {{dmem_mcpdm, dmem_mcpdm_size}}},                                                                            {0, 0},            {MIXDL1, EQ1, APS1, MIXDL2, EQ2L, EQ2R, APS2L, APS2R,0}, "PDM_DL" },
-		/*      MM_EXT_OUT*/    { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ext_out, 0,          {SRC_P, SERIAL_PORT_PROT,   {{MCBSP1_DMA_TX*ATC_SIZE,dmem_mm_ext_out,dmem_mm_ext_out_size, 2 * SCHED_LOOP_48kHz}}},                                             {0, 0},                                   {0},               "MM_EXT_OUT" },
-		/*      MM_EXT_IN */    { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, smem_mm_ext_in, 0,           {SNK_P, SERIAL_PORT_PROT,   {{MCBSP1_DMA_RX*ATC_SIZE,dmem_mm_ext_in ,dmem_mm_ext_in_size,  2 * SCHED_LOOP_48kHz}}},                                             {0, 0},                                   {0},               "MM_EXT_IN" },
-		/*      PCM3_TX */      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, 0, 0,			 {SRC_P, TDM_SERIAL_PORT_PROT,{{MCBSP3_DMA_TX*ATC_SIZE,dmem_mm_ext_out,dmem_mm_ext_out_size, 2 * SCHED_LOOP_48kHz}}},                                             {0, 0},                                   {0},               "TDM_OUT" },
-		/*      PCM3_RX */      { IDLE_P, {48000, STEREO_MSB}, NODRIFT, NOCALLBACK, 0, 0,			 {SRC_P, TDM_SERIAL_PORT_PROT,{{MCBSP3_DMA_RX*ATC_SIZE,dmem_mm_ext_in ,dmem_mm_ext_in_size,  2 * SCHED_LOOP_48kHz}}},                                             {0, 0},                                   {0},               "TDM_IN" },
-		/*      SCHD_DBG_PORT */{ IDLE_P, {48000, MONO_MSB},   NODRIFT, NOCALLBACK, 0,0,                         {SRC_P, DMAREQ_PORT_PROT,   {{CBPr_DMA_RTX7*ATC_SIZE,dmem_mm_trace,dmem_mm_trace_size,     2 * SCHED_LOOP_48kHz},ABE_DMASTATUS_RAW,(1<<4)}}, {CIRCULAR_BUFFER_PERIPHERAL_R__7,  24},   {SEQUENCE, CONTROL, GAINS, 0},  "SCHD_DBG" },
-	};
-/* abe_port_init : smem content for DMIC/PDM must be 0 or Dummy_AM_labelID */
-
-	const   abe_port_info_t abe_port_info [LAST_PORT_ID] = {
-		/*      DMIC    */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0}},
-		/*      PDM_UL  */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      BT_VX_UL*/      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      MM_UL   */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      MM_UL2  */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      VX_UL   */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      MM_DL   */      { ABE_OPP50, {SUB_WRITE_MIXER,     MM_DL_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      VX_DL   */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      TONES_DL*/      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      VIB_DL  */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      BT_VX_DL*/      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      PDM_DL  */      { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      MM_EXT_OUT*/    { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      MM_EXT_IN */    { ABE_OPP50, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		/*      SCHD_DBG_PORT { ABE_OPP25, {SUB_WRITE_PORT_GAIN, DMIC_PORT, MUTE_GAIN, 0, 0}, {0,0,0,0,0} },
-		                 */
-	};
-
-	/*
-	 *      Firmware features
-	 */
-	abe_feature_t all_feature [MAXNBFEATURE];
-	const abe_feature_t all_feature_init [] =  {
-		/* ON_reset          OFF           READ              WRITE   STATUS INPUT OUTPUT  SLOT/S OPP  NAME */
-		/* EQ1      */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq1, c_write_eq1, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  DLEQ1" }, /* equalizer downlink path headset + earphone */
-		/* EQ2L     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq2, c_write_eq2, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  DLEQ2L" }, /* equalizer downlink path integrated handsfree LEFT */
-		/* EQ2R     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  DLEQ2R"}, /* equalizer downlink path integrated handsfree RIGHT */
-		/* EQSDT    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  EQSDT" }, /* equalizer downlink path side-tone */
-		/* EQDMIC1  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  EQDMIC1" }, /* SRC+equalizer uplink DMIC 1st pair */
-		/* EQDMIC2  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  EQDMIC2" }, /* SRC+equalizer uplink DMIC 2nd pair */
-		/* EQDMIC3  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  EQDMIC3" }, /* SRC+equalizer uplink DMIC 3rd pair */
-		/* EQAMIC   */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  EQAMIC" }, /* SRC+equalizer uplink AMIC */
-		/* APS1     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  APS1" }, /* Acoustic protection for headset */
-		/* APS2     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  APS2" }, /* acoustic protection high-pass filter for handsfree "Left" */
-		/* APS3     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  APS3" }, /* acoustic protection high-pass filter for handsfree "Right" */
-		/* ASRC1    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  ASRC_VXDL" }, /* asynchronous sample-rate-converter for the downlink voice path */
-		/* ASRC2    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  ASRC_VXUL" }, /* asynchronous sample-rate-converter for the uplink voice path */
-		/* ASRC3    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  ASRC_MMDL" }, /* asynchronous sample-rate-converter for the multimedia player */
-		/* ASRC4    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  ASRC_ECHO" }, /* asynchronous sample-rate-converter for the echo reference */
-		/* MXDL1    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  MIX_DL1" }, /* mixer of the headset and earphone path */
-		/* MXDL2    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  MIX_DL2" }, /* mixer of the hands-free path */
-		/* MXAUDUL  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  MXSAUDUL" }, /* mixer for uplink tone mixer */
-		/* MXVXREC  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  MXVXREC" },  /* mixer for voice recording */
-		/* MXSDT    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  MIX_SDT" }, /* mixer for side-tone */
-		/* MXECHO   */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  MIX_ECHO" }, /* mixer for echo reference */
-		/* UPROUTE  */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP50, "  DLEQ3" }, /* router of the uplink path */
-		/* GAINS    */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  DLEQ3" }, /* all gains */
-		/* EANC     */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP100,"  DLEQ3" }, /* active noise canceller */
-		/* SEQ      */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  DLEQ3" }, /* sequencing queue of micro tasks */
-		/* CTL      */  { c_feat_init_eq, c_feat_init_eq, c_feat_read_eq3, c_write_eq3, 0, 0x1000, 0x1010, 2, 0, ABE_OPP25, "  DLEQ3" }, /* Phoenix control queue through McPDM */
-	};
-
-
-
-	/*
-	 *      MEMORY MAPPING OF THE DMEM FIFOs
-	 */
-
-	abe_uint32 abe_map_dmem [LAST_PORT_ID];			/* DMEM port map */
-	abe_uint32 abe_map_dmem_secondary [LAST_PORT_ID];
-	abe_uint32 abe_map_dmem_size [LAST_PORT_ID];		/* DMEM port buffer sizes */
-
-
-	/*
-	 *      AESS/ATC destination and source address translation (except McASPs) from the original 64bits words address
-	 */
-	const abe_uint32 abe_atc_dstid [ABE_ATC_DESC_SIZE>>3] = {
-	/*  DMA_0   DMIC    PDM_DL  PDM_UL  McB1TX  McB1RX  McB2TX  McB2RX          0  .. 7 */
-		0,      0,      12,     0,      1,      0,      2,      0,
-	/*  McB3TX  McB3RX  SLIMT0  SLIMT1  SLIMT2  SLIMT3  SLIMT4  SLIMT5          8  .. 15 */
-		3,      0,      4,      5,      6,      7,      8,      9,
-	/*  SLIMT6  SLIMT7  SLIMR0  SLIMR1  SLIMR2  SLIMR3  SLIMR4  SLIMR5          16 .. 23 */
-		10,     11,     0,      0,      0,      0,      0,      0,
-	/*  SLIMR6  SLIMR7  McASP1X -----   -----   McASP1R -----   -----           24 .. 31 */
-		0,      0,      14,     0,      0,      0,      0,      0,
-	/*  CBPrT0  CBPrT1  CBPrT2  CBPrT3  CBPrT4  CBPrT5  CBPrT6  CBPrT7          32 .. 39 */
-		63,     63,     63,     63,     63,     63,     63,     63,
-	/*  CBP_T0  CBP_T1  CBP_T2  CBP_T3  CBP_T4  CBP_T5  CBP_T6  CBP_T7          40 .. 47 */
-		0,      0,      0,      0,      0,      0,      0,      0,
-	/*  CBP_T8  CBP_T9  CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15         48 .. 63 */
-		0,      0,      0,      0,      0,      0,      0,      0,
-	};
-	const abe_uint32 abe_atc_srcid [ABE_ATC_DESC_SIZE>>3] = {
-	/*  DMA_0   DMIC    PDM_DL  PDM_UL  McB1TX  McB1RX  McB2TX  McB2RX          0  .. 7 */
-		0,      12,     0,      13,     0,      1,      0,      2,
-	/*  McB3TX  McB3RX  SLIMT0  SLIMT1  SLIMT2  SLIMT3  SLIMT4  SLIMT5          8  .. 15 */
-		0,      3,      0,      0,      0,      0,      0,      0,
-	/*  SLIMT6  SLIMT7  SLIMR0  SLIMR1  SLIMR2  SLIMR3  SLIMR4  SLIMR5          16 .. 23 */
-		0,      0,      4,      5,      6,      7,      8,      9,
-	/*  SLIMR6  SLIMR7  McASP1X -----   -----   McASP1R -----   -----           24 .. 31 */
-		10,     11,     0,      0,      0,      14,     0,      0,
-	/*  CBPrT0  CBPrT1  CBPrT2  CBPrT3  CBPrT4  CBPrT5  CBPrT6  CBPrT7          32 .. 39 */
-		63,     63,     63,     63,     63,     63,     63,     63,
-	/*  CBP_T0  CBP_T1  CBP_T2  CBP_T3  CBP_T4  CBP_T5  CBP_T6  CBP_T7          40 .. 47 */
-		0,      0,      0,      0,      0,      0,      0,      0,
-	/*  CBP_T8  CBP_T9  CBP_T10 CBP_T11 CBP_T12 CBP_T13 CBP_T14 CBP_T15         48 .. 63 */
-		0,      0,      0,      0,      0,      0,      0,      0,
-	};
-
-
-/*
- * preset default routing configurations
- * This is given as implementation EXAMPLES
- * the programmer uses "abe_set_router_configuration" with its own tables
-	*/
-
-	const  abe_router_t abe_router_ul_table_preset [NBROUTE_CONFIG][NBROUTE_UL] = {    {										/* VOICE UPLINK WITH PHOENIX MICROPHONES - UPROUTE_CONFIG_AMIC */
-			DMIC1_L_labelID, DMIC1_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,		/* 0  .. 9   = MM_UL */
-			MM_EXT_IN_L_labelID, MM_EXT_IN_R_labelID, ZERO_labelID, ZERO_labelID,
-			ZERO_labelID, ZERO_labelID,
-			DMIC3_L_labelID, DMIC3_R_labelID, 			   			/* 10 .. 11  = MM_UL2 */
-			AMIC_L_labelID, AMIC_R_labelID,						/* 12 .. 13  = VX_UL */
-			ZERO_labelID, ZERO_labelID,							/* 14 .. 15  = RESERVED */
-		},
-		{                                                                       /* VOICE UPLINK WITH THE FIRST DMIC PAIR - UPROUTE_CONFIG_DMIC1*/
-			DMIC2_L_labelID, DMIC2_R_labelID, DMIC3_L_labelID, DMIC3_R_labelID,     /* 0  .. 9   = MM_UL */
-			DMIC1_L_labelID, DMIC1_R_labelID, ZERO_labelID, ZERO_labelID,
-			ZERO_labelID, ZERO_labelID,
-			DMIC1_L_labelID, DMIC1_R_labelID,                                       /* 10 .. 11  = MM_UL2 */
-			DMIC1_L_labelID, DMIC1_R_labelID,                                       /* 12 .. 13  = VX_UL */
-			ZERO_labelID, ZERO_labelID,                                             /* 14 .. 15  = RESERVED */
-		},
-		{                                                                       /* VOICE UPLINK WITH THE SECOND DMIC PAIR - UPROUTE_CONFIG_DMIC2 */
-			DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,     /* 0  .. 9   = MM_UL */
-			DMIC2_L_labelID, DMIC2_R_labelID, ZERO_labelID, ZERO_labelID,
-			ZERO_labelID, ZERO_labelID,
-			DMIC2_L_labelID, DMIC2_R_labelID,                                       /* 10 .. 11  = MM_UL2 */
-			DMIC2_L_labelID, DMIC2_R_labelID,                                       /* 12 .. 13  = VX_UL */
-			ZERO_labelID, ZERO_labelID,                                             /* 14 .. 15  = RESERVED */
-		},
-		{                                                                       /* VOICE UPLINK WITH THE LAST DMIC PAIR - UPROUTE_CONFIG_DMIC3 */
-			AMIC_L_labelID, AMIC_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,       /* 0  .. 9   = MM_UL */
-			DMIC3_L_labelID, DMIC3_R_labelID, ZERO_labelID, ZERO_labelID,
-			ZERO_labelID, ZERO_labelID,
-			DMIC3_L_labelID, DMIC3_R_labelID,                                       /* 10 .. 11  = MM_UL2 */
-			DMIC3_L_labelID, DMIC3_R_labelID,                                       /* 12 .. 13  = VX_UL */
-			ZERO_labelID, ZERO_labelID,                                             /* 14 .. 15  = RESERVED */
-		},
-		{                                                                       /* VOICE UPLINK WITH THE BT - UPROUTE_CONFIG_BT */
-			BT_UL_L_labelID, BT_UL_R_labelID, DMIC2_L_labelID, DMIC2_R_labelID,	    /* 0  .. 9   = MM_UL */
-			DMIC3_L_labelID, DMIC3_R_labelID, DMIC1_L_labelID, DMIC1_R_labelID,
-			ZERO_labelID, ZERO_labelID,
-			AMIC_L_labelID, AMIC_R_labelID,                                         /* 10 .. 11  = MM_UL2 */
-			BT_UL_L_labelID, BT_UL_R_labelID,                                       /* 12 .. 13  = VX_UL */
-			ZERO_labelID, ZERO_labelID,                                             /* 14 .. 15  = RESERVED */
-		},
-	};
-
-	abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL];                  /* all default routing configurations */
-
-	/*
- * ABE_GLOBAL DATA
-	 */
-
-	abe_uint32 abe_global_mcpdm_control;                /* flag, indicates the allowed control of Phoenix through McPDM slot #6 */
-	abe_event_id abe_current_event_id;
-
-	/*
- * ABE SUBROUTINES AND SEQUENCES
-	 */
-
-
-	/*
-	const abe_seq_t abe_seq_array [MAXNBSEQUENCE] [MAXSEQUENCESTEPS] =
-	           {{0,      0,      0,      0}, {-1, 0, 0, 0}},
-	           {{0,      0,      0,      0}, {-1, 0, 0, 0}},
-	const seq_t setup_hw_sequence2 [ ] = { 0, C_AE_FUNC1,  0, 0, 0, 0,
-	                                      -1, C_CALLBACK1, 0, 0, 0, 0 };
-
-	const abe_subroutine2 abe_sub_array [MAXNBSUBROUTINE] =
-	            abe_init_atc,   0,      0,
-	            abe_init_atc,   0,      0,
-
-	 typedef double (*PtrFun) (double);
-	PtrFun pFun;
-	pFun = sin;
-	y = (* pFun) (x);
-	*/                                                               /* mask, { time id  param    tag1} */
-	const abe_sequence_t seq_null  =                                {NOMASK,    {CL_M1, 0, 0,0,0,0, 0 }, {CL_M1, 0, 0,0,0,0, 0 } };
-
-	abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE];        /* table of new subroutines called in the sequence */
-	abe_uint32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE];      /* number of parameters per calls */
-	abe_uint32 abe_subroutine_id [MAXNBSUBROUTINE];                 /* index of the subroutine */
-	abe_uint32* abe_all_subroutine_params[MAXNBSUBROUTINE];		/* paramters of the subroutine (if any) */
-	abe_uint32 abe_subroutine_write_pointer;
-
-	abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];                 /* table of all sequences */
-	abe_uint32 abe_sequence_write_pointer;
-	abe_uint32 abe_nb_pending_sequences;                            /* current number of pending sequences (avoids to look in the table) */
-	abe_uint32 abe_pending_sequences [MAXNBSEQUENCE];               /* pending sequences due to ressource collision */
-
-	abe_uint32 abe_global_sequence_mask;                            /* mask of unsharable ressources among other sequences */
-
-	abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS]; /* table of active sequences */
-
-	abe_uint32 abe_irq_pingpong_player_id;                          /* index of the plugged subroutine doing ping-pong cache-flush DMEM accesses */
-	abe_uint32 abe_irq_aps_adaptation_id;                           /* index of the plugged subroutine doing acoustics protection adaptation */
-
-	abe_uint32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS];    /* base addresses of the ping pong buffers in bytes addresses  */
-	abe_uint32 abe_size_pingpong;                                   /* size of each ping/pong buffers */
-	abe_uint32 abe_nb_pingpong;                                     /* number of ping/pong buffer being used */
-
-	/* @!!! in  "ABE_SPingPongDescriptor", the offset address of the field
-	        "nextbuff0_BaseAddr" must be aligned on 32bits boundaries
-	        typedef struct abepingpongdescriptorTag{
-	            ...
-	            ABE_uint16 workbuff_BaseAddr;   12        * current Base address of the working buffer
-	            ABE_uint16 workbuff_Samples;    14        * samples left in the working buffer *
-	            ABE_uint16 nextbuff0_BaseAddr;  16        * Base address of the pingpong buffer 0 *
-	            ABE_uint16 nextbuff0_Samples;   18        * samples available in the pingpong buffer 0 *
-	            ABE_uint16 nextbuff1_BaseAddr;  20        * Base address of the pingpong buffer 1 *
-	            ABE_uint16 nextbuff1_Samples;   22        * samples available in the pingpong buffer 1 *
-	         } ABE_SPingPongDescriptor;
-	 */
-
-
-	/*
- * ABE CONST AREA FOR PARAMETERS TRANSLATION
-	 */
-	const abe_uint32 abe_db2lin_table [sizeof_db2lin_table] = {
-
-		0x00000000,  /* SMEM coding of -120 dB */
-		0x00000000,  /* SMEM coding of -119 dB */
-		0x00000000,  /* SMEM coding of -118 dB */
-		0x00000000,  /* SMEM coding of -117 dB */
-		0x00000000,  /* SMEM coding of -116 dB */
-		0x00000000,  /* SMEM coding of -115 dB */
-		0x00000000,  /* SMEM coding of -114 dB */
-		0x00000000,  /* SMEM coding of -113 dB */
-		0x00000000,  /* SMEM coding of -112 dB */
-		0x00000000,  /* SMEM coding of -111 dB */
-		0x00000000,  /* SMEM coding of -110 dB */
-		0x00000000,  /* SMEM coding of -109 dB */
-		0x00000001,  /* SMEM coding of -108 dB */
-		0x00000001,  /* SMEM coding of -107 dB */
-		0x00000001,  /* SMEM coding of -106 dB */
-		0x00000001,  /* SMEM coding of -105 dB */
-		0x00000001,  /* SMEM coding of -104 dB */
-		0x00000001,  /* SMEM coding of -103 dB */
-		0x00000002,  /* SMEM coding of -102 dB */
-		0x00000002,  /* SMEM coding of -101 dB */
-		0x00000002,  /* SMEM coding of -100 dB */
-		0x00000002,  /* SMEM coding of  -99 dB */
-		0x00000003,  /* SMEM coding of  -98 dB */
-		0x00000003,  /* SMEM coding of  -97 dB */
-		0x00000004,  /* SMEM coding of  -96 dB */
-		0x00000004,  /* SMEM coding of  -95 dB */
-		0x00000005,  /* SMEM coding of  -94 dB */
-		0x00000005,  /* SMEM coding of  -93 dB */
-		0x00000006,  /* SMEM coding of  -92 dB */
-		0x00000007,  /* SMEM coding of  -91 dB */
-		0x00000008,  /* SMEM coding of  -90 dB */
-		0x00000009,  /* SMEM coding of  -89 dB */
-		0x0000000A,  /* SMEM coding of  -88 dB */
-		0x0000000B,  /* SMEM coding of  -87 dB */
-		0x0000000D,  /* SMEM coding of  -86 dB */
-		0x0000000E,  /* SMEM coding of  -85 dB */
-		0x00000010,  /* SMEM coding of  -84 dB */
-		0x00000012,  /* SMEM coding of  -83 dB */
-		0x00000014,  /* SMEM coding of  -82 dB */
-		0x00000017,  /* SMEM coding of  -81 dB */
-		0x0000001A,  /* SMEM coding of  -80 dB */
-		0x0000001D,  /* SMEM coding of  -79 dB */
-		0x00000021,  /* SMEM coding of  -78 dB */
-		0x00000025,  /* SMEM coding of  -77 dB */
-		0x00000029,  /* SMEM coding of  -76 dB */
-		0x0000002E,  /* SMEM coding of  -75 dB */
-		0x00000034,  /* SMEM coding of  -74 dB */
-		0x0000003A,  /* SMEM coding of  -73 dB */
-		0x00000041,  /* SMEM coding of  -72 dB */
-		0x00000049,  /* SMEM coding of  -71 dB */
-		0x00000052,  /* SMEM coding of  -70 dB */
-		0x0000005D,  /* SMEM coding of  -69 dB */
-		0x00000068,  /* SMEM coding of  -68 dB */
-		0x00000075,  /* SMEM coding of  -67 dB */
-		0x00000083,  /* SMEM coding of  -66 dB */
-		0x00000093,  /* SMEM coding of  -65 dB */
-		0x000000A5,  /* SMEM coding of  -64 dB */
-		0x000000B9,  /* SMEM coding of  -63 dB */
-		0x000000D0,  /* SMEM coding of  -62 dB */
-		0x000000E9,  /* SMEM coding of  -61 dB */
-		0x00000106,  /* SMEM coding of  -60 dB */
-		0x00000126,  /* SMEM coding of  -59 dB */
-		0x0000014A,  /* SMEM coding of  -58 dB */
-		0x00000172,  /* SMEM coding of  -57 dB */
-		0x0000019F,  /* SMEM coding of  -56 dB */
-		0x000001D2,  /* SMEM coding of  -55 dB */
-		0x0000020B,  /* SMEM coding of  -54 dB */
-		0x0000024A,  /* SMEM coding of  -53 dB */
-		0x00000292,  /* SMEM coding of  -52 dB */
-		0x000002E2,  /* SMEM coding of  -51 dB */
-		0x0000033C,  /* SMEM coding of  -50 dB */
-		0x000003A2,  /* SMEM coding of  -49 dB */
-		0x00000413,  /* SMEM coding of  -48 dB */
-		0x00000492,  /* SMEM coding of  -47 dB */
-		0x00000521,  /* SMEM coding of  -46 dB */
-		0x000005C2,  /* SMEM coding of  -45 dB */
-		0x00000676,  /* SMEM coding of  -44 dB */
-		0x0000073F,  /* SMEM coding of  -43 dB */
-		0x00000822,  /* SMEM coding of  -42 dB */
-		0x00000920,  /* SMEM coding of  -41 dB */
-		0x00000A3D,  /* SMEM coding of  -40 dB */
-		0x00000B7D,  /* SMEM coding of  -39 dB */
-		0x00000CE4,  /* SMEM coding of  -38 dB */
-		0x00000E76,  /* SMEM coding of  -37 dB */
-		0x0000103A,  /* SMEM coding of  -36 dB */
-		0x00001235,  /* SMEM coding of  -35 dB */
-		0x0000146E,  /* SMEM coding of  -34 dB */
-		0x000016EC,  /* SMEM coding of  -33 dB */
-		0x000019B8,  /* SMEM coding of  -32 dB */
-		0x00001CDC,  /* SMEM coding of  -31 dB */
-		0x00002061,  /* SMEM coding of  -30 dB */
-		0x00002455,  /* SMEM coding of  -29 dB */
-		0x000028C4,  /* SMEM coding of  -28 dB */
-		0x00002DBD,  /* SMEM coding of  -27 dB */
-		0x00003352,  /* SMEM coding of  -26 dB */
-		0x00003995,  /* SMEM coding of  -25 dB */
-		0x0000409C,  /* SMEM coding of  -24 dB */
-		0x0000487E,  /* SMEM coding of  -23 dB */
-		0x00005156,  /* SMEM coding of  -22 dB */
-		0x00005B43,  /* SMEM coding of  -21 dB */
-		0x00006666,  /* SMEM coding of  -20 dB */
-		0x000072E5,  /* SMEM coding of  -19 dB */
-		0x000080E9,  /* SMEM coding of  -18 dB */
-		0x000090A4,  /* SMEM coding of  -17 dB */
-		0x0000A24B,  /* SMEM coding of  -16 dB */
-		0x0000B618,  /* SMEM coding of  -15 dB */
-		0x0000CC50,  /* SMEM coding of  -14 dB */
-		0x0000E53E,  /* SMEM coding of  -13 dB */
-		0x00010137,  /* SMEM coding of  -12 dB */
-		0x0001209A,  /* SMEM coding of  -11 dB */
-		0x000143D1,  /* SMEM coding of  -10 dB */
-		0x00016B54,  /* SMEM coding of   -9 dB */
-		0x000197A9,  /* SMEM coding of   -8 dB */
-		0x0001C967,  /* SMEM coding of   -7 dB */
-		0x00020137,  /* SMEM coding of   -6 dB */
-		0x00023FD6,  /* SMEM coding of   -5 dB */
-		0x00028619,  /* SMEM coding of   -4 dB */
-		0x0002D4EF,  /* SMEM coding of   -3 dB */
-		0x00032D64,  /* SMEM coding of   -2 dB */
-		0x000390A4,  /* SMEM coding of   -1 dB */
-		0x00040000,  /* SMEM coding of    0 dB */
-		0x00047CF2,  /* SMEM coding of    1 dB */
-		0x00050923,  /* SMEM coding of    2 dB */
-		0x0005A670,  /* SMEM coding of    3 dB */
-		0x000656EE,  /* SMEM coding of    4 dB */
-		0x00071CF5,  /* SMEM coding of    5 dB */
-		0x0007FB26,  /* SMEM coding of    6 dB */
-		0x0008F473,  /* SMEM coding of    7 dB */
-		0x000A0C2B,  /* SMEM coding of    8 dB */
-		0x000B4606,  /* SMEM coding of    9 dB */
-		0x000CA62C,  /* SMEM coding of   10 dB */
-		0x000E314A,  /* SMEM coding of   11 dB */
-		0x000FEC9E,  /* SMEM coding of   12 dB */
-		0x0011DE0A,  /* SMEM coding of   13 dB */
-		0x00140C28,  /* SMEM coding of   14 dB */
-		0x00167E60,  /* SMEM coding of   15 dB */
-		0x00193D00,  /* SMEM coding of   16 dB */
-		0x001C515D,  /* SMEM coding of   17 dB */
-		0x001FC5EB,  /* SMEM coding of   18 dB */
-		0x0023A668,  /* SMEM coding of   19 dB */
-		0x00280000,  /* SMEM coding of   20 dB */
-		0x002CE178,  /* SMEM coding of   21 dB */
-		0x00325B65,  /* SMEM coding of   22 dB */
-		0x00388062,  /* SMEM coding of   23 dB */
-		0x003F654E,  /* SMEM coding of   24 dB */
-		0x00472194,  /* SMEM coding of   25 dB */
-		0x004FCF7C,  /* SMEM coding of   26 dB */
-		0x00598C81,  /* SMEM coding of   27 dB */
-		0x006479B7,  /* SMEM coding of   28 dB */
-		0x0070BC3D,  /* SMEM coding of   29 dB */
-		0x007E7DB9,  /* SMEM coding of   30 dB */
-
-	};
-
-	const abe_uint32 abe_1_alpha_iir [64] = {
-	0x040002, 0x040002, 0x040002, 0x040002, /*    0 */
-	0x50E955, 0x48CA65, 0x40E321, 0x72BE78, /*    1 [ms] */
-	0x64BA68, 0x57DF14, 0x4C3D60, 0x41D690, /*    2 */
-	0x38A084, 0x308974, 0x297B00, 0x235C7C, /*    4 */
-	0x1E14B0, 0x198AF0, 0x15A800, 0x125660, /*    8 */
-	0x0F82A0, 0x0D1B5C, 0x0B113C, 0x0956CC, /*   16 */
-	0x07E054, 0x06A3B8, 0x059844, 0x04B680, /*   32 */
-	0x03F80C, 0x035774, 0x02D018, 0x025E0C, /*   64 */
-	0x7F8057, 0x6B482F, 0x5A4297, 0x4BEECB, /*  128 */
-	0x3FE00B, 0x35BAA7, 0x2D3143, 0x2602AF, /*  256 */
-	0x1FF803, 0x1AE2FB, 0x169C9F, 0x13042B, /*  512 */
-	0x0FFE03, 0x0D72E7, 0x0B4F4F, 0x0982CB, /* 1.024 [s] */
-	0x07FF83, 0x06B9CF, 0x05A7E7, 0x04C193, /* 2.048 */
-	0x03FFE3, 0x035CFF, 0x02D403, 0x0260D7, /* 4.096 */
-	0x01FFFB, 0x01AE87, 0x016A07, 0x01306F, /* 8.192 */
-		0x00FFFF, 0x00D743, 0x00B503, 0x009837,
-	};
-
-	const abe_uint32 abe_alpha_iir [64] = {
-	0x000000, 0x000000, 0x000000, 0x000000, /*    0 */
-	0x5E2D58, 0x6E6B3C, 0x7E39C0, 0x46A0C5, /*    1 [ms] */
-	0x4DA2CD, 0x541079, 0x59E151, 0x5F14B9, /*    2 */
-	0x63AFC1, 0x67BB45, 0x6B4281, 0x6E51C1, /*    4 */
-	0x70F5A9, 0x733A89, 0x752C01, 0x76D4D1, /*    8 */
-	0x783EB1, 0x797251, 0x7A7761, 0x7B549D, /*   16 */
-	0x7C0FD5, 0x7CAE25, 0x7D33DD, 0x7DA4C1, /*   32 */
-	0x7E03FD, 0x7E5449, 0x7E97F5, 0x7ED0F9, /*   64 */
-	0x7F0101, 0x7F2971, 0x7F4B7D, 0x7F6825, /*  128 */
-	0x7F8041, 0x7F948D, 0x7FA59D, 0x7FB3FD, /*  256 */
-	0x7FC011, 0x7FCA3D, 0x7FD2C9, 0x7FD9F9, /*  512 */
-	0x7FE005, 0x7FE51D, 0x7FE961, 0x7FECFD, /* 1.024 [s] */
-	0x7FF001, 0x7FF28D, 0x7FF4B1, 0x7FF67D, /* 2.048 */
-	0x7FF801, 0x7FF949, 0x7FFA59, 0x7FFB41, /* 4.096 */
-	0x7FFC01, 0x7FFCA5, 0x7FFD2D, 0x7FFDA1, /* 8.192  */
-		0x7FFE01, 0x7FFE51, 0x7FFE95, 0x7FFED1,
-	};
-
-	/*
- * ABE_DEBUG DATA
-	 */
-
-	/*
-	 *  IRQ and trace pointer in DMEM:
-	 *  FW updates a write pointer at "MCU_IRQ_FIFO_ptr_labelID", the read pointer is in HAL
-	 */
-	abe_uint32 abe_irq_dbg_read_ptr;
-
-	/*
-	 *  General circular buffer used to trace APIs calls and AE activity.
-	 */
-	abe_uint32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof];
-	abe_uint32 abe_dbg_activity_log_write_pointer;
-	abe_uint32 abe_dbg_mask;
-
-	/*
-	 *  Global variable holding parameter errors
-	 */
-
-	abe_uint32 abe_dbg_param;
-
-
-	/*
-	 *  Output of messages selector
-	 */
-	abe_uint32 abe_dbg_output;
-
-	/*
-	 *  last parameters
-	 */
-
-#define SIZE_PARAM      10
-
-	abe_uint32 param1[SIZE_PARAM];
-	abe_uint32 param2[SIZE_PARAM];
-	abe_uint32 param3[SIZE_PARAM];
-	abe_uint32 param4[SIZE_PARAM];
-	abe_uint32 param5[SIZE_PARAM];
-
-	/*
- * END ABE_DEBUG DATA
-	 */
-
-	volatile abe_uint32		just_to_avoid_the_many_warnings;
-	volatile abe_gain_t		just_to_avoid_the_many_warnings_abe_gain_t;
-	volatile abe_ramp_t		just_to_avoid_the_many_warnings_abe_ramp_t;
-	volatile abe_dma_t		just_to_avoid_the_many_warnings_abe_dma_t;
-	volatile abe_port_id		just_to_avoid_the_many_warnings_abe_port_id;
-	volatile abe_millis_t		just_to_avoid_the_many_warnings_abe_millis_t;
-	volatile abe_micros_t		just_to_avoid_the_many_warnings_abe_micros_t;
-	volatile abe_patch_rev		just_to_avoid_the_many_warnings_abe_patch_rev;
-	volatile abe_sequence_t		just_to_avoid_the_many_warnings_abe_sequence_t;
-	volatile abe_ana_port_id	just_to_avoid_the_many_warnings_abe_ana_port_id;
-	volatile abe_time_stamp_t	just_to_avoid_the_many_warnings_abe_time_stamp_t;
-	volatile abe_data_format_t	just_to_avoid_the_many_warnings_abe_data_format_t;
-	volatile abe_port_protocol_t	just_to_avoid_the_many_warnings_abe_port_protocol_t;
-	volatile abe_router_t		just_to_avoid_the_many_warnings_abe_router_t;
-	volatile abe_router_id		just_to_avoid_the_many_warnings_abe_router_id;
-
-
-#endif /* abe_dat_def */
diff --git a/sound/soc/omap/abe/abe_dbg.c b/sound/soc/omap/abe/abe_dbg.c
index ec0360f0661d..d2717f28d3ac 100644
--- a/sound/soc/omap/abe/abe_dbg.c
+++ b/sound/soc/omap/abe/abe_dbg.c
@@ -18,9 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
 /**
  * abe_dbg_log - Log ABE trace inside circular buffer
  * @x: data to be logged
@@ -34,75 +32,70 @@
  *
  *	saves data in the log file
  */
-void    abe_dbg_log (u32 x, u32 y, u32 z, u32 t)
+void abe_dbg_log(u32 x, u32 y, u32 z, u32 t)
 {
 	u32 time_stamp, data;
-
 	if (abe_dbg_activity_log_write_pointer >= (D_DEBUG_HAL_TASK_sizeof - 2))
 		abe_dbg_activity_log_write_pointer = 0;
-
 	/* copy in DMEM trace buffer and CortexA9 local buffer and a small 7
-		words circular buffer of the DMA trace ending with 0x55555555
-		(tag for last word) */
-	abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_loopCounter_ADDR,
-			(u32 *)&time_stamp, sizeof (time_stamp));
-	abe_dbg_activity_log [abe_dbg_activity_log_write_pointer] = time_stamp;
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR +
-			(abe_dbg_activity_log_write_pointer<<2), (u32 *)&time_stamp,
-			sizeof (time_stamp));
-	abe_dbg_activity_log_write_pointer ++;
-
-	data = ((x&MAX_UINT8)<< 24) | ((y&MAX_UINT8)<< 16) | ((z&MAX_UINT8)<< 8)
-	       | (t&MAX_UINT8);
-	abe_dbg_activity_log [abe_dbg_activity_log_write_pointer] = data;
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR +
-			(abe_dbg_activity_log_write_pointer<<2), (u32 *)&data, sizeof (data));
-
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR +
-			((abe_dbg_activity_log_write_pointer<<2) & (D_DEBUG_FIFO_HAL_sizeof -1)),
-			(u32 *)&data, sizeof (data));
+	   words circular buffer of the DMA trace ending with 0x55555555
+	   (tag for last word) */
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, D_loopCounter_ADDR,
+		       (u32 *) &time_stamp, sizeof(time_stamp));
+	abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = time_stamp;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR +
+		       (abe_dbg_activity_log_write_pointer << 2),
+		       (u32 *) &time_stamp, sizeof(time_stamp));
+	abe_dbg_activity_log_write_pointer++;
+	data = ((x & MAX_UINT8) << 24) | ((y & MAX_UINT8) << 16) |
+		((z & MAX_UINT8) << 8)
+		| (t & MAX_UINT8);
+	abe_dbg_activity_log[abe_dbg_activity_log_write_pointer] = data;
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_HAL_TASK_ADDR +
+		       (abe_dbg_activity_log_write_pointer << 2),
+		       (u32 *) &data, sizeof(data));
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		       D_DEBUG_FIFO_HAL_ADDR +
+		       ((abe_dbg_activity_log_write_pointer << 2) &
+			(D_DEBUG_FIFO_HAL_sizeof - 1)), (u32 *) &data,
+		       sizeof(data));
 	data = ABE_DBG_MAGIC_NUMBER;
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR +
-			(((abe_dbg_activity_log_write_pointer+1)<<2) & (D_DEBUG_FIFO_HAL_sizeof -1)),
-			(u32 *)&data, sizeof (data));
-	abe_dbg_activity_log_write_pointer ++;
-
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_DEBUG_FIFO_HAL_ADDR +
+		       (((abe_dbg_activity_log_write_pointer +
+			  1) << 2) &(D_DEBUG_FIFO_HAL_sizeof - 1)),
+		       (u32 *) &data, sizeof(data));
+	abe_dbg_activity_log_write_pointer++;
 	if (abe_dbg_activity_log_write_pointer >= D_DEBUG_HAL_TASK_sizeof)
 		abe_dbg_activity_log_write_pointer = 0;
-
 }
-
 /**
  * abe_debug_output_pins
  * @x: d
  *
  * set the debug output pins of AESS
  */
-void    abe_debug_output_pins (u32 x)
+void abe_debug_output_pins(u32 x)
 {
 }
-
 /**
  * abe_dbg_error_log -  Log ABE error
  * @x: error to log
  *
  * log the error codes
  */
-void    abe_dbg_error_log (u32 x)
+void abe_dbg_error_log(u32 x)
 {
-	abe_dbg_log (x,  MAX_UINT8,  MAX_UINT8,  MAX_UINT8);
+	abe_dbg_log(x, MAX_UINT8, MAX_UINT8, MAX_UINT8);
 }
-
 /**
  * abe_debugger
  * @x: error to log
  *
  * log error for debugger
  */
-void    abe_debugger (u32 x)
+void abe_debugger(u32 x)
 {
 }
-
 /**
  * abe_load_embeddded_patterns
  *
@@ -115,92 +108,90 @@ void    abe_debugger (u32 x)
  *  N = 60; B = 2; F=[4/N 8/N]; gen_and_save('dbg_amic.txt', B, F, N, S);
  *  N = 10; B = 6; F=[1/N 2/N 3/N 1/N 2/N 3/N]; gen_and_save('dbg_dmic.txt', B, F, N, S);
 */
-void abe_load_embeddded_patterns (void)
+void abe_load_embeddded_patterns(void)
 {
 	u32 i;
-
 #define patterns_96k_len 48
 	const long patterns_96k[patterns_96k_len] = {
-		1620480,     1452800,
-		1452800,      838656,
-		1186304,           0,
-		838656,     -838912,
-		434176,    -1453056,
-		0,    -1677824,
-		-434432,    -1453056,
-		-838912,     -838912,
-		-1186560,        -256,
-		-1453056,      838656,
-		-1620736,     1452800,
-		-1677824,     1677568,
-		-1620736,     1452800,
-		-1453056,      838656,
-		-1186560,           0,
-		-838912,     -838912,
-		-434432,    -1453056,
-		-256,    -1677824,
-		434176,    -1453056,
-		838656,     -838912,
-		1186304,        -256,
-		1452800,      838656,
-		1620480,     1452800,
-		1677568,     1677568,
+		1620480, 1452800,
+		1452800, 838656,
+		1186304, 0,
+		838656, -838912,
+		434176, -1453056,
+		0, -1677824,
+		-434432, -1453056,
+		-838912, -838912,
+		-1186560, -256,
+		-1453056, 838656,
+		-1620736, 1452800,
+		-1677824, 1677568,
+		-1620736, 1452800,
+		-1453056, 838656,
+		-1186560, 0,
+		-838912, -838912,
+		-434432, -1453056,
+		-256, -1677824,
+		434176, -1453056,
+		838656, -838912,
+		1186304, -256,
+		1452800, 838656,
+		1620480, 1452800,
+		1677568, 1677568,
 	};
 #define patterns_48k_len 24
 	const long patterns_48k[patterns_48k_len] = {
-		1452800,      838656,
-		838656,     -838912,
-		0,    -1677824,
-		-838912,     -838912,
-		-1453056,      838656,
-		-1677824,     1677568,
-		-1453056,      838656,
-		-838912,     -838912,
-		-256,    -1677824,
-		838656,     -838912,
-		1452800,      838656,
-		1677568,     1677568,
+		1452800, 838656,
+		838656, -838912,
+		0, -1677824,
+		-838912, -838912,
+		-1453056, 838656,
+		-1677824, 1677568,
+		-1453056, 838656,
+		-838912, -838912,
+		-256, -1677824,
+		838656, -838912,
+		1452800, 838656,
+		1677568, 1677568,
 	};
 #define patterns_24k_len 12
 	const long patterns_24k[patterns_24k_len] = {
-		838656,     -838912,
-		-838912,     -838912,
-		-1677824,     1677568,
-		-838912,     -838912,
-		838656,     -838912,
-		1677568,     1677568,
+		838656, -838912,
+		-838912, -838912,
+		-1677824, 1677568,
+		-838912, -838912,
+		838656, -838912,
+		1677568, 1677568,
 	};
 #define patterns_16k_len 8
 	const long patterns_16k[patterns_16k_len] = {
-		0,           0,
-		-1677824,    -1677824,
-		-256,        -256,
-		1677568,     1677568,
+		0, 0,
+		-1677824, -1677824,
+		-256, -256,
+		1677568, 1677568,
 	};
 #define patterns_8k_len 4
 	const long patterns_8k[patterns_8k_len] = {
-		1677568,    -1677824,
-		1677568,     1677568,
+		1677568, -1677824,
+		1677568, 1677568,
 	};
-
 	for (i = 0; i < patterns_8k_len; i++)
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM,
-				(S_DBG_8K_PATTERN_ADDR *8)+(i*4),
-				(u32 *)(&(patterns_8k[i])),  4);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       (S_DBG_8K_PATTERN_ADDR * 8) + (i * 4),
+			       (u32 *) (&(patterns_8k[i])), 4);
 	for (i = 0; i < patterns_16k_len; i++)
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM,
-				(S_DBG_16K_PATTERN_ADDR *8)+(i*4),
-				(u32 *)(&(patterns_16k[i])), 4);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       (S_DBG_16K_PATTERN_ADDR * 8) + (i * 4),
+			       (u32 *) (&(patterns_16k[i])), 4);
 	for (i = 0; i < patterns_24k_len; i++)
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM,
-				(S_DBG_24K_PATTERN_ADDR *8)+(i*4),
-				(u32 *)(&(patterns_24k[i])), 4);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       (S_DBG_24K_PATTERN_ADDR * 8) + (i * 4),
+			       (u32 *) (&(patterns_24k[i])), 4);
 	for (i = 0; i < patterns_48k_len; i++)
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM,
-				(S_DBG_48K_PATTERN_ADDR *8)+(i*4),
-				(u32 *)(&(patterns_48k[i])), 4);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       (S_DBG_48K_PATTERN_ADDR * 8) + (i * 4),
+			       (u32 *) (&(patterns_48k[i])), 4);
 	for (i = 0; i < patterns_96k_len; i++)
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_SMEM,
-				(S_DBG_96K_PATTERN_ADDR *8)+(i*4),
-				(u32 *)(&(patterns_96k[i])), 4);
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM,
+			       (S_DBG_96K_PATTERN_ADDR * 8) + (i * 4),
+			       (u32 *) (&(patterns_96k[i])), 4);
 }
diff --git a/sound/soc/omap/abe/abe_dbg.h b/sound/soc/omap/abe/abe_dbg.h
index ffa421eedc5e..1e041db78309 100644
--- a/sound/soc/omap/abe/abe_dbg.h
+++ b/sound/soc/omap/abe/abe_dbg.h
@@ -18,9 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
 /*
  * DEFINE
  */
@@ -28,7 +26,6 @@
 #define TERMINAL_OUTPUT 1
 #define LINE_OUTPUT 2
 #define DEBUG_TRACE_OUTPUT 3
-
 /*
  *	Debug trace format
  *	TIME 2 bytes from ABE : 4kHz period of the FW scheduler
@@ -36,21 +33,14 @@
  * From 0 to 16 bytes : parameters of the subroutine
  * on every 32 dumps a tag is pushed on the debug trace : 0x55555555
  */
-
-
 #define dbg_bitfield_offset 8
-
 #define dbg_api_calls 0
 #define dbg_mapi (1L << (dbg_api_calls + dbg_bitfield_offset))
-
 #define dbg_external_data_access 1
 #define dbg_mdata (1L << (dbg_external_data_access + dbg_bitfield_offset))
-
 #define dbg_err_codes 2
 #define dbg_merr (1L << (dbg_api_calls + dbg_bitfield_offset))
-
 #define ABE_DBG_MAGIC_NUMBER 0x55555555
-
 /*
  * IDs used for traces
  */
@@ -122,8 +112,6 @@
 #define id_remote_debugger_interface (66 + dbg_mapi)
 #define id_enable_test_pattern (67 + dbg_mapi)
 #define id_connect_tdm_port (68 + dbg_mapi)
-
-
 /*
  * IDs used for error codes
  */
@@ -135,40 +123,27 @@
 #define ABE_SET_ATC_MEMORY_CONFIG_ERR (5 + dbg_merr)
 #define ABE_PROTOCOL_ERROR (6 + dbg_merr)
 #define ABE_PARAMETER_ERROR (7 + dbg_merr)
-
 /*  port programmed while still running */
 #define ABE_PORT_REPROGRAMMING (8 + dbg_merr)
 #define ABE_READ_USE_CASE_OPP_ERR (9 + dbg_merr)
 #define ABE_PARAMETER_OVERFLOW (10 + dbg_merr)
 #define ABE_FW_FIFO_WRITE_PTR_ERR (11 + dbg_merr)
-
-
 /*
  * IDs used for error codes
  */
 /* error in the LIB.C file */
 #define ERR_LIB (1 << 1)
-
 /* error in the API.C file */
 #define ERR_API (1 << 2)
-
 /* error in the INI.C file */
 #define ERR_INI (1 << 3)
-
 /* error in the SEQ.C file */
 #define ERR_SEQ (1 << 4)
-
 /* error in the DBG.C file */
 #define ERR_DBG (1 << 5)
-
 /* error in the DBG.C file */
 #define ERR_EXT (1 << 6)
-
 /*
  * MACROS
  */
-#ifdef CONFIG_OMAP_ABE_DEBUG
-#define _log(x,y,z,t) {if(x&abe_dbg_mask)abe_dbg_log(x,y,z,t);}
-#else
-#define _log(x,y,z,t) {;}
-#endif
+#define _log(x,y,z,t) {}
diff --git a/sound/soc/omap/abe/abe_def.h b/sound/soc/omap/abe/abe_def.h
index f524cc266019..dc9ba34dc11e 100644
--- a/sound/soc/omap/abe/abe_def.h
+++ b/sound/soc/omap/abe/abe_def.h
@@ -18,38 +18,27 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #ifndef _ABE_DEF_H_
 #define _ABE_DEF_H_
-
 /*
  * HARDWARE AND PERIPHERAL DEFINITIONS
  */
-
 /* MM_DL */
 #define ABE_CBPR0_IDX 0
-
 /* VX_DL */
 #define ABE_CBPR1_IDX 1
-
 /* VX_UL */
 #define ABE_CBPR2_IDX 2
-
 /* MM_UL */
 #define ABE_CBPR3_IDX 3
-
 /* MM_UL2 */
 #define ABE_CBPR4_IDX 4
-
 /* TONES */
 #define ABE_CBPR5_IDX 5
-
 /* VIB */
 #define ABE_CBPR6_IDX 6
-
 /* DEBUG/CTL */
 #define ABE_CBPR7_IDX 7
-
 #define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
 #define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
 #define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
@@ -58,72 +47,52 @@
 #define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
 #define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
 #define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
-
 #define PING_PONG_WITH_MCU_IRQ	 1
 #define PING_PONG_WITH_DSP_IRQ	 2
-
 /* ID used for LIB memory copy subroutines */
 #define COPY_FROM_ABE_TO_HOST 1
 #define COPY_FROM_HOST_TO_ABE 2
-
 /*
  * INTERNAL DEFINITIONS
  */
-
 #define ABE_FIRMWARE_MAX_SIZE 26629
-
 /* 24 Q6.26 coefficients */
 #define NBEQ1 25
-
 /* 2x12 Q6.26 coefficients */
 #define NBEQ2 13
-
 /* TBD APS first set of parameters */
 #define NBAPS1 10
-
 /* TBD APS second set of parameters */
 #define NBAPS2 10
-
 /* Mixer used for sending tones to the uplink voice path */
 #define NBMIX_AUDIO_UL 2
-
 /* Main downlink mixer */
 #define NBMIX_DL1 4
-
 /* Handsfree downlink mixer */
 #define NBMIX_DL2 4
-
 /* Side-tone mixer */
 #define NBMIX_SDT 2
-
 /* Echo reference mixer */
 #define NBMIX_ECHO 2
-
 /* Voice record mixer */
 #define NBMIX_VXREC 4
-
 /* unsigned version of (-1) */
 #define CC_M1 0xFF
 #define CS_M1 0xFFFF
 #define CL_M1 0xFFFFFFFFL
-
 /*
 	Mixer ID 	 Input port ID	 Comments
 	DL1_MIXER	 0 MMDL path
 	 1 MMUL2 path
 	 2 VXDL path
 	 3 TONES path
-
 	SDT_MIXER	 0 Uplink path
 	 1 Downlink path
-
 	ECHO_MIXER	 0 DL1_MIXER path
 	 1 DL2_MIXER path
-
 	AUDUL_MIXER	 0 TONES_DL path
 	 1 Uplink path
 	 2 MM_DL path
-
 	VXREC_MIXER	 0 TONES_DL path
 	 1 VX_DL path
 	 2 MM_DL path
@@ -133,116 +102,83 @@
 #define MIX_VXUL_INPUT_TONES 1
 #define MIX_VXUL_INPUT_VX_UL 2
 #define MIX_VXUL_INPUT_VX_DL 3
-
 #define MIX_DL1_INPUT_MM_DL 0
 #define MIX_DL1_INPUT_MM_UL2 1
 #define MIX_DL1_INPUT_VX_DL 2
 #define MIX_DL1_INPUT_TONES 3
-
 #define MIX_DL2_INPUT_MM_DL 0
 #define MIX_DL2_INPUT_MM_UL2 1
 #define MIX_DL2_INPUT_VX_DL 2
 #define MIX_DL2_INPUT_TONES 3
-
 #define MIX_SDT_INPUT_UP_MIXER	0
 #define MIX_SDT_INPUT_DL1_MIXER 1
-
 #define MIX_AUDUL_INPUT_MM_DL 0
 #define MIX_AUDUL_INPUT_TONES 1
 #define MIX_AUDUL_INPUT_UPLINK 2
 #define MIX_AUDUL_INPUT_VX_DL 3
-
 #define MIX_VXREC_INPUT_MM_DL 0
 #define MIX_VXREC_INPUT_TONES 1
 #define MIX_VXREC_INPUT_VX_UL 2
 #define MIX_VXREC_INPUT_VX_DL 3
-
 /* nb of samples to route */
 #define NBROUTE_UL 16
-
 /* 10 routing tables max */
 #define NBROUTE_CONFIG_MAX 10
-
 /* 5 pre-computed routing tables */
 #define NBROUTE_CONFIG 5
-
 /* AMIC on VX_UL */
 #define UPROUTE_CONFIG_AMIC 0
-
 /* DMIC first pair on VX_UL */
 #define UPROUTE_CONFIG_DMIC1 1
-
 /* DMIC second pair on VX_UL */
 #define UPROUTE_CONFIG_DMIC2 2
-
 /* DMIC last pair on VX_UL */
 #define UPROUTE_CONFIG_DMIC3 3
-
 /* BT_UL on VX_UL */
 #define UPROUTE_CONFIG_BT 4
-
 /* call-back indexes */
 #define MAXCALLBACK 100
-
 /* subroutines */
 #define MAXNBSUBROUTINE 100
-
 /* time controlled sequenced */
 #define MAXNBSEQUENCE 20
-
 /* maximum simultaneous active sequences */
 #define MAXACTIVESEQUENCE 20
-
 /* max number of steps in the sequences */
 #define MAXSEQUENCESTEPS 2
-
 /* max number of feature associated to a port */
 #define MAXFEATUREPORT 12
 #define SUB_0_PARAM 0
-
 /* number of parameters per sequence calls */
 #define SUB_1_PARAM 1
 #define SUB_2_PARAM 2
 #define SUB_3_PARAM 3
 #define SUB_4_PARAM 4
-
 /* active sequence mask = 0 means the line is free */
 #define FREE_LINE 0
-
 /* no ask for collision protection */
 #define NOMASK (1 << 0)
-
 /* do not allow a PDM OFF during the execution of this sequence */
 #define MASK_PDM_OFF (1 << 1)
-
 /* do not allow a PDM ON during the execution of this sequence */
 #define MASK_PDM_ON (1 << 2)
-
 /* explicit name of the feature */
 #define NBCHARFEATURENAME 16
-
 /* explicit name of the port */
 #define NBCHARPORTNAME 16
-
 /* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
 #define SNK_P ABE_ATC_DIRECTION_IN
-
 /* source / ouptut port */
 #define SRC_P ABE_ATC_DIRECTION_OUT
-
 /* no ASRC applied */
 #define NODRIFT 0
-
 /* for abe_set_asrc_drift_control */
 #define FORCED_DRIFT_CONTROL 1
-
 /* for abe_set_asrc_drift_control */
 #define ADPATIVE_DRIFT_CONTROL 2
-
 #define DOPPMODE32_OPP100 (0x00000010 | (0x00000000<<16))
 #define DOPPMODE32_OPP50 (0x0000000C | (0x0000004<<16))
 #define DOPPMODE32_OPP25 (0x0000004 | (0x0000000C<<16))
-
 /*
  * ABE CONST AREA FOR PARAMETERS TRANSLATION
  */
@@ -251,13 +187,11 @@
 #define sizeof_db2lin_table (1+ ((max_mdb - min_mdb)/100))
 #define sizeof_alpha_iir_table 61
 #define sizeof_beta_iir_table 61
-
 #define GAIN_MAXIMUM 3000L
 #define GAIN_24dB 2400L
 #define GAIN_18dB 1800L
 #define GAIN_12dB 1200L
 #define GAIN_6dB 600L
-
 /* default gain = 1 */
 #define GAIN_0dB  0L
 #define GAIN_M6dB -600L
@@ -267,13 +201,10 @@
 #define GAIN_M30dB -3000L
 #define GAIN_M40dB -4000L
 #define GAIN_M50dB -5000L
-
 /* muted gain = -120 decibels */
 #define MUTE_GAIN -12000L
 #define GAIN_MUTE MUTE_GAIN
-
 #define RAMP_MINLENGTH 3L
-
 /* ramp_t is in milli- seconds */
 #define RAMP_0MS 0L
 #define RAMP_1MS 1L
@@ -287,55 +218,42 @@
 #define RAMP_500MS  500L
 #define RAMP_1000MS  1000L
 #define RAMP_MAXLENGTH  10000L
-
 /* for abe_translate_gain_format */
 #define LINABE_TO_DECIBELS 1
 #define DECIBELS_TO_LINABE 2
-
 /* for abe_translate_ramp_format */
 #define IIRABE_TO_MICROS 1
 #define MICROS_TO_IIABE 2
-
 /*
  * ABE CONST AREA FOR PERIPHERAL TUNING
  */
-
 /* port idled IDLE_P */
 #define OMAP_ABE_PORT_ACTIVITY_IDLE	1
-
+/* port initialized, ready to be activated  */
+#define OMAP_ABE_PORT_INITIALIZED	 3
 /* port activated RUN_P */
 #define OMAP_ABE_PORT_ACTIVITY_RUNNING	 2
-
 #define NOCALLBACK 0
 #define NOPARAMETER 0
-
 /* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
 #define MCPDM_UL_ITER 4
-
 /* All the McPDM FIFOs are enabled simultaneously */
 #define MCPDM_DL_ITER 12
-
 /* All the DMIC FIFOs are enabled simultaneously */
 #define DMIC_ITER 12
-
 /* port / flow management */
 #define DEFAULT_THR_READ 1
-
 /* port / flow management */
 #define DEFAULT_THR_WRITE 1
-
 /* allows control on the PDM line */
 #define DEFAULT_CONTROL_MCPDMDL 1
-
 /* TBD later if needed */
 #define MAX_PINGPONG_BUFFERS 2
-
 /*
  * Indexes to the subroutines
  */
 #define SUB_WRITE_MIXER 1
 #define SUB_WRITE_PORT_GAIN 2
-
 /* OLD WAY */
 #define c_feat_init_eq 1
 #define c_feat_read_eq1 2
@@ -344,14 +262,14 @@
 #define c_write_eq2 5
 #define c_feat_read_eq3 6
 #define c_write_eq3 7
-
+/* ATC FIFOs pointer margin before the scheduler is resynchronized */
+#define JITTER_MARGIN 3
+/* max number of gain to be controlled by HAL */
+#define MAX_NBGAIN_CMEM 34
 /*
  * MACROS
  */
-
 #define maximum(a,b) (((a)<(b))?(b):(a))
 #define minimum(a,b) (((a)>(b))?(b):(a))
 #define absolute(a) (((a)>0)?(a):((-1)*(a)))
-
-
-#endif	/* _ABE_DEF_H_ */
+#endif/* _ABE_DEF_H_ */
diff --git a/sound/soc/omap/abe/abe_define.h b/sound/soc/omap/abe/abe_define.h
index 49ce1b581a62..6cf96eba3114 100644
--- a/sound/soc/omap/abe/abe_define.h
+++ b/sound/soc/omap/abe/abe_define.h
@@ -20,10 +20,9 @@
  */
 #ifndef _ABE_DEFINE_H_
 #define _ABE_DEFINE_H_
-
-#define ATC_DESCRIPTOR_NUMBER                               64 
-#define PROCESSING_SLOTS                                    25 
-#define TASK_POOL_LENGTH                                    128 
+#define ATC_DESCRIPTOR_NUMBER                               64
+#define PROCESSING_SLOTS                                    25
+#define TASK_POOL_LENGTH                                    128
 #define MCU_IRQ                                            0x24
 #define MCU_IRQ_SHIFT2                                     0x90
 #define DMA_REQ_SHIFT2                                     0x210
@@ -32,36 +31,35 @@
 #define IRQtag_COUNT                                       0x000c
 #define IRQtag_PP                                          0x000d
 #define DMAreq_7                                           0x0080
-#define IRQ_FIFO_LENGTH                                     16 
-#define SDT_EQ_ORDER                                        4 
-#define DL_EQ_ORDER                                         12 
-#define MIC_FILTER_ORDER                                    4 
-#define GAINS_WITH_RAMP1                                    14 
-#define GAINS_WITH_RAMP2                                    22 
-#define GAINS_WITH_RAMP_TOTAL                               36 
-#define EANC_FIR_TAPS                                       21 
-#define EANC_IIR_ORDER                                      8 
-#define ASRC_MEMLENGTH                                      40 
-#define ASRC_UL_VX_FIR_L                                    19 
-#define ASRC_DL_VX_FIR_L                                    19 
-#define ASRC_DL_MM_FIR_L                                    18 
-#define ASRC_margin                                         2 
-#define ASRC_N_8k                                           2 
-#define ASRC_N_16k                                          4 
-#define ASRC_N_48k                                          12 
-#define VIBRA_N                                             5 
-#define VIBRA1_IIR_MEMSIZE                                  11 
-#define SAMP_LOOP_96K                                       24 
-#define SAMP_LOOP_48K                                       12 
-#define SAMP_LOOP_16K                                       4 
-#define SAMP_LOOP_8K                                        2 
-#define INPUT_SCALE_SHIFTM2                                 5264 
-#define OUTPUT_SCALE_SHIFTM2                                5268 
-#define MUTE_SCALING                                        5272 
-#define ABE_PMEM                                            1 
-#define ABE_CMEM                                            2 
-#define ABE_SMEM                                            3 
-#define ABE_DMEM                                            4 
-#define ABE_ATC                                             5 
-
-#endif /* _ABE_DEFINE_H_ */
+#define IRQ_FIFO_LENGTH                                     16
+#define SDT_EQ_ORDER                                        4
+#define DL_EQ_ORDER                                         12
+#define MIC_FILTER_ORDER                                    4
+#define GAINS_WITH_RAMP1                                    14
+#define GAINS_WITH_RAMP2                                    22
+#define GAINS_WITH_RAMP_TOTAL                               36
+#define EANC_FIR_TAPS                                       21
+#define EANC_IIR_ORDER                                      8
+#define ASRC_MEMLENGTH                                      40
+#define ASRC_UL_VX_FIR_L                                    19
+#define ASRC_DL_VX_FIR_L                                    19
+#define ASRC_MM_EXT_IN_FIR_L                                18
+#define ASRC_margin                                         2
+#define ASRC_N_8k                                           2
+#define ASRC_N_16k                                          4
+#define ASRC_N_48k                                          12
+#define VIBRA_N                                             5
+#define VIBRA1_IIR_MEMSIZE                                  11
+#define SAMP_LOOP_96K                                       24
+#define SAMP_LOOP_48K                                       12
+#define SAMP_LOOP_16K                                       4
+#define SAMP_LOOP_8K                                        2
+#define INPUT_SCALE_SHIFTM2                                 5348
+#define OUTPUT_SCALE_SHIFTM2                                5352
+#define MUTE_SCALING                                        5356
+#define ABE_PMEM                                            1
+#define ABE_CMEM                                            2
+#define ABE_SMEM                                            3
+#define ABE_DMEM                                            4
+#define ABE_ATC                                             5
+#endif/* _ABE_DEFINE_H_ */
diff --git a/sound/soc/omap/abe/abe_dm_addr.h b/sound/soc/omap/abe/abe_dm_addr.h
index 93243de470f7..bdd0019b3d1c 100644
--- a/sound/soc/omap/abe/abe_dm_addr.h
+++ b/sound/soc/omap/abe/abe_dm_addr.h
@@ -20,394 +20,295 @@
  */
 #ifndef _ABE_DM_ADDR_H_
 #define _ABE_DM_ADDR_H_
-
-#define D_atcDescriptors_ADDR                               0 
-#define D_atcDescriptors_ADDR_END                           511 
-#define D_atcDescriptors_sizeof                             512 
-
-#define stack_ADDR                                          512 
-#define stack_ADDR_END                                      623 
-#define stack_sizeof                                        112 
-
-#define D_version_ADDR                                      624 
-#define D_version_ADDR_END                                  627 
-#define D_version_sizeof                                    4 
-
-#define D_BT_DL_FIFO_ADDR                                   1024 
-#define D_BT_DL_FIFO_ADDR_END                               1503 
-#define D_BT_DL_FIFO_sizeof                                 480 
-
-#define D_BT_UL_FIFO_ADDR                                   1536 
-#define D_BT_UL_FIFO_ADDR_END                               2015 
-#define D_BT_UL_FIFO_sizeof                                 480 
-
-#define D_MM_EXT_OUT_FIFO_ADDR                              2048 
-#define D_MM_EXT_OUT_FIFO_ADDR_END                          2527 
-#define D_MM_EXT_OUT_FIFO_sizeof                            480 
-
-#define D_MM_EXT_IN_FIFO_ADDR                               2560 
-#define D_MM_EXT_IN_FIFO_ADDR_END                           3039 
-#define D_MM_EXT_IN_FIFO_sizeof                             480 
-
-#define D_MM_UL2_FIFO_ADDR                                  3072 
-#define D_MM_UL2_FIFO_ADDR_END                              3551 
-#define D_MM_UL2_FIFO_sizeof                                480 
-
-#define D_VX_UL_FIFO_ADDR                                   3584 
-#define D_VX_UL_FIFO_ADDR_END                               4063 
-#define D_VX_UL_FIFO_sizeof                                 480 
-
-#define D_VX_DL_FIFO_ADDR                                   4096 
-#define D_VX_DL_FIFO_ADDR_END                               4575 
-#define D_VX_DL_FIFO_sizeof                                 480 
-
-#define D_DMIC_UL_FIFO_ADDR                                 4608 
-#define D_DMIC_UL_FIFO_ADDR_END                             5087 
-#define D_DMIC_UL_FIFO_sizeof                               480 
-
-#define D_MM_UL_FIFO_ADDR                                   5120 
-#define D_MM_UL_FIFO_ADDR_END                               5599 
-#define D_MM_UL_FIFO_sizeof                                 480 
-
-#define D_MM_DL_FIFO_ADDR                                   5632 
-#define D_MM_DL_FIFO_ADDR_END                               6111 
-#define D_MM_DL_FIFO_sizeof                                 480 
-
-#define D_TONES_DL_FIFO_ADDR                                6144 
-#define D_TONES_DL_FIFO_ADDR_END                            6623 
-#define D_TONES_DL_FIFO_sizeof                              480 
-
-#define D_VIB_DL_FIFO_ADDR                                  6656 
-#define D_VIB_DL_FIFO_ADDR_END                              7135 
-#define D_VIB_DL_FIFO_sizeof                                480 
-
-#define D_McPDM_DL_FIFO_ADDR                                7168 
-#define D_McPDM_DL_FIFO_ADDR_END                            7647 
-#define D_McPDM_DL_FIFO_sizeof                              480 
-
-#define D_McPDM_UL_FIFO_ADDR                                7680 
-#define D_McPDM_UL_FIFO_ADDR_END                            8159 
-#define D_McPDM_UL_FIFO_sizeof                              480 
-
-#define D_DEBUG_FIFO_ADDR                                   8160 
-#define D_DEBUG_FIFO_ADDR_END                               8255 
-#define D_DEBUG_FIFO_sizeof                                 96 
-
-#define D_DEBUG_FIFO_HAL_ADDR                               8256 
-#define D_DEBUG_FIFO_HAL_ADDR_END                           8287 
-#define D_DEBUG_FIFO_HAL_sizeof                             32 
-
-#define D_IOdescr_ADDR                                      8288 
-#define D_IOdescr_ADDR_END                                  8927 
-#define D_IOdescr_sizeof                                    640 
-
-#define d_zero_ADDR                                         8928 
-#define d_zero_ADDR_END                                     8931 
-#define d_zero_sizeof                                       4 
-
-#define dbg_trace1_ADDR                                     8932 
-#define dbg_trace1_ADDR_END                                 8932 
-#define dbg_trace1_sizeof                                   1 
-
-#define dbg_trace2_ADDR                                     8933 
-#define dbg_trace2_ADDR_END                                 8933 
-#define dbg_trace2_sizeof                                   1 
-
-#define dbg_trace3_ADDR                                     8934 
-#define dbg_trace3_ADDR_END                                 8934 
-#define dbg_trace3_sizeof                                   1 
-
-#define D_multiFrame_ADDR                                   8936 
-#define D_multiFrame_ADDR_END                               9335 
-#define D_multiFrame_sizeof                                 400 
-
-#define D_tasksList_ADDR                                    9336 
-#define D_tasksList_ADDR_END                                11383 
-#define D_tasksList_sizeof                                  2048 
-
-#define D_idleTask_ADDR                                     11384 
-#define D_idleTask_ADDR_END                                 11385 
-#define D_idleTask_sizeof                                   2 
-
-#define D_typeLengthCheck_ADDR                              11386 
-#define D_typeLengthCheck_ADDR_END                          11387 
-#define D_typeLengthCheck_sizeof                            2 
-
-#define D_maxTaskBytesInSlot_ADDR                           11388 
-#define D_maxTaskBytesInSlot_ADDR_END                       11389 
-#define D_maxTaskBytesInSlot_sizeof                         2 
-
-#define D_rewindTaskBytes_ADDR                              11390 
-#define D_rewindTaskBytes_ADDR_END                          11391 
-#define D_rewindTaskBytes_sizeof                            2 
-
-#define D_pCurrentTask_ADDR                                 11392 
-#define D_pCurrentTask_ADDR_END                             11393 
-#define D_pCurrentTask_sizeof                               2 
-
-#define D_pFastLoopBack_ADDR                                11394 
-#define D_pFastLoopBack_ADDR_END                            11395 
-#define D_pFastLoopBack_sizeof                              2 
-
-#define D_pNextFastLoopBack_ADDR                            11396 
-#define D_pNextFastLoopBack_ADDR_END                        11399 
-#define D_pNextFastLoopBack_sizeof                          4 
-
-#define D_ppCurrentTask_ADDR                                11400 
-#define D_ppCurrentTask_ADDR_END                            11401 
-#define D_ppCurrentTask_sizeof                              2 
-
-#define D_slotCounter_ADDR                                  11404 
-#define D_slotCounter_ADDR_END                              11405 
-#define D_slotCounter_sizeof                                2 
-
-#define D_loopCounter_ADDR                                  11408 
-#define D_loopCounter_ADDR_END                              11411 
-#define D_loopCounter_sizeof                                4 
-
-#define D_RewindFlag_ADDR                                   11412 
-#define D_RewindFlag_ADDR_END                               11413 
-#define D_RewindFlag_sizeof                                 2 
-
-#define D_Slot23_ctrl_ADDR                                  11416 
-#define D_Slot23_ctrl_ADDR_END                              11419 
-#define D_Slot23_ctrl_sizeof                                4 
-
-#define D_McuIrqFifo_ADDR                                   11420 
-#define D_McuIrqFifo_ADDR_END                               11483 
-#define D_McuIrqFifo_sizeof                                 64 
-
-#define D_PingPongDesc_ADDR                                 11484 
-#define D_PingPongDesc_ADDR_END                             11531 
-#define D_PingPongDesc_sizeof                               48 
-
-#define D_PP_MCU_IRQ_ADDR                                   11532 
-#define D_PP_MCU_IRQ_ADDR_END                               11533 
-#define D_PP_MCU_IRQ_sizeof                                 2 
-
-#define D_ctrlPortFifo_ADDR                                 11536 
-#define D_ctrlPortFifo_ADDR_END                             11551 
-#define D_ctrlPortFifo_sizeof                               16 
-
-#define D_Idle_State_ADDR                                   11552 
-#define D_Idle_State_ADDR_END                               11555 
-#define D_Idle_State_sizeof                                 4 
-
-#define D_Stop_Request_ADDR                                 11556 
-#define D_Stop_Request_ADDR_END                             11559 
-#define D_Stop_Request_sizeof                               4 
-
-#define D_Ref0_ADDR                                         11560 
-#define D_Ref0_ADDR_END                                     11561 
-#define D_Ref0_sizeof                                       2 
-
-#define D_DebugRegister_ADDR                                11564 
-#define D_DebugRegister_ADDR_END                            11703 
-#define D_DebugRegister_sizeof                              140 
-
-#define D_Gcount_ADDR                                       11704 
-#define D_Gcount_ADDR_END                                   11705 
-#define D_Gcount_sizeof                                     2 
-
-#define D_DCcounter_ADDR                                    11708 
-#define D_DCcounter_ADDR_END                                11711 
-#define D_DCcounter_sizeof                                  4 
-
-#define D_DCsum_ADDR                                        11712 
-#define D_DCsum_ADDR_END                                    11719 
-#define D_DCsum_sizeof                                      8 
-
-#define D_fastCounter_ADDR                                  11720 
-#define D_fastCounter_ADDR_END                              11723 
-#define D_fastCounter_sizeof                                4 
-
-#define D_slowCounter_ADDR                                  11724 
-#define D_slowCounter_ADDR_END                              11727 
-#define D_slowCounter_sizeof                                4 
-
-#define D_aUplinkRouting_ADDR                               11728 
-#define D_aUplinkRouting_ADDR_END                           11759 
-#define D_aUplinkRouting_sizeof                             32 
-
-#define D_VirtAudioLoop_ADDR                                11760 
-#define D_VirtAudioLoop_ADDR_END                            11763 
-#define D_VirtAudioLoop_sizeof                              4 
-
-#define D_AsrcVars_DL_VX_ADDR                               11764 
-#define D_AsrcVars_DL_VX_ADDR_END                           11795 
-#define D_AsrcVars_DL_VX_sizeof                             32 
-
-#define D_AsrcVars_UL_VX_ADDR                               11796 
-#define D_AsrcVars_UL_VX_ADDR_END                           11827 
-#define D_AsrcVars_UL_VX_sizeof                             32 
-
-#define D_CoefAddresses_VX_ADDR                             11828 
-#define D_CoefAddresses_VX_ADDR_END                         11859 
-#define D_CoefAddresses_VX_sizeof                           32 
-
-#define D_AsrcVars_DL_MM_ADDR                               11860 
-#define D_AsrcVars_DL_MM_ADDR_END                           11891 
-#define D_AsrcVars_DL_MM_sizeof                             32 
-
-#define D_CoefAddresses_DL_MM_ADDR                          11892 
-#define D_CoefAddresses_DL_MM_ADDR_END                      11923 
-#define D_CoefAddresses_DL_MM_sizeof                        32 
-
-#define D_APS_DL1_M_thresholds_ADDR                         11924 
-#define D_APS_DL1_M_thresholds_ADDR_END                     11931 
-#define D_APS_DL1_M_thresholds_sizeof                       8 
-
-#define D_APS_DL1_M_IRQ_ADDR                                11932 
-#define D_APS_DL1_M_IRQ_ADDR_END                            11933 
-#define D_APS_DL1_M_IRQ_sizeof                              2 
-
-#define D_APS_DL1_C_IRQ_ADDR                                11934 
-#define D_APS_DL1_C_IRQ_ADDR_END                            11935 
-#define D_APS_DL1_C_IRQ_sizeof                              2 
-
-#define D_TraceBufAdr_ADDR                                  11936 
-#define D_TraceBufAdr_ADDR_END                              11937 
-#define D_TraceBufAdr_sizeof                                2 
-
-#define D_TraceBufOffset_ADDR                               11938 
-#define D_TraceBufOffset_ADDR_END                           11939 
-#define D_TraceBufOffset_sizeof                             2 
-
-#define D_TraceBufLength_ADDR                               11940 
-#define D_TraceBufLength_ADDR_END                           11941 
-#define D_TraceBufLength_sizeof                             2 
-
-#define D_AsrcVars_ECHO_REF_ADDR                            11944 
-#define D_AsrcVars_ECHO_REF_ADDR_END                        11975 
-#define D_AsrcVars_ECHO_REF_sizeof                          32 
-
-#define D_Pempty_ADDR                                       11976 
-#define D_Pempty_ADDR_END                                   11979 
-#define D_Pempty_sizeof                                     4 
-
-#define D_APS_DL2_L_M_IRQ_ADDR                              11980 
-#define D_APS_DL2_L_M_IRQ_ADDR_END                          11981 
-#define D_APS_DL2_L_M_IRQ_sizeof                            2 
-
-#define D_APS_DL2_L_C_IRQ_ADDR                              11982 
-#define D_APS_DL2_L_C_IRQ_ADDR_END                          11983 
-#define D_APS_DL2_L_C_IRQ_sizeof                            2 
-
-#define D_APS_DL2_R_M_IRQ_ADDR                              11984 
-#define D_APS_DL2_R_M_IRQ_ADDR_END                          11985 
-#define D_APS_DL2_R_M_IRQ_sizeof                            2 
-
-#define D_APS_DL2_R_C_IRQ_ADDR                              11986 
-#define D_APS_DL2_R_C_IRQ_ADDR_END                          11987 
-#define D_APS_DL2_R_C_IRQ_sizeof                            2 
-
-#define D_APS_DL1_C_thresholds_ADDR                         11988 
-#define D_APS_DL1_C_thresholds_ADDR_END                     11995 
-#define D_APS_DL1_C_thresholds_sizeof                       8 
-
-#define D_APS_DL2_L_M_thresholds_ADDR                       11996 
-#define D_APS_DL2_L_M_thresholds_ADDR_END                   12003 
-#define D_APS_DL2_L_M_thresholds_sizeof                     8 
-
-#define D_APS_DL2_L_C_thresholds_ADDR                       12004 
-#define D_APS_DL2_L_C_thresholds_ADDR_END                   12011 
-#define D_APS_DL2_L_C_thresholds_sizeof                     8 
-
-#define D_APS_DL2_R_M_thresholds_ADDR                       12012 
-#define D_APS_DL2_R_M_thresholds_ADDR_END                   12019 
-#define D_APS_DL2_R_M_thresholds_sizeof                     8 
-
-#define D_APS_DL2_R_C_thresholds_ADDR                       12020 
-#define D_APS_DL2_R_C_thresholds_ADDR_END                   12027 
-#define D_APS_DL2_R_C_thresholds_sizeof                     8 
-
-#define D_ECHO_REF_48_16_WRAP_ADDR                          12028 
-#define D_ECHO_REF_48_16_WRAP_ADDR_END                      12035 
-#define D_ECHO_REF_48_16_WRAP_sizeof                        8 
-
-#define D_ECHO_REF_48_8_WRAP_ADDR                           12036 
-#define D_ECHO_REF_48_8_WRAP_ADDR_END                       12043 
-#define D_ECHO_REF_48_8_WRAP_sizeof                         8 
-
-#define D_BT_UL_16_48_WRAP_ADDR                             12044 
-#define D_BT_UL_16_48_WRAP_ADDR_END                         12051 
-#define D_BT_UL_16_48_WRAP_sizeof                           8 
-
-#define D_BT_UL_8_48_WRAP_ADDR                              12052 
-#define D_BT_UL_8_48_WRAP_ADDR_END                          12059 
-#define D_BT_UL_8_48_WRAP_sizeof                            8 
-
-#define D_BT_DL_48_16_WRAP_ADDR                             12060 
-#define D_BT_DL_48_16_WRAP_ADDR_END                         12067 
-#define D_BT_DL_48_16_WRAP_sizeof                           8 
-
-#define D_BT_DL_48_8_WRAP_ADDR                              12068 
-#define D_BT_DL_48_8_WRAP_ADDR_END                          12075 
-#define D_BT_DL_48_8_WRAP_sizeof                            8 
-
-#define D_VX_DL_16_48_WRAP_ADDR                             12076 
-#define D_VX_DL_16_48_WRAP_ADDR_END                         12083 
-#define D_VX_DL_16_48_WRAP_sizeof                           8 
-
-#define D_VX_DL_8_48_WRAP_ADDR                              12084 
-#define D_VX_DL_8_48_WRAP_ADDR_END                          12091 
-#define D_VX_DL_8_48_WRAP_sizeof                            8 
-
-#define D_VX_UL_48_16_WRAP_ADDR                             12092 
-#define D_VX_UL_48_16_WRAP_ADDR_END                         12099 
-#define D_VX_UL_48_16_WRAP_sizeof                           8 
-
-#define D_VX_UL_48_8_WRAP_ADDR                              12100 
-#define D_VX_UL_48_8_WRAP_ADDR_END                          12107 
-#define D_VX_UL_48_8_WRAP_sizeof                            8 
-
-#define D_APS_DL1_IRQs_WRAP_ADDR                            12108 
-#define D_APS_DL1_IRQs_WRAP_ADDR_END                        12115 
-#define D_APS_DL1_IRQs_WRAP_sizeof                          8 
-
-#define D_APS_DL2_L_IRQs_WRAP_ADDR                          12116 
-#define D_APS_DL2_L_IRQs_WRAP_ADDR_END                      12123 
-#define D_APS_DL2_L_IRQs_WRAP_sizeof                        8 
-
-#define D_APS_DL2_R_IRQs_WRAP_ADDR                          12124 
-#define D_APS_DL2_R_IRQs_WRAP_ADDR_END                      12131 
-#define D_APS_DL2_R_IRQs_WRAP_sizeof                        8 
-
-#define D_nextMultiFrame_ADDR                               12132 
-#define D_nextMultiFrame_ADDR_END                           12139 
-#define D_nextMultiFrame_sizeof                             8 
-
-#define D_HW_TEST_ADDR                                      12140 
-#define D_HW_TEST_ADDR_END                                  12147 
-#define D_HW_TEST_sizeof                                    8 
-
-#define D_TraceBufAdr_HAL_ADDR                              12148 
-#define D_TraceBufAdr_HAL_ADDR_END                          12151 
-#define D_TraceBufAdr_HAL_sizeof                            4 
-
-#define D_DEBUG_HAL_TASK_ADDR                               12288 
-#define D_DEBUG_HAL_TASK_ADDR_END                           14335 
-#define D_DEBUG_HAL_TASK_sizeof                             2048 
-
-#define D_DEBUG_FW_TASK_ADDR                                14336 
-#define D_DEBUG_FW_TASK_ADDR_END                            14591 
-#define D_DEBUG_FW_TASK_sizeof                              256 
-
-#define D_FwMemInit_ADDR                                    14592 
-#define D_FwMemInit_ADDR_END                                15383 
-#define D_FwMemInit_sizeof                                  792 
-
-#define D_FwMemInitDescr_ADDR                               15384 
-#define D_FwMemInitDescr_ADDR_END                           15399 
-#define D_FwMemInitDescr_sizeof                             16 
-
-#define D_PING_ADDR                                         16384 
-#define D_PING_ADDR_END                                     40959 
-#define D_PING_sizeof                                       24576 
-
-#define D_PONG_ADDR                                         40960 
-#define D_PONG_ADDR_END                                     65535 
-#define D_PONG_sizeof                                       24576 
-
-
-#endif /* _ABEDM_ADDR_H_ */
+#define D_atcDescriptors_ADDR                               0
+#define D_atcDescriptors_ADDR_END                           511
+#define D_atcDescriptors_sizeof                             512
+#define stack_ADDR                                          512
+#define stack_ADDR_END                                      623
+#define stack_sizeof                                        112
+#define D_version_ADDR                                      624
+#define D_version_ADDR_END                                  627
+#define D_version_sizeof                                    4
+#define D_BT_DL_FIFO_ADDR                                   1024
+#define D_BT_DL_FIFO_ADDR_END                               1503
+#define D_BT_DL_FIFO_sizeof                                 480
+#define D_BT_UL_FIFO_ADDR                                   1536
+#define D_BT_UL_FIFO_ADDR_END                               2015
+#define D_BT_UL_FIFO_sizeof                                 480
+#define D_MM_EXT_OUT_FIFO_ADDR                              2048
+#define D_MM_EXT_OUT_FIFO_ADDR_END                          2527
+#define D_MM_EXT_OUT_FIFO_sizeof                            480
+#define D_MM_EXT_IN_FIFO_ADDR                               2560
+#define D_MM_EXT_IN_FIFO_ADDR_END                           3039
+#define D_MM_EXT_IN_FIFO_sizeof                             480
+#define D_MM_UL2_FIFO_ADDR                                  3072
+#define D_MM_UL2_FIFO_ADDR_END                              3551
+#define D_MM_UL2_FIFO_sizeof                                480
+#define D_VX_UL_FIFO_ADDR                                   3584
+#define D_VX_UL_FIFO_ADDR_END                               4063
+#define D_VX_UL_FIFO_sizeof                                 480
+#define D_VX_DL_FIFO_ADDR                                   4096
+#define D_VX_DL_FIFO_ADDR_END                               4575
+#define D_VX_DL_FIFO_sizeof                                 480
+#define D_DMIC_UL_FIFO_ADDR                                 4608
+#define D_DMIC_UL_FIFO_ADDR_END                             5087
+#define D_DMIC_UL_FIFO_sizeof                               480
+#define D_MM_UL_FIFO_ADDR                                   5120
+#define D_MM_UL_FIFO_ADDR_END                               5599
+#define D_MM_UL_FIFO_sizeof                                 480
+#define D_MM_DL_FIFO_ADDR                                   5632
+#define D_MM_DL_FIFO_ADDR_END                               6111
+#define D_MM_DL_FIFO_sizeof                                 480
+#define D_TONES_DL_FIFO_ADDR                                6144
+#define D_TONES_DL_FIFO_ADDR_END                            6623
+#define D_TONES_DL_FIFO_sizeof                              480
+#define D_VIB_DL_FIFO_ADDR                                  6656
+#define D_VIB_DL_FIFO_ADDR_END                              7135
+#define D_VIB_DL_FIFO_sizeof                                480
+#define D_McPDM_DL_FIFO_ADDR                                7168
+#define D_McPDM_DL_FIFO_ADDR_END                            7647
+#define D_McPDM_DL_FIFO_sizeof                              480
+#define D_McPDM_UL_FIFO_ADDR                                7680
+#define D_McPDM_UL_FIFO_ADDR_END                            8159
+#define D_McPDM_UL_FIFO_sizeof                              480
+#define D_DEBUG_FIFO_ADDR                                   8160
+#define D_DEBUG_FIFO_ADDR_END                               8255
+#define D_DEBUG_FIFO_sizeof                                 96
+#define D_DEBUG_FIFO_HAL_ADDR                               8256
+#define D_DEBUG_FIFO_HAL_ADDR_END                           8287
+#define D_DEBUG_FIFO_HAL_sizeof                             32
+#define D_IOdescr_ADDR                                      8288
+#define D_IOdescr_ADDR_END                                  8927
+#define D_IOdescr_sizeof                                    640
+#define d_zero_ADDR                                         8928
+#define d_zero_ADDR_END                                     8931
+#define d_zero_sizeof                                       4
+#define dbg_trace1_ADDR                                     8932
+#define dbg_trace1_ADDR_END                                 8932
+#define dbg_trace1_sizeof                                   1
+#define dbg_trace2_ADDR                                     8933
+#define dbg_trace2_ADDR_END                                 8933
+#define dbg_trace2_sizeof                                   1
+#define dbg_trace3_ADDR                                     8934
+#define dbg_trace3_ADDR_END                                 8934
+#define dbg_trace3_sizeof                                   1
+#define D_multiFrame_ADDR                                   8936
+#define D_multiFrame_ADDR_END                               9335
+#define D_multiFrame_sizeof                                 400
+#define D_tasksList_ADDR                                    9336
+#define D_tasksList_ADDR_END                                11383
+#define D_tasksList_sizeof                                  2048
+#define D_idleTask_ADDR                                     11384
+#define D_idleTask_ADDR_END                                 11385
+#define D_idleTask_sizeof                                   2
+#define D_typeLengthCheck_ADDR                              11386
+#define D_typeLengthCheck_ADDR_END                          11387
+#define D_typeLengthCheck_sizeof                            2
+#define D_maxTaskBytesInSlot_ADDR                           11388
+#define D_maxTaskBytesInSlot_ADDR_END                       11389
+#define D_maxTaskBytesInSlot_sizeof                         2
+#define D_rewindTaskBytes_ADDR                              11390
+#define D_rewindTaskBytes_ADDR_END                          11391
+#define D_rewindTaskBytes_sizeof                            2
+#define D_pCurrentTask_ADDR                                 11392
+#define D_pCurrentTask_ADDR_END                             11393
+#define D_pCurrentTask_sizeof                               2
+#define D_pFastLoopBack_ADDR                                11394
+#define D_pFastLoopBack_ADDR_END                            11395
+#define D_pFastLoopBack_sizeof                              2
+#define D_pNextFastLoopBack_ADDR                            11396
+#define D_pNextFastLoopBack_ADDR_END                        11399
+#define D_pNextFastLoopBack_sizeof                          4
+#define D_ppCurrentTask_ADDR                                11400
+#define D_ppCurrentTask_ADDR_END                            11401
+#define D_ppCurrentTask_sizeof                              2
+#define D_slotCounter_ADDR                                  11404
+#define D_slotCounter_ADDR_END                              11405
+#define D_slotCounter_sizeof                                2
+#define D_loopCounter_ADDR                                  11408
+#define D_loopCounter_ADDR_END                              11411
+#define D_loopCounter_sizeof                                4
+#define D_RewindFlag_ADDR                                   11412
+#define D_RewindFlag_ADDR_END                               11413
+#define D_RewindFlag_sizeof                                 2
+#define D_Slot23_ctrl_ADDR                                  11416
+#define D_Slot23_ctrl_ADDR_END                              11419
+#define D_Slot23_ctrl_sizeof                                4
+#define D_McuIrqFifo_ADDR                                   11420
+#define D_McuIrqFifo_ADDR_END                               11483
+#define D_McuIrqFifo_sizeof                                 64
+#define D_PingPongDesc_ADDR                                 11484
+#define D_PingPongDesc_ADDR_END                             11531
+#define D_PingPongDesc_sizeof                               48
+#define D_PP_MCU_IRQ_ADDR                                   11532
+#define D_PP_MCU_IRQ_ADDR_END                               11533
+#define D_PP_MCU_IRQ_sizeof                                 2
+#define D_ctrlPortFifo_ADDR                                 11536
+#define D_ctrlPortFifo_ADDR_END                             11551
+#define D_ctrlPortFifo_sizeof                               16
+#define D_Idle_State_ADDR                                   11552
+#define D_Idle_State_ADDR_END                               11555
+#define D_Idle_State_sizeof                                 4
+#define D_Stop_Request_ADDR                                 11556
+#define D_Stop_Request_ADDR_END                             11559
+#define D_Stop_Request_sizeof                               4
+#define D_Ref0_ADDR                                         11560
+#define D_Ref0_ADDR_END                                     11561
+#define D_Ref0_sizeof                                       2
+#define D_DebugRegister_ADDR                                11564
+#define D_DebugRegister_ADDR_END                            11703
+#define D_DebugRegister_sizeof                              140
+#define D_Gcount_ADDR                                       11704
+#define D_Gcount_ADDR_END                                   11705
+#define D_Gcount_sizeof                                     2
+#define D_DCcounter_ADDR                                    11708
+#define D_DCcounter_ADDR_END                                11711
+#define D_DCcounter_sizeof                                  4
+#define D_DCsum_ADDR                                        11712
+#define D_DCsum_ADDR_END                                    11719
+#define D_DCsum_sizeof                                      8
+#define D_fastCounter_ADDR                                  11720
+#define D_fastCounter_ADDR_END                              11723
+#define D_fastCounter_sizeof                                4
+#define D_slowCounter_ADDR                                  11724
+#define D_slowCounter_ADDR_END                              11727
+#define D_slowCounter_sizeof                                4
+#define D_aUplinkRouting_ADDR                               11728
+#define D_aUplinkRouting_ADDR_END                           11759
+#define D_aUplinkRouting_sizeof                             32
+#define D_VirtAudioLoop_ADDR                                11760
+#define D_VirtAudioLoop_ADDR_END                            11763
+#define D_VirtAudioLoop_sizeof                              4
+#define D_AsrcVars_DL_VX_ADDR                               11764
+#define D_AsrcVars_DL_VX_ADDR_END                           11795
+#define D_AsrcVars_DL_VX_sizeof                             32
+#define D_AsrcVars_UL_VX_ADDR                               11796
+#define D_AsrcVars_UL_VX_ADDR_END                           11827
+#define D_AsrcVars_UL_VX_sizeof                             32
+#define D_CoefAddresses_VX_ADDR                             11828
+#define D_CoefAddresses_VX_ADDR_END                         11859
+#define D_CoefAddresses_VX_sizeof                           32
+#define D_AsrcVars_MM_EXT_IN_ADDR                           11860
+#define D_AsrcVars_MM_EXT_IN_ADDR_END                       11891
+#define D_AsrcVars_MM_EXT_IN_sizeof                         32
+#define D_CoefAddresses_MM_ADDR                             11892
+#define D_CoefAddresses_MM_ADDR_END                         11923
+#define D_CoefAddresses_MM_sizeof                           32
+#define D_APS_DL1_M_thresholds_ADDR                         11924
+#define D_APS_DL1_M_thresholds_ADDR_END                     11931
+#define D_APS_DL1_M_thresholds_sizeof                       8
+#define D_APS_DL1_M_IRQ_ADDR                                11932
+#define D_APS_DL1_M_IRQ_ADDR_END                            11933
+#define D_APS_DL1_M_IRQ_sizeof                              2
+#define D_APS_DL1_C_IRQ_ADDR                                11934
+#define D_APS_DL1_C_IRQ_ADDR_END                            11935
+#define D_APS_DL1_C_IRQ_sizeof                              2
+#define D_TraceBufAdr_ADDR                                  11936
+#define D_TraceBufAdr_ADDR_END                              11937
+#define D_TraceBufAdr_sizeof                                2
+#define D_TraceBufOffset_ADDR                               11938
+#define D_TraceBufOffset_ADDR_END                           11939
+#define D_TraceBufOffset_sizeof                             2
+#define D_TraceBufLength_ADDR                               11940
+#define D_TraceBufLength_ADDR_END                           11941
+#define D_TraceBufLength_sizeof                             2
+#define D_AsrcVars_ECHO_REF_ADDR                            11944
+#define D_AsrcVars_ECHO_REF_ADDR_END                        11975
+#define D_AsrcVars_ECHO_REF_sizeof                          32
+#define D_Pempty_ADDR                                       11976
+#define D_Pempty_ADDR_END                                   11979
+#define D_Pempty_sizeof                                     4
+#define D_APS_DL2_L_M_IRQ_ADDR                              11980
+#define D_APS_DL2_L_M_IRQ_ADDR_END                          11981
+#define D_APS_DL2_L_M_IRQ_sizeof                            2
+#define D_APS_DL2_L_C_IRQ_ADDR                              11982
+#define D_APS_DL2_L_C_IRQ_ADDR_END                          11983
+#define D_APS_DL2_L_C_IRQ_sizeof                            2
+#define D_APS_DL2_R_M_IRQ_ADDR                              11984
+#define D_APS_DL2_R_M_IRQ_ADDR_END                          11985
+#define D_APS_DL2_R_M_IRQ_sizeof                            2
+#define D_APS_DL2_R_C_IRQ_ADDR                              11986
+#define D_APS_DL2_R_C_IRQ_ADDR_END                          11987
+#define D_APS_DL2_R_C_IRQ_sizeof                            2
+#define D_APS_DL1_C_thresholds_ADDR                         11988
+#define D_APS_DL1_C_thresholds_ADDR_END                     11995
+#define D_APS_DL1_C_thresholds_sizeof                       8
+#define D_APS_DL2_L_M_thresholds_ADDR                       11996
+#define D_APS_DL2_L_M_thresholds_ADDR_END                   12003
+#define D_APS_DL2_L_M_thresholds_sizeof                     8
+#define D_APS_DL2_L_C_thresholds_ADDR                       12004
+#define D_APS_DL2_L_C_thresholds_ADDR_END                   12011
+#define D_APS_DL2_L_C_thresholds_sizeof                     8
+#define D_APS_DL2_R_M_thresholds_ADDR                       12012
+#define D_APS_DL2_R_M_thresholds_ADDR_END                   12019
+#define D_APS_DL2_R_M_thresholds_sizeof                     8
+#define D_APS_DL2_R_C_thresholds_ADDR                       12020
+#define D_APS_DL2_R_C_thresholds_ADDR_END                   12027
+#define D_APS_DL2_R_C_thresholds_sizeof                     8
+#define D_ECHO_REF_48_16_WRAP_ADDR                          12028
+#define D_ECHO_REF_48_16_WRAP_ADDR_END                      12035
+#define D_ECHO_REF_48_16_WRAP_sizeof                        8
+#define D_ECHO_REF_48_8_WRAP_ADDR                           12036
+#define D_ECHO_REF_48_8_WRAP_ADDR_END                       12043
+#define D_ECHO_REF_48_8_WRAP_sizeof                         8
+#define D_BT_UL_16_48_WRAP_ADDR                             12044
+#define D_BT_UL_16_48_WRAP_ADDR_END                         12051
+#define D_BT_UL_16_48_WRAP_sizeof                           8
+#define D_BT_UL_8_48_WRAP_ADDR                              12052
+#define D_BT_UL_8_48_WRAP_ADDR_END                          12059
+#define D_BT_UL_8_48_WRAP_sizeof                            8
+#define D_BT_DL_48_16_WRAP_ADDR                             12060
+#define D_BT_DL_48_16_WRAP_ADDR_END                         12067
+#define D_BT_DL_48_16_WRAP_sizeof                           8
+#define D_BT_DL_48_8_WRAP_ADDR                              12068
+#define D_BT_DL_48_8_WRAP_ADDR_END                          12075
+#define D_BT_DL_48_8_WRAP_sizeof                            8
+#define D_VX_DL_16_48_WRAP_ADDR                             12076
+#define D_VX_DL_16_48_WRAP_ADDR_END                         12083
+#define D_VX_DL_16_48_WRAP_sizeof                           8
+#define D_VX_DL_8_48_WRAP_ADDR                              12084
+#define D_VX_DL_8_48_WRAP_ADDR_END                          12091
+#define D_VX_DL_8_48_WRAP_sizeof                            8
+#define D_VX_UL_48_16_WRAP_ADDR                             12092
+#define D_VX_UL_48_16_WRAP_ADDR_END                         12099
+#define D_VX_UL_48_16_WRAP_sizeof                           8
+#define D_VX_UL_48_8_WRAP_ADDR                              12100
+#define D_VX_UL_48_8_WRAP_ADDR_END                          12107
+#define D_VX_UL_48_8_WRAP_sizeof                            8
+#define D_APS_DL1_IRQs_WRAP_ADDR                            12108
+#define D_APS_DL1_IRQs_WRAP_ADDR_END                        12115
+#define D_APS_DL1_IRQs_WRAP_sizeof                          8
+#define D_APS_DL2_L_IRQs_WRAP_ADDR                          12116
+#define D_APS_DL2_L_IRQs_WRAP_ADDR_END                      12123
+#define D_APS_DL2_L_IRQs_WRAP_sizeof                        8
+#define D_APS_DL2_R_IRQs_WRAP_ADDR                          12124
+#define D_APS_DL2_R_IRQs_WRAP_ADDR_END                      12131
+#define D_APS_DL2_R_IRQs_WRAP_sizeof                        8
+#define D_nextMultiFrame_ADDR                               12132
+#define D_nextMultiFrame_ADDR_END                           12139
+#define D_nextMultiFrame_sizeof                             8
+#define D_HW_TEST_ADDR                                      12140
+#define D_HW_TEST_ADDR_END                                  12147
+#define D_HW_TEST_sizeof                                    8
+#define D_TraceBufAdr_HAL_ADDR                              12148
+#define D_TraceBufAdr_HAL_ADDR_END                          12151
+#define D_TraceBufAdr_HAL_sizeof                            4
+#define D_DEBUG_HAL_TASK_ADDR                               12288
+#define D_DEBUG_HAL_TASK_ADDR_END                           14335
+#define D_DEBUG_HAL_TASK_sizeof                             2048
+#define D_DEBUG_FW_TASK_ADDR                                14336
+#define D_DEBUG_FW_TASK_ADDR_END                            14591
+#define D_DEBUG_FW_TASK_sizeof                              256
+#define D_FwMemInit_ADDR                                    14592
+#define D_FwMemInit_ADDR_END                                15383
+#define D_FwMemInit_sizeof                                  792
+#define D_FwMemInitDescr_ADDR                               15384
+#define D_FwMemInitDescr_ADDR_END                           15399
+#define D_FwMemInitDescr_sizeof                             16
+#define D_PING_ADDR                                         16384
+#define D_PING_ADDR_END                                     40959
+#define D_PING_sizeof                                       24576
+#define D_PONG_ADDR                                         40960
+#define D_PONG_ADDR_END                                     65535
+#define D_PONG_sizeof                                       24576
+#endif/* _ABEDM_ADDR_H_ */
diff --git a/sound/soc/omap/abe/abe_ext.c b/sound/soc/omap/abe/abe_ext.c
index 138f09a1b05b..e1c187189172 100644
--- a/sound/soc/omap/abe/abe_ext.c
+++ b/sound/soc/omap/abe/abe_ext.c
@@ -18,60 +18,57 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
 /**
  * abe_default_irq_pingpong_player
  *
  * generates data for the cache-flush buffer MODE 16+16
  */
-void abe_default_irq_pingpong_player (void)
+void abe_default_irq_pingpong_player(void)
 {
-#if 0
 #define N_SAMPLES_MAX ((int)(1024))	/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */
-
 	static s32 idx;
 	u32 i, dst, n_samples, n_bytes;
-	s32 temp [N_SAMPLES_MAX], audio_sample;
-#define DATA_SIZE 20 /* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */
-	const s32 audio_pattern [DATA_SIZE] = {
-  0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630, 
-5063, 0, -5063, -9630, -13254, -15581, -16383, -15581, 
+	s32 temp[N_SAMPLES_MAX], audio_sample;
+#define DATA_SIZE 20		/* t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */
+	const s32 audio_pattern[DATA_SIZE] = {
+		0, 5063, 9630, 13254, 15581, 16383, 15581, 13254, 9630,
+		5063, 0, -5063, -9630, -13254, -15581, -16383, -15581,
 		-13254, -9630, -5063
 	};
 #if 0
 #define DATA_SIZE 8
-        const s32 audio_pattern [DATA_SIZE] = {0, 11585, 16384, 11585, 0, -11586, -16384, -11586 };
-
+	const s32 audio_pattern[DATA_SIZE] = {
+		0, 11585, 16384, 11585, 0, -11586, -16384, -11586
+	};
 #define DATA_SIZE 12
-        const s32 audio_pattern [DATA_SIZE] = {0, 8191, 14188, 16383, 14188, 8191, 0, -8192, -14188, -16383, -14188, -8192};
-
-const s32 audio_pattern [8] = {16383,16383,16383,16383,-16384,-16384,-16384,-16384};
+	const s32 audio_pattern[DATA_SIZE] = {
+		0, 8191, 14188, 16383, 14188, 8191, 0,
+		-8192, -14188, -16383, -14188, -8192
+	};
+	const s32 audio_pattern[8] = {
+		16383, 16383, 16383, 16383, -16384, -16384, -16384, -16384
+	};
 #endif
-
 	/* read the address of the Pong buffer */
-	abe_read_next_ping_pong_buffer (MM_DL_PORT, &dst, &n_bytes);
-
-
-	n_samples = n_bytes / 4;	/* each stereo sample weights 4 bytes (format 16|16) */
-
+	abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes);
+	/* each stereo sample weights 4 bytes (format 16|16) */
+	n_samples = n_bytes / 4;
 	/* generate a test pattern */
 	for (i = 0; i < n_samples; i++) {
-		audio_sample = audio_pattern [idx];
-		idx = (idx >= (DATA_SIZE-1))? 0: (idx+1);
-		temp [i] = ((audio_sample << 16) + audio_sample); /* format 16|16 */
+		audio_sample = audio_pattern[idx];
+		idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1);
+		/* format 16|16 */
+		temp[i] = ((audio_sample << 16) + audio_sample);
 	}
-
 	/* copy the pattern (flush it) to DMEM pointer update
 	 * not necessary here because the buffer size do not
 	 * change from one ping to the other pong
 	 */
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (u32 *)&(temp[0]), n_bytes);
-	abe_set_ping_pong_buffer (MM_DL_PORT, n_bytes);
-#endif
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst,
+		       (u32 *) &(temp[0]), n_bytes);
+	abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes);
 }
-
 /**
  * abe_default_irq_pingpong_player_32bits
  *
@@ -79,72 +76,65 @@ const s32 audio_pattern [8] = {16383,16383,16383,16383,-16384,-16384,-16384,-163
  * Return value:
  * None.
  */
-void abe_default_irq_pingpong_player_32bits (void)
+void abe_default_irq_pingpong_player_32bits(void)
 {
-#if 0
 	/* ping-pong access to MM_DL at 48kHz Mono with 20ms packet sizes */
 	static s32 idx;
 	u32 i, dst, n_samples, n_bytes;
-	s32 temp [N_SAMPLES_MAX], audio_sample;
-#define DATA_SIZE 20 /*  t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */
-	const s32 audio_pattern [DATA_SIZE] = {
+	s32 temp[N_SAMPLES_MAX], audio_sample;
+#define DATA_SIZE 20		/*  t = [0:N-1]/N; x = round(16383*sin(2*pi*t)) */
+	const s32 audio_pattern[DATA_SIZE] = {
 		0, 5063, 9630, 13254, 15581, 16383, 15581, 13254,
 		9630, 5063, 0, -5063, -9630, -13254, -15581, -16383,
 		-15581, -13254, -9630, -5063
 	};
-
 	/* read the address of the Pong buffer */
-	abe_read_next_ping_pong_buffer (MM_DL_PORT, &dst, &n_bytes);
-	n_samples = n_bytes / 8;	/* each stereo sample weights 8 bytes (format 32|32) */
-
+	abe_read_next_ping_pong_buffer(MM_DL_PORT, &dst, &n_bytes);
+	/* each stereo sample weights 8 bytes (format 32|32) */
+	n_samples = n_bytes / 8;
 	/* generate a test pattern */
 	for (i = 0; i < n_samples; i++) {
 		/* circular addressing */
-		audio_sample = audio_pattern [idx];
-		idx = (idx >= (DATA_SIZE-1))? 0: (idx+1);
-		temp [i*2 +0] = (audio_sample << 16);
-		temp [i*2 +1] = (audio_sample << 16);
+		audio_sample = audio_pattern[idx];
+		idx = (idx >= (DATA_SIZE - 1)) ? 0 : (idx + 1);
+		temp[i * 2 + 0] = (audio_sample << 16);
+		temp[i * 2 + 1] = (audio_sample << 16);
 	}
-
+	abe_set_ping_pong_buffer(MM_DL_PORT, 0);
 	/* copy the pattern (flush it) to DMEM pointer update
 	 * not necessary here because the buffer size do not
 	 * change from one ping to the other pong
 	 */
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst, (u32 *)&(temp[0]), n_bytes);
-
-	abe_set_ping_pong_buffer (MM_DL_PORT, n_bytes);
-#endif
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, dst,
+		       (u32 *) &(temp[0]), n_bytes);
+	abe_set_ping_pong_buffer(MM_DL_PORT, n_bytes);
 }
-
 /**
  * abe_default_irq_aps_adaptation
  *
  * updates the APS filter and gain
  */
-void abe_default_irq_aps_adaptation (void)
+void abe_default_irq_aps_adaptation(void)
 {
 }
-
 /**
  * abe_read_sys_clock
  * @time: pointer to the system clock
  *
  * returns the current time indication for the LOG
  */
-void abe_read_sys_clock (u32 *time)
+void abe_read_sys_clock(u32 *time)
 {
 	static u32 clock;
-
 	*time = clock;
-	clock ++;
+	clock++;
 }
-
 /**
  * abe_aps_tuning
  *
  * Tune APS parameters
  *
  */
-void    abe_aps_tuning (void)
+void abe_aps_tuning(void)
 {
 }
diff --git a/sound/soc/omap/abe/abe_ext.h b/sound/soc/omap/abe/abe_ext.h
index 1711aeaae8ec..8c6f72832ae5 100644
--- a/sound/soc/omap/abe/abe_ext.h
+++ b/sound/soc/omap/abe/abe_ext.h
@@ -18,242 +18,180 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #ifndef _ABE_EXT_H_
 #define _ABE_EXT_H_
-
 /* Tuning is done on PC ? */
 #define PC_SIMULATION 0
-
-#include <linux/module.h>
-
 #if PC_SIMULATION
-extern void target_server_read_pmem  (u32 address,	 u32 *data, u32 nb_words_32bits);
-extern void target_server_write_pmem (u32 address,	 u32 *data, u32 nb_words_32bits);
-extern void target_server_read_cmem  (u32 address,	 u32 *data, u32 nb_words_32bits);
-extern void target_server_write_cmem (u32 address,	 u32 *data, u32 nb_words_32bits);
-extern void target_server_read_atc   (u32 address,	 u32 *data, u32 nb_words_32bits);
-extern void target_server_write_atc  (u32 address,        u32 *data, u32 nb_words_32bits);
-extern void target_server_read_smem  (u32 address_48bits, u32 *data, u32 nb_words_48bits);
-extern void target_server_write_smem (u32 address_48bits, u32 *data, u32 nb_words_48bits);
-extern void target_server_read_dmem  (u32 address_byte,   u32 *data, u32 nb_byte);
-extern void target_server_write_dmem (u32 address_byte,   u32 *data, u32 nb_byte);
-
-extern void target_server_activate_mcpdm_ul (void);
-extern void target_server_activate_mcpdm_dl (void);
-extern void target_server_activate_dmic (void);
-extern void target_server_set_voice_sampling (int dVirtAudioVoiceMode, int dVirtAudioVoiceSampleFrequency);
-extern void target_server_set_dVirtAudioMultimediaMode (int dVirtAudioMultimediaMode);
+extern void target_server_read_pmem(u32 address, u32 *data,
+				    u32 nb_words_32bits);
+extern void target_server_write_pmem(u32 address, u32 *data,
+				     u32 nb_words_32bits);
+extern void target_server_read_cmem(u32 address, u32 *data,
+				    u32 nb_words_32bits);
+extern void target_server_write_cmem(u32 address, u32 *data,
+				     u32 nb_words_32bits);
+extern void target_server_read_atc(u32 address, u32 *data,
+				   u32 nb_words_32bits);
+extern void target_server_write_atc(u32 address, u32 *data,
+				    u32 nb_words_32bits);
+extern void target_server_read_smem(u32 address_48bits, u32 *data,
+				    u32 nb_words_48bits);
+extern void target_server_write_smem(u32 address_48bits, u32 *data,
+				     u32 nb_words_48bits);
+extern void target_server_read_dmem(u32 address_byte, u32 *data, u32 nb_byte);
+extern void target_server_write_dmem(u32 address_byte, u32 *data, u32 nb_byte);
+extern void target_server_activate_mcpdm_ul(void);
+extern void target_server_activate_mcpdm_dl(void);
+extern void target_server_activate_dmic(void);
+extern void target_server_set_voice_sampling(int dVirtAudioVoiceMode,
+					     int
+					     dVirtAudioVoiceSampleFrequency);
+extern void target_server_set_dVirtAudioMultimediaMode(int
+						       dVirtAudioMultimediaMode);
 #endif
-
 /*
  * OS DEPENDENT MMU CONFIGURATION
  */
-
 #define _lock_enter
 #define _lock_exit
-
 /* base address used for L3/DMA access */
 #define ABE_ATC_BASE_ADDRESS_L3 0x490F1000L
-
 /* base address used for L4/MCU access */
 #define ABE_ATC_BASE_ADDRESS_L4 0x401F1000L
-
 /* 64kB as seen from DMA access */
 #define ABE_DMEM_BASE_ADDRESS_L3 0x49080000L
-
 /* 64kB as seen from MCU access */
 #define ABE_DMEM_BASE_ADDRESS_L4 0x40180000L
-
 /* 8kB as seen from MPU access */
 #define ABE_PMEM_BASE_ADDRESS_MPU 0x490E0000L
-
 /* 8kB */
 #define ABE_CMEM_BASE_ADDRESS_MPU 0x490A0000L
-
 /* 24kB */
 #define ABE_SMEM_BASE_ADDRESS_MPU 0x490C0000L
-
 /* 64kB */
 #define ABE_DMEM_BASE_ADDRESS_MPU 0x49080000L
 #define ABE_ATC_BASE_ADDRESS_MPU 0x490F1000L
-
 /*
  * HARDWARE AND PERIPHERAL DEFINITIONS
  */
-
 /* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/
 #define ABE_PMEM_SIZE 8192
-
 /* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/
 #define ABE_CMEM_SIZE 8192
-
 /* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/
 #define ABE_SMEM_SIZE 24576
-
 /* DMEM SIZE in bytes */
 #define ABE_DMEM_SIZE 65536L
-
 /* ATC REGISTERS SIZE in bytes */
 #define ABE_ATC_DESC_SIZE 512
-
 /* holds the MCU Irq signal */
 #define ABE_MCU_IRQSTATUS_RAW 0x24
-
 /* status : clear the IRQ */
 #define ABE_MCU_IRQSTATUS	0x28
-
 /* holds the DSP Irq signal */
 #define ABE_DSP_IRQSTATUS_RAW 0x4C
-
 /* holds the DMA req lines to the sDMA */
 #define ABE_DMASTATUS_RAW 0x84
-
-
 #define EVENT_GENERATOR_COUNTER 0x68
-
 /* PLL output/desired sampling rate = (32768 * 6000)/96000 */
 #define EVENT_GENERATOR_COUNTER_DEFAULT 2048
-
 /* PLL output/desired sampling rate = (32768 * 6000)/88200 */
 #define EVENT_GENERATOR_COUNTER_44100 2228
-
 /* start / stop the EVENT generator */
 #define EVENT_GENERATOR_START 0x6C
 #define EVENT_GENERATOR_ON 1
 #define EVENT_GENERATOR_OFF 0
-
 /* selection of the EVENT generator source */
 #define EVENT_SOURCE_SELECTION 0x70
 #define EVENT_SOURCE_DMA 0
 #define EVENT_SOURCE_COUNTER 1
-
 /* selection of the ABE DMA req line from ATC */
 #define AUDIO_ENGINE_SCHEDULER 0x74
 #define ABE_ATC_DMIC_DMA_REQ 1
 #define ABE_ATC_MCPDMDL_DMA_REQ 2
 #define ABE_ATC_MCPDMUL_DMA_REQ 3
-
 /* Direction=0 means input from ABE point of view */
 #define ABE_ATC_DIRECTION_IN 0
-
 /* Direction=1 means output from ABE point of view */
 #define ABE_ATC_DIRECTION_OUT 1
-
 /*
  * DMA requests
  */
 /*Internal connection doesn't connect at ABE boundary */
 #define External_DMA_0	0
-
 /*Transmit request digital microphone */
 #define DMIC_DMA_REQ	1
-
 /*Multichannel PDM downlink */
 #define McPDM_DMA_DL	2
-
 /*Multichannel PDM uplink */
 #define McPDM_DMA_UP	3
-
 /*MCBSP module 1 - transmit request */
 #define MCBSP1_DMA_TX	4
-
 /*MCBSP module 1 - receive request */
 #define MCBSP1_DMA_RX	5
-
 /*MCBSP module 2 - transmit request */
 #define MCBSP2_DMA_TX	6
-
 /*MCBSP module 2 - receive request */
 #define MCBSP2_DMA_RX	7
-
 /*MCBSP module 3 - transmit request */
 #define MCBSP3_DMA_TX	8
-
 /*MCBSP module 3 - receive request */
 #define MCBSP3_DMA_RX	9
-
 /*SLIMBUS module 1 - transmit request channel 0 */
 #define SLIMBUS1_DMA_TX0	10
-
 /*SLIMBUS module 1 - transmit request channel 1 */
 #define SLIMBUS1_DMA_TX1	11
-
 /*SLIMBUS module 1 - transmit request channel 2 */
 #define SLIMBUS1_DMA_TX2	12
-
 /*SLIMBUS module 1 - transmit request channel 3 */
 #define SLIMBUS1_DMA_TX3	13
-
 /*SLIMBUS module 1 - transmit request channel 4 */
 #define SLIMBUS1_DMA_TX4	14
-
 /*SLIMBUS module 1 - transmit request channel 5 */
 #define SLIMBUS1_DMA_TX5	15
-
 /*SLIMBUS module 1 - transmit request channel 6 */
 #define SLIMBUS1_DMA_TX6	16
-
 /*SLIMBUS module 1 - transmit request channel 7 */
 #define SLIMBUS1_DMA_TX7	17
-
 /*SLIMBUS module 1 - receive request channel 0 */
 #define SLIMBUS1_DMA_RX0	18
-
 /*SLIMBUS module 1 - receive request channel 1 */
 #define SLIMBUS1_DMA_RX1	19
-
 /*SLIMBUS module 1 - receive request channel 2 */
 #define SLIMBUS1_DMA_RX2	20
-
 /*SLIMBUS module 1 - receive request channel 3 */
 #define SLIMBUS1_DMA_RX3	21
-
 /*SLIMBUS module 1 - receive request channel 4 */
 #define SLIMBUS1_DMA_RX4	22
-
 /*SLIMBUS module 1 - receive request channel 5 */
 #define SLIMBUS1_DMA_RX5	23
-
 /*SLIMBUS module 1 - receive request channel 6 */
 #define SLIMBUS1_DMA_RX6	24
-
 /*SLIMBUS module 1 - receive request channel 7 */
 #define SLIMBUS1_DMA_RX7	25
-
 /*McASP - Data transmit DMA request line */
 #define McASP1_AXEVT	26
-
 /*McASP - Data receive DMA request line */
 #define McASP1_AREVT	29
-
 /*DUMMY FIFO @@@ */
 #define _DUMMY_FIFO_	30
-
 /*DMA of the Circular buffer peripheral 0 */
 #define CBPr_DMA_RTX0	32
-
 /*DMA of the Circular buffer peripheral 1 */
 #define CBPr_DMA_RTX1	33
-
 /*DMA of the Circular buffer peripheral 2 */
 #define CBPr_DMA_RTX2	34
-
 /*DMA of the Circular buffer peripheral 3 */
 #define CBPr_DMA_RTX3	35
-
 /*DMA of the Circular buffer peripheral 4 */
 #define CBPr_DMA_RTX4	36
-
 /*DMA of the Circular buffer peripheral 5 */
 #define CBPr_DMA_RTX5	37
-
 /*DMA of the Circular buffer peripheral 6 */
 #define CBPr_DMA_RTX6	38
-
 /*DMA of the Circular buffer peripheral 7 */
 #define CBPr_DMA_RTX7	39
-
 /*
  * ATC DESCRIPTORS - DESTINATIONS
  */
@@ -280,7 +218,6 @@ extern void target_server_set_dVirtAudioMultimediaMode (int dVirtAudioMultimedia
 #define DEST_EXTPORT3 0x14
 #define DEST_MCPDM_ON 0x15
 #define DEST_CBP_CBPr 0x3F
-
 /*
  * ATC DESCRIPTORS - SOURCES
  */
@@ -303,5 +240,4 @@ extern void target_server_set_dVirtAudioMultimediaMode (int dVirtAudioMultimedia
 #define SRC_MCASP_RX2 0x10
 #define SRC_MCASP_RX3 0x11
 #define SRC_CBP_CBPr 0x3F
-
-#endif	/* _ABE_EXT_H_ */
+#endif/* _ABE_EXT_H_ */
diff --git a/sound/soc/omap/abe/abe_firmware.c b/sound/soc/omap/abe/abe_firmware.c
index 33f6cea2744f..5e54fbdf49ee 100644
--- a/sound/soc/omap/abe/abe_firmware.c
+++ b/sound/soc/omap/abe/abe_firmware.c
@@ -1,8 +1,8 @@
-0x00008005,  /* VERSION NUMBER */
+0x00008052,  /* VERSION NUMBER */
 0x00002000,  /* PMEM LENGTH IN BYTES */
-0x000014A4,  /* CMEM LENGTH IN BYTES */
+0x000014F8,  /* CMEM LENGTH IN BYTES */
 0x00010000,  /* DMEM LENGTH IN BYTES */
-0x000045B0,  /* SMEM LENGTH IN BYTES */
+0x000045C0,  /* SMEM LENGTH IN BYTES */
 0x1600200f,
 0x0a000670,
 0x08200000,
@@ -27,31 +27,31 @@
 0x014000ef,
 0x144000e4,
 0x9e000000,
-0x0a202d70,
+0x0a202ec0,
 0x9e000040,
-0x0a202d70,
+0x0a202ec0,
 0x9e000080,
-0x0a202d70,
+0x0a202ec0,
 0x9e0000c0,
-0x0a202d70,
+0x0a202ec0,
 0x9e080000,
-0x0a202d70,
+0x0a202ec0,
 0x9e080100,
-0x0a202d70,
+0x0a202ec0,
 0x9e080200,
-0x0a202d70,
+0x0a202ec0,
 0x9e080300,
-0x0a202d70,
+0x0a202ec0,
 0x9e080400,
-0x0a202d70,
+0x0a202ec0,
 0x9e080500,
-0x0a202d70,
+0x0a202ec0,
 0x9e080600,
-0x0a202d70,
+0x0a202ec0,
 0x9e080700,
-0x0a202d70,
+0x0a202ec0,
 0x9c050800,
-0x0a202d70,
+0x0a202ec0,
 0x16000010,
 0x16000001,
 0x17000102,
@@ -343,6 +343,27 @@
 0x988014e0,
 0x9d188108,
 0x08200000,
+0x9e088100,
+0x07800000,
+0x07800000,
+0x12800277,
+0x04c0ff77,
+0x04a00174,
+0x12800266,
+0x04c0ff66,
+0x04000645,
+0x060ffff4,
+0x17000454,
+0x12000244,
+0x9e0f0140,
+0x07800000,
+0x07800000,
+0x9c0c0118,
+0x07800000,
+0x07800000,
+0x9d0c8118,
+0x98801660,
+0x08200000,
 0x08200000,
 0x08200000,
 0x08200000,
@@ -375,7 +396,7 @@
 0x9c0c0468,
 0x9f130462,
 0x9d0c8530,
-0x98801690,
+0x988017e0,
 0x9f1380ea,
 0x9f13056a,
 0x9c0c0428,
@@ -476,23 +497,23 @@
 0x9f0020b0,
 0x9f0400d0,
 0x05800560,
-0x0a801dc0,
+0x0a801f10,
 0x9c0c0510,
-0x0a001dd0,
+0x0a001f20,
 0x9c0c0618,
 0x16000014,
 0x9d0c81e8,
 0x9d0c8148,
-0x0a801e40,
+0x0a801f90,
 0x9c0c05b0,
 0x9c0c0510,
-0x0a001e60,
+0x0a001fb0,
 0x9c0c06b8,
 0x9c0c0618,
 0x07800000,
 0x9d0c81e8,
 0x9d0c8148,
-0x98801c40,
+0x98801d90,
 0x9d180750,
 0x08200000,
 0x9d019220,
@@ -501,13 +522,13 @@
 0x413ffefe,
 0x16000040,
 0x9c010910,
-0x0a2033b0,
+0x0a203500,
 0x14400040,
 0x9c030810,
 0x16000171,
 0x9c009f30,
 0x9c019220,
-0x0a202eb0,
+0x0a203000,
 0x9c009830,
 0x003ffefe,
 0x048ffeff,
@@ -520,7 +541,7 @@
 0x04000400,
 0x9e0f0150,
 0x01000025,
-0x0a202170,
+0x0a2022c0,
 0x403ffefe,
 0x16000007,
 0x9e0f0170,
@@ -530,7 +551,7 @@
 0x413ffefe,
 0x16000005,
 0x01000025,
-0x0a202170,
+0x0a2022c0,
 0x40000024,
 0x16000005,
 0x403ffefe,
@@ -555,25 +576,25 @@
 0x9c180674,
 0x9c180650,
 0x058001a0,
-0x0aa02670,
+0x0aa027c0,
 0x04800144,
 0x04400044,
 0x05800040,
-0x0aa023b0,
+0x0aa02500,
 0x05800160,
-0x0ac02350,
+0x0ac024a0,
 0x9e090000,
 0x07800000,
 0x07800000,
 0x9e0d0500,
 0x9d040508,
-0x0a002540,
+0x0a002690,
 0x9d040008,
 0x9e090000,
 0x07800000,
 0x9d040008,
 0x9e0d0500,
-0x0a002540,
+0x0a002690,
 0x9d040008,
 0x9e090000,
 0x07800000,
@@ -582,18 +603,18 @@
 0x1280010a,
 0x048001a9,
 0x05800940,
-0x0aa02540,
+0x0aa02690,
 0x05800160,
 0x40000628,
 0x160ffff9,
-0x0ac024d0,
+0x0ac02620,
 0x05800180,
-0x0ae02540,
+0x0ae02690,
 0x160ffff6,
 0x160ffff7,
-0x0a002510,
+0x0a002660,
 0x05800810,
-0x0ae02540,
+0x0ae02690,
 0x16000016,
 0x16000007,
 0x9d044690,
@@ -601,10 +622,10 @@
 0x9d180674,
 0x05800160,
 0x9d180654,
-0x0ac025b0,
+0x0ac02700,
 0x0420040a,
 0x04a001ab,
-0x4a0025e0,
+0x4a002730,
 0x044000bb,
 0x0480014b,
 0x044000bb,
@@ -616,24 +637,24 @@
 0x12000288,
 0x12000299,
 0x9e0e8280,
-0xca002780,
+0xca0028d0,
 0x1e0e8390,
 0xdd040604,
 0x05800160,
-0x0ac02720,
+0x0ac02870,
 0x9d040008,
 0x9e090000,
 0x07800000,
 0x05800040,
 0x9e0d0500,
-0x0aa02780,
+0x0aa028d0,
 0x9d040508,
-0x0a002780,
+0x0a0028d0,
 0x9e090000,
 0x05800040,
 0x9d040008,
 0x9e0d0500,
-0x0a802780,
+0x0a8028d0,
 0x9d040508,
 0x9c1d06c4,
 0xdc1d0644,
@@ -646,7 +667,7 @@
 0x9d108700,
 0x00000cc9,
 0x06000008,
-0x0aa02980,
+0x0aa02ad0,
 0xdc1d0684,
 0x14400005,
 0xdc1d0604,
@@ -657,16 +678,16 @@
 0xdd108700,
 0x160ffff8,
 0x05800540,
-0x0aa02940,
+0x0aa02a90,
 0x05800160,
-0x0ac02930,
+0x0ac02a80,
 0x01000027,
-0x0a002940,
+0x0a002a90,
 0x01000028,
 0x9e088000,
 0xa0054dba,
 0xa005c81a,
-0x0a002a10,
+0x0a002b60,
 0x9e088000,
 0xa0054dba,
 0xa005c81a,
@@ -679,7 +700,7 @@
 0x9d0446a0,
 0x9e0f0070,
 0x9d0c8118,
-0x98802210,
+0x98802360,
 0x003ffefb,
 0x003ffcfa,
 0x003ffaf9,
@@ -698,7 +719,7 @@
 0x9d0c82b8,
 0x07800000,
 0x9d0c8318,
-0x98802b10,
+0x98802c60,
 0x07800000,
 0xa00602ba,
 0x9c0c0118,
@@ -712,9 +733,9 @@
 0x9c1d0548,
 0x9f093860,
 0x06000006,
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 0x06000017,
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+0x0aa02de0,
 0x01800025,
 0x9c0c0118,
 0x9c0c01b0,
@@ -725,9 +746,9 @@
 0x9c1d0548,
 0x9f083860,
 0x06000006,
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 0x06000017,
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 0x01800125,
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@@ -761,7 +782,7 @@
 0x9d0c8318,
 0x9d0c81b8,
 0x9d0c02b8,
-0x98802f00,
+0x98803050,
 0x07800000,
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@@ -786,7 +807,7 @@
 0x07800000,
 0x9d0c8318,
 0x9d0c02b8,
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 0x9c0c0018,
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@@ -811,7 +832,7 @@
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 0x9d0c8198,
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 0x07800000,
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@@ -826,9 +847,9 @@
 0xdd040008,
 0x06000001,
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 0x9d0c8118,
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@@ -838,8 +859,8 @@
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@@ -859,7 +880,7 @@
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@@ -881,7 +902,7 @@
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@@ -889,14 +910,14 @@
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@@ -920,7 +941,7 @@
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@@ -933,7 +954,7 @@
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@@ -964,7 +985,7 @@
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@@ -976,27 +997,27 @@
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@@ -1014,7 +1035,7 @@
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@@ -1026,27 +1047,27 @@
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@@ -1070,8 +1091,8 @@
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@@ -1086,7 +1107,7 @@
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@@ -1137,17 +1158,53 @@
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@@ -1155,75 +1212,48 @@
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@@ -1248,13 +1278,13 @@
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@@ -1313,11 +1343,11 @@
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@@ -1329,12 +1359,12 @@
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@@ -1342,7 +1372,7 @@
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@@ -1351,7 +1381,7 @@
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@@ -1360,7 +1390,7 @@
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@@ -1375,7 +1405,7 @@
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@@ -1398,14 +1428,14 @@
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@@ -1414,7 +1444,7 @@
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@@ -1460,14 +1490,14 @@
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@@ -1476,7 +1506,7 @@
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@@ -1520,20 +1550,20 @@
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@@ -1541,37 +1571,7 @@
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@@ -2277,6 +2277,8 @@
 0x00001000,
 0x00001091,
 0x00001000,
+0x00001000,
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@@ -3367,6 +3369,25 @@
 0x0033fbe6,
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 0x00080002,
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@@ -3528,32 +3549,32 @@
 0x00000000,
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@@ -5739,7 +5760,7 @@
 0x0065005C,
 0x00000013,
 0x00680017,
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 0x00000012,
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@@ -5752,22 +5773,22 @@
 0x00000013,
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 0x00000000,
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@@ -5796,11 +5817,11 @@
 0x00000000,
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@@ -5827,7 +5848,7 @@
 0x0099007C,
 0x00000000,
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 0x00960077,
 0x00000000,
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@@ -5835,43 +5856,43 @@
 0x00970079,
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@@ -5924,14 +5945,6 @@
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@@ -5986,9 +5999,17 @@
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 0x00010001,
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@@ -6016,7 +6037,7 @@
 0x00000000,
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 0x00D70056,
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 0x00000000,
 0x00030004,
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@@ -6026,21 +6047,21 @@
 0x000C0023,
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+0x00FA2DC0,
 0x00000000,
 0x00002060,
 0x00000000,
@@ -20286,46 +20311,46 @@
 0x00000000,
 0x00000000,
 0x000B2710,
-0x000F00F8,
+0x000F00FA,
 0x00000000,
 0x00000002,
 0x00000000,
 0x00000000,
-0x00013000,
+0x00013200,
 0x00000000,
-0x00013A0C,
+0x00013C0C,
 0x00000000,
-0x00083D02,
+0x00083F02,
 0x00000000,
-0x00083F04,
+0x00084104,
 0x00000000,
-0x00084306,
+0x00084506,
 0x00000000,
-0x0008490C,
+0x00084B0C,
 0x00000000,
-0x00085548,
+0x00085748,
 0x00000000,
-0x0004250C,
+0x0004270C,
 0x00000000,
-0x0004310C,
+0x0004330C,
 0x00000000,
-0x0001D00C,
+0x0001D20C,
 0x00000000,
-0x0001DC0C,
+0x0001DE0C,
 0x00000000,
-0x0001E802,
+0x0001EA02,
 0x00000000,
-0x0001EA04,
+0x0001EC04,
 0x00000000,
-0x0001EE02,
+0x0001F002,
 0x00000000,
-0x0001F004,
+0x0001F204,
 0x00000000,
-0x00086D0C,
-0x00022118,
-0x0008790C,
-0x00022118,
-0x0008850C,
+0x00086F0C,
+0x00022318,
+0x00087B0C,
+0x00022318,
+0x0008870C,
 0x00002EFC,
 0x00000000,
 0x00002F04,
@@ -20357,11 +20382,11 @@
 0x00000000,
 0x000E4000,
 0x0008B800,
-0x00013000,
+0x00013200,
 0x00003C18,
 0x00000000,
-0x00052700,
-0x00052701,
+0x00053C00,
+0x00053C01,
 0x00000000,
 0x00000000,
 0x00000000,
diff --git a/sound/soc/omap/abe/abe_functionsid.h b/sound/soc/omap/abe/abe_functionsid.h
index 6d62ee56b84d..ed39ca179697 100644
--- a/sound/soc/omap/abe/abe_functionsid.h
+++ b/sound/soc/omap/abe/abe_functionsid.h
@@ -20,61 +20,59 @@
  */
 #ifndef _ABE_FUNCTIONSID_H_
 #define _ABE_FUNCTIONSID_H_
-
 /*
  *    TASK function ID definitions
  */
-#define C_ABE_FW_FUNCTION_IIR                               0 
-#define C_ABE_FW_FUNCTION_monoToStereoPack                  1 
-#define C_ABE_FW_FUNCTION_stereoToMonoSplit                 2 
-#define C_ABE_FW_FUNCTION_decimator                         3 
-#define C_ABE_FW_FUNCTION_OS0Fill                           4 
-#define C_ABE_FW_FUNCTION_mixer2                            5 
-#define C_ABE_FW_FUNCTION_mixer4                            6 
-#define C_ABE_FW_FUNCTION_inplaceGain                       7 
-#define C_ABE_FW_FUNCTION_StreamRouting                     8 
-#define C_ABE_FW_FUNCTION_gainConverge                      9 
-#define C_ABE_FW_FUNCTION_dualIir                           10 
-#define C_ABE_FW_FUNCTION_DCOFFSET                          11 
-#define C_ABE_FW_FUNCTION_IO_DL_pp                          12 
-#define C_ABE_FW_FUNCTION_IO_generic                        13 
-#define C_ABE_FW_FUNCTION_irq_fifo_debug                    14 
-#define C_ABE_FW_FUNCTION_synchronize_pointers              15 
-#define C_ABE_FW_FUNCTION_VIBRA2                            16 
-#define C_ABE_FW_FUNCTION_VIBRA1                            17 
-#define C_ABE_FW_FUNCTION_APS_core                          18 
-#define C_ABE_FW_FUNCTION_IIR_SRC_MIC                       19 
-#define C_ABE_FW_FUNCTION_wrappers                          20 
-#define C_ABE_FW_FUNCTION_EANCUpdateOutSample               21 
-#define C_ABE_FW_FUNCTION_EANC                              22 
-#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper                   23 
-#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper                   24 
-#define C_ABE_FW_FUNCTION_mem_init                          25 
-#define C_ABE_FW_FUNCTION_debug_vx_asrc                     26 
-#define C_ABE_FW_FUNCTION_IIR_SRC2                          27 
-
+#define C_ABE_FW_FUNCTION_IIR                               0
+#define C_ABE_FW_FUNCTION_monoToStereoPack                  1
+#define C_ABE_FW_FUNCTION_stereoToMonoSplit                 2
+#define C_ABE_FW_FUNCTION_decimator                         3
+#define C_ABE_FW_FUNCTION_OS0Fill                           4
+#define C_ABE_FW_FUNCTION_mixer2                            5
+#define C_ABE_FW_FUNCTION_mixer4                            6
+#define C_ABE_FW_FUNCTION_inplaceGain                       7
+#define C_ABE_FW_FUNCTION_StreamRouting                     8
+#define C_ABE_FW_FUNCTION_gainConverge                      9
+#define C_ABE_FW_FUNCTION_dualIir                           10
+#define C_ABE_FW_FUNCTION_DCOFFSET                          11
+#define C_ABE_FW_FUNCTION_IO_DL_pp                          12
+#define C_ABE_FW_FUNCTION_IO_generic                        13
+#define C_ABE_FW_FUNCTION_irq_fifo_debug                    14
+#define C_ABE_FW_FUNCTION_synchronize_pointers              15
+#define C_ABE_FW_FUNCTION_VIBRA2                            16
+#define C_ABE_FW_FUNCTION_VIBRA1                            17
+#define C_ABE_FW_FUNCTION_APS_core                          18
+#define C_ABE_FW_FUNCTION_IIR_SRC_MIC                       19
+#define C_ABE_FW_FUNCTION_wrappers                          20
+#define C_ABE_FW_FUNCTION_EANCUpdateOutSample               21
+#define C_ABE_FW_FUNCTION_EANC                              22
+#define C_ABE_FW_FUNCTION_ASRC_DL_wrapper                   23
+#define C_ABE_FW_FUNCTION_ASRC_UL_wrapper                   24
+#define C_ABE_FW_FUNCTION_mem_init                          25
+#define C_ABE_FW_FUNCTION_debug_vx_asrc                     26
+#define C_ABE_FW_FUNCTION_IIR_SRC2                          27
 /*
  *    COPY function ID definitions
  */
-#define NULL_COPY_CFPID                                     0 
-#define S2D_STEREO_16_16_CFPID                              1 
-#define S2D_MONO_MSB_CFPID                                  2 
-#define S2D_STEREO_MSB_CFPID                                3 
-#define S2D_STEREO_RSHIFTED_16_CFPID                        4 
-#define S2D_MONO_RSHIFTED_16_CFPID                          5 
-#define D2S_STEREO_16_16_CFPID                              6 
-#define D2S_MONO_MSB_CFPID                                  7 
-#define D2S_STEREO_MSB_CFPID                                8 
-#define D2S_STEREO_RSHIFTED_16_CFPID                        9 
-#define D2S_MONO_RSHIFTED_16_CFPID                          10 
-#define COPY_DMIC_CFPID                                     11 
-#define COPY_MCPDM_DL_CFPID                                 12 
-#define COPY_MM_UL_CFPID                                    13 
-#define SPLIT_SMEM_CFPID                                    14 
-#define MERGE_SMEM_CFPID                                    15 
-#define SPLIT_TDM_CFPID                                     16 
-#define MERGE_TDM_CFPID                                     17 
-#define ROUTE_MM_UL_CFPID                                   18 
-#define IO_IP_CFPID                                         19 
-
-#endif /* _ABE_FUNCTIONSID_H_ */
+#define NULL_COPY_CFPID                                     0
+#define S2D_STEREO_16_16_CFPID                              1
+#define S2D_MONO_MSB_CFPID                                  2
+#define S2D_STEREO_MSB_CFPID                                3
+#define S2D_STEREO_RSHIFTED_16_CFPID                        4
+#define S2D_MONO_RSHIFTED_16_CFPID                          5
+#define D2S_STEREO_16_16_CFPID                              6
+#define D2S_MONO_MSB_CFPID                                  7
+#define D2S_MONO_RSHIFTED_16_CFPID                          8
+#define D2S_STEREO_RSHIFTED_16_CFPID                        9
+#define D2S_STEREO_MSB_CFPID                                10
+#define COPY_DMIC_CFPID                                     11
+#define COPY_MCPDM_DL_CFPID                                 12
+#define COPY_MM_UL_CFPID                                    13
+#define SPLIT_SMEM_CFPID                                    14
+#define MERGE_SMEM_CFPID                                    15
+#define SPLIT_TDM_CFPID                                     16
+#define MERGE_TDM_CFPID                                     17
+#define ROUTE_MM_UL_CFPID                                   18
+#define IO_IP_CFPID                                         19
+#define COPY_UNDERFLOW_CFPID                                20
+#endif/* _ABE_FUNCTIONSID_H_ */
diff --git a/sound/soc/omap/abe/abe_fw.h b/sound/soc/omap/abe/abe_fw.h
index 828f400474f1..849e49270219 100644
--- a/sound/soc/omap/abe/abe_fw.h
+++ b/sound/soc/omap/abe/abe_fw.h
@@ -17,96 +17,68 @@
  * along with this program; if not, write to the Free Software`
  * 02110-1301 USA
  */
-
 #include "abe_cm_addr.h"
 #include "abe_sm_addr.h"
 #include "abe_dm_addr.h"
 #include "abe_typedef.h"
-
 /*
  * GLOBAL DEFINITION
  */
 /* one scheduler loop = 4kHz = 12 samples at 48kHz */
 #define FW_SCHED_LOOP_FREQ	4000
-
 /* one scheduler loop = 4kHz = 12 samples at 48kHz */
 #define FW_SCHED_LOOP_FREQ_DIV1000	(FW_SCHED_LOOP_FREQ/1000)
 #define EVENT_FREQUENCY 96000
 #define SLOTS_IN_SCHED_LOOP (96000/FW_SCHED_LOOP_FREQ)
-
 #define SCHED_LOOP_8kHz ( 8000/FW_SCHED_LOOP_FREQ)
 #define SCHED_LOOP_16kHz (16000/FW_SCHED_LOOP_FREQ)
 #define SCHED_LOOP_24kHz (24000/FW_SCHED_LOOP_FREQ)
 #define SCHED_LOOP_48kHz (48000/FW_SCHED_LOOP_FREQ)
-
 #define TASKS_IN_SLOT 8
 /*
  * DMEM AREA - SCHEDULER
  */
 #define dmem_mm_trace D_DEBUG_FIFO_ADDR
 #define dmem_mm_trace_size ((D_DEBUG_FIFO_ADDR_END-D_DEBUG_FIFO_ADDR+1)/4)
-
-#define ATC_SIZE 8 /* 8 bytes per descriptors */
-
+#define ATC_SIZE 8		/* 8 bytes per descriptors */
 typedef struct {
-unsigned rdpt :
-	7; /* first 32bits word of the descriptor */
-unsigned reserved0 :
-	1;
-unsigned cbsize :
-	7;
-unsigned irqdest :
-	1;
-unsigned cberr :
-	1;
-unsigned reserved1 :
-	5;
-unsigned cbdir :
-	1;
-unsigned nw :
-	1;
-unsigned wrpt :
-	7;
-unsigned reserved2 :
-	1;
-unsigned badd :
-	12; /* second 32bits word of the descriptor */
-unsigned iter :
-	7; /* iteration field overlaps the 16 bits boundary */
-unsigned srcid :
-	6;
-unsigned destid :
-	6;
-unsigned desen :
-	1;
+	unsigned rdpt:7;	/* first 32bits word of the descriptor */
+	unsigned reserved0:1;
+	unsigned cbsize:7;
+	unsigned irqdest:1;
+	unsigned cberr:1;
+	unsigned reserved1:5;
+	unsigned cbdir:1;
+	unsigned nw:1;
+	unsigned wrpt:7;
+	unsigned reserved2:1;
+	unsigned badd:12;	/* second 32bits word of the descriptor */
+	unsigned iter:7;	/* iteration field overlaps the 16 bits boundary */
+	unsigned srcid:6;
+	unsigned destid:6;
+	unsigned desen:1;
 } abe_satcdescriptor_aess;
-
 /*
  * table of scheduler tasks :
  * char scheduler_table[24 x 4] : four bytes used at OPP100%
  */
 #define dmem_scheduler_table	 D_multiFrame_ADDR
-
 #define dmem_eanc_task_pointer 	D_pFastLoopBack_ADDR
-
 /*
  * OPP value :
  * pointer increment steps in the scheduler table
  */
 #define dmem_scheduler_table_step	D_taskStep_ADDR
-
 /*
  * table of scheduler tasks (max 64) :
  * char task_descriptors[64 x 8] : eight bytes per task
  * TASK INDEX, INITPTR 1,2,3, INITREG, Loop Counter, Reserved 1,2
  */
 #define dmem_task_descriptor	D_tasksList_ADDR
-
 /*
  * I/O DESCRIPTORS
  */
 #define dmem_port_descriptors	D_IOdescr_ADDR
-
 /* ping_pong_t descriptors table
  * structure of 8 bytes:
  * uint16 base_address1
@@ -116,16 +88,13 @@ unsigned desen :
  * } ping_pong_t
  * ping_pong_t dmem_ping_pong_t [8]
  */
-
 /* U8 address */
 #define dmem_ping_pong_buffer	D_PING_ADDR
-
 /*
  * IRQ mask used with ports with IRQ (DMA or host)
  * uint32 dmem_irq_masks [8]
  */
 #define dmem_irq_masks	D_IRQMask_ADDR
-
 /*
  * tables of to the 8 FIFO sequences (delayed commands) holding 12bytes tasks
  * in the format
@@ -147,7 +116,6 @@ unsigned desen :
  */
 #define dmem_fifo_sequences	D_DCFifo_ADDR
 #define dmem_fifo_sequences_descriptors	D_DCFifoDesc_ADDR
-
 /*
  * IRQ FIFOs
  *
@@ -162,7 +130,6 @@ unsigned desen :
 #define dmem_fifo_irq_dsp_descriptor	D_DspIrqFifoDesc_ADDR
 #define dmem_fifo_irq_mcu	D_McuIrqFifo_ADDR
 #define dmem_fifo_irq_dsp	D_DspIrqFifo_ADDR
-
 /*
  * remote debugger exchange buffer
  * uint32 dmem_debug_ae2hal [32]
@@ -170,7 +137,6 @@ unsigned desen :
  */
 #define dmem_debug_ae2hal	D_DebugAbe2hal_ADDR
 #define dmem_debug_hal2ae	D_Debug_hal2abe_ADDR
-
 /*
  * DMEM address of the ASRC ppm drift parameter for ASRCs (voice and multimedia
  * paths)
@@ -178,15 +144,12 @@ unsigned desen :
  */
 #define dmem_asrc1_drift	D_ASRC1drift_ADDR
 #define dmem_asrc2_drift	D_ASRC2drift_ADDR
-
 /*
  * DMEM indexes of the router uplink paths
  * uint8 dmem_router_index [8]
  */
 // OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 //#define dmem_router_index
-
-
 /*
  * analog control circular buffer commands to Phoenix
  * structure {
@@ -197,7 +160,6 @@ unsigned desen :
  */
 #define dmem_commands_to_phoenix 	D_Cmd2PhenixFifo_ADDR
 #define dmem_commands_to_phoenix_descriptor 	D_Cmd2PhenixFifoDesc_ADDR
-
 /*
  * analog control circular buffer commands from Phoenix (status line)
  * structure {
@@ -208,16 +170,13 @@ unsigned desen :
  */
 #define dmem_commands_from_phoenix	D_StatusFromPhenixFifo_ADDR
 #define dmem_commands_from_phoenix_descriptor 	D_StatusFromPhenixFifoDesc_ADDR
-
 /*
  * DEBUG mask
  * uint16 dmem_debug_trace_mask
  * each bit of this word enables a type a trace in the debug circular buffer
  */
-
 // OC: TBD ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 //#define dmem_debug_trace_mask
-
 /*
  * DEBUG circular buffer
  * structure {
@@ -230,84 +189,62 @@ unsigned desen :
 #define dmem_debug_trace_buffer
 #define dmem_debug_trace_fifo	D_debugFifo_ADDR
 #define dmem_debug_trace_descriptor	D_debugFifoDesc_ADDR
-
 /*
  * Infinite counter incremented on each sheduler periods (~250 us)
  * uint16 dmem_debug_time_stamp
  */
 #define dmem_debug_time_stamp	D_loopCounter_ADDR
-
 /*
  * ATC BUFFERS + IO TASKS SMEM buffers
  */
 #define dmem_dmic D_DMIC_UL_FIFO_ADDR
 #define dmem_dmic_size (D_DMIC_UL_FIFO_sizeof/4)
-
 #define dmem_amic D_McPDM_UL_FIFO_ADDR
 #define dmem_amic_size (D_McPDM_UL_FIFO_sizeof/4)
 #define smem_amic	AMIC_96_labelID
-
 #define dmem_mcpdm D_McPDM_DL_FIFO_ADDR
 #define dmem_mcpdm_size (D_McPDM_DL_FIFO_sizeof/4)
-
 #define dmem_mm_ul D_MM_UL_FIFO_ADDR
 #define dmem_mm_ul_size (D_MM_UL_FIFO_sizeof/4)
-
 /* managed directly by the router */
 #define smem_mm_ul MM_UL_labelID
-
 #define dmem_mm_ul2 D_MM_UL2_FIFO_ADDR
 #define dmem_mm_ul2_size (D_MM_UL2_FIFO_sizeof/4)
-
 /* managed directly by the router */
 #define smem_mm_ul2 MM_UL2_labelID
-
 #define dmem_mm_dl D_MM_DL_FIFO_ADDR
 #define dmem_mm_dl_size (D_MM_DL_FIFO_sizeof/4)
-
-/*IO_MM_DL_ASRC_labelID	 ASRC input buffer, size 40 */
-#define smem_mm_dl_opp100 MM_DL_labelID
-
-/* at OPP 25/50 or without ASRC */
-#define smem_mm_dl_opp25 MM_DL_labelID
-
+#define smem_mm_dl MM_DL_labelID
 #define dmem_vx_dl D_VX_DL_FIFO_ADDR
 #define dmem_vx_dl_size (D_VX_DL_FIFO_sizeof/4)
-#define smem_vx_dl	IO_VX_DL_ASRC_labelID /* Voice_16k_DL_labelID */
-
+#define smem_vx_dl	IO_VX_DL_ASRC_labelID	/* Voice_16k_DL_labelID */
 #define dmem_vx_ul D_VX_UL_FIFO_ADDR
 #define dmem_vx_ul_size (D_VX_UL_FIFO_sizeof/4)
 #define smem_vx_ul Voice_16k_UL_labelID
-
 #define dmem_tones_dl D_TONES_DL_FIFO_ADDR
 #define dmem_tones_dl_size (D_TONES_DL_FIFO_sizeof/4)
 #define smem_tones_dl Tones_labelID
-
 #define dmem_vib_dl D_VIB_DL_FIFO_ADDR
 #define dmem_vib_dl_size (D_VIB_DL_FIFO_sizeof/4)
 #define smem_vib IO_VIBRA_DL_labelID
-
 #define dmem_mm_ext_out D_MM_EXT_OUT_FIFO_ADDR
 #define dmem_mm_ext_out_size (D_MM_EXT_OUT_FIFO_sizeof/4)
 #define smem_mm_ext_out DL1_GAIN_out_labelID
-
 #define dmem_mm_ext_in D_MM_EXT_IN_FIFO_ADDR
 #define dmem_mm_ext_in_size (D_MM_EXT_IN_FIFO_sizeof/4)
-#define smem_mm_ext_in MM_EXT_IN_labelID
-
+/*IO_MM_EXT_IN_ASRC_labelID	 ASRC input buffer, size 40 */
+#define smem_mm_ext_in_opp100 IO_MM_EXT_IN_ASRC_labelID
+/* at OPP 50 without ASRC */
+#define smem_mm_ext_in_opp50 MM_EXT_IN_labelID
 #define dmem_bt_vx_dl D_BT_DL_FIFO_ADDR
 #define dmem_bt_vx_dl_size (D_BT_DL_FIFO_sizeof/4)
 #define smem_bt_vx_dl BT_DL_8k_labelID
-
 #define dmem_bt_vx_ul D_BT_UL_FIFO_ADDR
 #define dmem_bt_vx_ul_size (D_BT_UL_FIFO_sizeof/4)
 #define smem_bt_vx_ul BT_UL_8k_labelID
-
-
 /*
  * INITPTR / INITREG AREA
  */
-
 /*
  * POINTER - used for the port descriptor programming
  * corresponds to 8bits addresses to the INITPTR area
@@ -320,19 +257,15 @@ unsigned desen :
 #define ptr_mm_ext
 #define ptr_tones
 #define ptr_vibra2
-
 /*
  * SMEM AREA
  */
-
 /*
  * PHOENIX OFFSET in SMEM
  * used to subtract a DC offset on the headset path (power consumption optimization)
  */
-
 /* OC: exact usage to be detailled */
 #define smem_phoenix_offset	S_PhoenixOffset_ADDR
-
 /*
  * EQUALIZERS Z AREA
  * used to reset the filter memory - IIR-8 (max)
@@ -343,7 +276,6 @@ unsigned desen :
 #define smem_equ3	S_EQU3_data_ADDR
 #define smem_equ4	S_EQU4_data_ADDR
 #define smem_sdt	S_SDT_data_ADDR
-
 /*
  * GAIN SMEM on PORT
  * int32 smem_G0 [18] : desired gain on the ports
@@ -364,11 +296,9 @@ unsigned desen :
 #define smem_g0	S_GTarget_ADDR	// [9] 2 gains in 1 SM address
 #define smem_g1	S_GCurrent_ADDR	// [9] 2 gains in 1 SM address
 #endif
-
 /*
  * COEFFICIENTS AREA
  */
-
 /*
  * delay coefficients used in the IIR-1 filters
  * int24 cmem_gain_delay_iir1[9 x 2] (a, (1-a))
@@ -380,16 +310,13 @@ unsigned desen :
  * 1 for 2 MM_VX_DL L R
  * 1 for 2 IHF L R
  */
-
 #define cmem_gain_alpha	C_Alpha_ADDR
 #define cmem_gain_1_alpha	C_1_Alpha_ADDR
-
 /*
  * gain controls
  */
 #define GAIN_LEFT_OFFSET 0
 #define GAIN_RIGHT_OFFSET 1
-
 /* stereo gains */
 #define dmic1_gains_offset 0
 #define dmic2_gains_offset 2
@@ -398,7 +325,6 @@ unsigned desen :
 #define dl1_gains_offset 8
 #define dl2_gains_offset 10
 #define splitters_gains_offset 12
-
 #define mixer_dl1_offset 14
 #define mixer_dl2_offset 18
 #define mixer_echo_offset 22
@@ -406,9 +332,6 @@ unsigned desen :
 #define mixer_vxrec_offset 26
 #define mixer_audul_offset 30
 #define gain_unused_offset 34
-
-
-
 /*
  * DMIC SRC 96->48
  * the filter is changed depending on the decimatio ratio used (16/25/32/40)
@@ -416,7 +339,6 @@ unsigned desen :
  * in the direct part
  */
 #define cmem_src2_dmic
-
 /*
  * EANC coefficients
  * structure of :
@@ -427,7 +349,6 @@ unsigned desen :
 #define cmem_eanc_coef_fir
 #define cmem_eanc_coef_iir
 #define cmem_eanc_coef_lambda
-
 /*
  * EQUALIZERS - SDT - COEF AREA
  * int24 cmem_equ(x) [8x2+1]
@@ -437,7 +358,6 @@ unsigned desen :
 #define cmem_equ3	C_EQU3_data_ADDR
 #define cmem_equ4	C_EQU4_data_ADDR
 #define cmem_sdt	C_SDT_data_ADDR
-
 /*
  * APS - COEF AREA
  * int24 cmem_aps(x) [16]
@@ -445,7 +365,6 @@ unsigned desen :
 #define cmem_aps1
 #define cmem_aps2
 #define cmem_aps3
-
 /*
  * DITHER - COEF AREA
  * int24 cmem_dither(x) [4]
diff --git a/sound/soc/omap/abe/abe_ini.c b/sound/soc/omap/abe/abe_ini.c
index 63a5e1082510..51d9cc18df93 100644
--- a/sound/soc/omap/abe/abe_ini.c
+++ b/sound/soc/omap/abe/abe_ini.c
@@ -18,12 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
 #include "abe_dm_addr.h"
-
-short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
-
 /*
  * initialize the default values for call-backs to subroutines
  * - FIFO IRQ call-backs for sequenced tasks
@@ -32,48 +28,42 @@ short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
  * - Error monitoring
  * - Activity Tracing
  */
-
+static short MultiFrame[PROCESSING_SLOTS][TASKS_IN_SLOT];
 /**
  * abe_hw_configuration
  *
  */
-void abe_hw_configuration ()
+void abe_hw_configuration()
 {
 	u32 atc_reg;
-
 	/* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */
 	atc_reg = 0xFF;
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4);
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_ATC, 0x60, &atc_reg, 4);
 }
-
 /**
  * abe_build_scheduler_table
  *
  */
-void abe_build_scheduler_table ()
+void abe_build_scheduler_table()
 {
 	u16 i, n;
 	u8 *ptr;
 	char aUplinkMuxing[16];
 #define ABE_TASK_ID(ID) (D_tasksList_ADDR + sizeof(ABE_STask)*(ID))
-
 	/* LOAD OF THE TASKS' MULTIFRAME */
 	/* WARNING ON THE LOCATION OF IO_MM_DL WHICH IS PATCHED
-		IN "abe_init_io_tasks" */
-
-	for (ptr = (u8 *)&(MultiFrame[0][0]), i=0;
-	     i < sizeof (MultiFrame); i++)
+	   IN "abe_init_io_tasks" */
+	for (ptr = (u8 *) &(MultiFrame[0][0]), i = 0;
+	     i < sizeof(MultiFrame); i++)
 		*ptr++ = 0;
-
 	/* MultiFrame[0][0] = 0; */
 	/* MultiFrame[0][1] = 0; */
 	MultiFrame[0][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VX_DL);
 	/* MultiFrame[0][3] = 0; */
 	/* MultiFrame[0][4] = 0; */
 	/* MultiFrame[0][5] = 0; */
-	/* MultiFrame[0][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_MM_DL);*/
+	/* MultiFrame[0][6] = 0; */
 	/* MultiFrame[0][7] = 0; */
-
 	/* MultiFrame[1][0] = 0; */
 	/* MultiFrame[1][1] = 0; */
 #define TASK_ASRC_VX_DL_SLT 1
@@ -86,7 +76,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[1][5] = 0; */
 	MultiFrame[1][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2Mixer);
 	MultiFrame[1][7] = ABE_TASK_ID(C_ABE_FW_TASK_IO_VIB_DL);
-
 	MultiFrame[2][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1Mixer);
 	MultiFrame[2][1] = ABE_TASK_ID(C_ABE_FW_TASK_SDTMixer);
 	/* MultiFrame[2][2] = 0; */
@@ -95,7 +84,6 @@ void abe_build_scheduler_table ()
 	MultiFrame[2][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_DMIC);
 	/* MultiFrame[2][6] = 0; */
 	/* MultiFrame[2][7] = 0; */
-
 	MultiFrame[3][1] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_GAIN);
 	MultiFrame[3][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_EQ);
 	MultiFrame[3][2] = ABE_TASK_ID(C_ABE_FW_TASK_EchoMixer);
@@ -104,7 +92,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[3][5] = 0; */
 	MultiFrame[3][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_GAIN);
 	MultiFrame[3][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_APS_EQ);
-
 	MultiFrame[4][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_EQ);
 	/* MultiFrame[4][1] = 0; */
 	MultiFrame[4][2] = ABE_TASK_ID(C_ABE_FW_TASK_VXRECMixer);
@@ -113,8 +100,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[4][5] = 0; */
 	MultiFrame[4][6] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA1);
 	MultiFrame[4][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA2);
-
-
 	MultiFrame[5][0] = 0;
 	MultiFrame[5][1] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP);
 	MultiFrame[5][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_UL);
@@ -123,7 +108,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[5][5] = 0; */
 	MultiFrame[5][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_EQ);
 	MultiFrame[5][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_SPLIT);
-
 	MultiFrame[6][0] = ABE_TASK_ID(C_ABE_FW_TASK_EARP_48_96_LP);
 	/* MultiFrame[6][1] = 0; */
 	/* MultiFrame[6][2] = 0; */
@@ -132,7 +116,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[6][5] = 0; */
 	MultiFrame[6][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_APS_SPLIT);
 	/* MultiFrame[6][7] = 0; */
-
 	MultiFrame[7][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL);
 	/* MultiFrame[7][1] = 0; */
 	MultiFrame[7][2] = ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_SPLIT);
@@ -141,7 +124,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[7][5] = 0; */
 	MultiFrame[7][6] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_R_APS_CORE);
 	MultiFrame[7][7] = ABE_TASK_ID(C_ABE_FW_TASK_DL2_L_APS_CORE);
-
 	/* MultiFrame[8][0] = 0; */
 	/* MultiFrame[8][1] = 0; */
 	MultiFrame[8][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC1_96_48_LP);
@@ -150,7 +132,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[8][5] = 0; */
 	/* MultiFrame[8][6] = 0; */
 	/* MultiFrame[8][7] = 0; */
-
 	/* MultiFrame[9][0] = 0; */
 	/* MultiFrame[9][1] = 0; */
 	MultiFrame[9][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC2_96_48_LP);
@@ -159,7 +140,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[9][5] = 0; */
 	MultiFrame[9][6] = 0;
 	MultiFrame[9][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP);
-
 	/* MultiFrame[10][0] = 0; */
 	/* MultiFrame[10][1] = 0; */
 	MultiFrame[10][2] = ABE_TASK_ID(C_ABE_FW_TASK_DMIC3_96_48_LP);
@@ -168,7 +148,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[10][5] = 0; */
 	/* MultiFrame[10][6] = 0; */
 	MultiFrame[10][7] = ABE_TASK_ID(C_ABE_FW_TASK_IHF_48_96_LP);
-
 	/* MultiFrame[11][0] = 0; */
 	/* MultiFrame[11][1] = 0; */
 	MultiFrame[11][2] = ABE_TASK_ID(C_ABE_FW_TASK_AMIC_96_48_LP);
@@ -177,7 +156,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[11][5] = 0; */
 	/* MultiFrame[11][6] = 0; */
 	MultiFrame[11][7] = ABE_TASK_ID(C_ABE_FW_TASK_VIBRA_PACK);
-
 	/* MultiFrame[12][0] = 0; */
 	/* MultiFrame[12][1] = 0; */
 	/* MultiFrame[12][2] = 0; */
@@ -188,7 +166,6 @@ void abe_build_scheduler_table ()
 	MultiFrame[12][5] = ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16);
 	/* MultiFrame[12][6] = 0; */
 	/* MultiFrame[12][7] = 0; */
-
 	/* MultiFrame[13][0] = 0; */
 	/* MultiFrame[13][1] = 0; */
 	MultiFrame[13][2] = ABE_TASK_ID(C_ABE_FW_TASK_MM_UL2_ROUTING);
@@ -197,7 +174,6 @@ void abe_build_scheduler_table ()
 	MultiFrame[13][5] = ABE_TASK_ID(C_ABE_FW_TASK_IO_BT_VX_DL);
 	/* MultiFrame[13][6] = 0; */
 	/* MultiFrame[13][7] = 0; */
-
 	/* MultiFrame[14][0] = 0; */
 	/* MultiFrame[14][1] = 0; */
 	/* MultiFrame[14][2] = 0; */
@@ -208,7 +184,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[14][5] = 0; */
 	/* MultiFrame[14][6] = 0; */
 	/* MultiFrame[14][7] = 0; */
-
 	MultiFrame[15][0] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_IIR);
 	MultiFrame[15][1] = ABE_TASK_ID(C_ABE_FW_TASK_DL1_APS_CORE);
 	/* MultiFrame[15][2] = 0; */
@@ -217,7 +192,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[15][5] = 0; */
 	/* MultiFrame[15][6] = 0; */
 	/* MultiFrame[15][7] = 0; */
-
 	/* MultiFrame[16][0] = 0; */
 	/* MultiFrame[16][1] = 0; */
 #define TASK_ASRC_VX_UL_SLT 16
@@ -228,7 +202,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[16][5] = 0; */
 	/* MultiFrame[16][6] = 0; */
 	/* MultiFrame[16][7] = 0; */
-
 	/* MultiFrame[17][0] = 0; */
 	/* MultiFrame[17][1] = 0; */
 #define TASK_BT_UL_8_48_SLT 17
@@ -239,7 +212,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[17][5] = 0; */
 	/* MultiFrame[17][6] = 0; */
 	/* MultiFrame[17][7] = 0; */
-
 #define TASK_IO_MM_DL_SLT 18
 #define TASK_IO_MM_DL_IDX 0
 	MultiFrame[18][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL);
@@ -250,7 +222,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[18][5] = 0; */
 	/* MultiFrame[18][6] = 0; */
 	/* MultiFrame[18][7] = 0; */
-
 	MultiFrame[19][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_PDM_DL);
 	/* MultiFrame[19][1] = 0 */
 	/* MultiFrame[19][2] = 0; */
@@ -260,36 +231,33 @@ void abe_build_scheduler_table ()
 	/*         MM_UL is moved to OPP 100% */
 	MultiFrame[19][6] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_UL);
 	/* MultiFrame[19][7] = 0; */
-
-
 	MultiFrame[20][0] = ABE_TASK_ID(C_ABE_FW_TASK_IO_TONES_DL);
 	/* MultiFrame[20][1] = 0; */
 	/* MultiFrame[20][2] = 0; */
 	/* MultiFrame[20][3] = 0; */
 	/* MultiFrame[20][4] = 0; */
 	/* MultiFrame[20][5] = 0; */
-	/* MultiFrame[20][6] = 0; */
+	MultiFrame[20][6] = ABE_TASK_ID(C_ABE_FW_TASK_ASRC_MM_EXT_IN);
 	/* MultiFrame[20][7] = 0; */
-
 	/* MultiFrame[21][0] = 0; */
 	MultiFrame[21][1] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs);
 	MultiFrame[21][2] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_OUT);
-	/* MultiFrame[21][3] = 0; */
+	MultiFrame[21][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN);
 	/* MultiFrame[21][4] = 0; */
 	/* MultiFrame[21][5] = 0; */
 	/* MultiFrame[21][6] = 0; */
 	/* MultiFrame[21][7] = 0; */
-
 	/* MUST STAY ON SLOT 22 */
 	MultiFrame[22][0] = ABE_TASK_ID(C_ABE_FW_TASK_DEBUG_IRQFIFO);
 	MultiFrame[22][1] = ABE_TASK_ID(C_ABE_FW_TASK_INIT_FW_MEMORY);
 	MultiFrame[22][2] = 0;
-	MultiFrame[22][3] = ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_EXT_IN);
+	/* MultiFrame[22][3] = 0; */
+	/* MM_EXT_IN_SPLIT task must be after IO_MM_EXT_IN and before
+	   ASRC_MM_EXT_IN in order to manage OPP50 <-> transitions */
 	MultiFrame[22][4] = ABE_TASK_ID(C_ABE_FW_TASK_MM_EXT_IN_SPLIT);
 	/* MultiFrame[22][5] = 0; */
 	/* MultiFrame[22][6] = 0; */
 	/* MultiFrame[22][7] = 0; */
-
 	MultiFrame[23][0] = ABE_TASK_ID(C_ABE_FW_TASK_GAIN_UPDATE);
 	/* MultiFrame[23][1] = 0; */
 	/* MultiFrame[23][2] = 0; */
@@ -298,7 +266,6 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[23][5] = 0; */
 	/* MultiFrame[23][6] = 0; */
 	/* MultiFrame[23][7] = 0; */
-
 	/* MultiFrame[24][0] = 0; */
 	/* MultiFrame[24][1] = 0; */
 	/* MultiFrame[24][2] = 0; */
@@ -307,43 +274,35 @@ void abe_build_scheduler_table ()
 	/* MultiFrame[24][5] = 0; */
 	/* MultiFrame[24][6] = 0; */
 	/* MultiFrame[24][7] = 0; */
-
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR,
-			(u32*)MultiFrame, sizeof (MultiFrame));
-
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_multiFrame_ADDR,
+		       (u32 *) MultiFrame, sizeof(MultiFrame));
 	/* reset the uplink router */
-	n = (D_aUplinkRouting_sizeof)>>1;
+	n = (D_aUplinkRouting_sizeof) >> 1;
 	for (i = 0; i < n; i++)
 		aUplinkMuxing[i] = ZERO_labelID;
-
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR,
-			(u32 *)aUplinkMuxing, sizeof (aUplinkMuxing));
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM, D_aUplinkRouting_ADDR,
+		       (u32 *) aUplinkMuxing, sizeof(aUplinkMuxing));
 }
-
 /**
  * abe_init_atc
  * @id: ABE port ID
  *
  * load the DMEM ATC/AESS descriptors
  */
-void abe_init_atc (u32 id)
+void abe_init_atc(u32 id)
 {
 	abe_satcdescriptor_aess desc;
 	u8 iter;
 	s32 datasize;
-
 	/* load default values of the descriptor */
 	desc.rdpt = desc.wrpt = desc.irqdest = desc.cberr = 0;
-	desc.desen = desc.nw =0;
+	desc.desen = desc.nw = 0;
 	desc.reserved0 = desc.reserved1 = desc.reserved2 = 0;
 	desc.srcid = desc.destid = desc.badd = desc.iter = desc.cbsize = 0;
-
-	datasize = abe_dma_port_iter_factor (&((abe_port[id]).format));
-	iter = (u8) abe_dma_port_iteration (&((abe_port[id]).format));
-
-
+	datasize = abe_dma_port_iter_factor(&((abe_port[id]).format));
+	iter = (u8) abe_dma_port_iteration(&((abe_port[id]).format));
 	/* if the ATC FIFO is too small there will be two ABE firmware
-		utasks to do the copy this happems on DMIC and MCPDMDL */
+	   utasks to do the copy this happems on DMIC and MCPDMDL */
 	/* VXDL_8kMono = 4 = 2 + 2x1 */
 	/* VXDL_16kstereo = 12 = 8 + 2x2 */
 	/* MM_DL_1616 = 14 = 12 + 2x1 */
@@ -352,121 +311,113 @@ void abe_init_atc (u32 id)
 	/* VXUL_16kstereo = 4 */
 	/* MM_UL2_Stereo = 4 */
 	/* PDMDL = 12 */
-
 	/* IN from AESS point of view */
 	if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
-		if (iter + 2*datasize > 126)
-			desc.wrpt = (iter >>1) + (3*datasize);
+		if (iter + 2 * datasize > 126)
+			desc.wrpt = (iter >> 1) + (JITTER_MARGIN * datasize);
 		else
-			desc.wrpt = iter + 3*datasize;
+			desc.wrpt = iter + (JITTER_MARGIN * datasize);
 	else
-		desc.wrpt = 0 + 3*datasize;
-
+		desc.wrpt = 0 + (JITTER_MARGIN * datasize);
 	switch ((abe_port[id]).protocol.protocol_switch) {
-	case SLIMBUS_PORT_PROT :
+	case SLIMBUS_PORT_PROT:
 		desc.cbdir = (abe_port[id]).protocol.direction;
-		desc.cbsize = (abe_port[id]).
-			      protocol.p.prot_slimbus.buf_size;
-		desc.badd = ((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4;
+		desc.cbsize = (abe_port[id]).protocol.p.prot_slimbus.buf_size;
+		desc.badd =
+			((abe_port[id]).protocol.p.prot_slimbus.buf_addr1) >> 4;
 		desc.iter = (abe_port[id]).protocol.p.prot_slimbus.iter;
-		desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.
-					    prot_slimbus.desc_addr1 >> 3];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				(abe_port[id]).protocol.p.prot_slimbus.desc_addr1,
-				(u32*)&desc, sizeof (desc));
-
+		desc.srcid =
+			abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus.
+				      desc_addr1 >> 3];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (abe_port[id]).protocol.p.prot_slimbus.
+			       desc_addr1, (u32 *) &desc, sizeof(desc));
 		desc.badd = (abe_port[id]).protocol.p.prot_slimbus.buf_addr2;
-		desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.
-					    prot_slimbus.desc_addr2 >> 3];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				(abe_port[id]).protocol.p.prot_slimbus.desc_addr2,
-				(u32*)&desc, sizeof (desc));
+		desc.srcid =
+			abe_atc_srcid[(abe_port[id]).protocol.p.prot_slimbus.
+				      desc_addr2 >> 3];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (abe_port[id]).protocol.p.prot_slimbus.
+			       desc_addr2, (u32 *) &desc, sizeof(desc));
 		break;
-	case SERIAL_PORT_PROT :
+	case SERIAL_PORT_PROT:
 		desc.cbdir = (abe_port[id]).protocol.direction;
 		desc.cbsize = (abe_port[id]).protocol.p.prot_serial.buf_size;
-		desc.badd = ((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4;
+		desc.badd =
+			((abe_port[id]).protocol.p.prot_serial.buf_addr) >> 4;
 		desc.iter = (abe_port[id]).protocol.p.prot_serial.iter;
-		desc.srcid = abe_atc_srcid [(abe_port[id]).protocol.p.
-					    prot_serial.desc_addr >> 3];
-		desc.destid = abe_atc_dstid [(abe_port[id]).protocol.p.
-					     prot_serial.desc_addr >> 3];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				(abe_port[id]).protocol.p.prot_serial.desc_addr,
-				(u32*)&desc, sizeof (desc));
+		desc.srcid =
+			abe_atc_srcid[(abe_port[id]).protocol.p.prot_serial.
+				      desc_addr >> 3];
+		desc.destid =
+			abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.
+				      desc_addr >> 3];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (abe_port[id]).protocol.p.prot_serial.desc_addr,
+			       (u32 *) &desc, sizeof(desc));
 		break;
-	case DMIC_PORT_PROT :
+	case DMIC_PORT_PROT:
 		desc.cbdir = ABE_ATC_DIRECTION_IN;
 		desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size;
 		desc.badd = ((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4;
 		desc.iter = DMIC_ITER;
-		desc.srcid = abe_atc_srcid [ABE_ATC_DMIC_DMA_REQ];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				ABE_ATC_DMIC_DMA_REQ * ATC_SIZE, (u32*)&desc,
-				sizeof (desc));
+		desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE),
+			       (u32 *) &desc, sizeof(desc));
 		break;
-	case MCPDMDL_PORT_PROT :
+	case MCPDMDL_PORT_PROT:
 		desc.cbdir = ABE_ATC_DIRECTION_OUT;
 		desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmdl.buf_size;
-		desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
+		desc.badd =
+			((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
 		desc.iter = MCPDM_DL_ITER;
-		desc.destid = abe_atc_dstid [ABE_ATC_MCPDMDL_DMA_REQ];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				ABE_ATC_MCPDMDL_DMA_REQ * ATC_SIZE, (u32*)&desc,
-				sizeof (desc));
+		desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE),
+			       (u32 *) &desc, sizeof(desc));
 		break;
-	case MCPDMUL_PORT_PROT :
+	case MCPDMUL_PORT_PROT:
 		desc.cbdir = ABE_ATC_DIRECTION_IN;
 		desc.cbsize = (abe_port[id]).protocol.p.prot_mcpdmul.buf_size;
-		desc.badd = ((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
+		desc.badd =
+			((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
 		desc.iter = MCPDM_UL_ITER;
-		desc.srcid = abe_atc_srcid [ABE_ATC_MCPDMUL_DMA_REQ];
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				ABE_ATC_MCPDMUL_DMA_REQ * ATC_SIZE, (u32*)&desc,
-				sizeof (desc));
+		desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ];
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE),
+			       (u32 *) &desc, sizeof(desc));
 		break;
 	case PINGPONG_PORT_PROT:
 		/* software protocol, nothing to do on ATC */
 		break;
-	case DMAREQ_PORT_PROT :
+	case DMAREQ_PORT_PROT:
 		desc.cbdir = (abe_port[id]).protocol.direction;
 		desc.cbsize = (abe_port[id]).protocol.p.prot_dmareq.buf_size;
-		desc.badd = ((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4;
-
+		desc.badd =
+			((abe_port[id]).protocol.p.prot_dmareq.buf_addr) >> 4;
 		/* CBPr needs ITER=1. this is the eDMA job to do the iterations */
 		desc.iter = 1;
-
 		/* input from ABE point of view */
 		if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN) {
-
 			/* desc.rdpt = 127; */
 			/* desc.wrpt = 0; */
 			desc.srcid = abe_atc_srcid
-				     [(abe_port[id]).protocol.p.
-				      prot_dmareq.desc_addr >> 3];
+				[(abe_port[id]).protocol.p.prot_dmareq.
+				 desc_addr >> 3];
 		} else {
-
 			/* desc.rdpt = 0; */
 			/* desc.wrpt = 127; */
 			desc.destid = abe_atc_dstid
-				      [(abe_port[id]).protocol.p.
-				       prot_dmareq.desc_addr >> 3];
+				[(abe_port[id]).protocol.p.prot_dmareq.
+				 desc_addr >> 3];
 		}
-
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				(abe_port[id]).protocol.p.
-				prot_dmareq.desc_addr,
-				(u32*)&desc, sizeof (desc));
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+			       (u32 *) &desc, sizeof(desc));
 		break;
 	}
 }
-
 /**
  * abe_init_dma_t
  * @ id: ABE port ID
@@ -474,99 +425,97 @@ void abe_init_atc (u32 id)
  *
  * load the dma_t with physical information from AE memory mapping
  */
-void abe_init_dma_t (u32 id, abe_port_protocol_t *prot)
+void abe_init_dma_t(u32 id, abe_port_protocol_t *prot)
 {
 	abe_dma_t_offset dma;
 	u32 idx;
-
 	/* default dma_t points to address 0000... */
 	dma.data = 0;
 	dma.iter = 0;
-
 	switch (prot->protocol_switch) {
 	case PINGPONG_PORT_PROT:
 		for (idx = 0; idx < 32; idx++) {
-			if (((prot->p).prot_pingpong.irq_data) == (u32)(1 << idx))
+			if (((prot->p).prot_pingpong.irq_data) ==
+			    (u32) (1 << idx))
 				break;
 		}
-		(prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE;
+		(prot->p).prot_dmareq.desc_addr =
+			((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
 		/* translate byte address/size in DMEM words */
 		dma.data = (prot->p).prot_pingpong.buf_addr >> 2;
 		dma.iter = (prot->p).prot_pingpong.buf_size >> 2;
 		break;
-	case DMAREQ_PORT_PROT :
+	case DMAREQ_PORT_PROT:
 		for (idx = 0; idx < 32; idx++) {
-			if (((prot->p).prot_dmareq.dma_data) == (u32)(1 << idx))
+			if (((prot->p).prot_dmareq.dma_data) ==
+			    (u32) (1 << idx))
 				break;
 		}
-		dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + idx*4);
+		dma.data = (CIRCULAR_BUFFER_PERIPHERAL_R__0 + (idx << 2));
 		dma.iter = (prot->p).prot_dmareq.iter;
-		(prot->p).prot_dmareq.desc_addr = (CBPr_DMA_RTX0+idx)*ATC_SIZE;
+		(prot->p).prot_dmareq.desc_addr =
+			((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
 		break;
-	case SLIMBUS_PORT_PROT :
-	case SERIAL_PORT_PROT :
-	case DMIC_PORT_PROT :
-	case MCPDMDL_PORT_PROT :
-	case MCPDMUL_PORT_PROT :
-	default :
+	case SLIMBUS_PORT_PROT:
+	case SERIAL_PORT_PROT:
+	case DMIC_PORT_PROT:
+	case MCPDMDL_PORT_PROT:
+	case MCPDMUL_PORT_PROT:
+	default:
 		break;
 	}
-
 	/* upload the dma type */
-	abe_port [id].dma = dma;
+	abe_port[id].dma = dma;
 }
-
 /**
  * abe_disenable_dma_request
  * Parameter:
  * Operations:
  * Return value:
  */
-void abe_disable_enable_dma_request (u32 id, u32 on_off)
+void abe_disable_enable_dma_request(u32 id, u32 on_off)
 {
 	ABE_SIODescriptor desc;
 	ABE_SPingPongDescriptor desc_pp;
 	u8 desc_third_word[4], irq_dmareq_field;
 	u32 sio_desc_address;
 	u32 struct_offset;
-
 	if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) {
-		irq_dmareq_field = (u8)(on_off * abe_port[id].protocol.p.prot_pingpong.irq_data);
+		irq_dmareq_field =
+			(u8) (on_off *
+			      abe_port[id].protocol.p.prot_pingpong.irq_data);
 		sio_desc_address = D_PingPongDesc_ADDR;
-		struct_offset = (u32)&(desc_pp.data_size) - (u32)&(desc_pp);
-
-		abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-				sio_desc_address + struct_offset,
-				(u32 *)desc_third_word, 4);
-		desc_third_word [2] = irq_dmareq_field;
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				sio_desc_address + struct_offset,
-				(u32 *)desc_third_word, 4);
+		struct_offset = (u32) &(desc_pp.data_size) - (u32) &(desc_pp);
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+			       sio_desc_address + struct_offset,
+			       (u32 *) desc_third_word, 4);
+		desc_third_word[2] = irq_dmareq_field;
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       sio_desc_address + struct_offset,
+			       (u32 *) desc_third_word, 4);
 	} else {
-		sio_desc_address = dmem_port_descriptors + (
-					   id * sizeof(ABE_SIODescriptor));
-		abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-				sio_desc_address, (u32*)&desc,
-				sizeof (desc));
-
+		sio_desc_address =
+			dmem_port_descriptors +
+			(id * sizeof(ABE_SIODescriptor));
+		abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+			       sio_desc_address, (u32 *) &desc, sizeof(desc));
 		if (on_off) {
-			desc.atc_irq_data = (u8) abe_port[id].protocol.p.
-					    prot_dmareq.dma_data;
+			desc.atc_irq_data =
+				(u8) abe_port[id].protocol.p.prot_dmareq.
+				dma_data;
 			desc.on_off = 0x80;
 		} else {
 			desc.atc_irq_data = 0;
 			desc.on_off = 0;
 		}
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
-				(u32*)&desc, sizeof (desc));
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       sio_desc_address, (u32 *) &desc, sizeof(desc));
 	}
 }
-
-void abe_enable_dma_request (u32 id)
+void abe_enable_dma_request(u32 id)
 {
-	abe_disable_enable_dma_request (id, 1);
+	abe_disable_enable_dma_request(id, 1);
 }
-
 /**
  * abe_disable_dma_request
  *
@@ -575,41 +524,36 @@ void abe_enable_dma_request (u32 id)
  * Return value:
  *
  */
-void abe_disable_dma_request (u32 id)
+void abe_disable_dma_request(u32 id)
 {
-	abe_disable_enable_dma_request (id, 0);
+	abe_disable_enable_dma_request(id, 0);
 }
-
 /**
  * abe_enable_atc
  * Parameter:
  * Operations:
  * Return value:
  */
-void abe_enable_atc (u32 id)
+void abe_enable_atc(u32 id)
 {
 }
-
-
 /**
  * abe_disable_atc
  * Parameter:
  * Operations:
  * Return value:
  */
-void abe_disable_atc (u32 id)
+void abe_disable_atc(u32 id)
 {
 	abe_satcdescriptor_aess desc;
-
-	abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-			(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
-			(u32*)&desc, sizeof (desc));
+	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+		       (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+		       (u32 *) &desc, sizeof(desc));
 	desc.desen = 0;
-	abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-			(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
-			(u32*)&desc, sizeof (desc));
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+		       (abe_port[id]).protocol.p.prot_dmareq.desc_addr,
+		       (u32 *) &desc, sizeof(desc));
 }
-
 /**
  * abe_init_io_tasks
  * @prot : protocol being used
@@ -621,386 +565,344 @@ void abe_disable_atc (u32 id)
  * For Write to DMEM usually THR1/THR2 = 2/0
  * UP_1/2 =X+1/X-1
  */
-void abe_init_io_tasks (u32 id, abe_data_format_t *format, abe_port_protocol_t *prot)
+void abe_init_io_tasks(u32 id, abe_data_format_t *format,
+		       abe_port_protocol_t *prot)
 {
 	ABE_SIODescriptor desc;
 	ABE_SPingPongDescriptor desc_pp;
-	u32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id;
+	u32 x_io, direction, iter_samples, smem1, smem2, smem3, io_sub_id,
+		io_flag;
 	u32 copy_func_index, before_func_index, after_func_index;
 	u32 dmareq_addr, dmareq_field;
 	u32 sio_desc_address, datasize, iter, nsamp, datasize2, dOppMode32;
 	u32 atc_ptr_saved, atc_ptr_saved2, copy_func_index1;
 	u32 copy_func_index2, atc_desc_address1, atc_desc_address2;
-
 	if (prot->protocol_switch == PINGPONG_PORT_PROT) {
-
 		/* MM_DL managed in ping-pong */
 		if (MM_DL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR,
-					(u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR,
+				       (u32 *) MultiFrame, sizeof(MultiFrame));
 			MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
 				ABE_TASK_ID(C_ABE_FW_TASK_IO_PING_PONG);
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 		} else {
 			abe_dbg_param |= ERR_API;
-			abe_dbg_error_log (ABE_PARAMETER_ERROR);
+			abe_dbg_error_log(ABE_PARAMETER_ERROR);
 		}
-
-		/* set the SMEM buffer -- programming sequence */
-		abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-				D_maxTaskBytesInSlot_ADDR,
-				&dOppMode32, sizeof (u32));
-		if (dOppMode32 == DOPPMODE32_OPP100)
-			/* ASRC input buffer, size 40 */
-			smem1 = smem_mm_dl_opp100;
-		else
-			/* at OPP 25/50 or without ASRC */
-			smem1 = smem_mm_dl_opp25;
-
-		copy_func_index = (u8) abe_dma_port_copy_subroutine_id (id);
+		smem1 = smem_mm_dl;
+		copy_func_index = (u8) abe_dma_port_copy_subroutine_id(id);
 		dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr;
 		dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data;
-		datasize = abe_dma_port_iter_factor (format);
-
+		datasize = abe_dma_port_iter_factor(format);
 		/* number of "samples" either mono or stereo */
-		iter = abe_dma_port_iteration (format);
+		iter = abe_dma_port_iteration(format);
 		iter_samples = (iter / datasize);
-
 		/* load the IO descriptor */
-
 		/* no drift */
 		desc_pp.drift_ASRC = 0;
-
 		/* no drift */
 		desc_pp.drift_io = 0;
 		desc_pp.hw_ctrl_addr = (u16) dmareq_addr;
 		desc_pp.copy_func_index = (u8) copy_func_index;
 		desc_pp.smem_addr = (u8) smem1;
-
 		/* DMA req 0 is used for CBPr0 */
 		desc_pp.atc_irq_data = (u8) dmareq_field;
-
 		/* size of block transfer */
 		desc_pp.x_io = (u8) iter_samples;
 		desc_pp.data_size = (u8) datasize;
-
 		/* address comunicated in Bytes */
-		desc_pp.workbuff_BaseAddr = (u16) (abe_base_address_pingpong [1]);
-
+		desc_pp.workbuff_BaseAddr =
+			(u16) (abe_base_address_pingpong[1]);
 		/* size comunicated in XIO sample */
 		desc_pp.workbuff_Samples = (u16) iter_samples;
-
-		desc_pp.nextbuff0_BaseAddr = (u16) (abe_base_address_pingpong [0]);
-		desc_pp.nextbuff0_Samples = (u16) ((abe_size_pingpong >> 2)/datasize);
-		desc_pp.nextbuff1_BaseAddr = (u16) (abe_base_address_pingpong [1]);
-		desc_pp.nextbuff1_Samples = (u16) ((abe_size_pingpong >> 2)/datasize);
-
+		desc_pp.nextbuff0_BaseAddr =
+			(u16) (abe_base_address_pingpong[0]);
+		desc_pp.nextbuff0_Samples =
+			(u16) ((abe_size_pingpong >> 2) / datasize);
+		desc_pp.nextbuff1_BaseAddr =
+			(u16) (abe_base_address_pingpong[1]);
+		desc_pp.nextbuff1_Samples =
+			(u16) ((abe_size_pingpong >> 2) / datasize);
 		/* next buffer to send is B1, first IRQ fills B0 */
 		desc_pp.counter = 1;
-
 		/* send a DMA req to fill B0 with N samples
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW,
-		&(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */
-
+		   abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_ATC, ABE_DMASTATUS_RAW,
+		   &(abe_port[id].protocol.p.prot_pingpong.irq_data), 4); */
 		sio_desc_address = D_PingPongDesc_ADDR;
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM, sio_desc_address,
-				(u32*)&desc_pp, sizeof (desc_pp));
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       sio_desc_address, (u32 *) &desc_pp,
+			       sizeof(desc_pp));
 	} else {
 		io_sub_id = dmareq_addr = ABE_DMASTATUS_RAW;
 		dmareq_field = 0;
 		atc_desc_address1 = atc_desc_address2 = 0;
-
-		datasize2=datasize = abe_dma_port_iter_factor (format);
-		x_io = (u8) abe_dma_port_iteration (format);
+		/* default: repeat of the last downlink samples in case of
+		   DMA errors, (disable=0x00) */
+		io_flag = 0xFF;
+		datasize2 = datasize = abe_dma_port_iter_factor(format);
+		x_io = (u8) abe_dma_port_iteration(format);
 		nsamp = (x_io / datasize);
-
-		atc_ptr_saved2=atc_ptr_saved = DMIC_ATC_PTR_labelID + id;
-
+		atc_ptr_saved2 = atc_ptr_saved = DMIC_ATC_PTR_labelID + id;
 		smem1 = abe_port[id].smem_buffer1;
 		smem3 = smem2 = abe_port[id].smem_buffer2;
-
-		copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id (id);
+		copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(id);
 		before_func_index = after_func_index =
-					    copy_func_index2 = NULL_COPY_CFPID;
-
-		/* MM_DL managed in non-ping-pong mode */
-		if (MM_DL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR,
-					(u32*)MultiFrame,
-					sizeof (MultiFrame));
-			MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
-				D_tasksList_ADDR +
-				sizeof(ABE_STask)*C_ABE_FW_TASK_IO_MM_DL;
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR,
-					(u32*)MultiFrame, sizeof (MultiFrame));
-		}
-
+			copy_func_index2 = NULL_COPY_CFPID;
 		switch (prot->protocol_switch) {
-		case DMIC_PORT_PROT :
+		case DMIC_PORT_PROT:
 			/* DMIC port is read in two steps */
 			x_io = x_io >> 1;
 			nsamp = nsamp >> 1;
-			atc_desc_address1 = ABE_ATC_DMIC_DMA_REQ*ATC_SIZE;
+			atc_desc_address1 = (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE);
 			io_sub_id = IO_IP_CFPID;
 			break;
-		case MCPDMDL_PORT_PROT :
+		case MCPDMDL_PORT_PROT:
 			/* PDMDL port is written to in two steps */
 			x_io = x_io >> 1;
-			atc_desc_address1 = ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE;
+			atc_desc_address1 =
+				(ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE);
 			io_sub_id = IO_IP_CFPID;
 			break;
-		case MCPDMUL_PORT_PROT :
-			atc_desc_address1 = ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE;
+		case MCPDMUL_PORT_PROT:
+			atc_desc_address1 =
+				(ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE);
 			io_sub_id = IO_IP_CFPID;
 			break;
-		case SLIMBUS_PORT_PROT :
-			atc_desc_address1 = abe_port[id].protocol.p.
-					    prot_slimbus.desc_addr1;
-			atc_desc_address2 = abe_port[id].protocol.p.
-					    prot_slimbus.desc_addr2;
+		case SLIMBUS_PORT_PROT:
+			atc_desc_address1 =
+				abe_port[id].protocol.p.prot_slimbus.desc_addr1;
+			atc_desc_address2 =
+				abe_port[id].protocol.p.prot_slimbus.desc_addr2;
 			copy_func_index2 = NULL_COPY_CFPID;
 			/* @@@@@@
-			 #define SPLIT_SMEM_CFPID 9
-			 #define MERGE_SMEM_CFPID 10
-			 #define SPLIT_TDM_12_CFPID 11
-			 #define MERGE_TDM_12_CFPID 12
-			*/
+			   #define SPLIT_SMEM_CFPID 9
+			   #define MERGE_SMEM_CFPID 10
+			   #define SPLIT_TDM_12_CFPID 11
+			   #define MERGE_TDM_12_CFPID 12
+			 */
 			io_sub_id = IO_IP_CFPID;
 			break;
-		case SERIAL_PORT_PROT : /* McBSP/McASP */
-			atc_desc_address1 = (s16) abe_port[id].protocol.p.
-					    prot_serial.desc_addr;
+		case SERIAL_PORT_PROT:	/* McBSP/McASP */
+			atc_desc_address1 =
+				(s16) abe_port[id].protocol.p.prot_serial.
+				desc_addr;
 			io_sub_id = IO_IP_CFPID;
 			break;
-		case DMAREQ_PORT_PROT : /* DMA w/wo CBPr */
-			dmareq_addr = abe_port[id].protocol.p.
-				      prot_dmareq.dma_addr;
+		case DMAREQ_PORT_PROT:	/* DMA w/wo CBPr */
+			dmareq_addr =
+				abe_port[id].protocol.p.prot_dmareq.dma_addr;
 			dmareq_field = 0;
-			atc_desc_address1 = abe_port[id].protocol.p.
-					    prot_dmareq.desc_addr;
+			atc_desc_address1 =
+				abe_port[id].protocol.p.prot_dmareq.desc_addr;
 			io_sub_id = IO_IP_CFPID;
 			break;
 		}
-
 		/* special situation of the PING_PONG protocol which has its own SIO descriptor format */
 		/*
-		 Sequence of operations on ping-pong buffers B0/B1
-
-		 ----------------------------------------------------------------- time --------------------------------------------->>>>
-		 Host Application is ready to send data from DDR to B0
-		 SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0
-
-		 FIRMWARE starts with #12 B1 data, sends IRQ/DMAreq sens #pong B1 data sends IRQ/DMAreq sends #ping B0 v sends B1 samples
-		 ARM / SDMA | fills B0 | fills B1 ... | fills B0 ...
-		 Counter 0 1 2 3
+		   Sequence of operations on ping-pong buffers B0/B1
+		   ----------------------------------------------------------------- time --------------------------------------------->>>>
+		   Host Application is ready to send data from DDR to B0
+		   SDMA is initialized from "abe_connect_irq_ping_pong_port" to B0
+		   FIRMWARE starts with #12 B1 data, sends IRQ/DMAreq sens #pong B1 data sends IRQ/DMAreq sends #ping B0 v sends B1 samples
+		   ARM / SDMA | fills B0 | fills B1 ... | fills B0 ...
+		   Counter 0 1 2 3
 		 */
-
 		if (MM_UL_PORT == id) {
 			copy_func_index1 = COPY_MM_UL_CFPID;
 			before_func_index = ROUTE_MM_UL_CFPID;
 		}
-
 		/* check for 8kHz/16kHz */
 		if (VX_DL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 			if (abe_port[id].format.f == 8000) {
-				MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX] =
+				MultiFrame[TASK_ASRC_VX_DL_SLT]
+					[TASK_ASRC_VX_DL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_8);
 				MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_8_48);
-
-				/*Voice_8k_DL_labelID*/
+				/*Voice_8k_DL_labelID */
 				smem1 = IO_VX_DL_ASRC_labelID;
 			} else {
-				MultiFrame[TASK_ASRC_VX_DL_SLT][TASK_ASRC_VX_DL_IDX] =
-					ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_DL_16);
+				MultiFrame[TASK_ASRC_VX_DL_SLT]
+					[TASK_ASRC_VX_DL_IDX] =
+					ABE_TASK_ID
+					(C_ABE_FW_TASK_ASRC_VX_DL_16);
 				MultiFrame[TASK_VX_DL_SLT][TASK_VX_DL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_VX_DL_16_48);
-
 				/* Voice_16k_DL_labelID */
 				smem1 = IO_VX_DL_ASRC_labelID;
 			}
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 		}
 		/* check for 8kHz/16kHz */
 		if (VX_UL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 			if (abe_port[id].format.f == 8000) {
-				MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] =
+				MultiFrame[TASK_ASRC_VX_UL_SLT]
+					[TASK_ASRC_VX_UL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_8);
 				MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_8);
 				/* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] =
-					ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_8); */
+				   ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_8); */
 				smem1 = Voice_8k_UL_labelID;
 			} else {
-				MultiFrame[TASK_ASRC_VX_UL_SLT][TASK_ASRC_VX_UL_IDX] =
-					ABE_TASK_ID(C_ABE_FW_TASK_ASRC_VX_UL_16);
+				MultiFrame[TASK_ASRC_VX_UL_SLT]
+					[TASK_ASRC_VX_UL_IDX] =
+					ABE_TASK_ID
+					(C_ABE_FW_TASK_ASRC_VX_UL_16);
 				MultiFrame[TASK_VX_UL_SLT][TASK_VX_UL_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_VX_UL_48_16);
 				/* MultiFrame[TASK_ECHO_SLT][TASK_ECHO_IDX] =
-					ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_16); */
+				   ABE_TASK_ID(C_ABE_FW_TASK_ECHO_REF_48_16); */
 				smem1 = Voice_16k_UL_labelID;
 			}
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 		}
-
 		/* check for 8kHz/16kHz */
 		if (BT_VX_DL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR,
-					(u32*)MultiFrame, sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR,
+				       (u32 *) MultiFrame, sizeof(MultiFrame));
 			if (abe_port[id].format.f == 8000) {
-				MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] =
+				MultiFrame[TASK_BT_DL_48_8_SLT]
+					[TASK_BT_DL_48_8_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_8);
 				smem1 = BT_DL_8k_labelID;
 			} else {
-				MultiFrame[TASK_BT_DL_48_8_SLT][TASK_BT_DL_48_8_IDX] =
+				MultiFrame[TASK_BT_DL_48_8_SLT]
+					[TASK_BT_DL_48_8_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_BT_DL_48_16);
 				smem1 = BT_DL_16k_labelID;
 			}
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 		}
-
 		/* check for 8kHz/16kHz */
 		if (BT_VX_UL_PORT == id) {
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR,
-					(u32*)MultiFrame, sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR,
+				       (u32 *) MultiFrame, sizeof(MultiFrame));
 			if (abe_port[id].format.f == 8000) {
-				MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] =
+				MultiFrame[TASK_BT_UL_8_48_SLT]
+					[TASK_BT_UL_8_48_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_8_48);
 				smem1 = BT_UL_8k_labelID;
 			} else {
-				MultiFrame[TASK_BT_UL_8_48_SLT][TASK_BT_UL_8_48_IDX] =
+				MultiFrame[TASK_BT_UL_8_48_SLT]
+					[TASK_BT_UL_8_48_IDX] =
 					ABE_TASK_ID(C_ABE_FW_TASK_BT_UL_16_48);
 				smem1 = BT_UL_16k_labelID;
 			}
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 		}
-
 		if (MM_DL_PORT == id) {
 			/* check for CBPr / serial_port / Ping-pong access */
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
 			MultiFrame[TASK_IO_MM_DL_SLT][TASK_IO_MM_DL_IDX] =
 				ABE_TASK_ID(C_ABE_FW_TASK_IO_MM_DL);
-			abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-					D_multiFrame_ADDR, (u32*)MultiFrame,
-					sizeof (MultiFrame));
-
+			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+				       D_multiFrame_ADDR, (u32 *) MultiFrame,
+				       sizeof(MultiFrame));
+			smem1 = smem_mm_dl;
+		}
+		if (MM_EXT_IN_PORT == id) {
 			/* set the SMEM buffer -- programming sequence */
-			abe_block_copy (COPY_FROM_ABE_TO_HOST, ABE_DMEM,
-					D_maxTaskBytesInSlot_ADDR, &dOppMode32,
-					sizeof (u32));
-
+			abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM,
+				       D_maxTaskBytesInSlot_ADDR, &dOppMode32,
+				       sizeof(u32));
 			if (dOppMode32 == DOPPMODE32_OPP100)
 				/* ASRC input buffer, size 40 */
-				smem1 = smem_mm_dl_opp100;
+				smem1 = smem_mm_ext_in_opp100;
 			else
-				/* at OPP 25/50 or without ASRC */
-				smem1 = smem_mm_dl_opp25;
+				/* at OPP 50 without ASRC */
+				smem1 = smem_mm_ext_in_opp50;
 		}
-
 		if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
 			direction = 0;
 		else
 			/* offset of the write pointer in the ATC descriptor */
 			direction = 3;
-
 		desc.drift_ASRC = 0;
 		desc.drift_io = 0;
 		desc.io_type_idx = (u8) io_sub_id;
 		desc.samp_size = (u8) datasize;
-
 		desc.hw_ctrl_addr = (u16) (dmareq_addr << 2);
 		desc.atc_irq_data = (u8) dmareq_field;
 		desc.flow_counter = (u16) 0;
-
 		desc.direction_rw = (u8) direction;
+		desc.repeat_last_samp = (u8) io_flag;
 		desc.nsamp = (u8) nsamp;
 		desc.x_io = (u8) x_io;
-		desc.on_off = 0x80; /* set ATC ON */
-
+		/* set ATC ON */
+		desc.on_off = 0x80;
 		desc.split_addr1 = (u16) smem1;
 		desc.split_addr2 = (u16) smem2;
 		desc.split_addr3 = (u16) smem3;
 		desc.before_f_index = (u8) before_func_index;
 		desc.after_f_index = (u8) after_func_index;
-
 		desc.smem_addr1 = (u16) smem1;
 		desc.atc_address1 = (u16) atc_desc_address1;
 		desc.atc_pointer_saved1 = (u16) atc_ptr_saved;
 		desc.data_size1 = (u8) datasize;
 		desc.copy_f_index1 = (u8) copy_func_index1;
-
 		desc.smem_addr2 = (u16) smem2;
 		desc.atc_address2 = (u16) atc_desc_address2;
 		desc.atc_pointer_saved2 = (u16) atc_ptr_saved2;
 		desc.data_size2 = (u8) datasize2;
 		desc.copy_f_index2 = (u8) copy_func_index2;
-
 		sio_desc_address = dmem_port_descriptors + (id *
-				   sizeof(ABE_SIODescriptor));
-		abe_block_copy (COPY_FROM_HOST_TO_ABE, ABE_DMEM,
-				sio_desc_address,
-				(u32*)&desc, sizeof (desc));
+							    sizeof
+							    (ABE_SIODescriptor));
+		abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
+			       sio_desc_address, (u32 *) &desc, sizeof(desc));
 	}
 }
-
 /**
  * abe_init_dmic
  * @x: d
  *
  *
  */
-void abe_init_dmic (u32 x)
+void abe_init_dmic(u32 x)
 {
-
 }
-
 /**
  * abe_init_mcpdm
  * @x: d
  *
  */
-void abe_init_mcpdm (u32 x)
+void abe_init_mcpdm(u32 x)
 {
-
 }
-
 /**
  * abe_reset_feature
  * @x: index of the feature to be initialized
  *
  * reload the configuration
  */
-void abe_reset_one_feature (u32 x)
+void abe_reset_one_feature(u32 x)
 {
-	all_feature [x] = all_feature_init [x]; /* load default fields */
+	all_feature[x] = all_feature_init[x];	/* load default fields */
 	/* abe_call_subroutine ((all_feature[x]).disable_feature, NOPARAMETER,
-	NOPARAMETER, NOPARAMETER, NOPARAMETER); */
+	   NOPARAMETER, NOPARAMETER, NOPARAMETER); */
 }
-
 /**
  * abe_reset_all_feature
  *
@@ -1018,228 +920,277 @@ void abe_reset_one_feature (u32 x)
  *		char name[NBCHARFEATURENAME];
  * } abe_feature_t;
  */
-void abe_reset_all_features (void)
+void abe_reset_all_features(void)
 {
 	u16 i;
-
 	for (i = 0; i < MAXNBFEATURE; i++)
-		abe_reset_one_feature (i);
+		abe_reset_one_feature(i);
 }
-
 /**
  * abe_reset_all_ports
  *
  * load default configuration for all features
  */
-void abe_reset_all_ports (void)
+void abe_reset_all_ports(void)
 {
 	u16 i;
-
 	for (i = 0; i < LAST_PORT_ID; i++)
-		abe_reset_port (i);
-
+		abe_reset_port(i);
 	/* mixers' configuration */
-	abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL);
-	abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2);
-	abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL);
-	abe_write_mixer (MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES);
-
-	abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES);
-	abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL);
-	abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL);
-	abe_write_mixer (MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2);
-
-	abe_write_mixer (MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER);
-	abe_write_mixer (MIXSDT, GAIN_0dB , RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER);
-
-	abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_mixer (MIXECHO, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-
-	abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL);
-	abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES);
-	abe_write_mixer (MIXAUDUL, GAIN_0dB , RAMP_100MS, MIX_AUDUL_INPUT_UPLINK);
-	abe_write_mixer (MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL);
-
-	abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES);
-	abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL);
-	abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL);
-	abe_write_mixer (MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL);
-
-	abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain(GAINS_DMIC1,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-	abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain(GAINS_DMIC2,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-	abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain(GAINS_DMIC3,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-	abe_write_gain(GAINS_AMIC ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain(GAINS_AMIC, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-
-	abe_write_gain(GAINS_SPLIT ,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain(GAINS_SPLIT, GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-
-	/*@@@Gain set to -6dB due to McPDM Limitation*/
-	/* cf CDDS 00635*/
-	abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain (GAINS_DL1,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
-	abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_100MS, GAIN_LEFT_OFFSET);
-	abe_write_gain (GAINS_DL2,GAIN_0dB , RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_MM_UL2);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_VX_DL);
+	abe_write_mixer(MIXDL1, MUTE_GAIN, RAMP_100MS, MIX_DL1_INPUT_TONES);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_TONES);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_VX_DL);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_DL);
+	abe_write_mixer(MIXDL2, MUTE_GAIN, RAMP_100MS, MIX_DL2_INPUT_MM_UL2);
+	abe_write_mixer(MIXSDT, MUTE_GAIN, RAMP_100MS, MIX_SDT_INPUT_UP_MIXER);
+	abe_write_mixer(MIXSDT, GAIN_0dB, RAMP_100MS, MIX_SDT_INPUT_DL1_MIXER);
+	abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_mixer(MIXECHO, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_MM_DL);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_TONES);
+	abe_write_mixer(MIXAUDUL, GAIN_0dB, RAMP_100MS, MIX_AUDUL_INPUT_UPLINK);
+	abe_write_mixer(MIXAUDUL, MUTE_GAIN, RAMP_100MS, MIX_AUDUL_INPUT_VX_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_TONES);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_MM_DL);
+	abe_write_mixer(MIXVXREC, MUTE_GAIN, RAMP_100MS, MIX_VXREC_INPUT_VX_UL);
+	abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC1, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC2, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DMIC3, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_AMIC, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_SPLIT, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DL1, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
+	abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_LEFT_OFFSET);
+	abe_write_gain(GAINS_DL2, GAIN_0dB, RAMP_100MS, GAIN_RIGHT_OFFSET);
 }
-
 /**
  * abe_clean_temporay buffers
  *
  * clear temporary buffers
  */
-void abe_clean_temporary_buffers (u32 id)
+void abe_clean_temporary_buffers(u32 id)
 {
 	switch (id) {
-	case	DMIC_PORT:
-		abe_reset_mem (ABE_DMEM, D_DMIC_UL_FIFO_ADDR,
-			       D_DMIC_UL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3,
-			       S_DMIC0_96_48_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3,
-			       S_DMIC1_96_48_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3,
-			       S_DMIC1_96_48_data_sizeof << 3);
-		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+dmic1_gains_offset) << 2,
-			      6 << 2); /* reset current gains */
-		abe_reset_mem (ABE_SMEM, (S_GCurrent_ADDR+dmic1_gains_offset) << 3,
-			       6 << 3);
+	case DMIC_PORT:
+		abe_reset_mem(ABE_DMEM, D_DMIC_UL_FIFO_ADDR,
+			      D_DMIC_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_DMIC0_96_48_data_ADDR << 3,
+			      S_DMIC0_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DMIC1_96_48_data_ADDR << 3,
+			      S_DMIC1_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3,
+			      S_DMIC1_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR + dmic1_gains_offset) << 2, 6 << 2);	/* reset current gains */
+		abe_reset_mem(ABE_SMEM,
+			      (S_GCurrent_ADDR + dmic1_gains_offset) << 3,
+			      6 << 3);
+		abe_reset_gain_mixer(GAINS_DMIC1, 0);
+		abe_reset_gain_mixer(GAINS_DMIC2, 0);
+		abe_reset_gain_mixer(GAINS_DMIC3, 0);
+		break;
+	case PDM_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_McPDM_UL_FIFO_ADDR,
+			      D_McPDM_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_AMIC_96_48_data_ADDR << 3,
+			      S_AMIC_96_48_data_sizeof << 3);
+		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR + amic_gains_offset) << 2, 2 << 2);	/* reset current gains */
+		abe_reset_mem(ABE_SMEM,
+			      (S_GCurrent_ADDR + amic_gains_offset) << 3,
+			      6 << 3);
+		abe_reset_gain_mixer(GAINS_AMIC, 0);
+		break;
+	case BT_VX_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_BT_UL_FIFO_ADDR, D_BT_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_ADDR << 3, S_BT_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_HP_data_ADDR << 3,
+			      S_BT_UL_8_48_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_8_48_LP_data_ADDR << 3,
+			      S_BT_UL_8_48_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_HP_data_ADDR << 3,
+			      S_BT_UL_16_48_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_UL_16_48_LP_data_ADDR << 3,
+			      S_BT_UL_16_48_LP_data_sizeof << 3);
+		break;
+	case MM_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_UL_FIFO_ADDR, D_MM_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_UL_ADDR << 3, S_MM_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3,
+			      D_MM_UL2_FIFO_sizeof << 3);
+		break;
+	case MM_UL2_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_UL2_FIFO_ADDR,
+			      D_MM_UL2_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_UL2_ADDR << 3,
+			      S_MM_UL2_sizeof << 3);
+		break;
+	case VX_UL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VX_UL_FIFO_ADDR, D_VX_UL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_ADDR << 3, S_VX_UL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_HP_data_ADDR << 3,
+			      S_VX_UL_48_8_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3,
+			      S_VX_UL_48_8_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3,
+			      S_VX_UL_48_16_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3,
+			      S_VX_UL_48_16_LP_data_sizeof << 3);
+		abe_reset_gain_mixer(MIXAUDUL, MIX_AUDUL_INPUT_UPLINK);
+		break;
+	case MM_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_DL_FIFO_ADDR, D_MM_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_MM_DL_ADDR << 3, S_MM_DL_sizeof << 3);
+		abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_MM_DL);
+		abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_MM_DL);
+		break;
+	case VX_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VX_DL_FIFO_ADDR, D_VX_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_ADDR << 3, S_VX_DL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_HP_data_ADDR << 3,
+			      S_VX_DL_8_48_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3,
+			      S_VX_DL_8_48_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3,
+			      S_VX_DL_16_48_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3,
+			      S_VX_DL_16_48_LP_data_sizeof << 3);
+		abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_VX_DL);
+		abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_VX_DL);
 		break;
-	case	PDM_UL_PORT:
-		abe_reset_mem (ABE_DMEM, D_McPDM_UL_FIFO_ADDR,
-			       D_McPDM_UL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3,
-			       S_BT_UL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_AMIC_96_48_data_ADDR << 3,
-			       S_AMIC_96_48_data_sizeof << 3);
-		abe_reset_mem(ABE_CMEM, (C_GainsWRamp_ADDR+amic_gains_offset) << 2,
-			      2 << 2); /* reset current gains */
-		abe_reset_mem (ABE_SMEM, (S_GCurrent_ADDR+amic_gains_offset) << 3,
-			       6 << 3);
+	case TONES_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_TONES_DL_FIFO_ADDR,
+			      D_TONES_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_Tones_ADDR << 3, S_Tones_sizeof << 3);
+		abe_reset_gain_mixer(MIXDL1, MIX_DL1_INPUT_TONES);
+		abe_reset_gain_mixer(MIXDL2, MIX_DL2_INPUT_TONES);
+		break;
+	case VIB_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_VIB_DL_FIFO_ADDR,
+			      D_VIB_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_VIBRA_ADDR << 3, S_VIBRA_sizeof << 3);
+		break;
+	case BT_VX_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_BT_DL_FIFO_ADDR, D_BT_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_ADDR << 3, S_BT_DL_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_HP_data_ADDR << 3,
+			      S_BT_DL_48_8_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_48_8_LP_data_ADDR << 3,
+			      S_BT_DL_48_8_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_HP_data_ADDR << 3,
+			      S_BT_DL_48_16_HP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_BT_DL_48_16_LP_data_ADDR << 3,
+			      S_BT_DL_48_16_LP_data_sizeof << 3);
+		break;
+	case PDM_DL_PORT:
+		abe_reset_mem(ABE_DMEM, D_McPDM_DL_FIFO_ADDR,
+			      D_McPDM_DL_FIFO_sizeof);
+		abe_reset_mem(ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3,
+			      S_DL2_M_LR_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3,
+			      S_DL1_M_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3,
+			      S_EARP_48_96_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3,
+			      S_IHF_48_96_LP_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3,
+			      S_APS_DL1_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3,
+			      S_APS_DL2_EQ_data_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL2_L_IIRmem1_ADDR << 3,
+			      S_APS_DL2_L_IIRmem1_sizeof << 3);
+		abe_reset_mem(ABE_SMEM, S_APS_DL2_R_IIRmem1_ADDR << 3,
+			      S_APS_DL2_R_IIRmem1_sizeof << 3);
+		abe_reset_gain_mixer(GAINS_DL1, GAIN_LEFT_OFFSET);
+		abe_reset_gain_mixer(GAINS_DL1, GAIN_RIGHT_OFFSET);
+		abe_reset_gain_mixer(GAINS_DL2, GAIN_LEFT_OFFSET);
+		abe_reset_gain_mixer(GAINS_DL2, GAIN_RIGHT_OFFSET);
+		abe_reset_gain_mixer(MIXSDT, MIX_SDT_INPUT_UP_MIXER);
+		abe_reset_gain_mixer(MIXSDT, MIX_SDT_INPUT_DL1_MIXER);
+		break;
+	case MM_EXT_OUT_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR,
+			      D_MM_EXT_OUT_FIFO_sizeof);
+		break;
+	case MM_EXT_IN_PORT:
+		abe_reset_mem(ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR,
+			      D_MM_EXT_IN_FIFO_sizeof);
+		break;
+	}
+}
+/**
+ * abe_clear_current_gain_mixer
+ * @id: name of the mixer
+ * @param: list of input gains of the mixer
+ * @p: list of port corresponding to the above gains
+ *
+ * restart the working gain value of the mixers when a port is enabled
+ */
+void abe_reset_gain_mixer(u32 id, u32 p)
+{
+	u32 lin_g, mixer_target, mixer_offset;
+	switch (id) {
+	default:
+	case GAINS_DMIC1:
+		mixer_offset = dmic1_gains_offset;
 		break;
-	case	BT_VX_UL_PORT:
-		abe_reset_mem (ABE_DMEM, D_BT_UL_FIFO_ADDR,
-			       D_BT_UL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3,
-			       S_BT_UL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_ADDR << 3,
-			       S_BT_UL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_8_48_HP_data_ADDR << 3,
-			       S_BT_UL_8_48_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_8_48_LP_data_ADDR << 3,
-			       S_BT_UL_8_48_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_16_48_HP_data_ADDR << 3,
-			       S_BT_UL_16_48_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_UL_16_48_LP_data_ADDR << 3,
-			       S_BT_UL_16_48_LP_data_sizeof << 3);
+	case GAINS_DMIC2:
+		mixer_offset = dmic2_gains_offset;
 		break;
-	case	MM_UL_PORT:
-		abe_reset_mem (ABE_DMEM, D_MM_UL_FIFO_ADDR,
-			       D_MM_UL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_MM_UL_ADDR << 3,
-			       S_MM_UL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_MM_UL2_ADDR << 3,
-			       D_MM_UL2_FIFO_sizeof << 3);
+	case GAINS_DMIC3:
+		mixer_offset = dmic3_gains_offset;
 		break;
-	case	MM_UL2_PORT:
-		abe_reset_mem (ABE_DMEM, D_MM_UL2_FIFO_ADDR,
-			       D_MM_UL2_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_MM_UL2_ADDR << 3,
-			       S_MM_UL2_sizeof << 3);
+	case GAINS_AMIC:
+		mixer_offset = amic_gains_offset;
 		break;
-	case	VX_UL_PORT:
-		abe_reset_mem (ABE_DMEM, D_VX_UL_FIFO_ADDR,
-			       D_VX_UL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_VX_UL_ADDR << 3,
-			       S_VX_UL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_UL_48_8_HP_data_ADDR << 3,
-			       S_VX_UL_48_8_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_UL_48_8_LP_data_ADDR << 3,
-			       S_VX_UL_48_8_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_UL_48_16_HP_data_ADDR << 3,
-			       S_VX_UL_48_16_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_UL_48_16_LP_data_ADDR << 3,
-			       S_VX_UL_48_16_LP_data_sizeof << 3);
+	case GAINS_DL1:
+		mixer_offset = dl1_gains_offset;
 		break;
-	case	MM_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_MM_DL_FIFO_ADDR,
-			       D_MM_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_MM_DL_ADDR << 3,
-			       S_MM_DL_sizeof << 3);
+	case GAINS_DL2:
+		mixer_offset = dl2_gains_offset;
 		break;
-	case	VX_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_VX_DL_FIFO_ADDR,
-			       D_VX_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_VX_DL_ADDR << 3,
-			       S_VX_DL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_DL_8_48_HP_data_ADDR << 3,
-			       S_VX_DL_8_48_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_DL_8_48_LP_data_ADDR << 3,
-			       S_VX_DL_8_48_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_DL_16_48_HP_data_ADDR << 3,
-			       S_VX_DL_16_48_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_VX_DL_16_48_LP_data_ADDR << 3,
-			       S_VX_DL_16_48_LP_data_sizeof << 3);
+	case GAINS_SPLIT:
+		mixer_offset = splitters_gains_offset;
 		break;
-	case	TONES_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_TONES_DL_FIFO_ADDR,
-			       D_TONES_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_Tones_ADDR << 3,
-			       S_Tones_sizeof << 3);
+	case MIXDL1:
+		mixer_offset = mixer_dl1_offset;
 		break;
-	case	VIB_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_VIB_DL_FIFO_ADDR,
-			       D_VIB_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_VIBRA_ADDR << 3,
-			       S_VIBRA_sizeof << 3);
+	case MIXDL2:
+		mixer_offset = mixer_dl2_offset;
 		break;
-	case	BT_VX_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_BT_DL_FIFO_ADDR,
-			       D_BT_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_BT_DL_ADDR << 3,
-			       S_BT_DL_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_DL_48_8_HP_data_ADDR << 3,
-			       S_BT_DL_48_8_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_DL_48_8_LP_data_ADDR << 3,
-			       S_BT_DL_48_8_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_DL_48_16_HP_data_ADDR << 3,
-			       S_BT_DL_48_16_HP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_BT_DL_48_16_LP_data_ADDR << 3,
-			       S_BT_DL_48_16_LP_data_sizeof << 3);
-
+	case MIXECHO:
+		mixer_offset = mixer_echo_offset;
 		break;
-	case	PDM_DL_PORT:
-		abe_reset_mem (ABE_DMEM, D_McPDM_DL_FIFO_ADDR,
-			       D_McPDM_DL_FIFO_sizeof);
-		abe_reset_mem (ABE_SMEM, S_DMIC2_96_48_data_ADDR << 3,
-			       S_DMIC1_96_48_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_DL2_M_LR_EQ_data_ADDR << 3,
-			       S_DL2_M_LR_EQ_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_DL1_M_EQ_data_ADDR << 3,
-			       S_DL1_M_EQ_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_EARP_48_96_LP_data_ADDR << 3,
-			       S_EARP_48_96_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_IHF_48_96_LP_data_ADDR << 3,
-			       S_IHF_48_96_LP_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_APS_DL1_EQ_data_ADDR << 3,
-			       S_APS_DL1_EQ_data_sizeof << 3);
-		abe_reset_mem (ABE_SMEM, S_APS_DL2_EQ_data_ADDR << 3,
-			       S_APS_DL2_EQ_data_sizeof << 3);
+	case MIXSDT:
+		mixer_offset = mixer_sdt_offset;
 		break;
-	case	MM_EXT_OUT_PORT:
-		abe_reset_mem (ABE_DMEM, D_MM_EXT_OUT_FIFO_ADDR,
-			       D_MM_EXT_OUT_FIFO_sizeof);
+	case MIXVXREC:
+		mixer_offset = mixer_vxrec_offset;
 		break;
-	case	MM_EXT_IN_PORT:
-		abe_reset_mem (ABE_DMEM, D_MM_EXT_IN_FIFO_ADDR,
-			       D_MM_EXT_IN_FIFO_sizeof);
+	case MIXAUDUL:
+		mixer_offset = mixer_audul_offset;
 		break;
 	}
-
+	/* SMEM word32 address for the CURRENT gain values */
+	mixer_target = (S_GCurrent_ADDR << 1);
+	mixer_target += mixer_offset;
+	mixer_target += p;
+	/* translate coef address in Bytes */
+	mixer_target <<= 2;
+	lin_g = 0;
+	/* load the S_G_Target SMEM table */
+	abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_SMEM, mixer_target,
+		       (u32 *) &lin_g, sizeof(lin_g));
 }
-
 /**
  * abe_init_asrc_vx_dl
  *
@@ -1264,205 +1215,161 @@ void abe_clean_temporary_buffers (u32 id)
  * 14. CMEM for IO_VX_DL_ASRC pointer
  * IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0
  */
-void abe_init_asrc_vx_dl ( s32 dppm)
+void abe_init_asrc_vx_dl(s32 dppm)
 {
 	s32 el[45];
 	s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
 	u32 i = 0;
-
 	temp0 = 0;
 	temp1 = 1;
-
 	/* 1. DriftSign = D_AsrcVars[1] = 1 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_VX_ADDR + 1*sizeof(s32);
+	mem_addr = D_AsrcVars_DL_VX_ADDR + (1 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm >= 0) {
-		el[i+1] = 1;
+		el[i + 1] = 1;
 		adppm = dppm;
 	} else {
-		el[i+1] = -1;
-		adppm = (-1*dppm);
+		el[i + 1] = -1;
+		adppm = (-1 * dppm);
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-	dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L);
-
+	dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
 	/* 2. Subblock = D_AsrcVars[2] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_VX_ADDR + 2*sizeof(s32);
+	mem_addr = D_AsrcVars_DL_VX_ADDR + (2 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_VX_ADDR + 3*sizeof(s32);
+	mem_addr = D_AsrcVars_DL_VX_ADDR + (3 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = dtemp<<2;
+		el[i + 1] = dtemp << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_VX_ADDR + 4*sizeof(s32);
+	mem_addr = D_AsrcVars_DL_VX_ADDR + (4 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = (-dtemp)<<2;
+		el[i + 1] = (-dtemp) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/*5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_VX_ADDR + 5*sizeof(s32);
+	mem_addr = D_AsrcVars_DL_VX_ADDR + (5 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0x00400000;
+		el[i + 1] = 0x00400000;
 	} else {
-		el[i+1] = (0x00100000-(dtemp/2))<<2;
+		el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 6. AlphaCurrent = 0x000020 (CMEM) */
 	mem_tag = ABE_CMEM;
 	mem_addr = C_AlphaCurrent_DL_VX_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x00000020;
+	el[i + 1] = 0x00000020;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 7. BetaCurrent = 0x3fffe0 (CMEM) */
 	mem_tag = ABE_CMEM;
 	mem_addr = C_BetaCurrent_DL_VX_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x003fffe0;
+	el[i + 1] = 0x003fffe0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 8. drift_ASRC = 0 & drift_io = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_IOdescr_ADDR + VX_DL_PORT*sizeof(ABE_SIODescriptor)
-		   + drift_asrc_;
+	mem_addr = D_IOdescr_ADDR + (VX_DL_PORT * sizeof(ABE_SIODescriptor))
+		+ drift_asrc_;
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 9. SMEM for ASRC_DL_VX_Coefs pointer */
 	/* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0
-		/1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+	   /1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
 	mem_tag = ABE_SMEM;
 	mem_addr = ASRC_DL_VX_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = C_CoefASRC16_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + C_CoefASRC16_VX_sizeof;
-
-	el[i+2] = C_CoefASRC15_VX_ADDR;
-	el[i+2] = (el[i+2]<<8) + C_CoefASRC15_VX_sizeof;
+	el[i + 1] = C_CoefASRC16_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_VX_sizeof;
+	el[i + 2] = C_CoefASRC15_VX_ADDR;
+	el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_VX_sizeof;
 	i = i + 3;
-
-
 	/* 10. CMEM for ASRC_DL_VX_Coefs pointer */
 	/* ASRC_DL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/
-		1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+	   1/C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
 	mem_tag = ABE_CMEM;
 	mem_addr = ASRC_DL_VX_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 11. SMEM for XinASRC_DL_VX pointer */
 	/* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
 	mem_addr = XinASRC_DL_VX_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_DL_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_VX_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_DL_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_DL_VX_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 12. CMEM for XinASRC_DL_VX pointer */
 	/* XinASRC_DL_VX = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
 	mem_addr = XinASRC_DL_VX_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 13. SMEM for IO_VX_DL_ASRC pointer */
 	/* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/
-		ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
 	mem_addr = IO_VX_DL_ASRC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_DL_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_VX_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_DL_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_DL_VX_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 14. CMEM for IO_VX_DL_ASRC pointer */
 	/* IO_VX_DL_ASRC = S_XinASRC_DL_VX_ADDR/S_XinASRC_DL_VX_sizeof/
-		ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_DL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
 	mem_addr = IO_VX_DL_ASRC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = ((ASRC_DL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12)
-		  + (temp0<<4) + temp0;
-
+	el[i + 1] = ((ASRC_DL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+		+ (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
-
-
-	abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR,(u32 *) &el[0], 42);
-
+	el[i + 2] = temp0;
+	abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 42);
 }
-
 /**
  * abe_init_asrc_vx_ul
  *
@@ -1492,239 +1399,187 @@ void abe_init_asrc_vx_dl ( s32 dppm)
  *		UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
  *	ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0
  */
-void abe_init_asrc_vx_ul ( s32 dppm)
+void abe_init_asrc_vx_ul(s32 dppm)
 {
 	s32 el[51];
 	s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
 	u32 i = 0;
-
 	temp0 = 0;
 	temp1 = 1;
-
-
 	/* 1. DriftSign = D_AsrcVars[1] = 1 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_UL_VX_ADDR + 1*sizeof(s32);
+	mem_addr = D_AsrcVars_UL_VX_ADDR + (1 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm >= 0) {
-		el[i+1] = 1;
+		el[i + 1] = 1;
 		adppm = dppm;
 	} else {
-		el[i+1] = -1;
-		adppm = (-1*dppm);
+		el[i + 1] = -1;
+		adppm = (-1 * dppm);
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-	dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L);
-
+	dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
 	/* 2. Subblock = D_AsrcVars[2] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_UL_VX_ADDR + 2*sizeof(s32);
+	mem_addr = D_AsrcVars_UL_VX_ADDR + (2 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_UL_VX_ADDR + 3*sizeof(s32);
+	mem_addr = D_AsrcVars_UL_VX_ADDR + (3 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = dtemp<<2;
+		el[i + 1] = dtemp << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
 	/* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_UL_VX_ADDR + 4*sizeof(s32);
+	mem_addr = D_AsrcVars_UL_VX_ADDR + (4 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = (-dtemp)<<2;
+		el[i + 1] = (-dtemp) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_UL_VX_ADDR + 5*sizeof(s32);
+	mem_addr = D_AsrcVars_UL_VX_ADDR + (5 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0x00400000;
+		el[i + 1] = 0x00400000;
 	} else {
-		el[i+1] = (0x00100000-(dtemp/2))<<2;
+		el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 6. AlphaCurrent = 0x000020 (CMEM) */
 	mem_tag = ABE_CMEM;
 	mem_addr = C_AlphaCurrent_UL_VX_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x00000020;
+	el[i + 1] = 0x00000020;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 7. BetaCurrent = 0x3fffe0 (CMEM) */
 	mem_tag = ABE_CMEM;
 	mem_addr = C_BetaCurrent_UL_VX_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x003fffe0;
+	el[i + 1] = 0x003fffe0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 8. drift_ASRC = 0 & drift_io = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_IOdescr_ADDR + VX_UL_PORT*sizeof(ABE_SIODescriptor)
-		   + drift_asrc_;
+	mem_addr = D_IOdescr_ADDR + (VX_UL_PORT * sizeof(ABE_SIODescriptor))
+		+ drift_asrc_;
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 9. SMEM for ASRC_UL_VX_Coefs pointer */
 	/* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
-		C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+	   C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
 	mem_tag = ABE_SMEM;
 	mem_addr = ASRC_UL_VX_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = C_CoefASRC16_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + C_CoefASRC16_VX_sizeof;
-
-	el[i+2] = C_CoefASRC15_VX_ADDR;
-	el[i+2] = (el[i+2]<<8) + C_CoefASRC15_VX_sizeof;
+	el[i + 1] = C_CoefASRC16_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_VX_sizeof;
+	el[i + 2] = C_CoefASRC15_VX_ADDR;
+	el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_VX_sizeof;
 	i = i + 3;
-
-
 	/* 10. CMEM for ASRC_UL_VX_Coefs pointer */
 	/* ASRC_UL_VX_Coefs = C_CoefASRC16_VX_ADDR/C_CoefASRC16_VX_sizeof/0/1/
-		C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
+	   C_CoefASRC15_VX_ADDR/C_CoefASRC15_VX_sizeof/0/1 */
 	mem_tag = ABE_CMEM;
 	mem_addr = ASRC_UL_VX_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 11. SMEM for XinASRC_UL_VX pointer */
 	/* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
 	mem_addr = XinASRC_UL_VX_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_UL_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_UL_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 12. CMEM for XinASRC_UL_VX pointer */
 	/* XinASRC_UL_VX = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
 	mem_addr = XinASRC_UL_VX_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 13. SMEM for UL_48_8_DEC pointer */
 	/* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
-		ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
 	mem_addr = UL_48_8_DEC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_UL_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_UL_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 14. CMEM for UL_48_8_DEC pointer */
 	/* UL_48_8_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
-		ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
 	mem_addr = UL_48_8_DEC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = ((ASRC_UL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12)
-		  + (temp0<<4) + temp0;
-
+	el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+		+ (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 15. SMEM for UL_48_16_DEC pointer */
 	/* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
-		ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
 	mem_addr = UL_48_16_DEC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_UL_VX_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_UL_VX_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_UL_VX_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_UL_VX_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 16. CMEM for UL_48_16_DEC pointer */
 	/* UL_48_16_DEC = S_XinASRC_UL_VX_ADDR/S_XinASRC_UL_VX_sizeof/
-		ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
+	   ASRC_UL_VX_FIR_L+ASRC_margin/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
 	mem_addr = UL_48_16_DEC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = ((ASRC_UL_VX_FIR_L+ASRC_margin)<<16) + (temp1<<12)
-		  + (temp0<<4) + temp0;
-
+	el[i + 1] = ((ASRC_UL_VX_FIR_L + ASRC_margin) << 16) + (temp1 << 12)
+		+ (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
-
-
-	abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *)&el[0], 48);
-
+	el[i + 2] = temp0;
+	abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 48);
 }
-
 /**
- * abe_init_asrc_mm_dl
+ * abe_init_asrc_mm_ext_in
  *
- *	Initialize the following ASRC MM_DL parameters :
+ *	Initialize the following ASRC MM_EXT_IN parameters :
  * 1. DriftSign = D_AsrcVars[1] = 1 or -1
  * 2. Subblock = D_AsrcVars[2] = 0
  * 3. DeltaAlpha = D_AsrcVars[3] = (round(nb_phases * drift[ppm] * 10^-6 * 2^20)) << 2
@@ -1734,214 +1589,170 @@ void abe_init_asrc_vx_ul ( s32 dppm)
  * 7. BetaCurrent = 0x3fffe0 (CMEM), initial value of Beta parameter
  * AlphaCurrent + BetaCurrent = 1 (=0x400000 in CMEM = 2^20 << 2)
  * 8. drift_ASRC = 0 & drift_io = 0
- *	9. SMEM for ASRC_DL_MM_Coefs pointer
- *	10. CMEM for ASRC_DL_MM_Coefs pointer
- *		ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof/
- *		0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1
- *	11. SMEM for XinASRC_DL_MM pointer
- *	12. CMEM for XinASRC_DL_MM pointer
- *		XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0
- *	13. SMEM for IO_MM_DL_ASRC pointer
- *	14. CMEM for IO_MM_DL_ASRC pointer
- *		IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/
- *		ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0
+ *	9. SMEM for ASRC_MM_EXT_IN_Coefs pointer
+ *	10. CMEM for ASRC_MM_EXT_IN_Coefs pointer
+ *		ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof/
+ *		0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1
+ *	11. SMEM for XinASRC_MM_EXT_IN pointer
+ *	12. CMEM for XinASRC_MM_EXT_IN pointer
+ *		XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0
+ *	13. SMEM for IO_MM_EXT_IN_ASRC pointer
+ *	14. CMEM for IO_MM_EXT_IN_ASRC pointer
+ *		IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+ *		ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0
  */
-void abe_init_asrc_mm_dl ( s32 dppm)
+void abe_init_asrc_mm_ext_in(s32 dppm)
 {
 	s32 el[45];
 	s32 temp0, temp1, adppm, dtemp, mem_tag, mem_addr;
 	u32 i = 0;
-
 	temp0 = 0;
 	temp1 = 1;
-
 	/* 1. DriftSign = D_AsrcVars[1] = 1 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_MM_ADDR + 1*sizeof(s32);
+	mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (1 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm >= 0) {
-		el[i+1] = 1;
+		el[i + 1] = 1;
 		adppm = dppm;
 	} else {
-		el[i+1] = -1;
-		adppm = (-1*dppm);
+		el[i + 1] = -1;
+		adppm = (-1 * dppm);
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-	dtemp = (adppm << 4) + adppm - ((adppm * 3481L)/15625L);
-
+	dtemp = (adppm << 4) + adppm - ((adppm * 3481L) / 15625L);
 	/* 2. Subblock = D_AsrcVars[2] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_MM_ADDR + 2*sizeof(s32);
+	mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (2 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 3. DeltaAlpha = D_AsrcVars[3] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_MM_ADDR + 3*sizeof(s32);
+	mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (3 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = dtemp<<2;
+		el[i + 1] = dtemp << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 4. MinusDeltaAlpha = D_AsrcVars[4] = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_MM_ADDR + 4*sizeof(s32);
+	mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (4 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0;
+		el[i + 1] = 0;
 	} else {
-		el[i+1] = (-dtemp)<<2;
+		el[i + 1] = (-dtemp) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 5. OneMinusEpsilon = D_AsrcVars[5] = 0x00400000 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_AsrcVars_DL_MM_ADDR + 5*sizeof(s32);
+	mem_addr = D_AsrcVars_MM_EXT_IN_ADDR + (5 * sizeof(s32));
 	el[i] = (mem_tag << 16) + mem_addr;
 	if (dppm == 0) {
-		el[i+1] = 0x00400000;
+		el[i + 1] = 0x00400000;
 	} else {
-		el[i+1] = (0x00100000-(dtemp/2))<<2;
+		el[i + 1] = (0x00100000 - (dtemp / 2)) << 2;
 	}
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 6. AlphaCurrent = 0x000020 (CMEM) */
 	mem_tag = ABE_CMEM;
-	mem_addr = C_AlphaCurrent_DL_MM_ADDR;
+	mem_addr = C_AlphaCurrent_MM_EXT_IN_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x00000020;
+	el[i + 1] = 0x00000020;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 7. BetaCurrent = 0x3fffe0 (CMEM) */
 	mem_tag = ABE_CMEM;
-	mem_addr = C_BetaCurrent_DL_MM_ADDR;
+	mem_addr = C_BetaCurrent_MM_EXT_IN_ADDR;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-	el[i+1] = 0x003fffe0;
+	el[i + 1] = 0x003fffe0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
 	/* 8. drift_ASRC = 0 & drift_io = 0 */
 	mem_tag = ABE_DMEM;
-	mem_addr = D_IOdescr_ADDR + MM_DL_PORT*sizeof(ABE_SIODescriptor)
-		   + drift_asrc_;
+	mem_addr = D_IOdescr_ADDR + (MM_EXT_IN_PORT * sizeof(ABE_SIODescriptor))
+		+ drift_asrc_;
 	el[i] = (mem_tag << 16) + mem_addr;
-	el[i+1] = temp0;
+	el[i + 1] = temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
-	/* 9. SMEM for ASRC_DL_MM_Coefs pointer */
-	/* ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof
-		/0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1 */
+	/* 9. SMEM for ASRC_MM_EXT_IN_Coefs pointer */
+	/* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof
+	   /0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */
 	mem_tag = ABE_SMEM;
-	mem_addr = ASRC_DL_MM_Coefs_labelID;
+	mem_addr = ASRC_MM_EXT_IN_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = C_CoefASRC16_DL_MM_ADDR;
-	el[i+1] = (el[i+1]<<8) + C_CoefASRC16_DL_MM_sizeof;
-
-	el[i+2] = C_CoefASRC15_DL_MM_ADDR;
-	el[i+2] = (el[i+2]<<8) + C_CoefASRC15_DL_MM_sizeof;
+	el[i + 1] = C_CoefASRC16_MM_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + C_CoefASRC16_MM_sizeof;
+	el[i + 2] = C_CoefASRC15_MM_ADDR;
+	el[i + 2] = (el[i + 2] << 8) + C_CoefASRC15_MM_sizeof;
 	i = i + 3;
-
-
-	/*10. 11. CMEM for ASRC_DL_MM_Coefs pointer */
-	/* ASRC_DL_MM_Coefs = C_CoefASRC16_DL_MM_ADDR/C_CoefASRC16_DL_MM_sizeof
-		/0/1/C_CoefASRC15_DL_MM_ADDR/C_CoefASRC15_DL_MM_sizeof/0/1 */
+	/*10. CMEM for ASRC_MM_EXT_IN_Coefs pointer */
+	/* ASRC_MM_EXT_IN_Coefs = C_CoefASRC16_MM_ADDR/C_CoefASRC16_MM_sizeof
+	   /0/1/C_CoefASRC15_MM_ADDR/C_CoefASRC15_MM_sizeof/0/1 */
 	mem_tag = ABE_CMEM;
-	mem_addr = ASRC_DL_MM_Coefs_labelID;
+	mem_addr = ASRC_MM_EXT_IN_Coefs_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp1;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp1;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
-	/* 11. SMEM for XinASRC_DL_MM pointer */
-	/* XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0 */
+	/* 11. SMEM for XinASRC_MM_EXT_IN pointer */
+	/* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
-	mem_addr = XinASRC_DL_MM_labelID;
+	mem_addr = XinASRC_MM_EXT_IN_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_DL_MM_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_MM_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_MM_EXT_IN_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_MM_EXT_IN_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
-
-	/* 12. CMEM for XinASRC_DL_MM pointer */
-	/* XinASRC_DL_MM = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/0/1/0/0/0/0 */
+	/* 12. CMEM for XinASRC_MM_EXT_IN pointer */
+	/* XinASRC_MM_EXT_IN = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/0/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
-	mem_addr = XinASRC_DL_MM_labelID;
+	mem_addr = XinASRC_MM_EXT_IN_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = (temp0<<16) + (temp1<<12) + (temp0<<4) + temp0;
-
+	el[i + 1] = (temp0 << 16) + (temp1 << 12) + (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
-	/* 13. SMEM for IO_MM_DL_ASRC pointer */
-	/* IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/
-		ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
+	/* 13. SMEM for IO_MM_EXT_IN_ASRC pointer */
+	/* IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+	   ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
 	mem_tag = ABE_SMEM;
-	mem_addr = IO_MM_DL_ASRC_labelID;
+	mem_addr = IO_MM_EXT_IN_ASRC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
-	el[i+1] = S_XinASRC_DL_MM_ADDR;
-	el[i+1] = (el[i+1]<<8) + S_XinASRC_DL_MM_sizeof;
-
-	el[i+2] = temp0;
+	el[i + 1] = S_XinASRC_MM_EXT_IN_ADDR;
+	el[i + 1] = (el[i + 1] << 8) + S_XinASRC_MM_EXT_IN_sizeof;
+	el[i + 2] = temp0;
 	i = i + 3;
-
-
-	/* 14. CMEM for IO_MM_DL_ASRC pointer */
-	/* IO_MM_DL_ASRC = S_XinASRC_DL_MM_ADDR/S_XinASRC_DL_MM_sizeof/
-		ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
+	/* 14. CMEM for IO_MM_EXT_IN_ASRC pointer */
+	/* IO_MM_EXT_IN_ASRC = S_XinASRC_MM_EXT_IN_ADDR/S_XinASRC_MM_EXT_IN_sizeof/
+	   ASRC_MM_EXT_IN_FIR_L+ASRC_margin+ASRC_N_48k/1/0/0/0/0 */
 	mem_tag = ABE_CMEM;
-	mem_addr = IO_MM_DL_ASRC_labelID;
+	mem_addr = IO_MM_EXT_IN_ASRC_labelID;
 	el[i] = (mem_tag << 16) + (mem_addr << 2);
-
 	/* el[i+1] = iam1<<16 + inc1<<12 + iam2<<4 + inc2 */
-	el[i+1] = ((ASRC_DL_MM_FIR_L+ASRC_margin+ASRC_N_48k)<<16) +
-		  (temp1<<12) + (temp0<<4) + temp0;
-
+	el[i + 1] = ((ASRC_MM_EXT_IN_FIR_L + ASRC_margin + ASRC_N_48k) << 16) +
+		(temp1 << 12) + (temp0 << 4) + temp0;
 	/* dummy field */
-	el[i+2] = temp0;
-
-
-	abe_write_fifo (ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *)&el[0], 42);
-
+	el[i + 2] = temp0;
+	abe_write_fifo(ABE_DMEM, D_FwMemInitDescr_ADDR, (u32 *) &el[0], 42);
 }
diff --git a/sound/soc/omap/abe/abe_initxxx_labels.h b/sound/soc/omap/abe/abe_initxxx_labels.h
index 5057be313abf..251dcbffe01d 100644
--- a/sound/soc/omap/abe/abe_initxxx_labels.h
+++ b/sound/soc/omap/abe/abe_initxxx_labels.h
@@ -20,309 +20,309 @@
  */
 #ifndef _ABE_INITXXX_LABELS_H_
 #define _ABE_INITXXX_LABELS_H_
-
-#define Dummy_Regs_labelID                                  0 
-#define Dummy_AM_labelID                                    1 
-#define Voice_8k_UL_labelID                                 2 
-#define Voice_8k_DL_labelID                                 3 
-#define ECHO_REF_8K_labelID                                 4 
-#define Voice_16k_UL_labelID                                5 
-#define Voice_16k_DL_labelID                                6 
-#define ECHO_REF_16K_labelID                                7 
-#define MM_DL_labelID                                       8 
-#define IO_VX_DL_ASRC_labelID                               9 
-#define IO_MM_DL_ASRC_labelID                               10 
-#define IO_VIBRA_DL_labelID                                 11 
-#define ZERO_labelID                                        12 
-#define GTarget_labelID                                     13 
-#define GCurrent_labelID                                    14 
-#define Gr_1_labelID                                        15 
-#define Gr_2_labelID                                        16 
-#define Gr_Regs_labelID                                     17 
-#define DMIC0_Gain_labelID                                  18 
-#define DMIC1_Gain_labelID                                  19 
-#define DMIC2_Gain_labelID                                  20 
-#define DMIC3_Gain_labelID                                  21 
-#define AMIC_Gain_labelID                                   22 
-#define MIXDL1_Gain_labelID                                 23 
-#define MIXDL2_Gain_labelID                                 24 
-#define DEFAULT_Gain_labelID                                25 
-#define DL1_M_G_Tones_labelID                               26 
-#define DL2_M_G_Tones_labelID                               27 
-#define Echo_M_G_labelID                                    28 
-#define SDT_M_G_labelID                                     29 
-#define VXREC_M_G_VX_DL_labelID                             30 
-#define UL_M_G_VX_DL_labelID                                31 
-#define DL1_M_labelID                                       32 
-#define DL2_M_labelID                                       33 
-#define MM_UL2_labelID                                      34 
-#define VX_DL_labelID                                       35 
-#define Tones_labelID                                       36 
-#define DL_M_MM_UL2_VX_DL_labelID                           37 
-#define Echo_M_labelID                                      38 
-#define VX_UL_labelID                                       39 
-#define VX_UL_M_labelID                                     40 
-#define SDT_F_labelID                                       41 
-#define SDT_F_data_labelID                                  42 
-#define SDT_Coef_labelID                                    43 
-#define SDT_Regs_labelID                                    44 
-#define SDT_M_labelID                                       45 
-#define DL1_EQ_labelID                                      46 
-#define DL2_EQ_labelID                                      47 
-#define DL1_GAIN_out_labelID                                48 
-#define DL2_GAIN_out_labelID                                49 
-#define DMIC1_labelID                                       50 
-#define DMIC1_L_labelID                                     51 
-#define DMIC1_R_labelID                                     52 
-#define DMIC2_labelID                                       53 
-#define DMIC2_L_labelID                                     54 
-#define DMIC2_R_labelID                                     55 
-#define DMIC3_labelID                                       56 
-#define DMIC3_L_labelID                                     57 
-#define DMIC3_R_labelID                                     58 
-#define MIC4_labelID                                        59 
-#define MIC4_L_labelID                                      60 
-#define MIC4_R_labelID                                      61 
-#define BT_UL_L_labelID                                     62 
-#define BT_UL_R_labelID                                     63 
-#define AMIC_labelID                                        64 
-#define AMIC_L_labelID                                      65 
-#define AMIC_R_labelID                                      66 
-#define EANC_FBK_In_labelID                                 67 
-#define EANC_FBK_Out_labelID                                68 
-#define EANC_FBK_L_labelID                                  69 
-#define EANC_FBK_R_labelID                                  70 
-#define EchoRef_L_labelID                                   71 
-#define EchoRef_R_labelID                                   72 
-#define MM_DL_L_labelID                                     73 
-#define MM_DL_R_labelID                                     74 
-#define MM_UL_labelID                                       75 
-#define AMIC_96_labelID                                     76 
-#define DMIC0_96_labelID                                    77 
-#define DMIC1_96_labelID                                    78 
-#define DMIC2_96_labelID                                    79 
-#define DMIC_desc_labelID                                   80 
-#define UL_MIC_48K_labelID                                  81 
-#define EQ_DL_48K_labelID                                   82 
-#define EQ_48K_labelID                                      83 
-#define McPDM_Out1_labelID                                  84 
-#define McPDM_Out2_labelID                                  85 
-#define McPDM_Out3_labelID                                  86 
-#define VX_UL_MUX_labelID                                   87 
-#define MM_UL2_MUX_labelID                                  88 
-#define MM_UL_MUX_labelID                                   89 
-#define XinASRC_DL_VX_labelID                               90 
-#define ASRC_DL_VX_Coefs_labelID                            91 
-#define ASRC_DL_VX_Alpha_labelID                            92 
-#define ASRC_DL_VX_VarsBeta_labelID                         93 
-#define ASRC_DL_VX_8k_Regs_labelID                          94 
-#define XinASRC_UL_VX_labelID                               95 
-#define ASRC_UL_VX_Coefs_labelID                            96 
-#define ASRC_UL_VX_Alpha_labelID                            97 
-#define ASRC_UL_VX_VarsBeta_labelID                         98 
-#define ASRC_UL_VX_8k_Regs_labelID                          99 
-#define UL_48_8_DEC_labelID                                 100 
-#define ASRC_DL_VX_16k_Regs_labelID                         101 
-#define ASRC_UL_VX_16k_Regs_labelID                         102 
-#define UL_48_16_DEC_labelID                                103 
-#define XinASRC_DL_MM_labelID                               104 
-#define ASRC_DL_MM_Coefs_labelID                            105 
-#define ASRC_DL_MM_Alpha_labelID                            106 
-#define ASRC_DL_MM_VarsBeta_labelID                         107 
-#define ASRC_DL_MM_Regs_labelID                             108 
-#define VX_REC_labelID                                      109 
-#define VXREC_UL_M_Tones_VX_UL_labelID                      110 
-#define VX_REC_L_labelID                                    111 
-#define VX_REC_R_labelID                                    112 
-#define DL2_M_L_labelID                                     113 
-#define DL2_M_R_labelID                                     114 
-#define DL1_M_data_labelID                                  115 
-#define DL1_M_Coefs_labelID                                 116 
-#define DL2_M_LR_data_labelID                               117 
-#define DL2_M_LR_Coefs_labelID                              118 
-#define SRC_6_LP_COEFS_labelID                              119 
-#define SRC_6_LP_GAIN_COEFS_labelID                         120 
-#define SRC_6_HP_COEFS_labelID                              121 
-#define SRC_3_LP_COEFS_labelID                              122 
-#define SRC_3_LP_GAIN_COEFS_labelID                         123 
-#define SRC_3_HP_COEFS_labelID                              124 
-#define VX_DL_8_48_LP_DATA_labelID                          125 
-#define VX_DL_8_48_HP_DATA_labelID                          126 
-#define VX_DL_16_48_LP_DATA_labelID                         127 
-#define VX_DL_16_48_HP_DATA_labelID                         128 
-#define VX_UL_48_8_LP_DATA_labelID                          129 
-#define VX_UL_48_8_HP_DATA_labelID                          130 
-#define VX_UL_48_16_LP_DATA_labelID                         131 
-#define VX_UL_48_16_HP_DATA_labelID                         132 
-#define BT_UL_8_48_LP_DATA_labelID                          133 
-#define BT_UL_8_48_HP_DATA_labelID                          134 
-#define BT_UL_16_48_LP_DATA_labelID                         135 
-#define BT_UL_16_48_HP_DATA_labelID                         136 
-#define BT_DL_48_8_LP_DATA_labelID                          137 
-#define BT_DL_48_8_HP_DATA_labelID                          138 
-#define BT_DL_48_16_LP_DATA_labelID                         139 
-#define BT_DL_48_16_HP_DATA_labelID                         140 
-#define ECHO_REF_48_16_LP_DATA_labelID                      141 
-#define ECHO_REF_48_16_HP_DATA_labelID                      142 
-#define ECHO_REF_48_8_LP_DATA_labelID                       143 
-#define ECHO_REF_48_8_HP_DATA_labelID                       144 
-#define ECHO_REF_DEC_labelID                                145 
-#define VX_UL_8_TEMP_labelID                                146 
-#define VX_UL_16_TEMP_labelID                               147 
-#define UP_DOWN_8_48_labelID                                148 
-#define UP_DOWN_16_48_labelID                               149 
-#define SRC_6_LP_48k_labelID                                150 
-#define SRC_6_HP_labelID                                    151 
-#define SRC_3_LP_48k_labelID                                152 
-#define SRC_3_HP_labelID                                    153 
-#define EARP_48_96_LP_DATA_labelID                          154 
-#define SRC_48_96_LP_labelID                                155 
-#define IHF_48_96_LP_DATA_labelID                           156 
-#define EQ_VX_UL_16K_labelID                                157 
-#define pAPS_iir1_p23_labelID                               158 
-#define pAPS_iir1_p45_labelID                               159 
-#define APS_IIR_Regs_labelID                                160 
-#define pAPS_core_DL1_p1_labelID                            161 
-#define pAPS_core_DL1_p23_labelID                           162 
-#define pAPS_core_DL1_p45_labelID                           163 
-#define pAPS_core_DL1_r_labelID                             164 
-#define pAPS_DL2L_core_r_labelID                            165 
-#define pAPS_DL2R_core_r_labelID                            166 
-#define pAPS_COIL_core_DL1_p1_labelID                       167 
-#define pAPS_COIL_core_DL1_p23_labelID                      168 
-#define pAPS_COIL_core_DL1_p45_labelID                      169 
-#define pAPS_COIL_core_DL1_r_labelID                        170 
-#define DL2_L_APS_IIR_p23_labelID                           171 
-#define DL2_R_APS_IIR_p23_labelID                           172 
-#define DL2_L_APS_IIR_p45_labelID                           173 
-#define DL2_R_APS_IIR_p45_labelID                           174 
-#define DL2_L_APS_CORE_p1_labelID                           175 
-#define DL2_L_APS_CORE_p23_labelID                          176 
-#define DL2_L_APS_CORE_p45_labelID                          177 
-#define DL2_R_APS_CORE_p1_labelID                           178 
-#define DL2_R_APS_CORE_p23_labelID                          179 
-#define DL2_R_APS_CORE_p45_labelID                          180 
-#define DL2_L_APS_COIL_CORE_p1_labelID                      181 
-#define DL2_L_APS_COIL_CORE_p23_labelID                     182 
-#define DL2_L_APS_COIL_CORE_p45_labelID                     183 
-#define pAPS_COIL_DL2L_core_r_labelID                       184 
-#define DL2_R_APS_COIL_CORE_p1_labelID                      185 
-#define DL2_R_APS_COIL_CORE_p23_labelID                     186 
-#define DL2_R_APS_COIL_CORE_p45_labelID                     187 
-#define pAPS_COIL_DL2R_core_r_labelID                       188 
-#define DL1_APS_labelID                                     189 
-#define DL2_L_APS_labelID                                   190 
-#define DL2_R_APS_labelID                                   191 
-#define pEANC_p0_labelID                                    192 
-#define pEANC_p1_labelID                                    193 
-#define pEANC_p23_labelID                                   194 
-#define pEANC_p45_labelID                                   195 
-#define pEANC_reg1_labelID                                  196 
-#define pEANC_reg2_labelID                                  197 
-#define pEANC_reg3_labelID                                  198 
-#define pEANC_r_labelID                                     199 
-#define DL1_APS_EQ_p23_labelID                              200 
-#define DL1_APS_EQ_p45_labelID                              201 
-#define DL2_APS_EQ_p23_labelID                              202 
-#define DL2_APS_EQ_p45_labelID                              203 
-#define pDC_EANC_p23_labelID                                204 
-#define pDC_EANC_r_labelID                                  205 
-#define pVIBRA1_p0_labelID                                  206 
-#define pVIBRA1_p1_labelID                                  207 
-#define pVIBRA1_p23_labelID                                 208 
-#define pVIBRA1_p45_labelID                                 209 
-#define pVibra1_pR1_labelID                                 210 
-#define pVibra1_pR2_labelID                                 211 
-#define pVibra1_pR3_labelID                                 212 
-#define pVIBRA1_r_labelID                                   213 
-#define pVIBRA2_p0_labelID                                  214 
-#define pVIBRA2_p1_labelID                                  215 
-#define pVIBRA2_p23_labelID                                 216 
-#define pVIBRA2_p45_labelID                                 217 
-#define pCtrl_p67_labelID                                   218 
-#define pVIBRA2_r_labelID                                   219 
-#define VIBRA_labelID                                       220 
-#define PING_labelID                                        221 
-#define PING_Regs_labelID                                   222 
-#define UP_48_96_LP_COEFS_labelID                           223 
-#define AMIC_96_48_data_labelID                             224 
-#define DOWN_96_48_Coefs_labelID                            225 
-#define DOWN_96_48_Regs_labelID                             226 
-#define DMIC0_96_48_data_labelID                            227 
-#define DMIC1_96_48_data_labelID                            228 
-#define DMIC2_96_48_data_labelID                            229 
-#define EANC_FBK_96_48_data_labelID                         230 
-#define pDC_EANC_r2_labelID                                 231 
-#define SIO_DMIC_labelID                                    232 
-#define SIO_PDM_UL_labelID                                  233 
-#define SIO_BT_VX_UL_labelID                                234 
-#define SIO_MM_UL_labelID                                   235 
-#define SIO_MM_UL2_labelID                                  236 
-#define SIO_VX_UL_labelID                                   237 
-#define SIO_MM_DL_labelID                                   238 
-#define SIO_VX_DL_labelID                                   239 
-#define SIO_TONES_DL_labelID                                240 
-#define SIO_VIB_DL_labelID                                  241 
-#define SIO_BT_VX_DL_labelID                                242 
-#define SIO_PDM_DL_labelID                                  243 
-#define SIO_MM_EXT_OUT_labelID                              244 
-#define SIO_MM_EXT_IN_labelID                               245 
-#define SIO_TDM_OUT_labelID                                 246 
-#define SIO_TDM_IN_labelID                                  247 
-#define DMIC_ATC_PTR_labelID                                248 
-#define MCPDM_UL_ATC_PTR_labelID                            249 
-#define BT_VX_UL_ATC_PTR_labelID                            250 
-#define MM_UL_ATC_PTR_labelID                               251 
-#define MM_UL2_ATC_PTR_labelID                              252 
-#define VX_UL_ATC_PTR_labelID                               253 
-#define MM_DL_ATC_PTR_labelID                               254 
-#define VX_DL_ATC_PTR_labelID                               255 
-#define TONES_DL_ATC_PTR_labelID                            256 
-#define VIB_DL_ATC_PTR_labelID                              257 
-#define BT_VX_DL_ATC_PTR_labelID                            258 
-#define PDM_DL_ATC_PTR_labelID                              259 
-#define MM_EXT_OUT_ATC_PTR_labelID                          260 
-#define MM_EXT_IN_ATC_PTR_labelID                           261 
-#define TDM_OUT_ATC_PTR_labelID                             262 
-#define TDM_IN_ATC_PTR_labelID                              263 
-#define MCU_IRQ_FIFO_ptr_labelID                            264 
-#define DEBUG_IRQ_FIFO_reg_labelID                          265 
-#define UP_DOWN_48_96_labelID                               266 
-#define OSR96_2_labelID                                     267 
-#define DEBUG_GAINS_labelID                                 268 
-#define DBG_8K_PATTERN_labelID                              269 
-#define DBG_16K_PATTERN_labelID                             270 
-#define DBG_24K_PATTERN_labelID                             271 
-#define DBG_48K_PATTERN_labelID                             272 
-#define DBG_96K_PATTERN_labelID                             273 
-#define UL_VX_UL_48_8K_labelID                              274 
-#define UL_VX_UL_48_16K_labelID                             275 
-#define BT_DL_labelID                                       276 
-#define BT_UL_labelID                                       277 
-#define BT_DL_8k_labelID                                    278 
-#define BT_DL_16k_labelID                                   279 
-#define BT_UL_8k_labelID                                    280 
-#define BT_UL_16k_labelID                                   281 
-#define MM_EXT_IN_labelID                                   282 
-#define MM_EXT_IN_L_labelID                                 283 
-#define MM_EXT_IN_R_labelID                                 284 
-#define ECHO_REF_48_16_WRAP_labelID                         285 
-#define ECHO_REF_48_8_WRAP_labelID                          286 
-#define BT_UL_16_48_WRAP_labelID                            287 
-#define BT_UL_8_48_WRAP_labelID                             288 
-#define BT_DL_48_16_WRAP_labelID                            289 
-#define BT_DL_48_8_WRAP_labelID                             290 
-#define VX_DL_16_48_WRAP_labelID                            291 
-#define VX_DL_8_48_WRAP_labelID                             292 
-#define VX_UL_48_16_WRAP_labelID                            293 
-#define VX_UL_48_8_WRAP_labelID                             294 
-#define APS_DL1_IRQs_WRAP_labelID                           295 
-#define APS_DL2_L_IRQs_WRAP_labelID                         296 
-#define APS_DL2_R_IRQs_WRAP_labelID                         297 
-#define ATC_NULL_BUFFER_labelID                             298 
-#define MEM_INIT_hal_mem_labelID                            299 
-#define MEM_INIT_write_mem_labelID                          300 
-#define MEM_INIT_regs_labelID                               301 
-#define GAIN_0DB_labelID                                    302 
-
-#endif /* _ABE_INITXXXX_LABELS_H_ */
+#define Dummy_Regs_labelID                                  0
+#define Dummy_AM_labelID                                    1
+#define Voice_8k_UL_labelID                                 2
+#define Voice_8k_DL_labelID                                 3
+#define ECHO_REF_8K_labelID                                 4
+#define Voice_16k_UL_labelID                                5
+#define Voice_16k_DL_labelID                                6
+#define ECHO_REF_16K_labelID                                7
+#define MM_DL_labelID                                       8
+#define IO_VX_DL_ASRC_labelID                               9
+#define IO_MM_EXT_IN_ASRC_labelID                           10
+#define IO_VIBRA_DL_labelID                                 11
+#define ZERO_labelID                                        12
+#define GTarget_labelID                                     13
+#define GCurrent_labelID                                    14
+#define Gr_1_labelID                                        15
+#define Gr_2_labelID                                        16
+#define Gr_Regs_labelID                                     17
+#define DMIC0_Gain_labelID                                  18
+#define DMIC1_Gain_labelID                                  19
+#define DMIC2_Gain_labelID                                  20
+#define DMIC3_Gain_labelID                                  21
+#define AMIC_Gain_labelID                                   22
+#define MIXDL1_Gain_labelID                                 23
+#define MIXDL2_Gain_labelID                                 24
+#define DEFAULT_Gain_labelID                                25
+#define DL1_M_G_Tones_labelID                               26
+#define DL2_M_G_Tones_labelID                               27
+#define Echo_M_G_labelID                                    28
+#define SDT_M_G_labelID                                     29
+#define VXREC_M_G_VX_DL_labelID                             30
+#define UL_M_G_VX_DL_labelID                                31
+#define DL1_M_labelID                                       32
+#define DL2_M_labelID                                       33
+#define MM_UL2_labelID                                      34
+#define VX_DL_labelID                                       35
+#define Tones_labelID                                       36
+#define DL_M_MM_UL2_VX_DL_labelID                           37
+#define Echo_M_labelID                                      38
+#define VX_UL_labelID                                       39
+#define VX_UL_M_labelID                                     40
+#define SDT_F_labelID                                       41
+#define SDT_F_data_labelID                                  42
+#define SDT_Coef_labelID                                    43
+#define SDT_Regs_labelID                                    44
+#define SDT_M_labelID                                       45
+#define DL1_EQ_labelID                                      46
+#define DL2_EQ_labelID                                      47
+#define DL1_GAIN_out_labelID                                48
+#define DL2_GAIN_out_labelID                                49
+#define DMIC1_labelID                                       50
+#define DMIC1_L_labelID                                     51
+#define DMIC1_R_labelID                                     52
+#define DMIC2_labelID                                       53
+#define DMIC2_L_labelID                                     54
+#define DMIC2_R_labelID                                     55
+#define DMIC3_labelID                                       56
+#define DMIC3_L_labelID                                     57
+#define DMIC3_R_labelID                                     58
+#define MIC4_labelID                                        59
+#define MIC4_L_labelID                                      60
+#define MIC4_R_labelID                                      61
+#define BT_UL_L_labelID                                     62
+#define BT_UL_R_labelID                                     63
+#define AMIC_labelID                                        64
+#define AMIC_L_labelID                                      65
+#define AMIC_R_labelID                                      66
+#define EANC_FBK_In_labelID                                 67
+#define EANC_FBK_Out_labelID                                68
+#define EANC_FBK_L_labelID                                  69
+#define EANC_FBK_R_labelID                                  70
+#define EchoRef_L_labelID                                   71
+#define EchoRef_R_labelID                                   72
+#define MM_DL_L_labelID                                     73
+#define MM_DL_R_labelID                                     74
+#define MM_UL_labelID                                       75
+#define AMIC_96_labelID                                     76
+#define DMIC0_96_labelID                                    77
+#define DMIC1_96_labelID                                    78
+#define DMIC2_96_labelID                                    79
+#define DMIC_desc_labelID                                   80
+#define UL_MIC_48K_labelID                                  81
+#define EQ_DL_48K_labelID                                   82
+#define EQ_48K_labelID                                      83
+#define McPDM_Out1_labelID                                  84
+#define McPDM_Out2_labelID                                  85
+#define McPDM_Out3_labelID                                  86
+#define VX_UL_MUX_labelID                                   87
+#define MM_UL2_MUX_labelID                                  88
+#define MM_UL_MUX_labelID                                   89
+#define XinASRC_DL_VX_labelID                               90
+#define ASRC_DL_VX_Coefs_labelID                            91
+#define ASRC_DL_VX_Alpha_labelID                            92
+#define ASRC_DL_VX_VarsBeta_labelID                         93
+#define ASRC_DL_VX_8k_Regs_labelID                          94
+#define XinASRC_UL_VX_labelID                               95
+#define ASRC_UL_VX_Coefs_labelID                            96
+#define ASRC_UL_VX_Alpha_labelID                            97
+#define ASRC_UL_VX_VarsBeta_labelID                         98
+#define ASRC_UL_VX_8k_Regs_labelID                          99
+#define UL_48_8_DEC_labelID                                 100
+#define ASRC_DL_VX_16k_Regs_labelID                         101
+#define ASRC_UL_VX_16k_Regs_labelID                         102
+#define UL_48_16_DEC_labelID                                103
+#define XinASRC_MM_EXT_IN_labelID                           104
+#define ASRC_MM_EXT_IN_Coefs_labelID                        105
+#define ASRC_MM_EXT_IN_Alpha_labelID                        106
+#define ASRC_MM_EXT_IN_VarsBeta_labelID                     107
+#define ASRC_MM_EXT_IN_Regs_labelID                         108
+#define VX_REC_labelID                                      109
+#define VXREC_UL_M_Tones_VX_UL_labelID                      110
+#define VX_REC_L_labelID                                    111
+#define VX_REC_R_labelID                                    112
+#define DL2_M_L_labelID                                     113
+#define DL2_M_R_labelID                                     114
+#define DL1_M_data_labelID                                  115
+#define DL1_M_Coefs_labelID                                 116
+#define DL2_M_LR_data_labelID                               117
+#define DL2_M_LR_Coefs_labelID                              118
+#define SRC_6_LP_COEFS_labelID                              119
+#define SRC_6_LP_GAIN_COEFS_labelID                         120
+#define SRC_6_HP_COEFS_labelID                              121
+#define SRC_3_LP_COEFS_labelID                              122
+#define SRC_3_LP_GAIN_COEFS_labelID                         123
+#define SRC_3_HP_COEFS_labelID                              124
+#define VX_DL_8_48_LP_DATA_labelID                          125
+#define VX_DL_8_48_HP_DATA_labelID                          126
+#define VX_DL_16_48_LP_DATA_labelID                         127
+#define VX_DL_16_48_HP_DATA_labelID                         128
+#define VX_UL_48_8_LP_DATA_labelID                          129
+#define VX_UL_48_8_HP_DATA_labelID                          130
+#define VX_UL_48_16_LP_DATA_labelID                         131
+#define VX_UL_48_16_HP_DATA_labelID                         132
+#define BT_UL_8_48_LP_DATA_labelID                          133
+#define BT_UL_8_48_HP_DATA_labelID                          134
+#define BT_UL_16_48_LP_DATA_labelID                         135
+#define BT_UL_16_48_HP_DATA_labelID                         136
+#define BT_DL_48_8_LP_DATA_labelID                          137
+#define BT_DL_48_8_HP_DATA_labelID                          138
+#define BT_DL_48_16_LP_DATA_labelID                         139
+#define BT_DL_48_16_HP_DATA_labelID                         140
+#define ECHO_REF_48_16_LP_DATA_labelID                      141
+#define ECHO_REF_48_16_HP_DATA_labelID                      142
+#define ECHO_REF_48_8_LP_DATA_labelID                       143
+#define ECHO_REF_48_8_HP_DATA_labelID                       144
+#define ECHO_REF_DEC_labelID                                145
+#define VX_UL_8_TEMP_labelID                                146
+#define VX_UL_16_TEMP_labelID                               147
+#define UP_DOWN_8_48_labelID                                148
+#define UP_DOWN_16_48_labelID                               149
+#define SRC_6_LP_48k_labelID                                150
+#define SRC_6_HP_labelID                                    151
+#define SRC_3_LP_48k_labelID                                152
+#define SRC_3_HP_labelID                                    153
+#define EARP_48_96_LP_DATA_labelID                          154
+#define SRC_48_96_LP_labelID                                155
+#define IHF_48_96_LP_DATA_labelID                           156
+#define EQ_VX_UL_16K_labelID                                157
+#define pAPS_iir1_p23_labelID                               158
+#define pAPS_iir1_p45_labelID                               159
+#define APS_IIR_Regs_labelID                                160
+#define pAPS_core_DL1_p1_labelID                            161
+#define pAPS_core_DL1_p23_labelID                           162
+#define pAPS_core_DL1_p45_labelID                           163
+#define pAPS_core_DL1_r_labelID                             164
+#define pAPS_DL2L_core_r_labelID                            165
+#define pAPS_DL2R_core_r_labelID                            166
+#define pAPS_COIL_core_DL1_p1_labelID                       167
+#define pAPS_COIL_core_DL1_p23_labelID                      168
+#define pAPS_COIL_core_DL1_p45_labelID                      169
+#define pAPS_COIL_core_DL1_r_labelID                        170
+#define DL2_L_APS_IIR_p23_labelID                           171
+#define DL2_R_APS_IIR_p23_labelID                           172
+#define DL2_L_APS_IIR_p45_labelID                           173
+#define DL2_R_APS_IIR_p45_labelID                           174
+#define DL2_L_APS_CORE_p1_labelID                           175
+#define DL2_L_APS_CORE_p23_labelID                          176
+#define DL2_L_APS_CORE_p45_labelID                          177
+#define DL2_R_APS_CORE_p1_labelID                           178
+#define DL2_R_APS_CORE_p23_labelID                          179
+#define DL2_R_APS_CORE_p45_labelID                          180
+#define DL2_L_APS_COIL_CORE_p1_labelID                      181
+#define DL2_L_APS_COIL_CORE_p23_labelID                     182
+#define DL2_L_APS_COIL_CORE_p45_labelID                     183
+#define pAPS_COIL_DL2L_core_r_labelID                       184
+#define DL2_R_APS_COIL_CORE_p1_labelID                      185
+#define DL2_R_APS_COIL_CORE_p23_labelID                     186
+#define DL2_R_APS_COIL_CORE_p45_labelID                     187
+#define pAPS_COIL_DL2R_core_r_labelID                       188
+#define DL1_APS_labelID                                     189
+#define DL2_L_APS_labelID                                   190
+#define DL2_R_APS_labelID                                   191
+#define pEANC_p0_labelID                                    192
+#define pEANC_p1_labelID                                    193
+#define pEANC_p23_labelID                                   194
+#define pEANC_p45_labelID                                   195
+#define pEANC_reg1_labelID                                  196
+#define pEANC_reg2_labelID                                  197
+#define pEANC_reg3_labelID                                  198
+#define pEANC_r_labelID                                     199
+#define DL1_APS_EQ_p23_labelID                              200
+#define DL1_APS_EQ_p45_labelID                              201
+#define DL2_APS_EQ_p23_labelID                              202
+#define DL2_APS_EQ_p45_labelID                              203
+#define pDC_EANC_p23_labelID                                204
+#define pDC_EANC_r_labelID                                  205
+#define pVIBRA1_p0_labelID                                  206
+#define pVIBRA1_p1_labelID                                  207
+#define pVIBRA1_p23_labelID                                 208
+#define pVIBRA1_p45_labelID                                 209
+#define pVibra1_pR1_labelID                                 210
+#define pVibra1_pR2_labelID                                 211
+#define pVibra1_pR3_labelID                                 212
+#define pVIBRA1_r_labelID                                   213
+#define pVIBRA2_p0_labelID                                  214
+#define pVIBRA2_p1_labelID                                  215
+#define pVIBRA2_p23_labelID                                 216
+#define pVIBRA2_p45_labelID                                 217
+#define pCtrl_p67_labelID                                   218
+#define pVIBRA2_r_labelID                                   219
+#define VIBRA_labelID                                       220
+#define PING_labelID                                        221
+#define PING_Regs_labelID                                   222
+#define UP_48_96_LP_COEFS_labelID                           223
+#define AMIC_96_48_data_labelID                             224
+#define DOWN_96_48_AMIC_Coefs_labelID                       225
+#define DOWN_96_48_DMIC_Coefs_labelID                       226
+#define DOWN_96_48_AMIC_Regs_labelID                        227
+#define DOWN_96_48_DMIC_Regs_labelID                        228
+#define DMIC0_96_48_data_labelID                            229
+#define DMIC1_96_48_data_labelID                            230
+#define DMIC2_96_48_data_labelID                            231
+#define EANC_FBK_96_48_data_labelID                         232
+#define pDC_EANC_r2_labelID                                 233
+#define SIO_DMIC_labelID                                    234
+#define SIO_PDM_UL_labelID                                  235
+#define SIO_BT_VX_UL_labelID                                236
+#define SIO_MM_UL_labelID                                   237
+#define SIO_MM_UL2_labelID                                  238
+#define SIO_VX_UL_labelID                                   239
+#define SIO_MM_DL_labelID                                   240
+#define SIO_VX_DL_labelID                                   241
+#define SIO_TONES_DL_labelID                                242
+#define SIO_VIB_DL_labelID                                  243
+#define SIO_BT_VX_DL_labelID                                244
+#define SIO_PDM_DL_labelID                                  245
+#define SIO_MM_EXT_OUT_labelID                              246
+#define SIO_MM_EXT_IN_labelID                               247
+#define SIO_TDM_OUT_labelID                                 248
+#define SIO_TDM_IN_labelID                                  249
+#define DMIC_ATC_PTR_labelID                                250
+#define MCPDM_UL_ATC_PTR_labelID                            251
+#define BT_VX_UL_ATC_PTR_labelID                            252
+#define MM_UL_ATC_PTR_labelID                               253
+#define MM_UL2_ATC_PTR_labelID                              254
+#define VX_UL_ATC_PTR_labelID                               255
+#define MM_DL_ATC_PTR_labelID                               256
+#define VX_DL_ATC_PTR_labelID                               257
+#define TONES_DL_ATC_PTR_labelID                            258
+#define VIB_DL_ATC_PTR_labelID                              259
+#define BT_VX_DL_ATC_PTR_labelID                            260
+#define PDM_DL_ATC_PTR_labelID                              261
+#define MM_EXT_OUT_ATC_PTR_labelID                          262
+#define MM_EXT_IN_ATC_PTR_labelID                           263
+#define TDM_OUT_ATC_PTR_labelID                             264
+#define TDM_IN_ATC_PTR_labelID                              265
+#define MCU_IRQ_FIFO_ptr_labelID                            266
+#define DEBUG_IRQ_FIFO_reg_labelID                          267
+#define UP_DOWN_48_96_labelID                               268
+#define OSR96_2_labelID                                     269
+#define DEBUG_GAINS_labelID                                 270
+#define DBG_8K_PATTERN_labelID                              271
+#define DBG_16K_PATTERN_labelID                             272
+#define DBG_24K_PATTERN_labelID                             273
+#define DBG_48K_PATTERN_labelID                             274
+#define DBG_96K_PATTERN_labelID                             275
+#define UL_VX_UL_48_8K_labelID                              276
+#define UL_VX_UL_48_16K_labelID                             277
+#define BT_DL_labelID                                       278
+#define BT_UL_labelID                                       279
+#define BT_DL_8k_labelID                                    280
+#define BT_DL_16k_labelID                                   281
+#define BT_UL_8k_labelID                                    282
+#define BT_UL_16k_labelID                                   283
+#define MM_EXT_IN_labelID                                   284
+#define MM_EXT_IN_L_labelID                                 285
+#define MM_EXT_IN_R_labelID                                 286
+#define ECHO_REF_48_16_WRAP_labelID                         287
+#define ECHO_REF_48_8_WRAP_labelID                          288
+#define BT_UL_16_48_WRAP_labelID                            289
+#define BT_UL_8_48_WRAP_labelID                             290
+#define BT_DL_48_16_WRAP_labelID                            291
+#define BT_DL_48_8_WRAP_labelID                             292
+#define VX_DL_16_48_WRAP_labelID                            293
+#define VX_DL_8_48_WRAP_labelID                             294
+#define VX_UL_48_16_WRAP_labelID                            295
+#define VX_UL_48_8_WRAP_labelID                             296
+#define APS_DL1_IRQs_WRAP_labelID                           297
+#define APS_DL2_L_IRQs_WRAP_labelID                         298
+#define APS_DL2_R_IRQs_WRAP_labelID                         299
+#define ATC_NULL_BUFFER_labelID                             300
+#define MEM_INIT_hal_mem_labelID                            301
+#define MEM_INIT_write_mem_labelID                          302
+#define MEM_INIT_regs_labelID                               303
+#define GAIN_0DB_labelID                                    304
+#endif/* _ABE_INITXXXX_LABELS_H_ */
diff --git a/sound/soc/omap/abe/abe_irq.c b/sound/soc/omap/abe/abe_irq.c
index 1a8efa599e52..8e271cb55e52 100644
--- a/sound/soc/omap/abe/abe_irq.c
+++ b/sound/soc/omap/abe/abe_irq.c
@@ -18,9 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
 /*
  *  initialize the default values for call-backs to subroutines
  *      - FIFO IRQ call-backs for sequenced tasks
@@ -29,7 +27,6 @@
  *      - Error monitoring
  *      - Activity Tracing
  */
-
 /**
  * abe_irq_ping_pong
  *
@@ -38,12 +35,11 @@
  * SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], loopCounter to [15:0]
  * Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], loopCounter to [15:0]
  */
-void abe_irq_ping_pong (void)
+void abe_irq_ping_pong(void)
 {
-	abe_call_subroutine (abe_irq_pingpong_player_id, NOPARAMETER, NOPARAMETER,
-			     NOPARAMETER, NOPARAMETER);
+	abe_call_subroutine(abe_irq_pingpong_player_id, NOPARAMETER,
+			    NOPARAMETER, NOPARAMETER, NOPARAMETER);
 }
-
 /**
  * abe_irq_check_for_sequences
 * @i: sequence ID
@@ -51,17 +47,16 @@ void abe_irq_ping_pong (void)
  * check the active sequence list
  *
  */
-void abe_irq_check_for_sequences (u32 i)
+void abe_irq_check_for_sequences(u32 i)
 {
 }
-
 /**
  * abe_irq_aps
  *
  * call the application subroutines that updates the acoustics protection filters
  */
-void abe_irq_aps (u32 aps_info)
+void abe_irq_aps(u32 aps_info)
 {
-	abe_call_subroutine (abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER,
-			     NOPARAMETER, NOPARAMETER);
+	abe_call_subroutine(abe_irq_aps_adaptation_id, NOPARAMETER, NOPARAMETER,
+			    NOPARAMETER, NOPARAMETER);
 }
diff --git a/sound/soc/omap/abe/abe_lib.c b/sound/soc/omap/abe/abe_lib.c
index 4ad2cdbf9b92..fb1b1d8bb9ce 100644
--- a/sound/soc/omap/abe/abe_lib.c
+++ b/sound/soc/omap/abe/abe_lib.c
@@ -18,23 +18,29 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
-
 #include "abe_main.h"
-
-
 #if PC_SIMULATION
 #include <stdlib.h>
 #endif
-
 #define ABE_PMEM_BASE_OFFSET_MPU	0xe0000
 #define ABE_CMEM_BASE_OFFSET_MPU	0xa0000
 #define ABE_SMEM_BASE_OFFSET_MPU	0xc0000
 #define ABE_DMEM_BASE_OFFSET_MPU	0x80000
 #define ABE_ATC_BASE_OFFSET_MPU		0xf1000
-
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
 void __iomem *io_base;
-
 /**
  * abe_init_mem - Allocate Kernel space memory map for ABE
  *
@@ -44,14 +50,12 @@ void abe_init_mem(void __iomem *_io_base)
 {
 	io_base = _io_base;
 }
-
 /**
 * abe_fprintf
 * @line: character line to be printed
 *
 * Print ABE debug messages.
 */
-
 /**
  * abe_read_feature_from_port
  * @x: d
@@ -62,7 +66,6 @@ void abe_init_mem(void __iomem *_io_base)
 void abe_read_feature_from_port(u32 x)
 {
 }
-
 /**
  * abe_write_feature_to_port
  * @x: d
@@ -73,7 +76,6 @@ void abe_read_feature_from_port(u32 x)
 void abe_write_feature_to_port(u32 x)
 {
 }
-
 /**
  * abe_read_fifo
  * @x: d
@@ -83,7 +85,6 @@ void abe_write_feature_to_port(u32 x)
 void abe_read_fifo(u32 x)
 {
 }
-
 /**
  * abe_write_fifo
  * @mem_bank: currently only ABE_DMEM supported
@@ -99,26 +100,21 @@ void abe_write_fifo(u32 memory_bank, u32 descr_addr, u32 *data, u32 nb_data32)
 {
 	u32 fifo_addr[4];
 	u32 i;
-
 	/* read FIFO descriptor from DMEM */
 	abe_block_copy(COPY_FROM_ABE_TO_HOST, ABE_DMEM, descr_addr,
 		       &fifo_addr[0], 4 * sizeof(u32));
-
 	/* WRITE ptr < FIFO start address */
 	if (fifo_addr[1] < fifo_addr[2])
 		abe_dbg_error_log(ABE_FW_FIFO_WRITE_PTR_ERR);
-
 	/* WRITE ptr > FIFO end address */
 	if (fifo_addr[1] > fifo_addr[3])
 		abe_dbg_error_log(ABE_FW_FIFO_WRITE_PTR_ERR);
-
 	switch (memory_bank) {
 	case ABE_DMEM:
 		for (i = 0; i < nb_data32; i++) {
 			abe_block_copy(COPY_FROM_HOST_TO_ABE, ABE_DMEM,
 				       (s32) fifo_addr[1], (u32 *) (data + i),
 				       4);
-
 			/* increment WRITE pointer */
 			fifo_addr[1] = fifo_addr[1] + 4;
 			if (fifo_addr[1] > fifo_addr[3])
@@ -134,10 +130,7 @@ void abe_write_fifo(u32 memory_bank, u32 descr_addr, u32 *data, u32 nb_data32)
 		/* printf("currently only DMEM FIFO write supported ERROR\n"); */
 		break;
 	}
-
-
 }
-
 /**
  * abe_block_copy
  * @direction: direction of the data move (Read/Write)
@@ -153,7 +146,6 @@ void abe_block_copy(u32 direction, u32 memory_bank, u32 address,
 {
 	u32 i;
 	u32 base_address = 0, *src_ptr, *dst_ptr, n;
-
 	switch (memory_bank) {
 	case ABE_PMEM:
 		base_address = (u32) io_base + ABE_PMEM_BASE_OFFSET_MPU;
@@ -176,7 +168,6 @@ void abe_block_copy(u32 direction, u32 memory_bank, u32 address,
 		abe_dbg_error_log(ABE_BLOCK_COPY_ERR);
 		break;
 	}
-
 	if (direction == COPY_FROM_HOST_TO_ABE) {
 		dst_ptr = (u32 *) (base_address + address);
 		src_ptr = (u32 *) data;
@@ -184,15 +175,10 @@ void abe_block_copy(u32 direction, u32 memory_bank, u32 address,
 		dst_ptr = (u32 *) data;
 		src_ptr = (u32 *) (base_address + address);
 	}
-
 	n = (nb_bytes / 4);
-
 	for (i = 0; i < n; i++)
 		*dst_ptr++ = *src_ptr++;
-
 }
-
-
 #if 0
 /*
  * ABE_SINGLE_COPY
@@ -208,15 +194,14 @@ void abe_block_copy(u32 direction, u32 memory_bank, u32 address,
  * Return value :
  * none
  */
-
 void abe_write_dmem(u32 address, u32 *data, u32 nb_bytes)
-void abe_read_dmem(u32 address, u32 *data, u32 nb_bytes)
-void abe_write_cmem(u32 address, u32 *data, u32 nb_bytes)
-void abe_read_cmem(u32 address, u32 *data, u32 nb_bytes)
-void abe_write_smem(u32 address, u32 *data, u32 nb_bytes)
-void abe_read_smem(u32 address, u32 *data, u32 nb_bytes)
-void abe_write_atc(u32 address, u32 *data, u32 nb_bytes)
-void abe_read_atc(u32 address, u32 *data, u32 nb_bytes)
+     void abe_read_dmem(u32 address, u32 *data, u32 nb_bytes)
+     void abe_write_cmem(u32 address, u32 *data, u32 nb_bytes)
+     void abe_read_cmem(u32 address, u32 *data, u32 nb_bytes)
+     void abe_write_smem(u32 address, u32 *data, u32 nb_bytes)
+     void abe_read_smem(u32 address, u32 *data, u32 nb_bytes)
+     void abe_write_atc(u32 address, u32 *data, u32 nb_bytes)
+     void abe_read_atc(u32 address, u32 *data, u32 nb_bytes)
 #endif
 /**
  * abe_reset_mem
@@ -227,12 +212,11 @@ void abe_read_atc(u32 address, u32 *data, u32 nb_bytes)
  *
  * Reset ABE memory
  */
-void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes)
+     void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes)
 {
 	u32 i;
 	u32 *dst_ptr, n;
 	u32 base_address = 0;
-
 	switch (memory_bank) {
 	case ABE_SMEM:
 		base_address = (u32) io_base + ABE_SMEM_BASE_OFFSET_MPU;
@@ -244,15 +228,11 @@ void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes)
 		base_address = (u32) io_base + ABE_CMEM_BASE_OFFSET_MPU;
 		break;
 	}
-
 	dst_ptr = (u32 *) (base_address + address);
-
 	n = (nb_bytes / 4);
-
 	for (i = 0; i < n; i++)
 		*dst_ptr++ = 0;
 }
-
 /**
  * abe_monitoring
  *
@@ -262,7 +242,6 @@ void abe_monitoring(void)
 {
 	abe_dbg_param = 0;
 }
-
 /**
  * abe_format_switch
  * @f: port format
@@ -276,10 +255,8 @@ void abe_monitoring(void)
 void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac)
 {
 	u32 n_freq;
-
 #if FW_SCHED_LOOP_FREQ==4000
 	switch (f->f) {
-
 		/* nb of samples processed by scheduling loop */
 	case 8000:
 		n_freq = 2;
@@ -296,7 +273,7 @@ void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac)
 	case 96000:
 		n_freq = 24;
 		break;
-	default /* case 48000 */ :
+	default/*case 48000 */ :
 		n_freq = 12;
 		break;
 	}
@@ -341,7 +318,6 @@ void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac)
 	}
 	*iter = (n_freq * (*mulfac));
 }
-
 /**
  * abe_dma_port_iteration
  * @f: port format
@@ -351,12 +327,9 @@ void abe_format_switch(abe_data_format_t *f, u32 *iter, u32 *mulfac)
 u32 abe_dma_port_iteration(abe_data_format_t *f)
 {
 	u32 iter, mulfac;
-
 	abe_format_switch(f, &iter, &mulfac);
-
 	return iter;
 }
-
 /**
  * abe_dma_port_iter_factor
  * @f: port format
@@ -366,12 +339,9 @@ u32 abe_dma_port_iteration(abe_data_format_t *f)
 u32 abe_dma_port_iter_factor(abe_data_format_t *f)
 {
 	u32 iter, mulfac;
-
 	abe_format_switch(f, &iter, &mulfac);
-
 	return mulfac;
 }
-
 /**
  * abe_dma_port_copy_subroutine_id
  *
@@ -382,7 +352,6 @@ u32 abe_dma_port_iter_factor(abe_data_format_t *f)
 u32 abe_dma_port_copy_subroutine_id(u32 port_id)
 {
 	u32 sub_id;
-
 	if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) {
 		switch (abe_port[port_id].format.samp_format) {
 		case MONO_MSB:
@@ -450,3 +419,107 @@ u32 abe_dma_port_copy_subroutine_id(u32 port_id)
 	}
 	return sub_id;
 }
+/**
+ * abe_int_2_float
+ * returns a mantissa on 16 bits and the exponent
+ * 0x4000.0000 leads to M=0x4000 X=15
+ * 0x0004.0000 leads to M=0x4000 X=4
+ * 0x0000.0001 leads to M=0x4000 X=-14
+ *
+ */
+void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp)
+{
+	u32 i;
+	*exp = 0;
+	*mantissa = 0;
+	for (i = 0; i < 32; i++) {
+		if ((1 << i) > data)
+			break;
+	}
+	*exp = i - 15;
+	*mantissa = (*exp > 0) ? data >> (*exp) : data << (*exp);
+}
+/**
+ * abe_gain_offset
+ * returns the offset to firmware data structures
+ *
+ */
+void abe_gain_offset(u32 id, u32 *mixer_offset)
+{
+	switch (id) {
+	default:
+	case GAINS_DMIC1:
+		*mixer_offset = dmic1_gains_offset;
+		break;
+	case GAINS_DMIC2:
+		*mixer_offset = dmic2_gains_offset;
+		break;
+	case GAINS_DMIC3:
+		*mixer_offset = dmic3_gains_offset;
+		break;
+	case GAINS_AMIC:
+		*mixer_offset = amic_gains_offset;
+		break;
+	case GAINS_DL1:
+		*mixer_offset = dl1_gains_offset;
+		break;
+	case GAINS_DL2:
+		*mixer_offset = dl2_gains_offset;
+		break;
+	case GAINS_SPLIT:
+		*mixer_offset = splitters_gains_offset;
+		break;
+	case MIXDL1:
+		*mixer_offset = mixer_dl1_offset;
+		break;
+	case MIXDL2:
+		*mixer_offset = mixer_dl2_offset;
+		break;
+	case MIXECHO:
+		*mixer_offset = mixer_echo_offset;
+		break;
+	case MIXSDT:
+		*mixer_offset = mixer_sdt_offset;
+		break;
+	case MIXVXREC:
+		*mixer_offset = mixer_vxrec_offset;
+		break;
+	case MIXAUDUL:
+		*mixer_offset = mixer_audul_offset;
+		break;
+	}
+}
+/**
+ * abe_decide_main_port - Select stynchronization port for Event generator.
+ * @id: audio port name
+ *
+ * tells the FW which is the reference stream for adjusting
+ * the processing on 23/24/25 slots
+ *
+ * takes the first port in a list which is slave on the data interface
+ */
+u32 abe_valid_port_for_synchro(u32 id)
+{
+	if ((abe_port[id].protocol.protocol_switch ==
+	     DMAREQ_PORT_PROT) ||
+	    (abe_port[id].protocol.protocol_switch ==
+	     PINGPONG_PORT_PROT) ||
+	    (abe_port[id].status != OMAP_ABE_PORT_ACTIVITY_RUNNING))
+		return 0;
+	else
+		return 1;
+}
+void abe_decide_main_port(u32 id)
+{
+	u32 i;
+	if (abe_valid_port_for_synchro(id)) {
+		for (i = 0; i < (LAST_PORT_ID - 1); i++) {
+			printk("Port (%d,%d) %d\n", i, abe_port_priority[i],
+			       abe_port[abe_port_priority[i]].status);
+			if (abe_port[abe_port_priority[i]].status ==
+			    OMAP_ABE_PORT_ACTIVITY_RUNNING)
+				break;
+		}
+		abe_select_main_port(abe_port_priority[i]);
+	}
+}
diff --git a/sound/soc/omap/abe/abe_lib.h b/sound/soc/omap/abe/abe_lib.h
index 6f80fd28f39b..d9154a16ae16 100644
--- a/sound/soc/omap/abe/abe_lib.h
+++ b/sound/soc/omap/abe/abe_lib.h
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 /**
  * abe_fprintf
 	 *
@@ -30,8 +29,7 @@
 	 *  Return value :
 	 *      None.
 	 */
-void abe_fprintf (char *line);
-
+void abe_fprintf(char *line);
 /*
  *  ABE_READ_FEATURE_FROM_PORT
  *
@@ -44,8 +42,7 @@ void abe_fprintf (char *line);
  *  Return value :
  *
  */
-void    abe_read_feature_from_port (u32 x);
-
+void abe_read_feature_from_port(u32 x);
 /*
  *  ABE_WRITE_FEATURE_TO_PORT
  *
@@ -58,8 +55,7 @@ void    abe_read_feature_from_port (u32 x);
  *  Return value :
  *
  */
-void    abe_write_feature_to_port (u32 x);
-
+void abe_write_feature_to_port(u32 x);
 /*
  *  ABE_READ_FIFO
  *
@@ -72,8 +68,7 @@ void    abe_write_feature_to_port (u32 x);
  *  Return value :
  *
  */
-void    abe_read_fifo (u32 x);
-
+void abe_read_fifo(u32 x);
 /*
  *  ABE_WRITE_FIFO
  *
@@ -91,9 +86,7 @@ void    abe_read_fifo (u32 x);
  *  Return value :
  *      none
  */
-void    abe_write_fifo (u32 mem_bank, u32 addr, u32 *data, u32 nb_data32);
-
-
+void abe_write_fifo(u32 mem_bank, u32 addr, u32 *data, u32 nb_data32);
 /*
  *  ABE_BLOCK_COPY
  *
@@ -110,9 +103,8 @@ void    abe_write_fifo (u32 mem_bank, u32 addr, u32 *data, u32 nb_data32);
  *  Return value :
  *      none
  */
-void abe_block_copy  (u32 direction, u32 memory_bank, u32 address, u32 *data,
-		      u32 nb);
-
+void abe_block_copy(u32 direction, u32 memory_bank, u32 address, u32 *data,
+		    u32 nb);
 /*
  *  ABE_RESET_MEM
  *
@@ -127,6 +119,4 @@ void abe_block_copy  (u32 direction, u32 memory_bank, u32 address, u32 *data,
  *  Return value :
  *      none
  */
-void  abe_reset_mem  (u32 memory_bank, u32 address, u32 nb_bytes);
-
-
+void abe_reset_mem(u32 memory_bank, u32 address, u32 nb_bytes);
diff --git a/sound/soc/omap/abe/abe_main.h b/sound/soc/omap/abe/abe_main.h
index 690ff3cd16b1..9b547aeed288 100644
--- a/sound/soc/omap/abe/abe_main.h
+++ b/sound/soc/omap/abe/abe_main.h
@@ -18,16 +18,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #ifndef _ABE_MAIN_H_
 #define _ABE_MAIN_H_
-
 #include <linux/io.h>
-
 #include "abe_dm_addr.h"
 #include "abe_sm_addr.h"
 #include "abe_cm_addr.h"
-
 #include "abe_def.h"
 #include "abe_typ.h"
 #include "abe_ext.h"
@@ -35,26 +31,17 @@
 #include "abe_lib.h"
 #include "abe_ref.h"
 #include "abe_api.h"
-
-
-
 #include "abe_typedef.h"
 #include "abe_functionsid.h"
 #include "abe_taskid.h"
 #include "abe_initxxx_labels.h"
-
 #include "abe_fw.h"
-
 /* pipe connection to the TARGET simulator */
-#define ABE_DEBUG_CHECKERS              0       
-
+#define ABE_DEBUG_CHECKERS              0
 /* simulator data extracted from a text-file */
-#define ABE_DEBUG_HWFILE                0       
-
+#define ABE_DEBUG_HWFILE                0
 /* low-level log files */
-#define ABE_DEBUG_LL_LOG                0       
-
+#define ABE_DEBUG_LL_LOG                0
 #define ABE_DEBUG (ABE_DEBUG_CHECKERS | ABE_DEBUG_HWFILE | ABE_DEBUG_LL_LOG)
-
-
-#endif /* _ABE_MAIN_H_ */
+extern void abe_init_mem(void __iomem *_io_base);
+#endif/* _ABE_MAIN_H_ */
diff --git a/sound/soc/omap/abe/abe_ref.h b/sound/soc/omap/abe/abe_ref.h
index c215750e8a01..b0b58a56848a 100644
--- a/sound/soc/omap/abe/abe_ref.h
+++ b/sound/soc/omap/abe/abe_ref.h
@@ -20,143 +20,126 @@
  */
 #ifndef _ABE_REF_H_
 #define _ABE_REF_H_
-
 /*
  * 'ABE_PRO.H' all non-API prototypes for INI, IRQ, SEQ ...
  */
-
 /*
- * HAL EXTERNAL API
+ * HAL EXTERNAL AP
  */
-
 /*
- * HAL INTERNAL API
+ * HAL INTERNAL AP
  */
-void abe_load_embeddded_patterns (void);
-void abe_build_scheduler_table (void);
-void abe_reset_one_feature (u32 x);
-void abe_reset_all_features (void);
-void abe_reset_all_ports (void);
-void abe_reset_all_fifo (void);
-void abe_reset_all_sequence (void);
-u32 abe_dma_port_iteration (abe_data_format_t *format);
-void abe_read_sys_clock (u32 *time);
-void abe_enable_dma_request (u32 id);
-void abe_disable_dma_request (u32 id);
-void abe_enable_atc (u32 id);
-void abe_disable_atc (u32 id);
-void abe_init_atc (u32 id);
-void abe_init_io_tasks (u32 id, abe_data_format_t *format,
-			abe_port_protocol_t *prot);
-void abe_init_dma_t (u32 id, abe_port_protocol_t *prot);
-u32 abe_dma_port_iter_factor (abe_data_format_t *f);
-u32 abe_dma_port_copy_subroutine_id (u32 i);
-void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4);
-void abe_monitoring (void);
-void abe_lock_execution (void);
-void abe_unlock_execution (void);
-void abe_hw_configuration (void);
-void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam,
-			 u32* params);
-abehal_status abe_read_next_ping_pong_buffer (u32 port, u32 *p, u32 *n);
-void abe_irq_ping_pong (void);
-void abe_irq_check_for_sequences (u32 seq_info);
+void abe_decide_main_port(u32 id);
+void abe_gain_offset(u32 id, u32 *mixer_offset);
+void abe_int_2_float16(u32 data, u32 *mantissa, u32 *exp);
+void abe_reset_gain_mixer(u32 id, u32 p);
+void abe_load_embeddded_patterns(void);
+void abe_build_scheduler_table(void);
+void abe_reset_one_feature(u32 x);
+void abe_reset_all_features(void);
+void abe_reset_all_ports(void);
+void abe_reset_all_fifo(void);
+void abe_reset_all_sequence(void);
+u32 abe_dma_port_iteration(abe_data_format_t *format);
+void abe_read_sys_clock(u32 *time);
+void abe_enable_dma_request(u32 id);
+void abe_disable_dma_request(u32 id);
+void abe_enable_atc(u32 id);
+void abe_disable_atc(u32 id);
+void abe_init_atc(u32 id);
+void abe_init_io_tasks(u32 id, abe_data_format_t *format,
+		       abe_port_protocol_t *prot);
+void abe_init_dma_t(u32 id, abe_port_protocol_t *prot);
+u32 abe_dma_port_iter_factor(abe_data_format_t *f);
+u32 abe_dma_port_copy_subroutine_id(u32 i);
+void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4);
+void abe_monitoring(void);
+void abe_lock_execution(void);
+void abe_unlock_execution(void);
+void abe_hw_configuration(void);
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params);
+abehal_status abe_read_next_ping_pong_buffer(u32 port, u32 *p, u32 *n);
+void abe_irq_ping_pong(void);
+void abe_irq_check_for_sequences(u32 seq_info);
 void abe_default_irq_pingpong_player(void);
 void abe_default_irq_pingpong_player_32bits(void);
 void abe_default_irq_aps_adaptation(void);
-void abe_irq_aps (u32 aps_info);
-void abe_clean_temporary_buffers (u32 id);
-void abe_dbg_log (u32 x, u32 y, u32 z, u32 t);
-void abe_dbg_error_log (u32 x);
-void abe_init_asrc_vx_dl ( s32 dppm);
-void abe_init_asrc_vx_ul ( s32 dppm);
-void abe_init_asrc_mm_dl ( s32 dppm);
+void abe_irq_aps(u32 aps_info);
+void abe_clean_temporary_buffers(u32 id);
+void abe_dbg_log(u32 x, u32 y, u32 z, u32 t);
+void abe_dbg_error_log(u32 x);
+void abe_init_asrc_vx_dl(s32 dppm);
+void abe_init_asrc_vx_ul(s32 dppm);
+void abe_init_asrc_mm_ext_in(s32 dppm);
 //u8 *memmove(u8 *dst, u8 *src, u32 n);
 //u32 __get_unaligned_memmove32(void *p);
 //void __put_unaligned_memmove32(u32 val, void *p);
-
 /*
  * HAL INTERNAL DATA
  */
+extern const u32 abe_port_priority[LAST_PORT_ID - 1];
+extern u32 abe_compensated_mixer_gain;
+extern u8 abe_muted_gains_indicator[MAX_NBGAIN_CMEM];
+extern u32 abe_unmuted_desired_gains[MAX_NBGAIN_CMEM];
+extern u32 abe_unmuted_compensated_gains[MAX_NBGAIN_CMEM];
+extern u32 pdm_dl1_status;
+extern u32 pdm_dl2_status;
+extern u32 pdm_vib_status;
 extern const u32 abe_firmware_array[ABE_FIRMWARE_MAX_SIZE];
 extern u32 abe_firmware_version_number;
-extern const u32 abe_atc_srcid [];
-extern const u32 abe_atc_dstid [];
+extern const u32 abe_atc_srcid[];
+extern const u32 abe_atc_dstid[];
 extern abe_port_t abe_port[];
-extern abe_feature_t feature [];
-
-extern const abe_port_t abe_port_init [];
-
-extern abe_feature_t all_feature [];
-extern const abe_feature_t all_feature_init [];
-
-extern abe_seq_t all_sequence [];
+extern abe_feature_t feature[];
+extern const abe_port_t abe_port_init[];
+extern abe_feature_t all_feature[];
+extern const abe_feature_t all_feature_init[];
+extern abe_seq_t all_sequence[];
 extern const abe_seq_t all_sequence_init[];
-
 extern const abe_router_t abe_router_ul_table_preset
-[NBROUTE_CONFIG][NBROUTE_UL];
-extern abe_router_t abe_router_ul_table [NBROUTE_CONFIG_MAX][NBROUTE_UL];
-
+	[NBROUTE_CONFIG][NBROUTE_UL];
+extern abe_router_t abe_router_ul_table[NBROUTE_CONFIG_MAX][NBROUTE_UL];
 extern u32 abe_dbg_output;
 extern u32 abe_dbg_mask;
-extern u32 abe_dbg_activity_log [D_DEBUG_HAL_TASK_sizeof];
+extern u32 abe_dbg_activity_log[D_DEBUG_HAL_TASK_sizeof];
 extern u32 abe_dbg_activity_log_write_pointer;
 extern u32 abe_dbg_param;
-
-extern u32  abe_current_event_id;
-
+extern u32 abe_current_event_id;
 extern const abe_sequence_t seq_null;
-
 /* table of new subroutines called in the sequence */
-extern abe_subroutine2 abe_all_subsubroutine [MAXNBSUBROUTINE];
-
+extern abe_subroutine2 abe_all_subsubroutine[MAXNBSUBROUTINE];
 /* number of parameters per calls */
-extern u32 abe_all_subsubroutine_nparam [MAXNBSUBROUTINE];
-extern u32 abe_subroutine_id [MAXNBSUBROUTINE];
-extern u32* abe_all_subroutine_params[MAXNBSUBROUTINE];
+extern u32 abe_all_subsubroutine_nparam[MAXNBSUBROUTINE];
+extern u32 abe_subroutine_id[MAXNBSUBROUTINE];
+extern u32 *abe_all_subroutine_params[MAXNBSUBROUTINE];
 extern u32 abe_subroutine_write_pointer;
-
-
 extern abe_sequence_t abe_all_sequence[MAXNBSEQUENCE];
 extern u32 abe_sequence_write_pointer;
-
 /* current number of pending sequences (avoids to look in the table) */
 extern u32 abe_nb_pending_sequences;
-
 /* pending sequences due to ressource collision */
-extern u32 abe_pending_sequences [MAXNBSEQUENCE];
-
+extern u32 abe_pending_sequences[MAXNBSEQUENCE];
 /* mask of unsharable ressources among other sequences */
 extern u32 abe_global_sequence_mask;
-
 /* table of active sequences */
-extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE] [MAXSEQUENCESTEPS];
-
+extern abe_seq_t abe_active_sequence[MAXACTIVESEQUENCE][MAXSEQUENCESTEPS];
 /* index of the plugged subroutine doing ping-pong cache-flush
 	DMEM accesses */
 extern u32 abe_irq_pingpong_player_id;
 extern u32 abe_irq_aps_adaptation_id;
-
 /* base addresses of the ping pong buffers */
-extern u32 abe_base_address_pingpong [MAX_PINGPONG_BUFFERS];
-
+extern u32 abe_base_address_pingpong[MAX_PINGPONG_BUFFERS];
 /* size of each ping/pong buffers */
 extern u32 abe_size_pingpong;
-
 /* number of ping/pong buffer being used */
 extern u32 abe_nb_pingpong;
-
 /* circular read pointer to IRQ/DBG DMEM buffer */
 extern u32 abe_irq_dbg_read_ptr;
-
-extern const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof];
+/* extern const s32 abe_dmic_40 [C_98_48_LP_Coefs_sizeof];
 extern const s32 abe_dmic_32 [C_98_48_LP_Coefs_sizeof];
 extern const s32 abe_dmic_25 [C_98_48_LP_Coefs_sizeof];
-extern const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof];
-
-extern const u32 abe_db2lin_table [];
-extern const u32 abe_alpha_iir [64];
-extern const u32 abe_1_alpha_iir [64];
-
-
-#endif	/* _ABE_REF_H_ */
+extern const s32 abe_dmic_16 [C_98_48_LP_Coefs_sizeof]; */
+extern const u32 abe_db2lin_table[];
+extern const u32 abe_alpha_iir[64];
+extern const u32 abe_1_alpha_iir[64];
+#endif/* _ABE_REF_H_ */
diff --git a/sound/soc/omap/abe/abe_seq.c b/sound/soc/omap/abe/abe_seq.c
index 9f7e1e96fcdb..48ce31a38b7a 100644
--- a/sound/soc/omap/abe/abe_seq.c
+++ b/sound/soc/omap/abe/abe_seq.c
@@ -18,51 +18,47 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_main.h"
-
-
 /**
  * abe_null_subroutine
  *
  */
-void abe_null_subroutine_0 (void) { }
-void abe_null_subroutine_2 (u32 a, u32 b)
+void abe_null_subroutine_0(void)
 {
 }
-void abe_null_subroutine_4 (u32 a, u32 b, u32 c, u32 d)
+void abe_null_subroutine_2(u32 a, u32 b)
+{
+}
+void abe_null_subroutine_4(u32 a, u32 b, u32 c, u32 d)
 {
 }
-
 /**
- * abe_init_subroutine_table - initializes the default table of pointers 
+ * abe_init_subroutine_table - initializes the default table of pointers
  * to subroutines
  *
  * initializes the default table of pointers to subroutines
  *
  */
-void abe_init_subroutine_table (void)
+void abe_init_subroutine_table(void)
 {
 	u32 id;
-
 	/* reset the table's pointers */
 	abe_subroutine_write_pointer = 0;
-	
 	/* the first index is the NULL task */
-	abe_add_subroutine(&id,(abe_subroutine2) abe_null_subroutine_2, 
-		SUB_0_PARAM, (u32*)0);
-	
+	abe_add_subroutine(&id, (abe_subroutine2) abe_null_subroutine_2,
+			   SUB_0_PARAM, (u32 *) 0);
 	/* write mixer has 4 parameters */
-	abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]), 
-		(abe_subroutine2) abe_write_mixer, SUB_4_PARAM, (u32*)0);
-	
+	abe_add_subroutine(&(abe_subroutine_id[SUB_WRITE_MIXER]),
+			   (abe_subroutine2) abe_write_mixer, SUB_4_PARAM,
+			   (u32 *) 0);
 	/* ping-pong player IRQ */
 	abe_add_subroutine(&abe_irq_pingpong_player_id,
-		(abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM, (u32*)0);
-	abe_add_subroutine (&abe_irq_aps_adaptation_id,		   
-		(abe_subroutine2) abe_default_irq_aps_adaptation, SUB_0_PARAM, (u32*)0);
+			   (abe_subroutine2) abe_null_subroutine_0, SUB_0_PARAM,
+			   (u32 *) 0);
+	abe_add_subroutine(&abe_irq_aps_adaptation_id,
+			   (abe_subroutine2) abe_default_irq_aps_adaptation,
+			   SUB_0_PARAM, (u32 *) 0);
 }
-
 /**
  * abe_add_subroutine
  * @id: ABE port id
@@ -72,31 +68,28 @@ void abe_init_subroutine_table (void)
  *
  * add one function pointer more and returns the index to it
  */
-void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam, u32* params)
+void abe_add_subroutine(u32 *id, abe_subroutine2 f, u32 nparam, u32 *params)
 {
 	u32 i, i_found;
-
-	if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE)  ||  
-		((u32)f == 0)) {
+	if ((abe_subroutine_write_pointer >= MAXNBSUBROUTINE) || ((u32) f == 0)) {
 		abe_dbg_param |= ERR_SEQ;
-		abe_dbg_error_log (ABE_PARAMETER_OVERFLOW);
+		abe_dbg_error_log(ABE_PARAMETER_OVERFLOW);
 	} else {
 		/* search if this subroutine address was not already
 		 * declared, then return the previous index
 		 */
-		for (i_found = abe_subroutine_write_pointer, i = 0; 
-			i < abe_subroutine_write_pointer; i++) {
+		for (i_found = abe_subroutine_write_pointer, i = 0;
+		     i < abe_subroutine_write_pointer; i++) {
 			if (f == abe_all_subsubroutine[i])
 				i_found = i;
 		}
-
 		if (i_found == abe_subroutine_write_pointer) {
 			*id = abe_subroutine_write_pointer;
-			abe_all_subsubroutine 
+			abe_all_subsubroutine
 				[abe_subroutine_write_pointer] = (f);
 			abe_all_subroutine_params
 				[abe_subroutine_write_pointer] = params;
-			abe_all_subsubroutine_nparam 
+			abe_all_subsubroutine_nparam
 				[abe_subroutine_write_pointer] = nparam;
 			abe_subroutine_write_pointer++;
 		} else {
@@ -105,7 +98,6 @@ void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam, u32* params)
 		}
 	}
 }
-
 /**
  * abe_add_sequence
  * @id: returned sequence index after pluging a new sequence (index in the tables)
@@ -113,43 +105,35 @@ void abe_add_subroutine (u32 *id, abe_subroutine2 f, u32 nparam, u32* params)
  *
  * Load a time-sequenced operations.
  */
-void abe_add_sequence (u32 *id, abe_sequence_t *s)
+void abe_add_sequence(u32 *id, abe_sequence_t *s)
 {
 	abe_seq_t *seq_src, *seq_dst;
 	u32 i, no_end_of_sequence_found;
-
 	seq_src = &(s->seq1);
-	seq_dst = &((abe_all_sequence [abe_sequence_write_pointer]).seq1);
-
-	if ((abe_sequence_write_pointer >= MAXNBSEQUENCE)  ||  ((u32)s == 0)) {
+	seq_dst = &((abe_all_sequence[abe_sequence_write_pointer]).seq1);
+	if ((abe_sequence_write_pointer >= MAXNBSEQUENCE) || ((u32) s == 0)) {
 		abe_dbg_param |= ERR_SEQ;
-		abe_dbg_error_log (ABE_PARAMETER_OVERFLOW);
+		abe_dbg_error_log(ABE_PARAMETER_OVERFLOW);
 	} else {
 		*id = abe_subroutine_write_pointer;
-		
 		/* copy the mask */
-		(abe_all_sequence [abe_sequence_write_pointer]).mask = s->mask;              
-
-		for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS; 
-			i++, seq_src++, seq_dst++) {
-			
+		(abe_all_sequence[abe_sequence_write_pointer]).mask = s->mask;
+		for (no_end_of_sequence_found = 1, i = 0; i < MAXSEQUENCESTEPS;
+		     i++, seq_src++, seq_dst++) {
 			/* sequence copied line by line */
-			(*seq_dst) = (*seq_src);                                                
-
+			(*seq_dst) = (*seq_src);
 			/* stop when the line start with time=(-1) */
-			if ((*(s32 *)seq_src) == (-1)) {                                  
+			if ((*(s32 *) seq_src) == (-1)) {
 				/* stop when the line start with time=(-1) */
 				no_end_of_sequence_found = 0;
 				break;
 			}
 		}
 		abe_subroutine_write_pointer++;
-
 		if (no_end_of_sequence_found)
-			abe_dbg_error_log (ABE_SEQTOOLONG);
+			abe_dbg_error_log(ABE_SEQTOOLONG);
 	}
 }
-
 /**
  * abe_reset_one_sequence
  * @id: sequence ID
@@ -157,92 +141,84 @@ void abe_add_sequence (u32 *id, abe_sequence_t *s)
  * load default configuration for that sequence
  * kill running activities
  */
-void abe_reset_one_sequence (u32 id)
+void abe_reset_one_sequence(u32 id)
 {
 }
-
 /**
  * abe_reset_all_sequence
  *
  * load default configuration for all sequences
  * kill any running activities
  */
-void abe_reset_all_sequence (void)
+void abe_reset_all_sequence(void)
 {
 	u32 i;
-
-	abe_init_subroutine_table ();
-
-	/* arrange to have the first sequence index=0 to the NULL operation 
-		sequence */
-	abe_add_sequence (&i, (abe_sequence_t *)&seq_null);
-
+	abe_init_subroutine_table();
+	/* arrange to have the first sequence index=0 to the NULL operation
+	   sequence */
+	abe_add_sequence(&i, (abe_sequence_t *) &seq_null);
 	/* reset the the collision protection mask */
 	abe_global_sequence_mask = 0;
-
 	/* reset the pending sequences list */
 	for (abe_nb_pending_sequences = i = 0; i < MAXNBSEQUENCE; i++)
-		abe_pending_sequences [i] = 0;
+		abe_pending_sequences[i] = 0;
 }
-
 /**
  * abe_call_subroutine
  * @idx: index to the table of all registered Call-backs and subroutines
  *
  * run and log a subroutine
  */
-void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
+void abe_call_subroutine(u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
 {
 	abe_subroutine0 f0;
 	abe_subroutine1 f1;
 	abe_subroutine2 f2;
 	abe_subroutine3 f3;
 	abe_subroutine4 f4;
-	u32* params;
-
+	u32 *params;
 	if (idx > MAXNBSUBROUTINE)
-	return;
-
+		return;
 	switch (idx) {
-		/* call the subroutines defined at compilation time 
-			(const .. sequences) */
+		/* call the subroutines defined at compilation time
+		   (const .. sequences) */
 #if 0
-	case SUB_WRITE_MIXER_DL1 :
-		                abe_write_mixer_dl1 (p1, p2, p3)
-		                abe_fprintf ("write_mixer");
-		                break;
+	case SUB_WRITE_MIXER_DL1:
+		abe_write_mixer_dl1(p1, p2, p3)
+			abe_fprintf("write_mixer");
+		break;
 #endif
-		/* call the subroutines defined at execution time 
-			(dynamic sequences) */
-	default :
-		switch (abe_all_subsubroutine_nparam [idx]) {
+		/* call the subroutines defined at execution time
+		   (dynamic sequences) */
+	default:
+		switch (abe_all_subsubroutine_nparam[idx]) {
 		case SUB_0_PARAM:
-			f0 = (abe_subroutine0) abe_all_subsubroutine [idx];
+			f0 = (abe_subroutine0) abe_all_subsubroutine[idx];
 			(*f0) ();
 			break;
 		case SUB_1_PARAM:
-			f1 = (abe_subroutine1) abe_all_subsubroutine [idx];
+			f1 = (abe_subroutine1) abe_all_subsubroutine[idx];
 			params = abe_all_subroutine_params
 				[abe_irq_pingpong_player_id];
-			if (params != (u32*)0)
+			if (params != (u32 *) 0)
 				p1 = params[0];
 			(*f1) (p1);
 			break;
 		case SUB_2_PARAM:
-			f2 =                   abe_all_subsubroutine [idx];
+			f2 = abe_all_subsubroutine[idx];
 			params = abe_all_subroutine_params
 				[abe_irq_pingpong_player_id];
-			if (params != (u32*)0) {
+			if (params != (u32 *) 0) {
 				p1 = params[0];
 				p2 = params[1];
 			}
 			(*f2) (p1, p2);
 			break;
 		case SUB_3_PARAM:
-			f3 = (abe_subroutine3) abe_all_subsubroutine [idx];
+			f3 = (abe_subroutine3) abe_all_subsubroutine[idx];
 			params = abe_all_subroutine_params
 				[abe_irq_pingpong_player_id];
-			if (params != (u32*)0) {
+			if (params != (u32 *) 0) {
 				p1 = params[0];
 				p2 = params[1];
 				p3 = params[2];
@@ -250,10 +226,10 @@ void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
 			(*f3) (p1, p2, p3);
 			break;
 		case SUB_4_PARAM:
-			f4 = (abe_subroutine4) abe_all_subsubroutine [idx];
+			f4 = (abe_subroutine4) abe_all_subsubroutine[idx];
 			params = abe_all_subroutine_params
 				[abe_irq_pingpong_player_id];
-			if (params != (u32*)0) {
+			if (params != (u32 *) 0) {
 				p1 = params[0];
 				p2 = params[1];
 				p3 = params[2];
@@ -261,7 +237,6 @@ void abe_call_subroutine (u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
 			}
 			(*f4) (p1, p2, p3, p4);
 			break;
-
 		default:
 			break;
 		}
diff --git a/sound/soc/omap/abe/abe_seq.h b/sound/soc/omap/abe/abe_seq.h
index f77fe2d02a78..3e93d4cd68bd 100644
--- a/sound/soc/omap/abe/abe_seq.h
+++ b/sound/soc/omap/abe/abe_seq.h
@@ -18,20 +18,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
-void abe_init_subroutine_table (void);
-
+void abe_init_subroutine_table(void);
 /*
  * Register Programming Examples
  *
  * 1. Power on sequence
  *
- * The modules HSLDO, NCP, LSLDO, LPPLL are enabled/disabled automatically by 
- * the TWL6040 power state machine after pin AUDPWRON transitions from 0 ' 1. 
+ * The modules HSLDO, NCP, LSLDO, LPPLL are enabled/disabled automatically by
+ * the TWL6040 power state machine after pin AUDPWRON transitions from 0 ' 1.
  * No register writes are necessary.
  *
- * For the purposes of test it is possible to bypass the power state machine 
- * and manually enable these modules in the same order as described in Fig 2-XX. 
+ * For the purposes of test it is possible to bypass the power state machine
+ * and manually enable these modules in the same order as described in Fig 2-XX.
  * This can be done after VIO comes up and I2C register writes are possible.
  *
  * The manual sequence could be as follows
@@ -40,10 +38,10 @@ void abe_init_subroutine_table (void);
  * LDOCTL = 0x05 (Enable LSLDO)
  * LPPLLCTL = 0x09 (Enable LPPLL with output frequency = 19.2MHz)
  *
- * Please see Fig 2-64 for details on details to be maintained between successive 
+ * Please see Fig 2-64 for details on details to be maintained between successive
  * I2C register writes.
  *
- * Further if the system MCLK is active the HPPLL could be enabled instead of the 
+ * Further if the system MCLK is active the HPPLL could be enabled instead of the
  * LPPLL.
  * (a) For a square wave where slicer is not required
  * HPPLLCTL = 0x11 (Select HPPLL output, Enable HPPLL)
@@ -51,7 +49,6 @@ void abe_init_subroutine_table (void);
  * HPPLLCTL = 0x19 (Select HPPLL output, Enable Slicer, Enable HPPLL)
  *
  */
-
 /*
  * 2. Setting up a stereo UPLINK path through MICAMPL, MICAMPR input amplifiers
  * AMICBCTL = 0x10
@@ -61,7 +58,6 @@ void abe_init_subroutine_table (void);
  * MICRCTL = 0x0D (Select SMIC input, Enable ADC)
  *
  */
-
 /*
  * 3. Setting up a stereo headset MP3 playback DNLINK path
  * Please see section 2.3.1.1 for details
@@ -78,7 +74,6 @@ void abe_init_subroutine_table (void);
  * HSRCTL = 0x25 (Close HSDACR switch)
  *
  */
-
 /*
  * (a) LP
  * HSGAIN = 0x22 (-4 dB gain on L and R amplifiers)
@@ -92,7 +87,6 @@ void abe_init_subroutine_table (void);
  * HSRCTL = 0x2F (Close HSDACR switch)
  *
  */
-
 /*
  * 4. Setting up a stereo FM playback path on headset
  * (a) HP
@@ -108,7 +102,6 @@ void abe_init_subroutine_table (void);
  *
  *
  */
-
 /*
  * (b) LP
  * LINEGAIN = 0x1B (0dB gain on L and R inputs)
@@ -122,8 +115,6 @@ void abe_init_subroutine_table (void);
  * HSRCTL = 0x4C (Close FMLOOP switch)
  *
  */
-
-
 /*
  * 5. Setting up a handset call
  *
@@ -139,7 +130,7 @@ void abe_init_subroutine_table (void);
  *
  * HSLCTL = 0x01 (Enable HSDACL, HP mode)
  * Wait 80us
- * EARCTL = 0x03 (Enable EAR, Gain = min, by default enabling EAR connects 
+ * EARCTL = 0x03 (Enable EAR, Gain = min, by default enabling EAR connects
  * HSDACL output to EAR)
  *
  */
diff --git a/sound/soc/omap/abe/abe_sm_addr.h b/sound/soc/omap/abe/abe_sm_addr.h
index fe445d5b0753..89c6e4be4ca8 100644
--- a/sound/soc/omap/abe/abe_sm_addr.h
+++ b/sound/soc/omap/abe/abe_sm_addr.h
@@ -20,666 +20,499 @@
  */
 #ifndef _ABE_SM_ADDR_H_
 #define _ABE_SM_ADDR_H_
-
-#define init_SM_ADDR                                        0 
-#define init_SM_ADDR_END                                    303 
-#define init_SM_sizeof                                      304 
-
-#define S_Data0_ADDR                                        304 
-#define S_Data0_ADDR_END                                    304 
-#define S_Data0_sizeof                                      1 
-
-#define S_Temp_ADDR                                         305 
-#define S_Temp_ADDR_END                                     305 
-#define S_Temp_sizeof                                       1 
-
-#define S_PhoenixOffset_ADDR                                306 
-#define S_PhoenixOffset_ADDR_END                            306 
-#define S_PhoenixOffset_sizeof                              1 
-
-#define S_GTarget1_ADDR                                     307 
-#define S_GTarget1_ADDR_END                                 313 
-#define S_GTarget1_sizeof                                   7 
-
-#define S_Gtarget_DL1_ADDR                                  314 
-#define S_Gtarget_DL1_ADDR_END                              315 
-#define S_Gtarget_DL1_sizeof                                2 
-
-#define S_Gtarget_DL2_ADDR                                  316 
-#define S_Gtarget_DL2_ADDR_END                              317 
-#define S_Gtarget_DL2_sizeof                                2 
-
-#define S_Gtarget_Echo_ADDR                                 318 
-#define S_Gtarget_Echo_ADDR_END                             318 
-#define S_Gtarget_Echo_sizeof                               1 
-
-#define S_Gtarget_SDT_ADDR                                  319 
-#define S_Gtarget_SDT_ADDR_END                              319 
-#define S_Gtarget_SDT_sizeof                                1 
-
-#define S_Gtarget_VxRec_ADDR                                320 
-#define S_Gtarget_VxRec_ADDR_END                            321 
-#define S_Gtarget_VxRec_sizeof                              2 
-
-#define S_Gtarget_UL_ADDR                                   322 
-#define S_Gtarget_UL_ADDR_END                               323 
-#define S_Gtarget_UL_sizeof                                 2 
-
-#define S_Gtarget_unused_ADDR                               324 
-#define S_Gtarget_unused_ADDR_END                           324 
-#define S_Gtarget_unused_sizeof                             1 
-
-#define S_GCurrent_ADDR                                     325 
-#define S_GCurrent_ADDR_END                                 342 
-#define S_GCurrent_sizeof                                   18 
-
-#define S_GAIN_ONE_ADDR                                     343 
-#define S_GAIN_ONE_ADDR_END                                 343 
-#define S_GAIN_ONE_sizeof                                   1 
-
-#define S_Tones_ADDR                                        344 
-#define S_Tones_ADDR_END                                    355 
-#define S_Tones_sizeof                                      12 
-
-#define S_VX_DL_ADDR                                        356 
-#define S_VX_DL_ADDR_END                                    367 
-#define S_VX_DL_sizeof                                      12 
-
-#define S_MM_UL2_ADDR                                       368 
-#define S_MM_UL2_ADDR_END                                   379 
-#define S_MM_UL2_sizeof                                     12 
-
-#define S_MM_DL_ADDR                                        380 
-#define S_MM_DL_ADDR_END                                    391 
-#define S_MM_DL_sizeof                                      12 
-
-#define S_DL1_M_Out_ADDR                                    392 
-#define S_DL1_M_Out_ADDR_END                                403 
-#define S_DL1_M_Out_sizeof                                  12 
-
-#define S_DL2_M_Out_ADDR                                    404 
-#define S_DL2_M_Out_ADDR_END                                415 
-#define S_DL2_M_Out_sizeof                                  12 
-
-#define S_Echo_M_Out_ADDR                                   416 
-#define S_Echo_M_Out_ADDR_END                               427 
-#define S_Echo_M_Out_sizeof                                 12 
-
-#define S_SDT_M_Out_ADDR                                    428 
-#define S_SDT_M_Out_ADDR_END                                439 
-#define S_SDT_M_Out_sizeof                                  12 
-
-#define S_VX_UL_ADDR                                        440 
-#define S_VX_UL_ADDR_END                                    451 
-#define S_VX_UL_sizeof                                      12 
-
-#define S_VX_UL_M_ADDR                                      452 
-#define S_VX_UL_M_ADDR_END                                  463 
-#define S_VX_UL_M_sizeof                                    12 
-
-#define S_BT_DL_ADDR                                        464 
-#define S_BT_DL_ADDR_END                                    475 
-#define S_BT_DL_sizeof                                      12 
-
-#define S_BT_UL_ADDR                                        476 
-#define S_BT_UL_ADDR_END                                    487 
-#define S_BT_UL_sizeof                                      12 
-
-#define S_BT_DL_8k_ADDR                                     488 
-#define S_BT_DL_8k_ADDR_END                                 489 
-#define S_BT_DL_8k_sizeof                                   2 
-
-#define S_BT_DL_16k_ADDR                                    490 
-#define S_BT_DL_16k_ADDR_END                                493 
-#define S_BT_DL_16k_sizeof                                  4 
-
-#define S_BT_UL_8k_ADDR                                     494 
-#define S_BT_UL_8k_ADDR_END                                 495 
-#define S_BT_UL_8k_sizeof                                   2 
-
-#define S_BT_UL_16k_ADDR                                    496 
-#define S_BT_UL_16k_ADDR_END                                499 
-#define S_BT_UL_16k_sizeof                                  4 
-
-#define S_SDT_F_ADDR                                        500 
-#define S_SDT_F_ADDR_END                                    511 
-#define S_SDT_F_sizeof                                      12 
-
-#define S_SDT_F_data_ADDR                                   512 
-#define S_SDT_F_data_ADDR_END                               520 
-#define S_SDT_F_data_sizeof                                 9 
-
-#define S_MM_DL_OSR_ADDR                                    521 
-#define S_MM_DL_OSR_ADDR_END                                544 
-#define S_MM_DL_OSR_sizeof                                  24 
-
-#define S_24_zeros_ADDR                                     545 
-#define S_24_zeros_ADDR_END                                 568 
-#define S_24_zeros_sizeof                                   24 
-
-#define S_DMIC1_ADDR                                        569 
-#define S_DMIC1_ADDR_END                                    580 
-#define S_DMIC1_sizeof                                      12 
-
-#define S_DMIC2_ADDR                                        581 
-#define S_DMIC2_ADDR_END                                    592 
-#define S_DMIC2_sizeof                                      12 
-
-#define S_DMIC3_ADDR                                        593 
-#define S_DMIC3_ADDR_END                                    604 
-#define S_DMIC3_sizeof                                      12 
-
-#define S_AMIC_ADDR                                         605 
-#define S_AMIC_ADDR_END                                     616 
-#define S_AMIC_sizeof                                       12 
-
-#define S_EANC_FBK_in_ADDR                                  617 
-#define S_EANC_FBK_in_ADDR_END                              640 
-#define S_EANC_FBK_in_sizeof                                24 
-
-#define S_EANC_FBK_out_ADDR                                 641 
-#define S_EANC_FBK_out_ADDR_END                             652 
-#define S_EANC_FBK_out_sizeof                               12 
-
-#define S_DMIC1_L_ADDR                                      653 
-#define S_DMIC1_L_ADDR_END                                  664 
-#define S_DMIC1_L_sizeof                                    12 
-
-#define S_DMIC1_R_ADDR                                      665 
-#define S_DMIC1_R_ADDR_END                                  676 
-#define S_DMIC1_R_sizeof                                    12 
-
-#define S_DMIC2_L_ADDR                                      677 
-#define S_DMIC2_L_ADDR_END                                  688 
-#define S_DMIC2_L_sizeof                                    12 
-
-#define S_DMIC2_R_ADDR                                      689 
-#define S_DMIC2_R_ADDR_END                                  700 
-#define S_DMIC2_R_sizeof                                    12 
-
-#define S_DMIC3_L_ADDR                                      701 
-#define S_DMIC3_L_ADDR_END                                  712 
-#define S_DMIC3_L_sizeof                                    12 
-
-#define S_DMIC3_R_ADDR                                      713 
-#define S_DMIC3_R_ADDR_END                                  724 
-#define S_DMIC3_R_sizeof                                    12 
-
-#define S_BT_UL_L_ADDR                                      725 
-#define S_BT_UL_L_ADDR_END                                  736 
-#define S_BT_UL_L_sizeof                                    12 
-
-#define S_BT_UL_R_ADDR                                      737 
-#define S_BT_UL_R_ADDR_END                                  748 
-#define S_BT_UL_R_sizeof                                    12 
-
-#define S_AMIC_L_ADDR                                       749 
-#define S_AMIC_L_ADDR_END                                   760 
-#define S_AMIC_L_sizeof                                     12 
-
-#define S_AMIC_R_ADDR                                       761 
-#define S_AMIC_R_ADDR_END                                   772 
-#define S_AMIC_R_sizeof                                     12 
-
-#define S_EANC_FBK_L_ADDR                                   773 
-#define S_EANC_FBK_L_ADDR_END                               784 
-#define S_EANC_FBK_L_sizeof                                 12 
-
-#define S_EANC_FBK_R_ADDR                                   785 
-#define S_EANC_FBK_R_ADDR_END                               796 
-#define S_EANC_FBK_R_sizeof                                 12 
-
-#define S_EchoRef_L_ADDR                                    797 
-#define S_EchoRef_L_ADDR_END                                808 
-#define S_EchoRef_L_sizeof                                  12 
-
-#define S_EchoRef_R_ADDR                                    809 
-#define S_EchoRef_R_ADDR_END                                820 
-#define S_EchoRef_R_sizeof                                  12 
-
-#define S_MM_DL_L_ADDR                                      821 
-#define S_MM_DL_L_ADDR_END                                  832 
-#define S_MM_DL_L_sizeof                                    12 
-
-#define S_MM_DL_R_ADDR                                      833 
-#define S_MM_DL_R_ADDR_END                                  844 
-#define S_MM_DL_R_sizeof                                    12 
-
-#define S_MM_UL_ADDR                                        845 
-#define S_MM_UL_ADDR_END                                    964 
-#define S_MM_UL_sizeof                                      120 
-
-#define S_AMIC_96k_ADDR                                     965 
-#define S_AMIC_96k_ADDR_END                                 988 
-#define S_AMIC_96k_sizeof                                   24 
-
-#define S_DMIC0_96k_ADDR                                    989 
-#define S_DMIC0_96k_ADDR_END                                1012 
-#define S_DMIC0_96k_sizeof                                  24 
-
-#define S_DMIC1_96k_ADDR                                    1013 
-#define S_DMIC1_96k_ADDR_END                                1036 
-#define S_DMIC1_96k_sizeof                                  24 
-
-#define S_DMIC2_96k_ADDR                                    1037 
-#define S_DMIC2_96k_ADDR_END                                1060 
-#define S_DMIC2_96k_sizeof                                  24 
-
-#define S_UL_VX_UL_48_8K_ADDR                               1061 
-#define S_UL_VX_UL_48_8K_ADDR_END                           1072 
-#define S_UL_VX_UL_48_8K_sizeof                             12 
-
-#define S_UL_VX_UL_48_16K_ADDR                              1073 
-#define S_UL_VX_UL_48_16K_ADDR_END                          1084 
-#define S_UL_VX_UL_48_16K_sizeof                            12 
-
-#define S_UL_MIC_48K_ADDR                                   1085 
-#define S_UL_MIC_48K_ADDR_END                               1096 
-#define S_UL_MIC_48K_sizeof                                 12 
-
-#define S_Voice_8k_UL_ADDR                                  1097 
-#define S_Voice_8k_UL_ADDR_END                              1099 
-#define S_Voice_8k_UL_sizeof                                3 
-
-#define S_Voice_8k_DL_ADDR                                  1100 
-#define S_Voice_8k_DL_ADDR_END                              1101 
-#define S_Voice_8k_DL_sizeof                                2 
-
-#define S_McPDM_Out1_ADDR                                   1102 
-#define S_McPDM_Out1_ADDR_END                               1125 
-#define S_McPDM_Out1_sizeof                                 24 
-
-#define S_McPDM_Out2_ADDR                                   1126 
-#define S_McPDM_Out2_ADDR_END                               1149 
-#define S_McPDM_Out2_sizeof                                 24 
-
-#define S_McPDM_Out3_ADDR                                   1150 
-#define S_McPDM_Out3_ADDR_END                               1173 
-#define S_McPDM_Out3_sizeof                                 24 
-
-#define S_Voice_16k_UL_ADDR                                 1174 
-#define S_Voice_16k_UL_ADDR_END                             1178 
-#define S_Voice_16k_UL_sizeof                               5 
-
-#define S_Voice_16k_DL_ADDR                                 1179 
-#define S_Voice_16k_DL_ADDR_END                             1182 
-#define S_Voice_16k_DL_sizeof                               4 
-
-#define S_XinASRC_DL_VX_ADDR                                1183 
-#define S_XinASRC_DL_VX_ADDR_END                            1222 
-#define S_XinASRC_DL_VX_sizeof                              40 
-
-#define S_XinASRC_UL_VX_ADDR                                1223 
-#define S_XinASRC_UL_VX_ADDR_END                            1262 
-#define S_XinASRC_UL_VX_sizeof                              40 
-
-#define S_XinASRC_DL_MM_ADDR                                1263 
-#define S_XinASRC_DL_MM_ADDR_END                            1302 
-#define S_XinASRC_DL_MM_sizeof                              40 
-
-#define S_VX_REC_ADDR                                       1303 
-#define S_VX_REC_ADDR_END                                   1314 
-#define S_VX_REC_sizeof                                     12 
-
-#define S_VX_REC_L_ADDR                                     1315 
-#define S_VX_REC_L_ADDR_END                                 1326 
-#define S_VX_REC_L_sizeof                                   12 
-
-#define S_VX_REC_R_ADDR                                     1327 
-#define S_VX_REC_R_ADDR_END                                 1338 
-#define S_VX_REC_R_sizeof                                   12 
-
-#define S_DL2_M_L_ADDR                                      1339 
-#define S_DL2_M_L_ADDR_END                                  1350 
-#define S_DL2_M_L_sizeof                                    12 
-
-#define S_DL2_M_R_ADDR                                      1351 
-#define S_DL2_M_R_ADDR_END                                  1362 
-#define S_DL2_M_R_sizeof                                    12 
-
-#define S_DL2_M_LR_EQ_data_ADDR                             1363 
-#define S_DL2_M_LR_EQ_data_ADDR_END                         1387 
-#define S_DL2_M_LR_EQ_data_sizeof                           25 
-
-#define S_DL1_M_EQ_data_ADDR                                1388 
-#define S_DL1_M_EQ_data_ADDR_END                            1412 
-#define S_DL1_M_EQ_data_sizeof                              25 
-
-#define S_EARP_48_96_LP_data_ADDR                           1413 
-#define S_EARP_48_96_LP_data_ADDR_END                       1427 
-#define S_EARP_48_96_LP_data_sizeof                         15 
-
-#define S_IHF_48_96_LP_data_ADDR                            1428 
-#define S_IHF_48_96_LP_data_ADDR_END                        1442 
-#define S_IHF_48_96_LP_data_sizeof                          15 
-
-#define S_VX_UL_8_TEMP_ADDR                                 1443 
-#define S_VX_UL_8_TEMP_ADDR_END                             1444 
-#define S_VX_UL_8_TEMP_sizeof                               2 
-
-#define S_VX_UL_16_TEMP_ADDR                                1445 
-#define S_VX_UL_16_TEMP_ADDR_END                            1448 
-#define S_VX_UL_16_TEMP_sizeof                              4 
-
-#define S_VX_DL_8_48_LP_data_ADDR                           1449 
-#define S_VX_DL_8_48_LP_data_ADDR_END                       1459 
-#define S_VX_DL_8_48_LP_data_sizeof                         11 
-
-#define S_VX_DL_8_48_HP_data_ADDR                           1460 
-#define S_VX_DL_8_48_HP_data_ADDR_END                       1466 
-#define S_VX_DL_8_48_HP_data_sizeof                         7 
-
-#define S_VX_DL_16_48_LP_data_ADDR                          1467 
-#define S_VX_DL_16_48_LP_data_ADDR_END                      1477 
-#define S_VX_DL_16_48_LP_data_sizeof                        11 
-
-#define S_VX_DL_16_48_HP_data_ADDR                          1478 
-#define S_VX_DL_16_48_HP_data_ADDR_END                      1482 
-#define S_VX_DL_16_48_HP_data_sizeof                        5 
-
-#define S_VX_UL_48_8_LP_data_ADDR                           1483 
-#define S_VX_UL_48_8_LP_data_ADDR_END                       1493 
-#define S_VX_UL_48_8_LP_data_sizeof                         11 
-
-#define S_VX_UL_48_8_HP_data_ADDR                           1494 
-#define S_VX_UL_48_8_HP_data_ADDR_END                       1500 
-#define S_VX_UL_48_8_HP_data_sizeof                         7 
-
-#define S_VX_UL_48_16_LP_data_ADDR                          1501 
-#define S_VX_UL_48_16_LP_data_ADDR_END                      1511 
-#define S_VX_UL_48_16_LP_data_sizeof                        11 
-
-#define S_VX_UL_48_16_HP_data_ADDR                          1512 
-#define S_VX_UL_48_16_HP_data_ADDR_END                      1518 
-#define S_VX_UL_48_16_HP_data_sizeof                        7 
-
-#define S_BT_UL_8_48_LP_data_ADDR                           1519 
-#define S_BT_UL_8_48_LP_data_ADDR_END                       1529 
-#define S_BT_UL_8_48_LP_data_sizeof                         11 
-
-#define S_BT_UL_8_48_HP_data_ADDR                           1530 
-#define S_BT_UL_8_48_HP_data_ADDR_END                       1536 
-#define S_BT_UL_8_48_HP_data_sizeof                         7 
-
-#define S_BT_UL_16_48_LP_data_ADDR                          1537 
-#define S_BT_UL_16_48_LP_data_ADDR_END                      1547 
-#define S_BT_UL_16_48_LP_data_sizeof                        11 
-
-#define S_BT_UL_16_48_HP_data_ADDR                          1548 
-#define S_BT_UL_16_48_HP_data_ADDR_END                      1552 
-#define S_BT_UL_16_48_HP_data_sizeof                        5 
-
-#define S_BT_DL_48_8_LP_data_ADDR                           1553 
-#define S_BT_DL_48_8_LP_data_ADDR_END                       1563 
-#define S_BT_DL_48_8_LP_data_sizeof                         11 
-
-#define S_BT_DL_48_8_HP_data_ADDR                           1564 
-#define S_BT_DL_48_8_HP_data_ADDR_END                       1570 
-#define S_BT_DL_48_8_HP_data_sizeof                         7 
-
-#define S_BT_DL_48_16_LP_data_ADDR                          1571 
-#define S_BT_DL_48_16_LP_data_ADDR_END                      1581 
-#define S_BT_DL_48_16_LP_data_sizeof                        11 
-
-#define S_BT_DL_48_16_HP_data_ADDR                          1582 
-#define S_BT_DL_48_16_HP_data_ADDR_END                      1586 
-#define S_BT_DL_48_16_HP_data_sizeof                        5 
-
-#define S_ECHO_REF_48_8_LP_data_ADDR                        1587 
-#define S_ECHO_REF_48_8_LP_data_ADDR_END                    1597 
-#define S_ECHO_REF_48_8_LP_data_sizeof                      11 
-
-#define S_ECHO_REF_48_8_HP_data_ADDR                        1598 
-#define S_ECHO_REF_48_8_HP_data_ADDR_END                    1604 
-#define S_ECHO_REF_48_8_HP_data_sizeof                      7 
-
-#define S_ECHO_REF_48_16_LP_data_ADDR                       1605 
-#define S_ECHO_REF_48_16_LP_data_ADDR_END                   1615 
-#define S_ECHO_REF_48_16_LP_data_sizeof                     11 
-
-#define S_ECHO_REF_48_16_HP_data_ADDR                       1616 
-#define S_ECHO_REF_48_16_HP_data_ADDR_END                   1620 
-#define S_ECHO_REF_48_16_HP_data_sizeof                     5 
-
-#define S_EANC_IIR_data_ADDR                                1621 
-#define S_EANC_IIR_data_ADDR_END                            1637 
-#define S_EANC_IIR_data_sizeof                              17 
-
-#define S_EANC_SignalTemp_ADDR                              1638 
-#define S_EANC_SignalTemp_ADDR_END                          1658 
-#define S_EANC_SignalTemp_sizeof                            21 
-
-#define S_EANC_Input_ADDR                                   1659 
-#define S_EANC_Input_ADDR_END                               1659 
-#define S_EANC_Input_sizeof                                 1 
-
-#define S_EANC_Output_ADDR                                  1660 
-#define S_EANC_Output_ADDR_END                              1660 
-#define S_EANC_Output_sizeof                                1 
-
-#define S_APS_IIRmem1_ADDR                                  1661 
-#define S_APS_IIRmem1_ADDR_END                              1669 
-#define S_APS_IIRmem1_sizeof                                9 
-
-#define S_APS_M_IIRmem2_ADDR                                1670 
-#define S_APS_M_IIRmem2_ADDR_END                            1672 
-#define S_APS_M_IIRmem2_sizeof                              3 
-
-#define S_APS_C_IIRmem2_ADDR                                1673 
-#define S_APS_C_IIRmem2_ADDR_END                            1675 
-#define S_APS_C_IIRmem2_sizeof                              3 
-
-#define S_APS_DL1_OutSamples_ADDR                           1676 
-#define S_APS_DL1_OutSamples_ADDR_END                       1677 
-#define S_APS_DL1_OutSamples_sizeof                         2 
-
-#define S_APS_DL1_COIL_OutSamples_ADDR                      1678 
-#define S_APS_DL1_COIL_OutSamples_ADDR_END                  1679 
-#define S_APS_DL1_COIL_OutSamples_sizeof                    2 
-
-#define S_APS_DL2_L_OutSamples_ADDR                         1680 
-#define S_APS_DL2_L_OutSamples_ADDR_END                     1681 
-#define S_APS_DL2_L_OutSamples_sizeof                       2 
-
-#define S_APS_DL2_L_COIL_OutSamples_ADDR                    1682 
-#define S_APS_DL2_L_COIL_OutSamples_ADDR_END                1683 
-#define S_APS_DL2_L_COIL_OutSamples_sizeof                  2 
-
-#define S_APS_DL2_R_OutSamples_ADDR                         1684 
-#define S_APS_DL2_R_OutSamples_ADDR_END                     1685 
-#define S_APS_DL2_R_OutSamples_sizeof                       2 
-
-#define S_APS_DL2_R_COIL_OutSamples_ADDR                    1686 
-#define S_APS_DL2_R_COIL_OutSamples_ADDR_END                1687 
-#define S_APS_DL2_R_COIL_OutSamples_sizeof                  2 
-
-#define S_XinASRC_ECHO_REF_ADDR                             1688 
-#define S_XinASRC_ECHO_REF_ADDR_END                         1727 
-#define S_XinASRC_ECHO_REF_sizeof                           40 
-
-#define S_ECHO_REF_16K_ADDR                                 1728 
-#define S_ECHO_REF_16K_ADDR_END                             1732 
-#define S_ECHO_REF_16K_sizeof                               5 
-
-#define S_ECHO_REF_8K_ADDR                                  1733 
-#define S_ECHO_REF_8K_ADDR_END                              1735 
-#define S_ECHO_REF_8K_sizeof                                3 
-
-#define S_DL1_EQ_ADDR                                       1736 
-#define S_DL1_EQ_ADDR_END                                   1747 
-#define S_DL1_EQ_sizeof                                     12 
-
-#define S_DL2_EQ_ADDR                                       1748 
-#define S_DL2_EQ_ADDR_END                                   1759 
-#define S_DL2_EQ_sizeof                                     12 
-
-#define S_DL1_GAIN_out_ADDR                                 1760 
-#define S_DL1_GAIN_out_ADDR_END                             1771 
-#define S_DL1_GAIN_out_sizeof                               12 
-
-#define S_DL2_GAIN_out_ADDR                                 1772 
-#define S_DL2_GAIN_out_ADDR_END                             1783 
-#define S_DL2_GAIN_out_sizeof                               12 
-
-#define S_APS_DL2_L_IIRmem1_ADDR                            1784 
-#define S_APS_DL2_L_IIRmem1_ADDR_END                        1792 
-#define S_APS_DL2_L_IIRmem1_sizeof                          9 
-
-#define S_APS_DL2_R_IIRmem1_ADDR                            1793 
-#define S_APS_DL2_R_IIRmem1_ADDR_END                        1801 
-#define S_APS_DL2_R_IIRmem1_sizeof                          9 
-
-#define S_APS_DL2_L_M_IIRmem2_ADDR                          1802 
-#define S_APS_DL2_L_M_IIRmem2_ADDR_END                      1804 
-#define S_APS_DL2_L_M_IIRmem2_sizeof                        3 
-
-#define S_APS_DL2_R_M_IIRmem2_ADDR                          1805 
-#define S_APS_DL2_R_M_IIRmem2_ADDR_END                      1807 
-#define S_APS_DL2_R_M_IIRmem2_sizeof                        3 
-
-#define S_APS_DL2_L_C_IIRmem2_ADDR                          1808 
-#define S_APS_DL2_L_C_IIRmem2_ADDR_END                      1810 
-#define S_APS_DL2_L_C_IIRmem2_sizeof                        3 
-
-#define S_APS_DL2_R_C_IIRmem2_ADDR                          1811 
-#define S_APS_DL2_R_C_IIRmem2_ADDR_END                      1813 
-#define S_APS_DL2_R_C_IIRmem2_sizeof                        3 
-
-#define S_DL1_APS_ADDR                                      1814 
-#define S_DL1_APS_ADDR_END                                  1825 
-#define S_DL1_APS_sizeof                                    12 
-
-#define S_DL2_L_APS_ADDR                                    1826 
-#define S_DL2_L_APS_ADDR_END                                1837 
-#define S_DL2_L_APS_sizeof                                  12 
-
-#define S_DL2_R_APS_ADDR                                    1838 
-#define S_DL2_R_APS_ADDR_END                                1849 
-#define S_DL2_R_APS_sizeof                                  12 
-
-#define S_APS_DL1_EQ_data_ADDR                              1850 
-#define S_APS_DL1_EQ_data_ADDR_END                          1858 
-#define S_APS_DL1_EQ_data_sizeof                            9 
-
-#define S_APS_DL2_EQ_data_ADDR                              1859 
-#define S_APS_DL2_EQ_data_ADDR_END                          1867 
-#define S_APS_DL2_EQ_data_sizeof                            9 
-
-#define S_DC_DCvalue_ADDR                                   1868 
-#define S_DC_DCvalue_ADDR_END                               1868 
-#define S_DC_DCvalue_sizeof                                 1 
-
-#define S_VIBRA_ADDR                                        1869 
-#define S_VIBRA_ADDR_END                                    1874 
-#define S_VIBRA_sizeof                                      6 
-
-#define S_Vibra2_in_ADDR                                    1875 
-#define S_Vibra2_in_ADDR_END                                1880 
-#define S_Vibra2_in_sizeof                                  6 
-
-#define S_Vibra2_addr_ADDR                                  1881 
-#define S_Vibra2_addr_ADDR_END                              1881 
-#define S_Vibra2_addr_sizeof                                1 
-
-#define S_VibraCtrl_forRightSM_ADDR                         1882 
-#define S_VibraCtrl_forRightSM_ADDR_END                     1905 
-#define S_VibraCtrl_forRightSM_sizeof                       24 
-
-#define S_Rnoise_mem_ADDR                                   1906 
-#define S_Rnoise_mem_ADDR_END                               1906 
-#define S_Rnoise_mem_sizeof                                 1 
-
-#define S_Ctrl_ADDR                                         1907 
-#define S_Ctrl_ADDR_END                                     1924 
-#define S_Ctrl_sizeof                                       18 
-
-#define S_Vibra1_in_ADDR                                    1925 
-#define S_Vibra1_in_ADDR_END                                1930 
-#define S_Vibra1_in_sizeof                                  6 
-
-#define S_Vibra1_temp_ADDR                                  1931 
-#define S_Vibra1_temp_ADDR_END                              1954 
-#define S_Vibra1_temp_sizeof                                24 
-
-#define S_VibraCtrl_forLeftSM_ADDR                          1955 
-#define S_VibraCtrl_forLeftSM_ADDR_END                      1978 
-#define S_VibraCtrl_forLeftSM_sizeof                        24 
-
-#define S_Vibra1_mem_ADDR                                   1979 
-#define S_Vibra1_mem_ADDR_END                               1989 
-#define S_Vibra1_mem_sizeof                                 11 
-
-#define S_VibraCtrl_Stereo_ADDR                             1990 
-#define S_VibraCtrl_Stereo_ADDR_END                         2013 
-#define S_VibraCtrl_Stereo_sizeof                           24 
-
-#define S_AMIC_96_48_data_ADDR                              2014 
-#define S_AMIC_96_48_data_ADDR_END                          2032 
-#define S_AMIC_96_48_data_sizeof                            19 
-
-#define S_DMIC0_96_48_data_ADDR                             2033 
-#define S_DMIC0_96_48_data_ADDR_END                         2051 
-#define S_DMIC0_96_48_data_sizeof                           19 
-
-#define S_DMIC1_96_48_data_ADDR                             2052 
-#define S_DMIC1_96_48_data_ADDR_END                         2070 
-#define S_DMIC1_96_48_data_sizeof                           19 
-
-#define S_DMIC2_96_48_data_ADDR                             2071 
-#define S_DMIC2_96_48_data_ADDR_END                         2089 
-#define S_DMIC2_96_48_data_sizeof                           19 
-
-#define S_EANC_FBK_96_48_data_ADDR                          2090 
-#define S_EANC_FBK_96_48_data_ADDR_END                      2108 
-#define S_EANC_FBK_96_48_data_sizeof                        19 
-
-#define S_DBG_8K_PATTERN_ADDR                               2109 
-#define S_DBG_8K_PATTERN_ADDR_END                           2110 
-#define S_DBG_8K_PATTERN_sizeof                             2 
-
-#define S_DBG_16K_PATTERN_ADDR                              2111 
-#define S_DBG_16K_PATTERN_ADDR_END                          2114 
-#define S_DBG_16K_PATTERN_sizeof                            4 
-
-#define S_DBG_24K_PATTERN_ADDR                              2115 
-#define S_DBG_24K_PATTERN_ADDR_END                          2120 
-#define S_DBG_24K_PATTERN_sizeof                            6 
-
-#define S_DBG_48K_PATTERN_ADDR                              2121 
-#define S_DBG_48K_PATTERN_ADDR_END                          2132 
-#define S_DBG_48K_PATTERN_sizeof                            12 
-
-#define S_DBG_96K_PATTERN_ADDR                              2133 
-#define S_DBG_96K_PATTERN_ADDR_END                          2156 
-#define S_DBG_96K_PATTERN_sizeof                            24 
-
-#define S_MM_EXT_IN_ADDR                                    2157 
-#define S_MM_EXT_IN_ADDR_END                                2168 
-#define S_MM_EXT_IN_sizeof                                  12 
-
-#define S_MM_EXT_IN_L_ADDR                                  2169 
-#define S_MM_EXT_IN_L_ADDR_END                              2180 
-#define S_MM_EXT_IN_L_sizeof                                12 
-
-#define S_MM_EXT_IN_R_ADDR                                  2181 
-#define S_MM_EXT_IN_R_ADDR_END                              2192 
-#define S_MM_EXT_IN_R_sizeof                                12 
-
-#define S_MIC4_ADDR                                         2193 
-#define S_MIC4_ADDR_END                                     2204 
-#define S_MIC4_sizeof                                       12 
-
-#define S_MIC4_L_ADDR                                       2205 
-#define S_MIC4_L_ADDR_END                                   2216 
-#define S_MIC4_L_sizeof                                     12 
-
-#define S_MIC4_R_ADDR                                       2217 
-#define S_MIC4_R_ADDR_END                                   2228 
-#define S_MIC4_R_sizeof                                     12 
-
-#define S_HW_TEST_ADDR                                      2229 
-#define S_HW_TEST_ADDR_END                                  2229 
-#define S_HW_TEST_sizeof                                    1 
-
-
-#endif /* _ABESM_ADDR_H_ */
+#define init_SM_ADDR                                        0
+#define init_SM_ADDR_END                                    305
+#define init_SM_sizeof                                      306
+#define S_Data0_ADDR                                        306
+#define S_Data0_ADDR_END                                    306
+#define S_Data0_sizeof                                      1
+#define S_Temp_ADDR                                         307
+#define S_Temp_ADDR_END                                     307
+#define S_Temp_sizeof                                       1
+#define S_PhoenixOffset_ADDR                                308
+#define S_PhoenixOffset_ADDR_END                            308
+#define S_PhoenixOffset_sizeof                              1
+#define S_GTarget1_ADDR                                     309
+#define S_GTarget1_ADDR_END                                 315
+#define S_GTarget1_sizeof                                   7
+#define S_Gtarget_DL1_ADDR                                  316
+#define S_Gtarget_DL1_ADDR_END                              317
+#define S_Gtarget_DL1_sizeof                                2
+#define S_Gtarget_DL2_ADDR                                  318
+#define S_Gtarget_DL2_ADDR_END                              319
+#define S_Gtarget_DL2_sizeof                                2
+#define S_Gtarget_Echo_ADDR                                 320
+#define S_Gtarget_Echo_ADDR_END                             320
+#define S_Gtarget_Echo_sizeof                               1
+#define S_Gtarget_SDT_ADDR                                  321
+#define S_Gtarget_SDT_ADDR_END                              321
+#define S_Gtarget_SDT_sizeof                                1
+#define S_Gtarget_VxRec_ADDR                                322
+#define S_Gtarget_VxRec_ADDR_END                            323
+#define S_Gtarget_VxRec_sizeof                              2
+#define S_Gtarget_UL_ADDR                                   324
+#define S_Gtarget_UL_ADDR_END                               325
+#define S_Gtarget_UL_sizeof                                 2
+#define S_Gtarget_unused_ADDR                               326
+#define S_Gtarget_unused_ADDR_END                           326
+#define S_Gtarget_unused_sizeof                             1
+#define S_GCurrent_ADDR                                     327
+#define S_GCurrent_ADDR_END                                 344
+#define S_GCurrent_sizeof                                   18
+#define S_GAIN_ONE_ADDR                                     345
+#define S_GAIN_ONE_ADDR_END                                 345
+#define S_GAIN_ONE_sizeof                                   1
+#define S_Tones_ADDR                                        346
+#define S_Tones_ADDR_END                                    357
+#define S_Tones_sizeof                                      12
+#define S_VX_DL_ADDR                                        358
+#define S_VX_DL_ADDR_END                                    369
+#define S_VX_DL_sizeof                                      12
+#define S_MM_UL2_ADDR                                       370
+#define S_MM_UL2_ADDR_END                                   381
+#define S_MM_UL2_sizeof                                     12
+#define S_MM_DL_ADDR                                        382
+#define S_MM_DL_ADDR_END                                    393
+#define S_MM_DL_sizeof                                      12
+#define S_DL1_M_Out_ADDR                                    394
+#define S_DL1_M_Out_ADDR_END                                405
+#define S_DL1_M_Out_sizeof                                  12
+#define S_DL2_M_Out_ADDR                                    406
+#define S_DL2_M_Out_ADDR_END                                417
+#define S_DL2_M_Out_sizeof                                  12
+#define S_Echo_M_Out_ADDR                                   418
+#define S_Echo_M_Out_ADDR_END                               429
+#define S_Echo_M_Out_sizeof                                 12
+#define S_SDT_M_Out_ADDR                                    430
+#define S_SDT_M_Out_ADDR_END                                441
+#define S_SDT_M_Out_sizeof                                  12
+#define S_VX_UL_ADDR                                        442
+#define S_VX_UL_ADDR_END                                    453
+#define S_VX_UL_sizeof                                      12
+#define S_VX_UL_M_ADDR                                      454
+#define S_VX_UL_M_ADDR_END                                  465
+#define S_VX_UL_M_sizeof                                    12
+#define S_BT_DL_ADDR                                        466
+#define S_BT_DL_ADDR_END                                    477
+#define S_BT_DL_sizeof                                      12
+#define S_BT_UL_ADDR                                        478
+#define S_BT_UL_ADDR_END                                    489
+#define S_BT_UL_sizeof                                      12
+#define S_BT_DL_8k_ADDR                                     490
+#define S_BT_DL_8k_ADDR_END                                 491
+#define S_BT_DL_8k_sizeof                                   2
+#define S_BT_DL_16k_ADDR                                    492
+#define S_BT_DL_16k_ADDR_END                                495
+#define S_BT_DL_16k_sizeof                                  4
+#define S_BT_UL_8k_ADDR                                     496
+#define S_BT_UL_8k_ADDR_END                                 497
+#define S_BT_UL_8k_sizeof                                   2
+#define S_BT_UL_16k_ADDR                                    498
+#define S_BT_UL_16k_ADDR_END                                501
+#define S_BT_UL_16k_sizeof                                  4
+#define S_SDT_F_ADDR                                        502
+#define S_SDT_F_ADDR_END                                    513
+#define S_SDT_F_sizeof                                      12
+#define S_SDT_F_data_ADDR                                   514
+#define S_SDT_F_data_ADDR_END                               522
+#define S_SDT_F_data_sizeof                                 9
+#define S_MM_DL_OSR_ADDR                                    523
+#define S_MM_DL_OSR_ADDR_END                                546
+#define S_MM_DL_OSR_sizeof                                  24
+#define S_24_zeros_ADDR                                     547
+#define S_24_zeros_ADDR_END                                 570
+#define S_24_zeros_sizeof                                   24
+#define S_DMIC1_ADDR                                        571
+#define S_DMIC1_ADDR_END                                    582
+#define S_DMIC1_sizeof                                      12
+#define S_DMIC2_ADDR                                        583
+#define S_DMIC2_ADDR_END                                    594
+#define S_DMIC2_sizeof                                      12
+#define S_DMIC3_ADDR                                        595
+#define S_DMIC3_ADDR_END                                    606
+#define S_DMIC3_sizeof                                      12
+#define S_AMIC_ADDR                                         607
+#define S_AMIC_ADDR_END                                     618
+#define S_AMIC_sizeof                                       12
+#define S_EANC_FBK_in_ADDR                                  619
+#define S_EANC_FBK_in_ADDR_END                              642
+#define S_EANC_FBK_in_sizeof                                24
+#define S_EANC_FBK_out_ADDR                                 643
+#define S_EANC_FBK_out_ADDR_END                             654
+#define S_EANC_FBK_out_sizeof                               12
+#define S_DMIC1_L_ADDR                                      655
+#define S_DMIC1_L_ADDR_END                                  666
+#define S_DMIC1_L_sizeof                                    12
+#define S_DMIC1_R_ADDR                                      667
+#define S_DMIC1_R_ADDR_END                                  678
+#define S_DMIC1_R_sizeof                                    12
+#define S_DMIC2_L_ADDR                                      679
+#define S_DMIC2_L_ADDR_END                                  690
+#define S_DMIC2_L_sizeof                                    12
+#define S_DMIC2_R_ADDR                                      691
+#define S_DMIC2_R_ADDR_END                                  702
+#define S_DMIC2_R_sizeof                                    12
+#define S_DMIC3_L_ADDR                                      703
+#define S_DMIC3_L_ADDR_END                                  714
+#define S_DMIC3_L_sizeof                                    12
+#define S_DMIC3_R_ADDR                                      715
+#define S_DMIC3_R_ADDR_END                                  726
+#define S_DMIC3_R_sizeof                                    12
+#define S_BT_UL_L_ADDR                                      727
+#define S_BT_UL_L_ADDR_END                                  738
+#define S_BT_UL_L_sizeof                                    12
+#define S_BT_UL_R_ADDR                                      739
+#define S_BT_UL_R_ADDR_END                                  750
+#define S_BT_UL_R_sizeof                                    12
+#define S_AMIC_L_ADDR                                       751
+#define S_AMIC_L_ADDR_END                                   762
+#define S_AMIC_L_sizeof                                     12
+#define S_AMIC_R_ADDR                                       763
+#define S_AMIC_R_ADDR_END                                   774
+#define S_AMIC_R_sizeof                                     12
+#define S_EANC_FBK_L_ADDR                                   775
+#define S_EANC_FBK_L_ADDR_END                               786
+#define S_EANC_FBK_L_sizeof                                 12
+#define S_EANC_FBK_R_ADDR                                   787
+#define S_EANC_FBK_R_ADDR_END                               798
+#define S_EANC_FBK_R_sizeof                                 12
+#define S_EchoRef_L_ADDR                                    799
+#define S_EchoRef_L_ADDR_END                                810
+#define S_EchoRef_L_sizeof                                  12
+#define S_EchoRef_R_ADDR                                    811
+#define S_EchoRef_R_ADDR_END                                822
+#define S_EchoRef_R_sizeof                                  12
+#define S_MM_DL_L_ADDR                                      823
+#define S_MM_DL_L_ADDR_END                                  834
+#define S_MM_DL_L_sizeof                                    12
+#define S_MM_DL_R_ADDR                                      835
+#define S_MM_DL_R_ADDR_END                                  846
+#define S_MM_DL_R_sizeof                                    12
+#define S_MM_UL_ADDR                                        847
+#define S_MM_UL_ADDR_END                                    966
+#define S_MM_UL_sizeof                                      120
+#define S_AMIC_96k_ADDR                                     967
+#define S_AMIC_96k_ADDR_END                                 990
+#define S_AMIC_96k_sizeof                                   24
+#define S_DMIC0_96k_ADDR                                    991
+#define S_DMIC0_96k_ADDR_END                                1014
+#define S_DMIC0_96k_sizeof                                  24
+#define S_DMIC1_96k_ADDR                                    1015
+#define S_DMIC1_96k_ADDR_END                                1038
+#define S_DMIC1_96k_sizeof                                  24
+#define S_DMIC2_96k_ADDR                                    1039
+#define S_DMIC2_96k_ADDR_END                                1062
+#define S_DMIC2_96k_sizeof                                  24
+#define S_UL_VX_UL_48_8K_ADDR                               1063
+#define S_UL_VX_UL_48_8K_ADDR_END                           1074
+#define S_UL_VX_UL_48_8K_sizeof                             12
+#define S_UL_VX_UL_48_16K_ADDR                              1075
+#define S_UL_VX_UL_48_16K_ADDR_END                          1086
+#define S_UL_VX_UL_48_16K_sizeof                            12
+#define S_UL_MIC_48K_ADDR                                   1087
+#define S_UL_MIC_48K_ADDR_END                               1098
+#define S_UL_MIC_48K_sizeof                                 12
+#define S_Voice_8k_UL_ADDR                                  1099
+#define S_Voice_8k_UL_ADDR_END                              1101
+#define S_Voice_8k_UL_sizeof                                3
+#define S_Voice_8k_DL_ADDR                                  1102
+#define S_Voice_8k_DL_ADDR_END                              1103
+#define S_Voice_8k_DL_sizeof                                2
+#define S_McPDM_Out1_ADDR                                   1104
+#define S_McPDM_Out1_ADDR_END                               1127
+#define S_McPDM_Out1_sizeof                                 24
+#define S_McPDM_Out2_ADDR                                   1128
+#define S_McPDM_Out2_ADDR_END                               1151
+#define S_McPDM_Out2_sizeof                                 24
+#define S_McPDM_Out3_ADDR                                   1152
+#define S_McPDM_Out3_ADDR_END                               1175
+#define S_McPDM_Out3_sizeof                                 24
+#define S_Voice_16k_UL_ADDR                                 1176
+#define S_Voice_16k_UL_ADDR_END                             1180
+#define S_Voice_16k_UL_sizeof                               5
+#define S_Voice_16k_DL_ADDR                                 1181
+#define S_Voice_16k_DL_ADDR_END                             1184
+#define S_Voice_16k_DL_sizeof                               4
+#define S_XinASRC_DL_VX_ADDR                                1185
+#define S_XinASRC_DL_VX_ADDR_END                            1224
+#define S_XinASRC_DL_VX_sizeof                              40
+#define S_XinASRC_UL_VX_ADDR                                1225
+#define S_XinASRC_UL_VX_ADDR_END                            1264
+#define S_XinASRC_UL_VX_sizeof                              40
+#define S_XinASRC_MM_EXT_IN_ADDR                            1265
+#define S_XinASRC_MM_EXT_IN_ADDR_END                        1304
+#define S_XinASRC_MM_EXT_IN_sizeof                          40
+#define S_VX_REC_ADDR                                       1305
+#define S_VX_REC_ADDR_END                                   1316
+#define S_VX_REC_sizeof                                     12
+#define S_VX_REC_L_ADDR                                     1317
+#define S_VX_REC_L_ADDR_END                                 1328
+#define S_VX_REC_L_sizeof                                   12
+#define S_VX_REC_R_ADDR                                     1329
+#define S_VX_REC_R_ADDR_END                                 1340
+#define S_VX_REC_R_sizeof                                   12
+#define S_DL2_M_L_ADDR                                      1341
+#define S_DL2_M_L_ADDR_END                                  1352
+#define S_DL2_M_L_sizeof                                    12
+#define S_DL2_M_R_ADDR                                      1353
+#define S_DL2_M_R_ADDR_END                                  1364
+#define S_DL2_M_R_sizeof                                    12
+#define S_DL2_M_LR_EQ_data_ADDR                             1365
+#define S_DL2_M_LR_EQ_data_ADDR_END                         1389
+#define S_DL2_M_LR_EQ_data_sizeof                           25
+#define S_DL1_M_EQ_data_ADDR                                1390
+#define S_DL1_M_EQ_data_ADDR_END                            1414
+#define S_DL1_M_EQ_data_sizeof                              25
+#define S_EARP_48_96_LP_data_ADDR                           1415
+#define S_EARP_48_96_LP_data_ADDR_END                       1429
+#define S_EARP_48_96_LP_data_sizeof                         15
+#define S_IHF_48_96_LP_data_ADDR                            1430
+#define S_IHF_48_96_LP_data_ADDR_END                        1444
+#define S_IHF_48_96_LP_data_sizeof                          15
+#define S_VX_UL_8_TEMP_ADDR                                 1445
+#define S_VX_UL_8_TEMP_ADDR_END                             1446
+#define S_VX_UL_8_TEMP_sizeof                               2
+#define S_VX_UL_16_TEMP_ADDR                                1447
+#define S_VX_UL_16_TEMP_ADDR_END                            1450
+#define S_VX_UL_16_TEMP_sizeof                              4
+#define S_VX_DL_8_48_LP_data_ADDR                           1451
+#define S_VX_DL_8_48_LP_data_ADDR_END                       1461
+#define S_VX_DL_8_48_LP_data_sizeof                         11
+#define S_VX_DL_8_48_HP_data_ADDR                           1462
+#define S_VX_DL_8_48_HP_data_ADDR_END                       1468
+#define S_VX_DL_8_48_HP_data_sizeof                         7
+#define S_VX_DL_16_48_LP_data_ADDR                          1469
+#define S_VX_DL_16_48_LP_data_ADDR_END                      1479
+#define S_VX_DL_16_48_LP_data_sizeof                        11
+#define S_VX_DL_16_48_HP_data_ADDR                          1480
+#define S_VX_DL_16_48_HP_data_ADDR_END                      1484
+#define S_VX_DL_16_48_HP_data_sizeof                        5
+#define S_VX_UL_48_8_LP_data_ADDR                           1485
+#define S_VX_UL_48_8_LP_data_ADDR_END                       1495
+#define S_VX_UL_48_8_LP_data_sizeof                         11
+#define S_VX_UL_48_8_HP_data_ADDR                           1496
+#define S_VX_UL_48_8_HP_data_ADDR_END                       1502
+#define S_VX_UL_48_8_HP_data_sizeof                         7
+#define S_VX_UL_48_16_LP_data_ADDR                          1503
+#define S_VX_UL_48_16_LP_data_ADDR_END                      1513
+#define S_VX_UL_48_16_LP_data_sizeof                        11
+#define S_VX_UL_48_16_HP_data_ADDR                          1514
+#define S_VX_UL_48_16_HP_data_ADDR_END                      1520
+#define S_VX_UL_48_16_HP_data_sizeof                        7
+#define S_BT_UL_8_48_LP_data_ADDR                           1521
+#define S_BT_UL_8_48_LP_data_ADDR_END                       1531
+#define S_BT_UL_8_48_LP_data_sizeof                         11
+#define S_BT_UL_8_48_HP_data_ADDR                           1532
+#define S_BT_UL_8_48_HP_data_ADDR_END                       1538
+#define S_BT_UL_8_48_HP_data_sizeof                         7
+#define S_BT_UL_16_48_LP_data_ADDR                          1539
+#define S_BT_UL_16_48_LP_data_ADDR_END                      1549
+#define S_BT_UL_16_48_LP_data_sizeof                        11
+#define S_BT_UL_16_48_HP_data_ADDR                          1550
+#define S_BT_UL_16_48_HP_data_ADDR_END                      1554
+#define S_BT_UL_16_48_HP_data_sizeof                        5
+#define S_BT_DL_48_8_LP_data_ADDR                           1555
+#define S_BT_DL_48_8_LP_data_ADDR_END                       1565
+#define S_BT_DL_48_8_LP_data_sizeof                         11
+#define S_BT_DL_48_8_HP_data_ADDR                           1566
+#define S_BT_DL_48_8_HP_data_ADDR_END                       1572
+#define S_BT_DL_48_8_HP_data_sizeof                         7
+#define S_BT_DL_48_16_LP_data_ADDR                          1573
+#define S_BT_DL_48_16_LP_data_ADDR_END                      1583
+#define S_BT_DL_48_16_LP_data_sizeof                        11
+#define S_BT_DL_48_16_HP_data_ADDR                          1584
+#define S_BT_DL_48_16_HP_data_ADDR_END                      1588
+#define S_BT_DL_48_16_HP_data_sizeof                        5
+#define S_ECHO_REF_48_8_LP_data_ADDR                        1589
+#define S_ECHO_REF_48_8_LP_data_ADDR_END                    1599
+#define S_ECHO_REF_48_8_LP_data_sizeof                      11
+#define S_ECHO_REF_48_8_HP_data_ADDR                        1600
+#define S_ECHO_REF_48_8_HP_data_ADDR_END                    1606
+#define S_ECHO_REF_48_8_HP_data_sizeof                      7
+#define S_ECHO_REF_48_16_LP_data_ADDR                       1607
+#define S_ECHO_REF_48_16_LP_data_ADDR_END                   1617
+#define S_ECHO_REF_48_16_LP_data_sizeof                     11
+#define S_ECHO_REF_48_16_HP_data_ADDR                       1618
+#define S_ECHO_REF_48_16_HP_data_ADDR_END                   1622
+#define S_ECHO_REF_48_16_HP_data_sizeof                     5
+#define S_EANC_IIR_data_ADDR                                1623
+#define S_EANC_IIR_data_ADDR_END                            1639
+#define S_EANC_IIR_data_sizeof                              17
+#define S_EANC_SignalTemp_ADDR                              1640
+#define S_EANC_SignalTemp_ADDR_END                          1660
+#define S_EANC_SignalTemp_sizeof                            21
+#define S_EANC_Input_ADDR                                   1661
+#define S_EANC_Input_ADDR_END                               1661
+#define S_EANC_Input_sizeof                                 1
+#define S_EANC_Output_ADDR                                  1662
+#define S_EANC_Output_ADDR_END                              1662
+#define S_EANC_Output_sizeof                                1
+#define S_APS_IIRmem1_ADDR                                  1663
+#define S_APS_IIRmem1_ADDR_END                              1671
+#define S_APS_IIRmem1_sizeof                                9
+#define S_APS_M_IIRmem2_ADDR                                1672
+#define S_APS_M_IIRmem2_ADDR_END                            1674
+#define S_APS_M_IIRmem2_sizeof                              3
+#define S_APS_C_IIRmem2_ADDR                                1675
+#define S_APS_C_IIRmem2_ADDR_END                            1677
+#define S_APS_C_IIRmem2_sizeof                              3
+#define S_APS_DL1_OutSamples_ADDR                           1678
+#define S_APS_DL1_OutSamples_ADDR_END                       1679
+#define S_APS_DL1_OutSamples_sizeof                         2
+#define S_APS_DL1_COIL_OutSamples_ADDR                      1680
+#define S_APS_DL1_COIL_OutSamples_ADDR_END                  1681
+#define S_APS_DL1_COIL_OutSamples_sizeof                    2
+#define S_APS_DL2_L_OutSamples_ADDR                         1682
+#define S_APS_DL2_L_OutSamples_ADDR_END                     1683
+#define S_APS_DL2_L_OutSamples_sizeof                       2
+#define S_APS_DL2_L_COIL_OutSamples_ADDR                    1684
+#define S_APS_DL2_L_COIL_OutSamples_ADDR_END                1685
+#define S_APS_DL2_L_COIL_OutSamples_sizeof                  2
+#define S_APS_DL2_R_OutSamples_ADDR                         1686
+#define S_APS_DL2_R_OutSamples_ADDR_END                     1687
+#define S_APS_DL2_R_OutSamples_sizeof                       2
+#define S_APS_DL2_R_COIL_OutSamples_ADDR                    1688
+#define S_APS_DL2_R_COIL_OutSamples_ADDR_END                1689
+#define S_APS_DL2_R_COIL_OutSamples_sizeof                  2
+#define S_XinASRC_ECHO_REF_ADDR                             1690
+#define S_XinASRC_ECHO_REF_ADDR_END                         1729
+#define S_XinASRC_ECHO_REF_sizeof                           40
+#define S_ECHO_REF_16K_ADDR                                 1730
+#define S_ECHO_REF_16K_ADDR_END                             1734
+#define S_ECHO_REF_16K_sizeof                               5
+#define S_ECHO_REF_8K_ADDR                                  1735
+#define S_ECHO_REF_8K_ADDR_END                              1737
+#define S_ECHO_REF_8K_sizeof                                3
+#define S_DL1_EQ_ADDR                                       1738
+#define S_DL1_EQ_ADDR_END                                   1749
+#define S_DL1_EQ_sizeof                                     12
+#define S_DL2_EQ_ADDR                                       1750
+#define S_DL2_EQ_ADDR_END                                   1761
+#define S_DL2_EQ_sizeof                                     12
+#define S_DL1_GAIN_out_ADDR                                 1762
+#define S_DL1_GAIN_out_ADDR_END                             1773
+#define S_DL1_GAIN_out_sizeof                               12
+#define S_DL2_GAIN_out_ADDR                                 1774
+#define S_DL2_GAIN_out_ADDR_END                             1785
+#define S_DL2_GAIN_out_sizeof                               12
+#define S_APS_DL2_L_IIRmem1_ADDR                            1786
+#define S_APS_DL2_L_IIRmem1_ADDR_END                        1794
+#define S_APS_DL2_L_IIRmem1_sizeof                          9
+#define S_APS_DL2_R_IIRmem1_ADDR                            1795
+#define S_APS_DL2_R_IIRmem1_ADDR_END                        1803
+#define S_APS_DL2_R_IIRmem1_sizeof                          9
+#define S_APS_DL2_L_M_IIRmem2_ADDR                          1804
+#define S_APS_DL2_L_M_IIRmem2_ADDR_END                      1806
+#define S_APS_DL2_L_M_IIRmem2_sizeof                        3
+#define S_APS_DL2_R_M_IIRmem2_ADDR                          1807
+#define S_APS_DL2_R_M_IIRmem2_ADDR_END                      1809
+#define S_APS_DL2_R_M_IIRmem2_sizeof                        3
+#define S_APS_DL2_L_C_IIRmem2_ADDR                          1810
+#define S_APS_DL2_L_C_IIRmem2_ADDR_END                      1812
+#define S_APS_DL2_L_C_IIRmem2_sizeof                        3
+#define S_APS_DL2_R_C_IIRmem2_ADDR                          1813
+#define S_APS_DL2_R_C_IIRmem2_ADDR_END                      1815
+#define S_APS_DL2_R_C_IIRmem2_sizeof                        3
+#define S_DL1_APS_ADDR                                      1816
+#define S_DL1_APS_ADDR_END                                  1827
+#define S_DL1_APS_sizeof                                    12
+#define S_DL2_L_APS_ADDR                                    1828
+#define S_DL2_L_APS_ADDR_END                                1839
+#define S_DL2_L_APS_sizeof                                  12
+#define S_DL2_R_APS_ADDR                                    1840
+#define S_DL2_R_APS_ADDR_END                                1851
+#define S_DL2_R_APS_sizeof                                  12
+#define S_APS_DL1_EQ_data_ADDR                              1852
+#define S_APS_DL1_EQ_data_ADDR_END                          1860
+#define S_APS_DL1_EQ_data_sizeof                            9
+#define S_APS_DL2_EQ_data_ADDR                              1861
+#define S_APS_DL2_EQ_data_ADDR_END                          1869
+#define S_APS_DL2_EQ_data_sizeof                            9
+#define S_DC_DCvalue_ADDR                                   1870
+#define S_DC_DCvalue_ADDR_END                               1870
+#define S_DC_DCvalue_sizeof                                 1
+#define S_VIBRA_ADDR                                        1871
+#define S_VIBRA_ADDR_END                                    1876
+#define S_VIBRA_sizeof                                      6
+#define S_Vibra2_in_ADDR                                    1877
+#define S_Vibra2_in_ADDR_END                                1882
+#define S_Vibra2_in_sizeof                                  6
+#define S_Vibra2_addr_ADDR                                  1883
+#define S_Vibra2_addr_ADDR_END                              1883
+#define S_Vibra2_addr_sizeof                                1
+#define S_VibraCtrl_forRightSM_ADDR                         1884
+#define S_VibraCtrl_forRightSM_ADDR_END                     1907
+#define S_VibraCtrl_forRightSM_sizeof                       24
+#define S_Rnoise_mem_ADDR                                   1908
+#define S_Rnoise_mem_ADDR_END                               1908
+#define S_Rnoise_mem_sizeof                                 1
+#define S_Ctrl_ADDR                                         1909
+#define S_Ctrl_ADDR_END                                     1926
+#define S_Ctrl_sizeof                                       18
+#define S_Vibra1_in_ADDR                                    1927
+#define S_Vibra1_in_ADDR_END                                1932
+#define S_Vibra1_in_sizeof                                  6
+#define S_Vibra1_temp_ADDR                                  1933
+#define S_Vibra1_temp_ADDR_END                              1956
+#define S_Vibra1_temp_sizeof                                24
+#define S_VibraCtrl_forLeftSM_ADDR                          1957
+#define S_VibraCtrl_forLeftSM_ADDR_END                      1980
+#define S_VibraCtrl_forLeftSM_sizeof                        24
+#define S_Vibra1_mem_ADDR                                   1981
+#define S_Vibra1_mem_ADDR_END                               1991
+#define S_Vibra1_mem_sizeof                                 11
+#define S_VibraCtrl_Stereo_ADDR                             1992
+#define S_VibraCtrl_Stereo_ADDR_END                         2015
+#define S_VibraCtrl_Stereo_sizeof                           24
+#define S_AMIC_96_48_data_ADDR                              2016
+#define S_AMIC_96_48_data_ADDR_END                          2034
+#define S_AMIC_96_48_data_sizeof                            19
+#define S_DMIC0_96_48_data_ADDR                             2035
+#define S_DMIC0_96_48_data_ADDR_END                         2053
+#define S_DMIC0_96_48_data_sizeof                           19
+#define S_DMIC1_96_48_data_ADDR                             2054
+#define S_DMIC1_96_48_data_ADDR_END                         2072
+#define S_DMIC1_96_48_data_sizeof                           19
+#define S_DMIC2_96_48_data_ADDR                             2073
+#define S_DMIC2_96_48_data_ADDR_END                         2091
+#define S_DMIC2_96_48_data_sizeof                           19
+#define S_EANC_FBK_96_48_data_ADDR                          2092
+#define S_EANC_FBK_96_48_data_ADDR_END                      2110
+#define S_EANC_FBK_96_48_data_sizeof                        19
+#define S_DBG_8K_PATTERN_ADDR                               2111
+#define S_DBG_8K_PATTERN_ADDR_END                           2112
+#define S_DBG_8K_PATTERN_sizeof                             2
+#define S_DBG_16K_PATTERN_ADDR                              2113
+#define S_DBG_16K_PATTERN_ADDR_END                          2116
+#define S_DBG_16K_PATTERN_sizeof                            4
+#define S_DBG_24K_PATTERN_ADDR                              2117
+#define S_DBG_24K_PATTERN_ADDR_END                          2122
+#define S_DBG_24K_PATTERN_sizeof                            6
+#define S_DBG_48K_PATTERN_ADDR                              2123
+#define S_DBG_48K_PATTERN_ADDR_END                          2134
+#define S_DBG_48K_PATTERN_sizeof                            12
+#define S_DBG_96K_PATTERN_ADDR                              2135
+#define S_DBG_96K_PATTERN_ADDR_END                          2158
+#define S_DBG_96K_PATTERN_sizeof                            24
+#define S_MM_EXT_IN_ADDR                                    2159
+#define S_MM_EXT_IN_ADDR_END                                2170
+#define S_MM_EXT_IN_sizeof                                  12
+#define S_MM_EXT_IN_L_ADDR                                  2171
+#define S_MM_EXT_IN_L_ADDR_END                              2182
+#define S_MM_EXT_IN_L_sizeof                                12
+#define S_MM_EXT_IN_R_ADDR                                  2183
+#define S_MM_EXT_IN_R_ADDR_END                              2194
+#define S_MM_EXT_IN_R_sizeof                                12
+#define S_MIC4_ADDR                                         2195
+#define S_MIC4_ADDR_END                                     2206
+#define S_MIC4_sizeof                                       12
+#define S_MIC4_L_ADDR                                       2207
+#define S_MIC4_L_ADDR_END                                   2218
+#define S_MIC4_L_sizeof                                     12
+#define S_MIC4_R_ADDR                                       2219
+#define S_MIC4_R_ADDR_END                                   2230
+#define S_MIC4_R_sizeof                                     12
+#define S_HW_TEST_ADDR                                      2231
+#define S_HW_TEST_ADDR_END                                  2231
+#define S_HW_TEST_sizeof                                    1
+#endif/* _ABESM_ADDR_H_ */
diff --git a/sound/soc/omap/abe/abe_sys.h b/sound/soc/omap/abe/abe_sys.h
index 792638df38bd..08fee17f2baa 100644
--- a/sound/soc/omap/abe/abe_sys.h
+++ b/sound/soc/omap/abe/abe_sys.h
@@ -17,4 +17,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
- */
\ No newline at end of file
+ */
diff --git a/sound/soc/omap/abe/abe_taskid.h b/sound/soc/omap/abe/abe_taskid.h
index be152545e825..3b50f2b6d968 100644
--- a/sound/soc/omap/abe/abe_taskid.h
+++ b/sound/soc/omap/abe/abe_taskid.h
@@ -18,127 +18,124 @@
  * 02110-1301 USA
  *
  */
-
 #ifndef _ABE_TASKID_H_
 #define _ABE_TASKID_H_
-
-#define C_ABE_FW_TASK_DL1_APS_CORE                          0 
-#define C_ABE_FW_TASK_DL1_APS_COIL_CORE                     1 
-#define C_ABE_FW_TASK_DL2_L_APS_CORE                        2 
-#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE                   3 
-#define C_ABE_FW_TASK_DL2_R_APS_CORE                        4 
-#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE                   5 
-#define C_ABE_FW_TASK_ASRC_VX_DL_8                          6 
-#define C_ABE_FW_TASK_ASRC_VX_DL_16                         7 
-#define C_ABE_FW_TASK_ASRC_MM_DL                            8 
-#define C_ABE_FW_TASK_ASRC_VX_UL_8                          9 
-#define C_ABE_FW_TASK_ASRC_VX_UL_16                         10 
-#define C_ABE_FW_TASK_DC_REMOVAL                            11 
-#define C_ABE_FW_TASK_VX_UL_48_8_DEC                        12 
-#define C_ABE_FW_TASK_VX_UL_48_16_DEC                       13 
-#define C_ABE_FW_TASK_BT_DL_48_8_DEC                        14 
-#define C_ABE_FW_TASK_BT_DL_48_16_DEC                       15 
-#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC                     16 
-#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC                    17 
-#define C_ABE_FW_TASK_DL2_EQ                                18 
-#define C_ABE_FW_TASK_DL2_L_APS_IIR                         19 
-#define C_ABE_FW_TASK_DL2_R_APS_IIR                         20 
-#define C_ABE_FW_TASK_DL2_APS_EQ                            21 
-#define C_ABE_FW_TASK_ECHO_REF_48_16                        22 
-#define C_ABE_FW_TASK_ECHO_REF_48_8                         23 
-#define C_ABE_FW_TASK_GAIN_UPDATE                           24 
-#define C_ABE_FW_TASK_SideTone                              25 
-#define C_ABE_FW_TASK_VX_DL_8_48_LP                         26 
-#define C_ABE_FW_TASK_VX_DL_8_48_HP                         27 
-#define C_ABE_FW_TASK_VX_DL_16_48_LP                        28 
-#define C_ABE_FW_TASK_VX_DL_16_48_HP                        29 
-#define C_ABE_FW_TASK_VX_UL_48_8_LP                         30 
-#define C_ABE_FW_TASK_VX_UL_48_8_HP                         31 
-#define C_ABE_FW_TASK_VX_UL_48_16_LP                        32 
-#define C_ABE_FW_TASK_VX_UL_48_16_HP                        33 
-#define C_ABE_FW_TASK_BT_UL_8_48_LP                         34 
-#define C_ABE_FW_TASK_BT_UL_8_48_HP                         35 
-#define C_ABE_FW_TASK_BT_UL_16_48_LP                        36 
-#define C_ABE_FW_TASK_BT_UL_16_48_HP                        37 
-#define C_ABE_FW_TASK_BT_DL_48_8_LP                         38 
-#define C_ABE_FW_TASK_BT_DL_48_8_HP                         39 
-#define C_ABE_FW_TASK_BT_DL_48_16_LP                        40 
-#define C_ABE_FW_TASK_BT_DL_48_16_HP                        41 
-#define C_ABE_FW_TASK_ECHO_REF_48_8_LP                      42 
-#define C_ABE_FW_TASK_ECHO_REF_48_8_HP                      43 
-#define C_ABE_FW_TASK_ECHO_REF_48_16_LP                     44 
-#define C_ABE_FW_TASK_ECHO_REF_48_16_HP                     45 
-#define C_ABE_FW_TASK_DL1_EQ                                46 
-#define C_ABE_FW_TASK_DL1_APS_IIR                           47 
-#define C_ABE_FW_TASK_DL1_APS_EQ                            48 
-#define C_ABE_FW_TASK_IHF_48_96_LP                          49 
-#define C_ABE_FW_TASK_EARP_48_96_LP                         50 
-#define C_ABE_FW_TASK_DL1_GAIN                              51 
-#define C_ABE_FW_TASK_DL2_GAIN                              52 
-#define C_ABE_FW_TASK_IO_PING_PONG                          53 
-#define C_ABE_FW_TASK_IO_DMIC                               54 
-#define C_ABE_FW_TASK_IO_PDM_UL                             55 
-#define C_ABE_FW_TASK_IO_BT_VX_UL                           56 
-#define C_ABE_FW_TASK_IO_MM_UL                              57 
-#define C_ABE_FW_TASK_IO_MM_UL2                             58 
-#define C_ABE_FW_TASK_IO_VX_UL                              59 
-#define C_ABE_FW_TASK_IO_MM_DL                              60 
-#define C_ABE_FW_TASK_IO_VX_DL                              61 
-#define C_ABE_FW_TASK_IO_TONES_DL                           62 
-#define C_ABE_FW_TASK_IO_VIB_DL                             63 
-#define C_ABE_FW_TASK_IO_BT_VX_DL                           64 
-#define C_ABE_FW_TASK_IO_PDM_DL                             65 
-#define C_ABE_FW_TASK_IO_MM_EXT_OUT                         66 
-#define C_ABE_FW_TASK_IO_MM_EXT_IN                          67 
-#define C_ABE_FW_TASK_IO_TDM_OUT                            68 
-#define C_ABE_FW_TASK_IO_TDM_IN                             69 
-#define C_ABE_FW_TASK_DEBUG_IRQFIFO                         70 
-#define C_ABE_FW_TASK_EchoMixer                             71 
-#define C_ABE_FW_TASK_SDTMixer                              72 
-#define C_ABE_FW_TASK_DL1Mixer                              73 
-#define C_ABE_FW_TASK_DL2Mixer                              74 
-#define C_ABE_FW_TASK_VXRECMixer                            75 
-#define C_ABE_FW_TASK_ULMixer                               76 
-#define C_ABE_FW_TASK_VIBRA_PACK                            77 
-#define C_ABE_FW_TASK_VX_DL_8_48_0SR                        78 
-#define C_ABE_FW_TASK_VX_DL_16_48_0SR                       79 
-#define C_ABE_FW_TASK_BT_UL_8_48_0SR                        80 
-#define C_ABE_FW_TASK_BT_UL_16_48_0SR                       81 
-#define C_ABE_FW_TASK_IHF_48_96_0SR                         82 
-#define C_ABE_FW_TASK_EARP_48_96_0SR                        83 
-#define C_ABE_FW_TASK_AMIC_SPLIT                            84 
-#define C_ABE_FW_TASK_DMIC1_SPLIT                           85 
-#define C_ABE_FW_TASK_DMIC2_SPLIT                           86 
-#define C_ABE_FW_TASK_DMIC3_SPLIT                           87 
-#define C_ABE_FW_TASK_VXREC_SPLIT                           88 
-#define C_ABE_FW_TASK_BT_UL_SPLIT                           89 
-#define C_ABE_FW_TASK_MM_SPLIT                              90 
-#define C_ABE_FW_TASK_DL2_APS_SPLIT                         91 
-#define C_ABE_FW_TASK_VIBRA_SPLIT                           92 
-#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT                       93 
-#define C_ABE_FW_TASK_EANC_FBK_SPLIT                        94 
-#define C_ABE_FW_TASK_MIC4_SPLIT                            95 
-#define C_ABE_FW_TASK_VX_UL_ROUTING                         96 
-#define C_ABE_FW_TASK_MM_UL2_ROUTING                        97 
-#define C_ABE_FW_TASK_VIBRA1                                98 
-#define C_ABE_FW_TASK_VIBRA2                                99 
-#define C_ABE_FW_TASK_BT_UL_16_48                           100 
-#define C_ABE_FW_TASK_BT_UL_8_48                            101 
-#define C_ABE_FW_TASK_BT_DL_48_16                           102 
-#define C_ABE_FW_TASK_BT_DL_48_8                            103 
-#define C_ABE_FW_TASK_VX_DL_16_48                           104 
-#define C_ABE_FW_TASK_VX_DL_8_48                            105 
-#define C_ABE_FW_TASK_VX_UL_48_16                           106 
-#define C_ABE_FW_TASK_VX_UL_48_8                            107 
-#define C_ABE_FW_TASK_DBG_SYNC                              108 
-#define C_ABE_FW_TASK_APS_DL1_IRQs                          109 
-#define C_ABE_FW_TASK_APS_DL2_L_IRQs                        110 
-#define C_ABE_FW_TASK_APS_DL2_R_IRQs                        111 
-#define C_ABE_FW_TASK_AMIC_96_48_LP                         112 
-#define C_ABE_FW_TASK_DMIC1_96_48_LP                        113 
-#define C_ABE_FW_TASK_DMIC2_96_48_LP                        114 
-#define C_ABE_FW_TASK_DMIC3_96_48_LP                        115 
-#define C_ABE_FW_TASK_INIT_FW_MEMORY                        116 
-#define C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs                   117 
-
-#endif /* _ABE_TASKID_H_ */
+#define C_ABE_FW_TASK_DL1_APS_CORE                          0
+#define C_ABE_FW_TASK_DL1_APS_COIL_CORE                     1
+#define C_ABE_FW_TASK_DL2_L_APS_CORE                        2
+#define C_ABE_FW_TASK_DL2_L_APS_COIL_CORE                   3
+#define C_ABE_FW_TASK_DL2_R_APS_CORE                        4
+#define C_ABE_FW_TASK_DL2_R_APS_COIL_CORE                   5
+#define C_ABE_FW_TASK_ASRC_VX_DL_8                          6
+#define C_ABE_FW_TASK_ASRC_VX_DL_16                         7
+#define C_ABE_FW_TASK_ASRC_MM_EXT_IN                        8
+#define C_ABE_FW_TASK_ASRC_VX_UL_8                          9
+#define C_ABE_FW_TASK_ASRC_VX_UL_16                         10
+#define C_ABE_FW_TASK_DC_REMOVAL                            11
+#define C_ABE_FW_TASK_VX_UL_48_8_DEC                        12
+#define C_ABE_FW_TASK_VX_UL_48_16_DEC                       13
+#define C_ABE_FW_TASK_BT_DL_48_8_DEC                        14
+#define C_ABE_FW_TASK_BT_DL_48_16_DEC                       15
+#define C_ABE_FW_TASK_ECHO_REF_48_8_DEC                     16
+#define C_ABE_FW_TASK_ECHO_REF_48_16_DEC                    17
+#define C_ABE_FW_TASK_DL2_EQ                                18
+#define C_ABE_FW_TASK_DL2_L_APS_IIR                         19
+#define C_ABE_FW_TASK_DL2_R_APS_IIR                         20
+#define C_ABE_FW_TASK_DL2_APS_EQ                            21
+#define C_ABE_FW_TASK_ECHO_REF_48_16                        22
+#define C_ABE_FW_TASK_ECHO_REF_48_8                         23
+#define C_ABE_FW_TASK_GAIN_UPDATE                           24
+#define C_ABE_FW_TASK_SideTone                              25
+#define C_ABE_FW_TASK_VX_DL_8_48_LP                         26
+#define C_ABE_FW_TASK_VX_DL_8_48_HP                         27
+#define C_ABE_FW_TASK_VX_DL_16_48_LP                        28
+#define C_ABE_FW_TASK_VX_DL_16_48_HP                        29
+#define C_ABE_FW_TASK_VX_UL_48_8_LP                         30
+#define C_ABE_FW_TASK_VX_UL_48_8_HP                         31
+#define C_ABE_FW_TASK_VX_UL_48_16_LP                        32
+#define C_ABE_FW_TASK_VX_UL_48_16_HP                        33
+#define C_ABE_FW_TASK_BT_UL_8_48_LP                         34
+#define C_ABE_FW_TASK_BT_UL_8_48_HP                         35
+#define C_ABE_FW_TASK_BT_UL_16_48_LP                        36
+#define C_ABE_FW_TASK_BT_UL_16_48_HP                        37
+#define C_ABE_FW_TASK_BT_DL_48_8_LP                         38
+#define C_ABE_FW_TASK_BT_DL_48_8_HP                         39
+#define C_ABE_FW_TASK_BT_DL_48_16_LP                        40
+#define C_ABE_FW_TASK_BT_DL_48_16_HP                        41
+#define C_ABE_FW_TASK_ECHO_REF_48_8_LP                      42
+#define C_ABE_FW_TASK_ECHO_REF_48_8_HP                      43
+#define C_ABE_FW_TASK_ECHO_REF_48_16_LP                     44
+#define C_ABE_FW_TASK_ECHO_REF_48_16_HP                     45
+#define C_ABE_FW_TASK_DL1_EQ                                46
+#define C_ABE_FW_TASK_DL1_APS_IIR                           47
+#define C_ABE_FW_TASK_DL1_APS_EQ                            48
+#define C_ABE_FW_TASK_IHF_48_96_LP                          49
+#define C_ABE_FW_TASK_EARP_48_96_LP                         50
+#define C_ABE_FW_TASK_DL1_GAIN                              51
+#define C_ABE_FW_TASK_DL2_GAIN                              52
+#define C_ABE_FW_TASK_IO_PING_PONG                          53
+#define C_ABE_FW_TASK_IO_DMIC                               54
+#define C_ABE_FW_TASK_IO_PDM_UL                             55
+#define C_ABE_FW_TASK_IO_BT_VX_UL                           56
+#define C_ABE_FW_TASK_IO_MM_UL                              57
+#define C_ABE_FW_TASK_IO_MM_UL2                             58
+#define C_ABE_FW_TASK_IO_VX_UL                              59
+#define C_ABE_FW_TASK_IO_MM_DL                              60
+#define C_ABE_FW_TASK_IO_VX_DL                              61
+#define C_ABE_FW_TASK_IO_TONES_DL                           62
+#define C_ABE_FW_TASK_IO_VIB_DL                             63
+#define C_ABE_FW_TASK_IO_BT_VX_DL                           64
+#define C_ABE_FW_TASK_IO_PDM_DL                             65
+#define C_ABE_FW_TASK_IO_MM_EXT_OUT                         66
+#define C_ABE_FW_TASK_IO_MM_EXT_IN                          67
+#define C_ABE_FW_TASK_IO_TDM_OUT                            68
+#define C_ABE_FW_TASK_IO_TDM_IN                             69
+#define C_ABE_FW_TASK_DEBUG_IRQFIFO                         70
+#define C_ABE_FW_TASK_EchoMixer                             71
+#define C_ABE_FW_TASK_SDTMixer                              72
+#define C_ABE_FW_TASK_DL1Mixer                              73
+#define C_ABE_FW_TASK_DL2Mixer                              74
+#define C_ABE_FW_TASK_VXRECMixer                            75
+#define C_ABE_FW_TASK_ULMixer                               76
+#define C_ABE_FW_TASK_VIBRA_PACK                            77
+#define C_ABE_FW_TASK_VX_DL_8_48_0SR                        78
+#define C_ABE_FW_TASK_VX_DL_16_48_0SR                       79
+#define C_ABE_FW_TASK_BT_UL_8_48_0SR                        80
+#define C_ABE_FW_TASK_BT_UL_16_48_0SR                       81
+#define C_ABE_FW_TASK_IHF_48_96_0SR                         82
+#define C_ABE_FW_TASK_EARP_48_96_0SR                        83
+#define C_ABE_FW_TASK_AMIC_SPLIT                            84
+#define C_ABE_FW_TASK_DMIC1_SPLIT                           85
+#define C_ABE_FW_TASK_DMIC2_SPLIT                           86
+#define C_ABE_FW_TASK_DMIC3_SPLIT                           87
+#define C_ABE_FW_TASK_VXREC_SPLIT                           88
+#define C_ABE_FW_TASK_BT_UL_SPLIT                           89
+#define C_ABE_FW_TASK_MM_SPLIT                              90
+#define C_ABE_FW_TASK_DL2_APS_SPLIT                         91
+#define C_ABE_FW_TASK_VIBRA_SPLIT                           92
+#define C_ABE_FW_TASK_MM_EXT_IN_SPLIT                       93
+#define C_ABE_FW_TASK_EANC_FBK_SPLIT                        94
+#define C_ABE_FW_TASK_MIC4_SPLIT                            95
+#define C_ABE_FW_TASK_VX_UL_ROUTING                         96
+#define C_ABE_FW_TASK_MM_UL2_ROUTING                        97
+#define C_ABE_FW_TASK_VIBRA1                                98
+#define C_ABE_FW_TASK_VIBRA2                                99
+#define C_ABE_FW_TASK_BT_UL_16_48                           100
+#define C_ABE_FW_TASK_BT_UL_8_48                            101
+#define C_ABE_FW_TASK_BT_DL_48_16                           102
+#define C_ABE_FW_TASK_BT_DL_48_8                            103
+#define C_ABE_FW_TASK_VX_DL_16_48                           104
+#define C_ABE_FW_TASK_VX_DL_8_48                            105
+#define C_ABE_FW_TASK_VX_UL_48_16                           106
+#define C_ABE_FW_TASK_VX_UL_48_8                            107
+#define C_ABE_FW_TASK_DBG_SYNC                              108
+#define C_ABE_FW_TASK_APS_DL1_IRQs                          109
+#define C_ABE_FW_TASK_APS_DL2_L_IRQs                        110
+#define C_ABE_FW_TASK_APS_DL2_R_IRQs                        111
+#define C_ABE_FW_TASK_AMIC_96_48_LP                         112
+#define C_ABE_FW_TASK_DMIC1_96_48_LP                        113
+#define C_ABE_FW_TASK_DMIC2_96_48_LP                        114
+#define C_ABE_FW_TASK_DMIC3_96_48_LP                        115
+#define C_ABE_FW_TASK_INIT_FW_MEMORY                        116
+#define C_ABE_FW_TASK_DEBUGTRACE_VX_ASRCs                   117
+#endif/* _ABE_TASKID_H_ */
diff --git a/sound/soc/omap/abe/abe_typ.h b/sound/soc/omap/abe/abe_typ.h
index 76de2c370675..dde508485a72 100644
--- a/sound/soc/omap/abe/abe_typ.h
+++ b/sound/soc/omap/abe/abe_typ.h
@@ -18,53 +18,40 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #include "abe_def.h"
 #include "abe_initxxx_labels.h"
-
 #ifndef ABETYP
 #define ABETYP
-
-
 /*
  * BASIC TYPES
  */
 #define MAX_UINT8	((((1L <<  7) -1)<<1) +1)
 #define MAX_UINT16	((((1L << 15) -1)<<1) +1)
 #define MAX_UINT32	((((1L << 31) -1)<<1) +1)
-
 #define s8 char
 #define u8 unsigned char
 #define s16 short
 #define u16 unsigned short
 #define s32 int
 #define u32 unsigned int
-
 /* returned status from HAL APIs */
 #define abehal_status u32
-
 /* 4 bytes    Bit field indicating the type of informations to be traced */
-typedef u32  abe_dbg_mask_t;
-
-/* scheduling task loops (250us / 272us with respectively 48kHz / 
+typedef u32 abe_dbg_mask_t;
+/* scheduling task loops (250us / 272us with respectively 48kHz /
 	44.1kHz on Phoenix). */
-typedef u32   abe_dbg_t;
-
+typedef u32 abe_dbg_t;
 /* Index to the table of sequences */
-typedef u32  abe_seq_code_t;
-
+typedef u32 abe_seq_code_t;
 /* Index to the table of subroutines called in the sequence */
-typedef u32  abe_sub_code_t;
-
+typedef u32 abe_sub_code_t;
 /* subroutine with no parameter */
-typedef void (* abe_subroutine0) (void);
-
+typedef void (*abe_subroutine0) (void);
 /* subroutine with one parameter */
-typedef void (* abe_subroutine1) (u32);
-typedef void (* abe_subroutine2) (u32, u32);
-typedef void (* abe_subroutine3) (u32, u32, u32);
-typedef void (* abe_subroutine4) (u32, u32, u32, u32);
-
+typedef void (*abe_subroutine1) (u32);
+typedef void (*abe_subroutine2) (u32, u32);
+typedef void (*abe_subroutine3) (u32, u32, u32);
+typedef void (*abe_subroutine4) (u32, u32, u32, u32);
 /*
  *      CODE PORTABILITY - FUTURE PATCHES
  *
@@ -73,11 +60,9 @@ typedef void (* abe_subroutine4) (u32, u32, u32, u32);
  * 	partitionning. Used for the highest level APIs (launch_sequences)
  */
 typedef u32 abe_patch_rev;
-
 /*
  * ENUMS
  */
-
 /*
  *      MEMORY CONFIG TYPE
  *
@@ -86,7 +71,6 @@ typedef u32 abe_patch_rev;
  *         2: OPP 50% (multimedia and voice calls)
  *         3: OPP100% (multimedia complex use-cases)
  */
-
 #define ABE_AUDIO_PLAYER_ON_HEADSET_OR_EARPHONE 1
 #define ABE_DRIFT_MANAGEMENT_FOR_AUDIO_PLAYER 2
 #define ABE_DRIFT_MANAGEMENT_FOR_VOICE_CALL 3
@@ -97,8 +81,6 @@ typedef u32 abe_patch_rev;
 #define ABE_RINGER_TONES 8
 #define ABE_VOICE_CALL_WITH_EARPHONE_ACTIVE_NOISE_CANCELLER 9
 #define ABE_LAST_USE_CASE 10
-
-
 /*
  *      OPP TYPE
  *
@@ -111,7 +93,6 @@ typedef u32 abe_patch_rev;
 #define ABE_OPP25 1
 #define ABE_OPP50 2
 #define ABE_OPP100 3
-
 /*
  *      DMIC DECIMATION RATIO
  *
@@ -120,13 +101,11 @@ typedef u32 abe_patch_rev;
 #define ABE_DEC25 25
 #define ABE_DEC32 32
 #define ABE_DEC40 40
-
-
 /*
  *      SAMPLES TYPE
  *
  *    mono 16bits sample LSB aligned, 16 MSB bits are unused
- *    mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP 
+ *    mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
  *	TX purpose.
  *    mono sample MSB aligned (16/24/32bits)
  *      two successive mono samples in one 32bits container
@@ -150,7 +129,6 @@ typedef u32 abe_patch_rev;
 #define EIGHT_MSB 11
 #define NINE_MSB 12
 #define TEN_MSB 13
-
 /*
  *      PORT PROTOCOL TYPE - abe_port_protocol_switch_id
  */
@@ -162,8 +140,6 @@ typedef u32 abe_patch_rev;
 #define MCPDMUL_PORT_PROT 6
 #define PINGPONG_PORT_PROT 7
 #define DMAREQ_PORT_PROT 8
-
-
 /*
  *      PORT IDs, this list is aligned with the FW data mapping
  */
@@ -185,20 +161,18 @@ typedef u32 abe_patch_rev;
 #define TDM_UL_PORT 15
 #define DEBUG_PORT 16
 #define LAST_PORT_ID 17
-
-
 /* definitions for the compatibility with HAL05xx */
-#define PDM_DL1_PORT PDM_DL_PORT
-#define PDM_DL2_PORT PDM_DL_PORT
-#define PDM_VIB_PORT PDM_DL_PORT
+#define PDM_DL1_PORT 18
+#define PDM_DL2_PORT 19
+#define PDM_VIB_PORT 20
+/* There is only one DMIC port, always used with 6 samples
+   per 96kHz periods */
 #define DMIC_PORT1 DMIC_PORT
 #define DMIC_PORT2 DMIC_PORT
 #define DMIC_PORT3 DMIC_PORT
-
 /*
  *      ABE_DL_SRC_ID     source of samples
  */
-
 #define SRC_DL1_MIXER_OUTPUT DL1_M_labelID
 #define SRC_SDT_MIXER_OUTPUT SDT_M_labelID
 #define SRC_DL1_GAIN_OUTPUT DL1_GAIN_out_labelID
@@ -211,12 +185,10 @@ typedef u32 abe_patch_rev;
 #define SRC_VX_UL VX_UL_labelID
 #define SRC_MM_UL2 MM_UL2_labelID
 #define SRC_MM_UL MM_UL_labelID
-
 /*
  *      abe_patched_pattern_id     selection of the audio engine signal to
  *	replace by a precomputed pattern
  */
-
 #define DBG_PATCH_AMIC 1
 #define DBG_PATCH_DMIC1 2
 #define DBG_PATCH_DMIC2 3
@@ -231,121 +203,89 @@ typedef u32 abe_patch_rev;
 #define DBG_PATCH_MIC4 12
 #define DBG_PATCH_MM_DL_MIXDL1 13
 #define DBG_PATCH_MM_DL_MIXDL2 14
-
 /*
  *      Signal processing module names - EQ APS MIX ROUT
  */
-
 /* equalizer downlink path headset + earphone */
 #define FEAT_EQ1            1
-
 /* equalizer downlink path integrated handsfree LEFT */
-#define FEAT_EQ2L           FEAT_EQ1+1
-
+#define FEAT_EQ2L           (FEAT_EQ1+1)
 /* equalizer downlink path integrated handsfree RIGHT */
-#define FEAT_EQ2R           FEAT_EQ2L+1
-
+#define FEAT_EQ2R           (FEAT_EQ2L+1)
 /* equalizer downlink path side-tone */
-#define FEAT_EQSDT          FEAT_EQ2R+1
-
-/* equalizer uplink path MIC pair */
-#define FEAT_EQMIC          FEAT_EQSDT+1
-
+#define FEAT_EQSDT          (FEAT_EQ2R+1)
+/* equalizer uplink path AMIC */
+#define FEAT_EQAMIC         (FEAT_EQSDT+1)
+/* equalizer uplink path DMIC */
+#define FEAT_EQDMIC         (FEAT_EQAMIC+1)
 /* Acoustic protection for headset */
-#define FEAT_APS1           FEAT_EQMIC+1
-
+#define FEAT_APS1           (FEAT_EQDMIC+1)
 /* acoustic protection high-pass filter for handsfree "Left" */
-#define FEAT_APS2           FEAT_APS1+1
-
+#define FEAT_APS2           (FEAT_APS1+1)
 /* acoustic protection high-pass filter for handsfree "Right" */
-#define FEAT_APS3           FEAT_APS2+1
-
+#define FEAT_APS3           (FEAT_APS2+1)
 /* asynchronous sample-rate-converter for the downlink voice path */
-#define FEAT_ASRC1          FEAT_APS3+1
-
+#define FEAT_ASRC1          (FEAT_APS3+1)
 /* asynchronous sample-rate-converter for the uplink voice path */
-#define FEAT_ASRC2          FEAT_ASRC1+1
-
+#define FEAT_ASRC2          (FEAT_ASRC1+1)
 /* asynchronous sample-rate-converter for the multimedia player */
-#define FEAT_ASRC3          FEAT_ASRC2+1
-
+#define FEAT_ASRC3          (FEAT_ASRC2+1)
 /* asynchronous sample-rate-converter for the echo reference */
-#define FEAT_ASRC4          FEAT_ASRC3+1
-
+#define FEAT_ASRC4          (FEAT_ASRC3+1)
 /* mixer of the headset and earphone path */
-#define FEAT_MIXDL1         FEAT_ASRC4+1
-
+#define FEAT_MIXDL1         (FEAT_ASRC4+1)
 /* mixer of the hands-free path */
-#define FEAT_MIXDL2         FEAT_MIXDL1+1
-
+#define FEAT_MIXDL2         (FEAT_MIXDL1+1)
 /* mixer for audio being sent on the voice_ul path */
-#define FEAT_MIXAUDUL       FEAT_MIXDL2+1
-
+#define FEAT_MIXAUDUL       (FEAT_MIXDL2+1)
 /* mixer for voice communication recording */
-#define FEAT_MIXVXREC       FEAT_MIXAUDUL+1
-
+#define FEAT_MIXVXREC       (FEAT_MIXAUDUL+1)
 /* mixer for side-tone */
-#define FEAT_MIXSDT         FEAT_MIXVXREC+1
-
+#define FEAT_MIXSDT         (FEAT_MIXVXREC+1)
 /* mixer for echo reference */
-#define FEAT_MIXECHO        FEAT_MIXSDT+1
-
+#define FEAT_MIXECHO        (FEAT_MIXSDT+1)
 /* router of the uplink path */
-#define FEAT_UPROUTE        FEAT_MIXECHO+1
-
+#define FEAT_UPROUTE        (FEAT_MIXECHO+1)
 /* all gains */
-#define FEAT_GAINS          FEAT_UPROUTE+1
-#define FEAT_GAINS_DMIC1    FEAT_GAINS+1
-#define FEAT_GAINS_DMIC2    FEAT_GAINS_DMIC1+1
-#define FEAT_GAINS_DMIC3    FEAT_GAINS_DMIC2+1
-#define FEAT_GAINS_AMIC     FEAT_GAINS_DMIC3+1
-#define FEAT_GAINS_SPLIT    FEAT_GAINS_AMIC+1
-#define FEAT_GAINS_DL1      FEAT_GAINS_SPLIT+1
-#define FEAT_GAINS_DL2      FEAT_GAINS_DL1+1
-#define FEAT_GAIN_EANC      FEAT_GAINS_DL2+1
-
+#define FEAT_GAINS          (FEAT_UPROUTE+1)
+#define FEAT_GAINS_DMIC1    (FEAT_GAINS+1)
+#define FEAT_GAINS_DMIC2    (FEAT_GAINS_DMIC1+1)
+#define FEAT_GAINS_DMIC3    (FEAT_GAINS_DMIC2+1)
+#define FEAT_GAINS_AMIC     (FEAT_GAINS_DMIC3+1)
+#define FEAT_GAINS_SPLIT    (FEAT_GAINS_AMIC+1)
+#define FEAT_GAINS_DL1      (FEAT_GAINS_SPLIT+1)
+#define FEAT_GAINS_DL2      (FEAT_GAINS_DL1+1)
+#define FEAT_GAIN_EANC      (FEAT_GAINS_DL2+1)
 /* sequencing queue of micro tasks */
-#define FEAT_SEQ            FEAT_GAIN_EANC+1
-
+#define FEAT_SEQ            (FEAT_GAIN_EANC+1)
 /* Phoenix control queue through McPDM */
-#define FEAT_CTL            FEAT_SEQ+1
-
+#define FEAT_CTL            (FEAT_SEQ+1)
 /* list of features of the firmware -------------------------------*/
 #define MAXNBFEATURE    FEAT_CTL
-
 /* abe_equ_id */
 /* equalizer downlink path headset + earphone */
 #define EQ1 FEAT_EQ1
-
 /* equalizer downlink path integrated handsfree LEFT */
 #define EQ2L FEAT_EQ2L
 #define EQ2R FEAT_EQ2R
-
 /* equalizer downlink path side-tone */
-#define EQSDT FEAT_EQSDT
-#define EQMIC FEAT_EQMIC
-
-
+#define EQSDT  FEAT_EQSDT
+#define EQAMIC FEAT_EQAMIC
+#define EQDMIC FEAT_EQDMIC
 /* abe_aps_id */
 /* Acoustic protection for headset */
 #define APS1 FEAT_APS1
 #define APS2L FEAT_APS2
 #define APS2R FEAT_APS3
-
 /* abe_asrc_id */
 /* asynchronous sample-rate-converter for the downlink voice path */
 #define ASRC1 FEAT_ASRC1
-
 /* asynchronous sample-rate-converter for the uplink voice path */
 #define ASRC2 FEAT_ASRC2
-
 /* asynchronous sample-rate-converter for the multimedia player */
 #define ASRC3 FEAT_ASRC3
-
 /* asynchronous sample-rate-converter for the voice uplink echo_reference */
 #define ASRC4 FEAT_ASRC4
-
-
 /* abe_mixer_id */
 #define MIXDL1 FEAT_MIXDL1
 #define MIXDL2 FEAT_MIXDL2
@@ -354,12 +294,9 @@ typedef u32 abe_patch_rev;
 #define MIXEANC FEAT_GAIN_EANC
 #define MIXAUDUL FEAT_MIXAUDUL
 #define MIXVXREC FEAT_MIXVXREC
-
 /* abe_router_id */
 /* there is only one router up to now */
 #define UPROUTE  FEAT_UPROUTE
-
-
 /*
  *      GAIN IDs
  */
@@ -371,27 +308,20 @@ typedef u32 abe_patch_rev;
 #define GAINS_DL1       FEAT_GAINS_DL1
 #define GAINS_DL2       FEAT_GAINS_DL2
 #define GAINS_EANC      FEAT_GAIN_EANC
-
-
 /*
  *      EVENT GENERATORS - abe_event_id
  */
 #define EVENT_TIMER 0
 #define EVENT_44100 1
-
-
 /*
  *      SERIAL PORTS IDs - abe_mcbsp_id
  */
-
 #define MCBSP1_TX MCBSP1_DMA_TX
 #define MCBSP1_RX MCBSP1_DMA_RX
 #define MCBSP2_TX MCBSP2_DMA_TX
 #define MCBSP2_RX MCBSP2_DMA_RX
 #define MCBSP3_TX MCBSP3_DMA_TX
 #define MCBSP3_RX MCBSP3_DMA_RX
-
-
 /*
  *      SERIAL PORTS IDs - abe_slimbus_id;
  */
@@ -412,31 +342,24 @@ typedef u32 abe_patch_rev;
 #define SLIMBUS1_RX6  SLIMBUS1_DMA_RX6
 #define SLIMBUS1_RX7  SLIMBUS1_DMA_RX7
 #define SLIMBUS_UNUSED  _DUMMY_FIFO_
-
-
 /*
  *      ---------------------------------   TYPES USED FOR APIS  ---------------
  */
 /*
  *      HARDWARE CONFIG TYPE
  */
-typedef struct  {
+typedef struct {
 	/* EVENT_GENERATOR_COUNTER_DEFAULT gives about 96kHz */
 	u32 AESS_EVENT_GENERATOR_COUNTER__COUNTER_VALUE;
-
 	/* 0: DMAreq, 1:Counter */
 	u32 AESS_EVENT_SOURCE_SELECTION__SELECTION;
-
 	/* 5bits DMAreq selection */
 	u32 AESS_AUDIO_ENGINE_SCHEDULER__DMA_REQ_SELECTION;
 	u32 HAL_EVENT_SELECTION;
-
 	/* 0: 96kHz   1:192kHz */
 	u32 MCPDM_CTRL__DIV_SEL;
-
-	/* 0: no command in the FIFO,  1: 6 data on each lines (with commands)*/
+	/* 0: no command in the FIFO,  1: 6 data on each lines (with commands) */
 	u32 MCPDM_CTRL__CMD_INT;
-
 	/* 0:MSB aligned  1:LSB aligned */
 	u32 MCPDM_CTRL__PDMOUTFORMAT;
 	u32 MCPDM_CTRL__PDM_DN5_EN;
@@ -449,89 +372,68 @@ typedef struct  {
 	u32 MCPDM_CTRL__PDM_UP1_EN;
 	u32 MCPDM_FIFO_CTRL_DN__DN_TRESH;
 	u32 MCPDM_FIFO_CTRL_UP__UP_TRESH;
-
 	/* 0:2.4MHz  1:3.84MHz */
 	u32 DMIC_CTRL__DMIC_CLK_DIV;
-
 	/* 0:MSB aligned  1:LSB aligned */
 	u32 DMIC_CTRL__DMICOUTFORMAT;
 	u32 DMIC_CTRL__DMIC_UP3_EN;
 	u32 DMIC_CTRL__DMIC_UP2_EN;
 	u32 DMIC_CTRL__DMIC_UP1_EN;
-
 	/* 1*(DMIC_UP1_EN+ 2+ 3)*2 OCP read access every 96/88.1 KHz. */
 	u32 DMIC_FIFO_CTRL__DMIC_TRESH;
-
 	/* 1:MSB  2:LSB aligned */
 	u32 MCBSP_SPCR1_REG__RJUST;
-
 	/* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
 	u32 MCBSP_THRSH2_REG_REG__XTHRESHOLD;
-
 	/* 1=MONO, 2=STEREO, 3=TDM_3_CHANNELS, 4=TDM_4_CHANNELS, .... */
 	u32 MCBSP_THRSH1_REG_REG__RTHRESHOLD;
-
 	u32 SLIMBUS_DCT_FIFO_SETUP_REG__SB_THRESHOLD;
-
-}  abe_hw_config_init_t;
-
-
+} abe_hw_config_init_t;
 /*
  *      EQU_T
  *
  *      coefficients of the equalizer
  */
-typedef struct  {
+typedef struct {
 	/* type of filter */
 	u32 equ_type;
-
 	/* filter length */
 	u32 equ_length;
 	union {
 		/* parameters are the direct and recursive coefficients in */
-
 		/* Q6.26 integer fixed-point format. */
-		s32 type1 [NBEQ1];
+		s32 type1[NBEQ1];
 		struct {
 			/* center frequency of the band [Hz] */
-			s32 freq [NBEQ2];
-
-			/* gain of each band. [dB]*/
-			s32 gain [NBEQ2];
-
+			s32 freq[NBEQ2];
+			/* gain of each band. [dB] */
+			s32 gain[NBEQ2];
 			/* Q factor of this band [dB] */
-			s32 q    [NBEQ2];
+			s32 q[NBEQ2];
 		} type2;
 	} coef;
 	s32 equ_param3;
-} abe_equ_t ;
-
+} abe_equ_t;
 /*
  *      APS_T
  *
  *      coefficients of the Acoustics Protection and Safety
  */
-typedef struct  {
-	s32 coef1 [NBAPS1];
-	s32 coef2 [NBAPS2];
+typedef struct {
+	s32 coef1[NBAPS1];
+	s32 coef2[NBAPS2];
 } abe_aps_t;
-
-typedef struct  {
+typedef struct {
 	/* structure of two energy_t estimation for coil and membrane */
 	u32 e1;
 	u32 e2;
 } abe_aps_energy_t;
-
-
-
 /*
  *      ROUTER_T
  *
  *      table of indexes in unsigned bytes
  */
 typedef u16 abe_router_t;
-
-
 /*
  *      DATA_FORMAT_T
  *
@@ -540,21 +442,17 @@ typedef u16 abe_router_t;
 typedef struct {
 	/* Sampling frequency of the stream */
 	u32 f;
-
 	/* Sample format type  */
 	u32 samp_format;
 } abe_data_format_t;
-
 /*
  *      PORT_PROTOCOL_T
  *
  *      port declaration
  */
-typedef struct  {
-
+typedef struct {
 	/* Direction=0 means input from AESS point of view */
 	u32 direction;
-
 	/* Protocol type (switch) during the data transfers */
 	u32 protocol_switch;
 	union {
@@ -562,155 +460,114 @@ typedef struct  {
 		struct {
 			/* Address of ATC Slimbus descriptor's index */
 			u32 desc_addr1;
-
-			/* Second ATC index for SlimBus reception (or NULL) */
-			u32 desc_addr2;
-
 			/* DMEM address 1 in bytes */
 			u32 buf_addr1;
-
-			/* DMEM address 2 in bytes */
-			u32 buf_addr2;
-
 			/* DMEM buffer size size in bytes */
 			u32 buf_size;
-
 			/* ITERation on each DMAreq signals */
 			u32 iter;
+			/* Second ATC index for SlimBus reception (or NULL) */
+			u32 desc_addr2;
+			/* DMEM address 2 in bytes */
+			u32 buf_addr2;
 		} prot_slimbus;
-
 		/* McBSP/McASP peripheral connected to ATC */
 		struct {
-
 			u32 desc_addr;
-
 			/* Address of ATC McBSP/McASP descriptor's in bytes */
 			u32 buf_addr;
-
 			/* DMEM address in bytes */
 			u32 buf_size;
-
 			/* ITERation on each DMAreq signals */
 			u32 iter;
 		} prot_serial;
-
 		/* DMIC peripheral connected to ATC */
-		struct {
+		struct	{
 			/* DMEM address in bytes */
 			u32 buf_addr;
-
 			/* DMEM buffer size in bytes */
 			u32 buf_size;
-
 			/* Number of activated DMIC */
 			u32 nbchan;
 		} prot_dmic;
-
 		/* McPDMDL peripheral connected to ATC */
 		struct {
 			/* DMEM address in bytes */
 			u32 buf_addr;
-
 			/* DMEM size in bytes */
 			u32 buf_size;
-
 			/* Control allowed on McPDM DL */
 			u32 control;
 		} prot_mcpdmdl;
-
 		/* McPDMUL peripheral connected to ATC */
 		struct {
 			/* DMEM address size in bytes */
 			u32 buf_addr;
-
 			/* DMEM buffer size size in bytes */
 			u32 buf_size;
 		} prot_mcpdmul;
-
 		/* Ping-Pong interface to the Host using cache-flush */
 		struct {
 			/* Address of ATC descriptor's */
 			u32 desc_addr;
-
 			/* DMEM buffer base address in bytes */
 			u32 buf_addr;
-
 			/* DMEM size in bytes for each ping and pong buffers */
 			u32 buf_size;
-
 			/* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
 			u32 irq_addr;
-
 			/* IRQ data content loaded in the AESS IRQ register */
 			u32 irq_data;
-
 			/* Call-back function upon IRQ reception */
 			u32 callback;
 		} prot_pingpong;
-
 		/* DMAreq line to CBPr */
 		struct {
 			/* Address of ATC descriptor's */
 			u32 desc_addr;
-
 			/* DMEM buffer address in bytes */
 			u32 buf_addr;
-
 			/* DMEM buffer size size in bytes */
 			u32 buf_size;
-
 			/* ITERation on each DMAreq signals */
 			u32 iter;
-
 			/* DMAreq address */
 			u32 dma_addr;
-
 			/* DMA/AESS = 1 << #DMA */
 			u32 dma_data;
 		} prot_dmareq;
-
 		/* Circular buffer - direct addressing to DMEM */
 		struct {
 			/* DMEM buffer base address in bytes */
 			u32 buf_addr;
-
 			/* DMEM buffer size in bytes */
 			u32 buf_size;
-
 			/* DMAreq address */
 			u32 dma_addr;
-
 			/* DMA/AESS = 1 << #DMA */
 			u32 dma_data;
 		} prot_circular_buffer;
 	} p;
 } abe_port_protocol_t;
-
-
-
 /*
  *      DMA_T
  *
  *      dma structure for easing programming
  */
-typedef struct  {
+typedef struct {
 	/* OCP L3 pointer to the first address of the */
 	void *data;
 	/* destination buffer (either DMA or Ping-Pong read/write pointers). */
 	/* address L3 when addressing the DMEM buffer instead of CBPr */
 	void *l3_dmem;
-
 	/* address L3 translated to L4 the ARM memory space */
 	void *l4_dmem;
-
 	/* number of iterations for the DMA data moves. */
 	u32 iter;
 } abe_dma_t;
-
-typedef struct  {
+typedef struct {
 	/* Offset to the first address of the */
 	u32 data;
-
 	/* number of iterations for the DMA data moves. */
 	u32 iter;
 } abe_dma_t_offset;
@@ -719,118 +576,94 @@ typedef struct  {
  *
  *      struct {
  *      micros_t time;          Waiting time before executing next line
- *      seq_code_t code         Subroutine index interpreted in the HAL and 
+ *      seq_code_t code         Subroutine index interpreted in the HAL and
  *				translated to
  *                                FW subroutine codes in case of ABE tasks
  *      int32 param[2]          Two parameters
  *      } seq_t
  *
  */
-typedef struct  {
+typedef struct {
 	u32 delta_time;
 	u32 code;
 	u32 param[4];
 	u8 tag;
 } abe_seq_t;
-
-typedef struct  {
+typedef struct {
 	u32 mask;
 	abe_seq_t seq1;
 	abe_seq_t seq2;
 } abe_sequence_t;
-
-
 /*
  *      DRIFT_T abe_drift_t = s32
  *
  *      ASRC drift parameter in [ppm] value
  */
-
 /*
  *      ---------------------------------   INTERNAL DATA TYPES  ---------------------
  */
-
-
 /*
  *      ABE_IRQ_DATA_T
  *
  *      IRQ FIFO content declaration
- *      APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16], 
+ *      APS interrupts : IRQtag_APS to [31:28], APS_IRQs to [27:16],
  *		loopCounter to [15:0]
- *      SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16], 
+ *      SEQ interrupts : IRQtag_COUNT to [31:28], Count_IRQs to [27:16],
  *		loopCounter to [15:0]
- *      Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16], 
+ *      Ping-Pong Interrupts : IRQtag_PP to [31:28], PP_MCU_IRQ to [27:16],
  *		loopCounter to [15:0]
  */
-typedef struct  {
+typedef struct {
 	unsigned int counter:16;
 	unsigned int data:12;
 	unsigned int tag:4;
 } abe_irq_data_t;
-
-
 /*
- *      ABE_PORT_T status / format / sampling / protocol(call_back) / features / 
+ *      ABE_PORT_T status / format / sampling / protocol(call_back) / features /
  *	gain / name ..
  *
  */
-
-typedef struct  {
+typedef struct {
 	/* running / idled */
-	u16  status;
-
+	u16 status;
 	/* Sample format type  */
 	abe_data_format_t format;
-
 	/* API : for ASRC */
 	s32 drift;
-
 	/* optionnal call-back index for errors and ack */
 	u16 callback;
-
 	/* IO tasks buffers */
 	u16 smem_buffer1;
 	u16 smem_buffer2;
 	abe_port_protocol_t protocol;
-
 	/* pointer and iteration counter of the xDMA */
 	abe_dma_t_offset dma;
-
 	/* list of features associated to a port (EQ, APS, ... , ends with 0) */
-	u16 feature_index [MAXFEATUREPORT];
+	u16 feature_index[MAXFEATUREPORT];
 	char name[NBCHARPORTNAME];
 } abe_port_t;
-
-
-
-
 /*
  *      ABE_SUBROUTINE_T
  *
  */
-
-typedef struct  {
+typedef struct {
 	u32 sub_id;
 	s32 param[4];
-} abe_subroutine_t ;
-
+} abe_subroutine_t;
 /*
  *      ABE_PORT_INFO_T    OPP, subroutines to call on reset
  *
  */
-
-typedef struct  {
-	u32  min_opp;
+typedef struct {
+	u32 min_opp;
 	abe_subroutine_t sub1;
 	abe_subroutine_t sub2;
 } abe_port_info_t;
-
 /*
  *      ABE_FEATURE_T
  *
  */
-
-typedef struct  {
+typedef struct {
 	u16 enable_with_default_data;
 	u16 disable_feature;
 	u16 read_parameter;
@@ -840,11 +673,7 @@ typedef struct  {
 	u16 fw_output_buffer_address;
 	u16 fw_scheduler_slot_position;
 	u16 fw_scheduler_subslot_position;
-	u32  min_opp;
+	u32 min_opp;
 	char name[NBCHARFEATURENAME];
 } abe_feature_t;
-
-
-
-
-#endif /* ifndef ABETYP */
+#endif/* ifndef ABETYP */
diff --git a/sound/soc/omap/abe/abe_typedef.h b/sound/soc/omap/abe/abe_typedef.h
index 347145b84b39..d19993f890fd 100644
--- a/sound/soc/omap/abe/abe_typedef.h
+++ b/sound/soc/omap/abe/abe_typedef.h
@@ -18,11 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  * 02110-1301 USA
  */
-
 #ifndef _ABE_TYPEDEF_H_
 #define _ABE_TYPEDEF_H_
-
-
 #include "abe_define.h"
 /*
  * Basic types definition
@@ -33,332 +30,234 @@ typedef unsigned short ABE_uint16;
 typedef short ABE_int16;
 typedef long ABE_int32;
 typedef unsigned long ABE_uint32;
-
-typedef ABE_uchar* pABE_uchar;
-typedef ABE_char* pABE_char;
-typedef ABE_uint16* pABE_uint16;
-typedef ABE_int16* pABE_int16;
-typedef ABE_int32* pABE_int32;
-typedef ABE_uint32* pABE_uint32;
-
-
+typedef ABE_uchar *pABE_uchar;
+typedef ABE_char *pABE_char;
+typedef ABE_uint16 *pABE_uint16;
+typedef ABE_int16 *pABE_int16;
+typedef ABE_int32 *pABE_int32;
+typedef ABE_uint32 *pABE_uint32;
 #ifdef __chess__
 typedef struct abeatcdescTag {
 	unsigned long a;
 	unsigned long b;
 } ABE_SAtcDescriptor;
-typedef void (*pABE_voidFunction)()clobbers(R0, R1, R2, R3, R4, 
-	R5, R6, R7, R13);
-typedef void (*pABE_voidFunctionsList[])()clobbers(R0, R1, R2, R3, R4, 
-	R5, R6, R7, R13);
-typedef void (*pABE_cmdFunction)() clobbers(R0, R1, R2, R3, R4, 
-	R5, R6, R7, R13);
-typedef void (*pABE_cmdFunctionsList[])() clobbers(R0, R1, R2, R3, R4, 
-	R5, R6, R7, R13);
-typedef void (*pABE_copyFunction)(ABE_uint16 chess_storage(R13))
-	clobbers(R13);
-typedef void (*pABE_copyFunctionsList[])(ABE_uint16 chess_storage(R13))
-	clobbers(R13);
+typedef void (*pABE_voidFunction) () clobbers(R0, R1, R2, R3, R4,
+					      R5, R6, R7, R13);
+typedef void (*pABE_voidFunctionsList[]) () clobbers(R0, R1, R2, R3, R4,
+						     R5, R6, R7, R13);
+typedef void (*pABE_cmdFunction) () clobbers(R0, R1, R2, R3, R4,
+					     R5, R6, R7, R13);
+typedef void (*pABE_cmdFunctionsList[]) () clobbers(R0, R1, R2, R3, R4,
+						    R5, R6, R7, R13);
+typedef void (*pABE_copyFunction) (ABE_uint16 chess_storage(R13)) clobbers(R13);
+typedef void (*pABE_copyFunctionsList[]) (ABE_uint16 chess_storage(R13))
+clobbers(R13);
 #endif
 /*
  * Commonly used structures
  */
 typedef struct abetaskTag {
 	/* 0 ... Index of called function */
-	ABE_uint16 iF; 
-	
+	ABE_uint16 iF;
 	/* 2 ... for INITPTR of A0 */
-	ABE_uint16 A0; 
-	
+	ABE_uint16 A0;
 	/* 4 ... for INITPTR of A1 */
-	ABE_uint16 A1; 
-	
+	ABE_uint16 A1;
 	/* 6 ... for INITPTR of A2 & A3 */
-	ABE_uint16 A2_3; 
-	
+	ABE_uint16 A2_3;
 	/* 8 ... for INITPTR of A4 & A5 */
-	ABE_uint16 A4_5; 
-	
+	ABE_uint16 A4_5;
 	/* 10 ... for INITREG of R0, R1, R2, R3 */
-	ABE_uint16 R; 
-	
+	ABE_uint16 R;
 	/* 12 */
-	ABE_uint16 misc0; 
-	
+	ABE_uint16 misc0;
 	/* 14 */
-	ABE_uint16 misc1; 
+	ABE_uint16 misc1;
 } ABE_STask;
-typedef ABE_STask* pABE_STask;
-typedef ABE_STask** ppABE_STask;
-
+typedef ABE_STask *pABE_STask;
+typedef ABE_STask **ppABE_STask;
 typedef struct {
 	/* 0 */
-	ABE_uint16 drift_ASRC; 
-	
+	ABE_uint16 drift_ASRC;
 	/* 2 */
-	ABE_uint16 drift_io; 
-	
+	ABE_uint16 drift_io;
 	/* 4 "Function index" of XLS sheet "Functions" */
-	ABE_uchar io_type_idx; 
-	
+	ABE_uchar io_type_idx;
 	/* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
-	ABE_uchar samp_size; 
-	
+	ABE_uchar samp_size;
 	/* 6 drift "issues" for ASRC */
-	ABE_int16 flow_counter; 
-
+	ABE_int16 flow_counter;
 	/* 8 address for IRQ or DMArequests */
-	ABE_uint16 hw_ctrl_addr; 
-	
+	ABE_uint16 hw_ctrl_addr;
 	/* 10 DMA request bit-field or IRQ (DSP/MCU) */
-	ABE_uchar atc_irq_data; 
-	
+	ABE_uchar atc_irq_data;
 	/* 11 0 = Read, 3 = Write */
-	ABE_uchar direction_rw; 
-	
+	ABE_uchar direction_rw;
 	/* 12 */
-	ABE_uchar unused1; 
-	
+	ABE_uchar repeat_last_samp;
 	/* 13 12 at 48kHz, ... */
-	ABE_uchar nsamp; 
-	
+	ABE_uchar nsamp;
 	/* 14 nsamp x samp_size */
-	ABE_uchar x_io; 
-	
+	ABE_uchar x_io;
 	/* 15 ON = 0x80, OFF = 0x00 */
-	ABE_uchar on_off; 
-
+	ABE_uchar on_off;
 	/* 16 For Slimbus and TDM purpose */
-	ABE_uint16 split_addr1; 
-	
+	ABE_uint16 split_addr1;
 	/* 18 */
-	ABE_uint16 split_addr2; 
-	
+	ABE_uint16 split_addr2;
 	/* 20 */
-	ABE_uint16 split_addr3; 
-	
+	ABE_uint16 split_addr3;
 	/* 22 */
-	ABE_uchar before_f_index; 
-	
+	ABE_uchar before_f_index;
 	/* 23 */
-	ABE_uchar after_f_index; 
-
+	ABE_uchar after_f_index;
 	/* 24 SM/CM INITPTR field */
-	ABE_uint16 smem_addr1; 
-	
+	ABE_uint16 smem_addr1;
 	/* 26 in bytes */
-	ABE_uint16 atc_address1; 
-	
+	ABE_uint16 atc_address1;
 	/* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
-	ABE_uint16 atc_pointer_saved1; 
-	
+	ABE_uint16 atc_pointer_saved1;
 	/* 30 samp_size (except in TDM or Slimbus) */
-	ABE_uchar data_size1; 
-	
+	ABE_uchar data_size1;
 	/* 31 "Function index" of XLS sheet "Functions" */
-	ABE_uchar copy_f_index1; 
-
+	ABE_uchar copy_f_index1;
 	/* 32 For Slimbus and TDM purpose */
-	ABE_uint16 smem_addr2; 
-	
+	ABE_uint16 smem_addr2;
 	/* 34 */
-	ABE_uint16 atc_address2; 
-	
+	ABE_uint16 atc_address2;
 	/* 36 */
-	ABE_uint16 atc_pointer_saved2; 
-	
+	ABE_uint16 atc_pointer_saved2;
 	/* 38 */
-	ABE_uchar data_size2; 
-	
+	ABE_uchar data_size2;
 	/* 39 */
-	ABE_uchar copy_f_index2; 
-
-} ABE_SIODescriptor ;
-
+	ABE_uchar copy_f_index2;
+} ABE_SIODescriptor;
 /* [w] asrc output used for the next asrc call (+/- 1 / 0) */
-#define drift_asrc_ 0 
-
- /* [w] asrc output used for controlling the number of samples to be 
-	exchanged (+/- 1 / 0) */
+#define drift_asrc_ 0
+/* [w] asrc output used for controlling the number of samples to be
+    exchanged (+/- 1 / 0) */
 #define drift_io_ 2
-
 /* address of the IO subroutine */
-#define io_type_idx_ 4 
+#define io_type_idx_ 4
 #define samp_size_ 5
-
 /* flow error counter */
-#define flow_counter_ 6 
-
+#define flow_counter_ 6
 /* dmareq address or host irq buffer address (atc address) */
-#define hw_ctrl_addr_ 8 
-
+#define hw_ctrl_addr_ 8
 /* data content to be loaded to "hw_ctrl_addr" */
-#define atc_irq_data_ 10 
-
+#define atc_irq_data_ 10
 /* read dmem =0, write dmem =3 (atc offset of the access pointer) */
-#define direction_rw_ 11 
-
+#define direction_rw_ 11
+/* flag set to allow repeating the last sample on downlink paths */
+#define repeat_last_samp_ 12
 /* number of samples (either mono stereo...) */
-#define nsamp_ 13 
-
+#define nsamp_ 13
 /* x number of raw DMEM data moved */
-#define x_io_ 14 
+#define x_io_ 14
 #define on_off_ 15
-
 /* internal smem buffer initptr pointer index */
-#define split_addr1_ 16 
-
+#define split_addr1_ 16
 /* internal smem buffer initptr pointer index */
-#define split_addr2_ 18 
-
+#define split_addr2_ 18
 /* internal smem buffer initptr pointer index */
-#define split_addr3_ 20 
-
+#define split_addr3_ 20
 /* index of the copy subroutine */
-#define before_f_index_ 22 
-
+#define before_f_index_ 22
 /* index of the copy subroutine */
-#define after_f_index_ 23 
-
+#define after_f_index_ 23
 #define minidesc1_ 24
-
 /* internal smem buffer initptr pointer index */
-#define rel_smem_ 0 
-
+#define rel_smem_ 0
 /* atc descriptor address (byte address x4) */
-#define rel_atc_ 2 
-
+#define rel_atc_ 2
 /* location of the saved ATC pointer (+debug info) */
-#define rel_atc_saved 4 
-
+#define rel_atc_saved 4
 /* size of each sample (1:mono/1616 2:stereo ... ) */
-#define rel_size_ 6 
-
+#define rel_size_ 6
 /* index of the copy subroutine */
-#define rel_f_ 7 
-
+#define rel_f_ 7
 #define s_mem_mm_ul 24
 #define s_mm_ul_size 30
-
 #define minidesc2_ 32
 #define Struct_Size 40
-
 typedef struct {
-	/* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0)*/
+	/* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0) */
 	ABE_uint16 drift_ASRC;
-
-	/* 2: [W] asrc output used for controlling the number of 
-		samples to be exchanged (+/- 1 / 0) */
-	ABE_uint16 drift_io; 
-	
+	/* 2: [W] asrc output used for controlling the number of
+	   samples to be exchanged (+/- 1 / 0) */
+	ABE_uint16 drift_io;
 	/* 4: DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */
-	ABE_uint16 hw_ctrl_addr; 
-	
+	ABE_uint16 hw_ctrl_addr;
 	/* 6: index of the copy subroutine */
-	ABE_uchar copy_func_index; 
-	
+	ABE_uchar copy_func_index;
 	/* 7: X number of SMEM samples to move */
-	ABE_uchar x_io; 
-	
+	ABE_uchar x_io;
 	/* 8: 0 for mono data, 1 for stereo data */
-	ABE_uchar data_size; 
-	
+	ABE_uchar data_size;
 	/* 9: internal SMEM buffer INITPTR pointer index */
-	ABE_uchar smem_addr; 
-	
+	ABE_uchar smem_addr;
 	/* 10: data content to be loaded to "hw_ctrl_addr" */
-	ABE_uchar atc_irq_data; 
-	
+	ABE_uchar atc_irq_data;
 	/* 11: ping/pong buffer flag */
-	ABE_uchar counter; 
-	
+	ABE_uchar counter;
 	/* 12: current Base address of the working buffer */
 	ABE_uint16 workbuff_BaseAddr;
-
 	/* 14: samples left in the working buffer */
-	ABE_uint16 workbuff_Samples; 
-	
+	ABE_uint16 workbuff_Samples;
 	/* 16: Base address of the ping/pong buffer 0 */
 	ABE_uint16 nextbuff0_BaseAddr;
-
 	/* 18: samples available in the ping/pong buffer 0 */
-	ABE_uint16 nextbuff0_Samples; 
-	
+	ABE_uint16 nextbuff0_Samples;
 	/* 20: Base address of the ping/pong buffer 1 */
 	ABE_uint16 nextbuff1_BaseAddr;
-
 	/* 22: samples available in the ping/pong buffer 1 */
-	ABE_uint16 nextbuff1_Samples; 
+	ABE_uint16 nextbuff1_Samples;
 } ABE_SPingPongDescriptor;
-
-
 #ifdef __chess__
 /* [W] asrc output used for the next ASRC call (+/- 1 / 0)*/
 #define drift_ASRC 0
-
-/* [W] asrc output used for controlling the number of samples to be 
-	exchanged (+/- 1 / 0) */ 
-#define drift_io 2 
-
+/* [W] asrc output used for controlling the number of samples to be
+	exchanged (+/- 1 / 0) */
+#define drift_io 2
 /* DMAReq address or HOST IRQ buffer address (ATC ADDRESS) */
-#define hw_ctrl_addr 4 
-
+#define hw_ctrl_addr 4
 /* index of the copy subroutine */
-#define copy_func_index 6 
-
+#define copy_func_index 6
 /* X number of SMEM samples to move */
-#define x_io 7 
-
+#define x_io 7
 /* 0 for mono data, 1 for stereo data */
-#define data_size 8 
-
+#define data_size 8
 /* internal SMEM buffer INITPTR pointer index */
-#define smem_addr 9 
-
+#define smem_addr 9
 /* data content to be loaded to "hw_ctrl_addr" */
 #define atc_irq_data 10
-
-/* ATC descriptor address */ 
-#define atc_address 11 
-
+/* ATC descriptor address */
+#define atc_address 11
 /* THR1; For stereo data, THR1 is provided by HAL as THR1<<1 */
-#define threshold_1 12 
-
+#define threshold_1 12
 /* THR2; For stereo data, THR2 is provided by HAL as THR2<<1 */
 #define threshold_2 13
-
-/* UP_1; For stereo data, UP_1 is provided by HAL as UP_1<<1 */ 
-#define update_1 14 
-
+/* UP_1; For stereo data, UP_1 is provided by HAL as UP_1<<1 */
+#define update_1 14
 /* UP_2; For stereo data, UP_2 is provided by HAL as UP_2<<1 */
-#define update_2 15 
-
+#define update_2 15
 /* Flow error counter */
-#define flow_counter 16 
-
+#define flow_counter 16
 /* Read DMEM =0, Write DMEM =3 (ATC offset of the access pointer) */
-#define direction_rw 17 
-
+#define direction_rw 17
 /* ping/pong buffer flag */
-#define counter 11 
-
+#define counter 11
 /* current Base address of the working buffer */
 #define workbuff_BaseAddr 12
-
-/* samples left in the working buffer */ 
-#define workbuff_Samples 14 
-
+/* samples left in the working buffer */
+#define workbuff_Samples 14
 /* Base address of the ping/pong buffer 0 */
 #define nextbuff0_BaseAddr 16
-
-/* samples available in the ping/pong buffer 0 */ 
-#define nextbuff0_Samples 18 
-
+/* samples available in the ping/pong buffer 0 */
+#define nextbuff0_Samples 18
 /* samples available in the ping/pong buffer 0 */
 #define nextbuff1_BaseAddr 20
-
-/* samples available in the ping/pong buffer 1 */ 
-#define nextbuff1_Samples 22 
+/* samples available in the ping/pong buffer 1 */
+#define nextbuff1_Samples 22
 #endif
-
-#endif /* _ABE_TYPEDEF_H_ */
+#endif/* _ABE_TYPEDEF_H_ */
diff --git a/sound/soc/omap/abe/c_abe_fw_size.h b/sound/soc/omap/abe/c_abe_fw_size.h
index bda16787a9ba..280af1aba020 100644
--- a/sound/soc/omap/abe/c_abe_fw_size.h
+++ b/sound/soc/omap/abe/c_abe_fw_size.h
@@ -1,6 +1,6 @@
-/* 
+/*
         FW 05.10  MEMORY SIZES
 */
 #define ABE_DMEM_SIZE_OPTIMIZED 16384
 #define ABE_SMEM_SIZE_OPTIMIZED 15360
-#define ABE_CMEM_SIZE_OPTIMIZED 6552
\ No newline at end of file
+#define ABE_CMEM_SIZE_OPTIMIZED 6552