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authorGeert Uytterhoeven <geert+renesas@glider.be>2025-02-21 09:44:47 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2025-03-04 09:04:23 +0100
commit5288fe0e2e9d2c147e18c5ce4d03d17f34132dde (patch)
treeea99daf6c4b51a50bb5f25f75c4185f62ada7a05
parent653395e63d53723f29b8cc1aa6bc4cbb873c7b7b (diff)
clk: renesas: r7s9210: Distinguish clocks by clock type
When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be
-rw-r--r--drivers/clk/renesas/r7s9210-cpg-mssr.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index a85227c248f3..e1812867a6da 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev,
if (IS_ERR(parent))
return ERR_CAST(parent);
- switch (core->id) {
- case CLK_MAIN:
+ switch (core->type) {
+ case CLK_TYPE_RZA_MAIN:
+ r7s9210_update_clk_table(parent, base);
break;
- case CLK_PLL:
+ case CLK_TYPE_RZA_PLL:
if (cpg_mode)
mult = 44; /* Divider 1 is 1/2 */
else
@@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev,
return ERR_PTR(-EINVAL);
}
- if (core->id == CLK_MAIN)
- r7s9210_update_clk_table(parent, base);
-
return clk_register_fixed_factor(NULL, core->name,
__clk_get_name(parent), 0, mult, div);
}