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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2025-02-21 17:52:00 +0200
committerKrzysztof Wilczyński <kwilczynski@kernel.org>2025-02-24 18:29:52 +0000
commit8f5bd6cfc94a376e5fd8a6d4d1c559407942004f (patch)
treeb45e03e5431a446a07c1288e74efc3184599b455
parenta22d3039a1d25312ecde0d02bcad4dd235f03e5e (diff)
dt-bindings: PCI: qcom-ep: Describe optional IOMMU
Some of Qualcomm platforms have an IOMMU unit between the PCIe IP and DDR. For example, the SA8775P specifies the iommu alththough it is not a part of bindings. Thus, change the schema in order to require the IOMMU for SA8775P and forbid it from being used on SDX55 (SM8450 will be handled in a later patch). This fixes the following warning: pcie-ep@1c10000: Unevaluated properties are not allowed ('iommus' was unexpected) Fixes: 9d3d5e75f31c ("dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250221-sar2130p-pci-v3-2-61a0fdfb75b4@linaro.org [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 0c2ca4cfa3b1..607536134835 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -75,6 +75,9 @@ properties:
- const: doorbell
- const: dma
+ iommus:
+ maxItems: 1
+
reset-gpios:
description: GPIO used as PERST# input signal
maxItems: 1
@@ -162,6 +165,7 @@ allOf:
maxItems: 2
interrupt-names:
maxItems: 2
+ iommus: false
- if:
properties:
@@ -234,6 +238,8 @@ allOf:
interrupt-names:
minItems: 3
maxItems: 3
+ required:
+ - iommus
unevaluatedProperties: false