diff options
| author | Rohit Visavalia <rohit.visavalia@amd.com> | 2025-01-06 20:40:38 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-01-07 11:48:23 -0800 |
| commit | b00b08a59674eacc77848d852d7c37de485add81 (patch) | |
| tree | 9e4269ae8526b51e2f57c0d59e18711f1ab7a65d | |
| parent | b51adc77557a15c1598bd70365bee253d16a306b (diff) | |
dt-bindings: clock: xilinx: Add reset GPIO for VCU
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,vcu.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml index 02d27d11a452..19dc923e2ee9 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,vcu.yaml @@ -33,6 +33,9 @@ properties: - const: pll_ref - const: aclk + reset-gpios: + maxItems: 1 + required: - reg - clocks @@ -49,6 +52,7 @@ examples: xlnx_vcu: vcu@a0040000 { compatible = "xlnx,vcu-logicoreip-1.0"; reg = <0x0 0xa0040000 0x0 0x1000>; + reset-gpios = <&gpio 78 GPIO_ACTIVE_HIGH>; clocks = <&si570_1>, <&clkc 71>; clock-names = "pll_ref", "aclk"; }; |