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| author | Cyan Yang <cyan.yang@sifive.com> | 2025-04-18 13:32:36 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2025-05-08 11:01:44 -0700 |
| commit | d5ca02b25f5dbe44a25afe35cd75d49f1f0b9763 (patch) | |
| tree | a1439afa3db4438bd2bb4515f873249b7ced2fa2 | |
| parent | 1d91224394c92245942c402245370c4abb0fcbfb (diff) | |
dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description
Add "xsfvfwmaccqqq" ISA extension which is provided by SiFive for
matrix multiply accumulate instructions support.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250418053239.4351-10-cyan.yang@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index be203df29eb8..ede6a58ccf53 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -681,6 +681,12 @@ properties: See more details in https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions + - const: xsfvfwmaccqqq + description: + SiFive Matrix Multiply Accumulate Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction + # T-HEAD - const: xtheadvector description: |