diff options
| author | Manikanta Mylavarapu <quic_mmanikan@quicinc.com> | 2025-03-06 16:59:00 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2025-03-13 17:43:35 -0500 |
| commit | e9ed0ac3ccba65c17ed0d59c77a340a75abc317b (patch) | |
| tree | a48d07157bbd734e00303b6d50d3f103e2f4ca02 | |
| parent | cdbbc480f4146cb659af97f4020601fde5fb65a7 (diff) | |
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
The divider values in the sdcc1_apps frequency table were incorrectly
updated, assuming the frequency of gpll2_out_main to be 1152MHz.
However, the frequency of the gpll2_out_main clock is actually 576MHz
(gpll2/2).
Due to these incorrect divider values, the sdcc1_apps clock is running
at half of the expected frequency.
Fixing the frequency table of sdcc1_apps allows the sdcc1_apps clock to
run according to the frequency plan.
Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250306112900.3319330-1-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq5424.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c index 37b1a3ff8f4e..3d42f3d85c7a 100644 --- a/drivers/clk/qcom/gcc-ipq5424.c +++ b/drivers/clk/qcom/gcc-ipq5424.c @@ -640,11 +640,11 @@ static struct clk_rcg2 gcc_qupv3_uart1_clk_src = { static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { F(144000, P_XO, 16, 12, 125), F(400000, P_XO, 12, 1, 5), - F(24000000, P_XO, 1, 0, 0), - F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2), - F(96000000, P_GPLL2_OUT_MAIN, 6, 1, 2), + F(24000000, P_GPLL2_OUT_MAIN, 12, 1, 2), + F(48000000, P_GPLL2_OUT_MAIN, 12, 0, 0), + F(96000000, P_GPLL2_OUT_MAIN, 6, 0, 0), F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL2_OUT_MAIN, 3, 0, 0), F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0), { } }; |