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authorArchit Taneja <archit@ti.com>2012-07-20 18:47:35 +0200
committerXavier Boudet <x-boudet@ti.com>2012-07-23 10:56:36 +0200
commit927423bcf39cf2ea845e409e380c5ddfc72de96d (patch)
tree6e2ceb4f11dc1c87ae3b0c4d3e5cd6409f54f4cc
parent268956bc5c02d4598b00a8f19a72fe7c55d7d13f (diff)
OMAPDSS: DISPC: HACK: Transfer writeback pipeline FIFOs to graphics pipeline FIFO
The Writeback pipeline isn't currently supported by OMAPDSS. Use it's free FIFO and make it available to the GFX pipe. This is achieved by configuring the register DISPC_GLOBAL_BUFFER to assign Writeback's FIFOs to GFX. Create a generic function dispc_transfer_fifo() which takes in the pipeline whose FIFO we want to give away, and the pipeline which receives the FIFO. This can be used later when support for dynamic sharing of FIFOs is added. Underflows are seen on GFX pipe when it's routed to a high resolution display (1920x1080 and above) and when a Tiler buffer is used in 2D mode. To resolve this, create a function named dispc_transfer_wb_fifo_to_gfx(), this calls the above function if writeback is available on the OMAP platform. This is a temporary solution which will be used till the time dynamic sharing of pipeline FIFOs is added.
-rw-r--r--drivers/video/omap2/dss/dispc.c35
-rw-r--r--drivers/video/omap2/dss/dispc.h1
2 files changed, 36 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index ced91ce214b4..ee2b915805df 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -1011,6 +1011,39 @@ static void dispc_read_plane_fifo_sizes(void)
}
}
+static void dispc_transfer_fifo(enum omap_plane src_plane,
+ enum omap_plane dest_plane)
+{
+ u8 top_fifo_start, top_fifo_end, bot_fifo_start, bot_fifo_end;
+
+ /*
+ * calculate start and end bits corresponding to the source plane
+ * in DISPC_GLOBAL_BUFFER
+ */
+ top_fifo_end = src_plane * 6;
+ top_fifo_start = top_fifo_end + 2;
+ bot_fifo_end = top_fifo_start + 1;
+ bot_fifo_start = bot_fifo_end + 2;
+
+ REG_FLD_MOD(DISPC_GLOBAL_BUFFER, src_plane, top_fifo_start,
+ top_fifo_end);
+ REG_FLD_MOD(DISPC_GLOBAL_BUFFER, src_plane, bot_fifo_start,
+ bot_fifo_end);
+
+ dispc.fifo_size[dest_plane] += dispc.fifo_size[src_plane];
+ dispc.fifo_size[src_plane] = 0;
+}
+
+static void dispc_transfer_wb_fifo_to_gfx(void)
+{
+ const int num_wbs = dss_feat_get_num_wbs();
+
+ if (!num_wbs)
+ return;
+
+ dispc_transfer_fifo(OMAP_DSS_WB, OMAP_DSS_GFX);
+}
+
static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
{
return dispc.fifo_size[plane];
@@ -3664,6 +3697,8 @@ static void _omap_dispc_initial_config(void)
dispc_read_plane_fifo_sizes();
+ dispc_transfer_wb_fifo_to_gfx();
+
dispc_configure_burst_sizes();
dispc_ovl_enable_zorder_planes();
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
index 30832c7868fc..d870b5f00480 100644
--- a/drivers/video/omap2/dss/dispc.h
+++ b/drivers/video/omap2/dss/dispc.h
@@ -35,6 +35,7 @@
#define DISPC_GLOBAL_ALPHA 0x0074
#define DISPC_CONTROL2 0x0238
#define DISPC_CONFIG2 0x0620
+#define DISPC_GLOBAL_BUFFER 0x0800
#define DISPC_DIVISOR 0x0804
/* DISPC overlay registers */