Merge branch 'omap4_next' of git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into L24x6P2

3 files changed, 53 insertions, 1 deletions

diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 683c7a39095a..8b2c8d9b8760 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -260,7 +260,7 @@ CONFIG_OMAP_PM_NOOP=y
 # CONFIG_WIFI_CONTROL_FUNC is not set
 # CONFIG_TIWLAN_SDIO is not set
 CONFIG_MACH_OMAP_4430SDP=y
-
+CONFIG_ERRATA_OMAP4_AXI2OCP=y
 #
 # Processor Type
 #
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 6f077e31341d..e416733c1c64 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -179,6 +179,19 @@ config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
 	depends on ARCH_OMAP4
 
+config ERRATA_OMAP4_AXI2OCP
+	bool "OMAP 4430 axi2ocp errata workaround"
+	depends on ARCH_OMAP4
+	help
+	Pending response counter logic is incorrectly implemented
+	It decrements by only 1 even when there are 2+ responses in the
+	same cycle. If 2 MCMDs send out bridge at the same time counter
+	increments by.1 but when it decrement for 2 responses counter does
+	not go beyond 0.
+	Work-around:
+	Any new request before timer max out resets the timer. With this hang
+	issue will not happen.
+
 config OMAP3_EMU
 	bool "OMAP3 debugging peripherals"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index d5f2ba7f56e6..66c635aa4c36 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -66,6 +66,21 @@ static struct irqaction omap2_gp_timer_irq = {
 	.handler	= omap2_gp_timer_interrupt,
 };
 
+#ifdef CONFIG_ERRATA_OMAP4_AXI2OCP
+static struct omap_dm_timer *gptimer2;
+static irqreturn_t gpt2_timer_interrupt(int irq, void *dev_id)
+{
+	omap_dm_timer_write_status(gptimer2, OMAP_TIMER_INT_OVERFLOW);
+	return IRQ_HANDLED;
+}
+
+static struct irqaction gpt2_timer_irq = {
+	.name		= "gpt2 timer",
+	.flags		= IRQF_DISABLED,
+	.handler	= gpt2_timer_interrupt,
+};
+#endif
+
 static int omap2_gp_timer_set_next_event(unsigned long cycles,
 					 struct clock_event_device *evt)
 {
@@ -166,8 +181,32 @@ static void __init omap2_gp_clockevent_init(void)
 
 	clockevent_gpt.cpumask = cpumask_of(0);
 	clockevents_register_device(&clockevent_gpt);
+
 }
 
+#ifdef CONFIG_ERRATA_OMAP4_AXI2OCP
+static int __init omap4_setup_gpt2(void)
+{
+	/*  Set up GPT2 for the WA */
+	gptimer2 = omap_dm_timer_request_specific(2);
+	BUG_ON(gptimer2 == NULL);
+
+	printk(KERN_INFO " Enabling AXI2OCP errata Fix \n");
+	omap_dm_timer_set_source(gptimer2, OMAP_TIMER_SRC_32_KHZ);
+	gpt2_timer_irq.dev_id = (void *)gptimer2;
+	setup_irq(omap_dm_timer_get_irq(gptimer2), &gpt2_timer_irq);
+	omap_dm_timer_set_int_enable(gptimer2, OMAP_TIMER_INT_OVERFLOW);
+	/*
+	 * Timer reload value is used based on mpu @ 600 MHz
+	 * And hence bridge is at 300 MHz. 65K cycle = 216 uS
+	 * 6 * 1/32 kHz => ~187 us
+	 */
+	omap_dm_timer_set_load_start(gptimer2, 1, 0xffffff06);
+
+	return 0;
+}
+late_initcall(omap4_setup_gpt2);
+#endif
 /* Clocksource code */
 
 #ifdef CONFIG_OMAP_32K_TIMER