diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2020-04-21 11:20:39 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-04-26 18:39:48 +0200 |
| commit | 96f59fe291d2cdc0fcb6f5f2f4b7c9cea9533fc3 (patch) | |
| tree | 9ea46077dba10eb3c59fdfebae65b2d3ebd0bbc5 | |
| parent | 69de6c1a7fc730260d39f09432d69abc99f5f344 (diff) | |
x86/tlb: Move cr4_set_bits_and_update_boot() to the usage site
No point in having this exposed.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200421092559.940978251@linutronix.de
| -rw-r--r-- | arch/x86/include/asm/tlbflush.h | 14 | ||||
| -rw-r--r-- | arch/x86/mm/init.c | 13 |
2 files changed, 13 insertions, 14 deletions
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index c22fc72c126d..917deea058d5 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -322,23 +322,9 @@ static inline void cr4_clear_bits(unsigned long mask) local_irq_restore(flags); } -/* - * Save some of cr4 feature set we're using (e.g. Pentium 4MB - * enable and PPro Global page enable), so that any CPU's that boot - * up after us can get the correct flags. This should only be used - * during boot on the boot cpu. - */ extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; -static inline void cr4_set_bits_and_update_boot(unsigned long mask) -{ - mmu_cr4_features |= mask; - if (trampoline_cr4_features) - *trampoline_cr4_features = mmu_cr4_features; - cr4_set_bits(mask); -} - extern void initialize_tlbstate_and_flush(void); #define TLB_FLUSH_ALL -1UL diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 71720dd8f28a..d37e8164022e 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -194,6 +194,19 @@ struct map_range { static int page_size_mask; +/* + * Save some of cr4 feature set we're using (e.g. Pentium 4MB + * enable and PPro Global page enable), so that any CPU's that boot + * up after us can get the correct flags. Invoked on the boot CPU. + */ +static inline void cr4_set_bits_and_update_boot(unsigned long mask) +{ + mmu_cr4_features |= mask; + if (trampoline_cr4_features) + *trampoline_cr4_features = mmu_cr4_features; + cr4_set_bits(mask); +} + static void __init probe_page_size_mask(void) { /* |