diff options
author | Sebastien Jan <s-jan@ti.com> | 2012-09-10 17:44:25 +0200 |
---|---|---|
committer | Xavier Boudet <x-boudet@ti.com> | 2012-09-12 19:15:00 +0200 |
commit | 83b7cf3ef0b51bdc20e7569f6948269b1bd257de (patch) | |
tree | d378780153a0893acb72254c1f0b36328e3b4e44 | |
parent | 12ccf57d7a70cb075d7092ca6596bfc2782f6a13 (diff) |
OMAP4: L2X0: fine tune PL310 configuration
Align with TI Android 3.0 kernel on following setup:
- read/modify/write for AUX_CTRL register (reserved bits shall be
preserved)
- disable Instruction prefetch as it does not bring better performances
- setup Prefetch Offset (or Control) Register:
- disable double line fill to avoid ARM errata 732672
(potentially prevents data corruption)
- optimized prefetch offset value (considering no double line fetch)
This is a collection of changes brough up by following contributors:
Santosh Shilimkar <santosh.shilimkar@ti.com>
Colin Cross <ccross@android.com>
Konstantin Shlyakhovoy <x0155534@ti.com>
Main Android patches references:
6f07d8f2 OMAP4: L2X0: Update PL310 register bits for OMAP4460
1773e60a omap4: l2x0: Construct the AUXCTRL value using defines
6f07d8f2 OMAP4: L2X0: Update PL310 register bits for OMAP4460
e46d9adf ARM: omap4: disable PL310 double linefill
0314b56d ARM: OMAP4: l2x0: Set optimized value for prefetch offset
Signed-off-by: Sebastien Jan <s-jan@ti.com>
-rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 1 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap4-common.c | 27 |
2 files changed, 26 insertions, 2 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 7ce84add2f1b..06413e34bd7e 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -100,6 +100,7 @@ #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 +#define L2X0_AUX_CTRL_REPLACE_POLICY_SHIFT 25 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 #define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28 diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 42a9a91789c1..d697b3d22d55 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -36,6 +36,8 @@ #include <linux/export.h> #ifdef CONFIG_CACHE_L2X0 +#define L2X0_POR_OFFSET_VALUE 0x5 +#define L2X0_POR_OFFSET_MASK 0x1f static void __iomem *l2cache_base; #endif @@ -181,6 +183,7 @@ static void omap4_l2x0_set_debug(unsigned long val) static int __init omap_l2_cache_init(void) { u32 aux_ctrl = 0; + u32 por_ctrl = 0; u32 lockdown = 0; /* @@ -200,23 +203,43 @@ static int __init omap_l2_cache_init(void) * Way size - 32KB (es1.0) * Way size - 64KB (es2.0 +) */ + aux_ctrl = readl_relaxed(l2cache_base + L2X0_AUX_CTRL); aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) | - (0x1 << 25) | + (0x1 << L2X0_AUX_CTRL_REPLACE_POLICY_SHIFT) | (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) | (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT)); if (omap_rev() == OMAP4430_REV_ES1_0) { aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; } else { + /* + * Drop instruction prefetch as it degrades performances + */ aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | - (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT)); } if (omap_rev() != OMAP4430_REV_ES1_0) omap_smc1(0x109, aux_ctrl); + /* Setup POR Control register */ + por_ctrl = readl_relaxed(l2cache_base + L2X0_PREFETCH_CTRL); + + /* + * Double linefill is available only on OMAP4460 L2X0. + * It may cause single cache line memory corruption, leave it disabled + * on all devices + */ + por_ctrl &= ~(1 << L2X0_PREFETCH_DOUBLE_LINEFILL_SHIFT); + por_ctrl &= ~L2X0_POR_OFFSET_MASK; + por_ctrl |= L2X0_POR_OFFSET_VALUE; + + /* Set POR through Monitor API only in GP devices */ + if (omap_type() == OMAP2_DEVICE_TYPE_GP && + omap_rev() >= OMAP4430_REV_ES2_2) + omap_smc1(0x113, por_ctrl); + /* * WA for OMAP4460 stability issue on ES1.0 * Lock-down specific L2 cache ways which makes effective |