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| author | Jonathan Corbet <corbet@lwn.net> | 2019-07-22 13:42:10 -0600 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2019-07-22 13:42:10 -0600 |
| commit | e27a24210aa17b8a0cd462865130fe73afd7e001 (patch) | |
| tree | b2d7b8311d280244fad3166792e8f447081a8bc9 /Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | |
| parent | 224d5fd43d250f850d64fb6d668114aff29d7022 (diff) | |
| parent | 5f9e832c137075045d15cd6899ab0505cfb2ca4b (diff) | |
Merge tag 'v5.3-rc1' into docs-next
Pull in all of the massive docs changes from elsewhere.
Diffstat (limited to 'Documentation/devicetree/bindings/pci/mobiveil-pcie.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt index a618d4787dd7..64156993e052 100644 --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt @@ -10,8 +10,10 @@ Required properties: interrupt source. The value must be 1. - compatible: Should contain "mbvl,gpex40-pcie" - reg: Should contain PCIe registers location and length + Mandatory: "config_axi_slave": PCIe controller registers "csr_axi_slave" : Bridge config registers + Optional: "gpio_slave" : GPIO registers to control slot power "apb_csr" : MSI registers |