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authorGerhard Bertelsmann <info@gerhard-bertelsmann.de>2015-09-16 13:21:19 +0200
committerMarc Kleine-Budde <mkl@pengutronix.de>2015-09-17 22:39:01 +0200
commit4366bd4fa8c46b61ec0a7d564bd978cfa882692b (patch)
tree5fc51209a2b33174077855180b5f0693aee87b3b /Documentation
parent37d2dbcdcca88e392009d7cbe8617d5af0ebcb32 (diff)
can: Allwinner A10/A20 CAN Controller support - Devicetree bindings
Devicetree bindings for Allwinner A10/A20 CAN controller. Signed-off-by: Gerhard Bertelsmann <info@gerhard-bertelsmann.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/net/can/sun4i_can.txt36
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+Allwinner A10/A20 CAN controller Device Tree Bindings
+-----------------------------------------------------
+
+Required properties:
+- compatible: "allwinner,sun4i-a10-can"
+- reg: physical base address and size of the Allwinner A10/A20 CAN register map.
+- interrupts: interrupt specifier for the sole interrupt.
+- clock: phandle and clock specifier.
+
+Example
+-------
+
+SoC common .dtsi file:
+
+ can0_pins_a: can0@0 {
+ allwinner,pins = "PH20","PH21";
+ allwinner,function = "can";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+...
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <0 26 4>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
+
+Board specific .dts file:
+
+ can0: can@01c2bc00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins_a>;
+ status = "okay";
+ };