MMC SLOT0&SLOT1 support on OMAP4-SDP

3 files changed, 79 insertions, 42 deletions

diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index d9df37bb58ed..dc5ca3574d17 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -236,22 +236,26 @@ static struct twl4030_hsmmc_info mmc[] = {
 	{
 		.mmc            = 2,
 		.wires          = 8,
-		.gpio_wp        = 7,
+		.gpio_cd	= -EINVAL,
+		.gpio_wp        = -EINVAL,
 	},
 	{
 		.mmc            = 3,
-		.wires          = 8,
-		.gpio_wp        = 4,
+		.wires          = -EINVAL,
+		.gpio_cd	= -EINVAL,
+		.gpio_wp        = -EINVAL,
 	},
 	{
 		.mmc            = 4,
-		.wires          = 8,
-		.gpio_wp        = 4,
+		.wires          = -EINVAL,
+		.gpio_cd	= -EINVAL,
+		.gpio_wp        = -EINVAL,
 	},
 	{
 		.mmc            = 5,
-		.wires          = 8,
-		.gpio_wp        = 4,
+		.wires          = -EINVAL,
+		.gpio_cd	= -EINVAL,
+		.gpio_wp        = -EINVAL,
 	},
 	{}	/* Terminator */
 };
@@ -278,10 +282,6 @@ static int __init sdp4430_mmc_init(void)
 {
 	/* Hard Coding Values for testing */
 	mmc[0].gpio_cd = 373;
-	mmc[1].gpio_cd = 0;
-	mmc[2].gpio_cd = 1;
-	mmc[3].gpio_cd = 2;
-	mmc[4].gpio_cd = 3;
 	twl4030_mmc_init(mmc);
 	/* link regulators to MMC adapters ... we "know" the
 	 * regulators will be set up only *after* we return.
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 400f8e167280..b6b437e6fc6b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -606,8 +606,6 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 		if (!mmc_data[i])
 			continue;
 
-		omap2_mmc_mux(mmc_data[i], i);
-
 		switch (i) {
 		case 0:
 			base = OMAP2_MMC1_BASE;
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index b2a5086f1827..70814dde24f6 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -32,6 +32,8 @@
 
 static u16 control_pbias_offset;
 static u16 control_devconf1_offset;
+static u16 control_mmc1;
+static u16 control_mmc2;
 
 #define HSMMC_NAME_LEN	9
 #define REG_SIMCTRL	0x0C
@@ -245,41 +247,68 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on,
 			omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
 		}
 
-		if (mmc->slots[0].internal_clock) {
-			reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-			reg |= OMAP2_MMCSDIO1ADPCLKISEL;
-			omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
+		if (!cpu_is_omap44xx()) {
+			if (mmc->slots[0].internal_clock) {
+				reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+				reg |= OMAP2_MMCSDIO1ADPCLKISEL;
+				omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
+			}
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg |= OMAP2_PBIASSPEEDCTRL0;
+			reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+			omap_ctrl_writel(reg, control_pbias_offset);
+		} else {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg &= ~(1 << 20);
+			omap_ctrl_writel(reg, control_pbias_offset);
 		}
 
-		reg = omap_ctrl_readl(control_pbias_offset);
-		reg |= OMAP2_PBIASSPEEDCTRL0;
-		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
-		omap_ctrl_writel(reg, control_pbias_offset);
-
 		ret = mmc_regulator_set_ocr(c->vcc, vdd);
 
 		/* 100ms delay required for PBIAS configuration */
 		msleep(100);
-		reg = omap_ctrl_readl(control_pbias_offset);
-		reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
-		if ((1 << vdd) <= MMC_VDD_165_195)
-			reg &= ~OMAP2_PBIASLITEVMODE0;
-		else
-			reg |= OMAP2_PBIASLITEVMODE0;
-		omap_ctrl_writel(reg, control_pbias_offset);
+		if (!cpu_is_omap44xx()) {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
+			if ((1 << vdd) <= MMC_VDD_165_195)
+				reg &= ~OMAP2_PBIASLITEVMODE0;
+			else
+				reg |= OMAP2_PBIASLITEVMODE0;
+			omap_ctrl_writel(reg, control_pbias_offset);
+		} else {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg |= (1 << 20);
+			if ((1 << vdd) <= MMC_VDD_165_195)
+				reg &= ~(1 << 21);
+			else
+				reg |= (1 << 21);
+			omap_ctrl_writel(reg, control_pbias_offset);
+		}
 	} else {
-		reg = omap_ctrl_readl(control_pbias_offset);
-		reg &= ~OMAP2_PBIASLITEPWRDNZ0;
-		omap_ctrl_writel(reg, control_pbias_offset);
+		if (!cpu_is_omap44xx()) {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg &= ~OMAP2_PBIASLITEPWRDNZ0;
+			omap_ctrl_writel(reg, control_pbias_offset);
+		} else {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg &= ~(1 << 20);
+			omap_ctrl_writel(reg, control_pbias_offset);
+		}
 
 		ret = mmc_regulator_set_ocr(c->vcc, 0);
 
 		/* 100ms delay required for PBIAS configuration */
 		msleep(100);
-		reg = omap_ctrl_readl(control_pbias_offset);
-		reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
-			OMAP2_PBIASLITEVMODE0);
-		omap_ctrl_writel(reg, control_pbias_offset);
+		if (!cpu_is_omap44xx()) {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
+				OMAP2_PBIASLITEVMODE0);
+			omap_ctrl_writel(reg, control_pbias_offset);
+		} else {
+			reg = omap_ctrl_readl(control_pbias_offset);
+			reg |= (1 << 20 | 1 << 21);
+			omap_ctrl_writel(reg, control_pbias_offset);
+		}
 	}
 
 	return ret;
@@ -325,10 +354,11 @@ static int twl_mmc23_set_power(struct device *dev, int slot, int power_on, int v
 		/* only MMC2 supports a CLKIN */
 		if (mmc->slots[0].internal_clock) {
 			u32 reg;
-
-			reg = omap_ctrl_readl(control_devconf1_offset);
-			reg |= OMAP2_MMCSDIO2ADPCLKISEL;
-			omap_ctrl_writel(reg, control_devconf1_offset);
+			if (!cpu_is_omap44xx()) {
+				reg = omap_ctrl_readl(control_devconf1_offset);
+				reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+				omap_ctrl_writel(reg, control_devconf1_offset);
+			}
 		}
 		ret = mmc_regulator_set_ocr(c->vcc, vdd);
 		/* enable interface voltage rail, if needed */
@@ -353,11 +383,20 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 {
 	struct twl4030_hsmmc_info *c;
 	int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
+	u32 reg;
 
 	if (cpu_is_omap2430()) {
 		control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 		control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 		nr_hsmmc = 2;
+	}
+
+	if (cpu_is_omap44xx()) {
+		control_pbias_offset = 0x600;
+		control_mmc1 = 0x628;
+		reg = omap_ctrl_readl(control_mmc1);
+		reg |= 0xbe000000;
+		omap_ctrl_writel(reg, control_mmc1);
 	} else {
 		control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 		control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
@@ -466,11 +505,11 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers)
 			mmc->slots[0].set_power = twl_mmc23_set_power;
 			break;
 		case 4:
-			/* off-chip level shifting, or none */
+			/* TODO */
 			mmc->slots[0].set_power = twl_mmc23_set_power;
 			break;
 		case 5:
-			/* off-chip level shifting, or none */
+			/* TODO */
 			mmc->slots[0].set_power = twl_mmc23_set_power;
 			break;
 		default: