diff options
| author | Will Deacon <will.deacon@arm.com> | 2010-07-16 10:45:53 +0530 |
|---|---|---|
| committer | Ricardo Perez Olivares <x0081762@ti.com> | 2010-09-14 19:25:53 -0500 |
| commit | 42690f9cec3dd80547b4063eb8577df2bd0df0ee (patch) | |
| tree | 96cac996a87a7cc8b7d9ed0e2656d1d4004033dd /arch/arm/mm | |
| parent | fb08209b6179884cbce5c98c7fbc71b4543f3b24 (diff) | |
ARM: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID
On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
ASID match can result in the incorrect ASID being broadcast to other CPUs.
As a consequence of this, the targetted TLB entries are not invalidated
across the system.
This workaround changes the TLB flushing routines to invalidate entries
regardless of the ASID.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm/mm')
0 files changed, 0 insertions, 0 deletions