Merge branch 'display-next' of git://dev.omapzoom.org/pub/scm/axelcx/kernel-display into L24x8

Conflicts:
	arch/arm/configs/omap_4430sdp_defconfig
	drivers/Kconfig
	drivers/Makefile
	drivers/media/video/Makefile
	drivers/media/video/dmm/tmm_pat.c
	drivers/media/video/tiler/tiler.c

Signed-off-by: Ricardo Perez Olivares <x0081762@ti.com>

10 files changed, 2627 insertions, 28 deletions

diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 23627207716d..360c3bc099c6 100644..100755
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -951,23 +951,160 @@ CONFIG_REGULATOR_TWL4030=y
 CONFIG_MEDIA_SUPPORT=y
 
 #
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_SG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_OMAP2_VOUT=y
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_DAB is not set
+CONFIG_DMM_OMAP=y
+CONFIG_TILER_OMAP=y
+
+#
 # Graphics support
 #
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set
+CONFIG_OMAP2_VRAM=y
+CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_VRAM_SIZE=4
+CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y
+# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set
+CONFIG_OMAP2_DSS_DPI=y
+# CONFIG_OMAP2_DSS_RFBI is not set
+# CONFIG_OMAP2_DSS_VENC is not set
+CONFIG_OMAP2_DSS_HDMI=y
+CONFIG_OMAP2_DSS_DSI=y
+# CONFIG_OMAP2_DSS_USE_DSI_PLL is not set
+CONFIG_OMAP2_DSS_FAKE_VSYNC=y
+CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
+CONFIG_FB_OMAP2=y
+CONFIG_FB_OMAP2_DEBUG_SUPPORT=y
+CONFIG_FB_OMAP2_NUM_FBS=2
+
+#
+# OMAP2/3 Display Device Drivers
+#
+# CONFIG_PANEL_GENERIC is not set
+# CONFIG_PANEL_SHARP_LS037V7DW01 is not set
+# CONFIG_PANEL_SHARP_LQ043T1DG01 is not set
+CONFIG_PANEL_PICO_DLP=y
+CONFIG_PANEL_TAAL=y
+# CONFIG_PANEL_TOPPOLY_TDO35S is not set
+# CONFIG_PANEL_TPO_TD043MTEA1 is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
 
 #
 # Display device support
 #
-# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
 
 #
 # Console display driver support
 #
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_SUPPORT=y
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c980156f3263..ea6123b8fcc3 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -79,6 +79,9 @@ extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
 
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
 extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
+extern void __iomem * __arm_multi_strided_ioremap(int, unsigned long *,
+        size_t *,unsigned long *, unsigned long *, unsigned int);
+
 extern void __iounmap(volatile void __iomem *addr);
 
 /*
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c6f319c03096..f2ba4ff103b1 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -38,6 +38,8 @@
 #include <plat/common.h>
 #include <plat/control.h>
 #include <plat/timer-gp.h>
+#include <plat/display.h>
+#include <linux/delay.h>
 #include <plat/usb.h>
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
@@ -361,8 +363,6 @@ error1:
 	return status;
 }
 
-/* Begin Synaptic Touchscreen TM-01217 */
-
 static char *tm12xx_idev_names[] = {
 	"Synaptic TM12XX TouchPoint 1",
 	"Synaptic TM12XX TouchPoint 2",
@@ -396,16 +396,232 @@ static struct tm12xx_ts_platform_data tm12xx_platform_data[] = {
 		.swap_xy = 1,
 	},
 };
+/* Begin Synaptic Touchscreen TM-01217 */
+static int sdp4430_taal_enable(struct omap_dss_device *dssdev)
+{
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+		gpio_request(102, "dsi1_en_gpio");	/* DSI1_GPIO_102*/
+		gpio_direction_output(102, 0);
+		mdelay(500);
+		gpio_set_value(102, 1);
+		mdelay(500);
+		gpio_set_value(102, 0);
+		mdelay(500);
+		gpio_set_value(102, 1);
+
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03);
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04);
+		twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92);
+
+		gpio_request(27, "dsi1_bl_gpio");	/*DSI1_GPIO_27*/
+		gpio_direction_output(27, 1);
+		mdelay(120);
+		gpio_set_value(27, 0);
+		mdelay(120);
+		gpio_set_value(27, 1);
+	} else {
+		gpio_request(104, "dsi2_en_gpio");	/* DSI2_GPIO_104 */
+		gpio_direction_output(104, 0);
+		mdelay(500);
+		gpio_set_value(104, 1);
+		mdelay(500);
+		gpio_set_value(104, 0);
+		mdelay(500);
+		gpio_set_value(104, 1);
+
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0xFF, 0x03);
+		twl_i2c_write_u8(TWL_MODULE_PWM, 0x7F, 0x04);
+		twl_i2c_write_u8(TWL6030_MODULE_ID1, 0x30, 0x92);
+
+		gpio_request(59, "dsi2_bl_gpio");	/* DSI2_GPIO_59 */
+		gpio_direction_output(59, 1);
+		mdelay(120);
+		gpio_set_value(59, 0);
+		mdelay(120);
+		gpio_set_value(59, 1);
+	}
+	return 0;
+}
 
-/* End Synaptic Touchscreen TM-01217 */
+static void sdp4430_taal_disable(struct omap_dss_device *dssdev)
+{
+	if (dssdev->channel == OMAP_DSS_CHANNEL_LCD) {
+		gpio_set_value(102, 1);	/*DSI1_GPIO_102*/
+		gpio_set_value(27, 0);	/*DSI1_GPIO_27*/
+	} else {
+		gpio_set_value(104, 1);	/* DSI2_GPIO_104 */
+		gpio_set_value(59, 0);	/* DSI2_GPIO_59 */
+	}
+}
 
-static struct platform_device sdp4430_lcd_device = {
-	.name		= "sdp4430_lcd",
-	.id		= -1,
+static struct omap_dss_device sdp4430_lcd_device = {
+	.name			= "lcd",
+	.driver_name		= "taal",
+	.type			= OMAP_DISPLAY_TYPE_DSI,
+	.reset_gpio		= 102,
+	.phy.dsi		= {
+		.clk_lane	= 1,
+		.clk_pol	= 0,
+		.data1_lane	= 2,
+		.data1_pol	= 0,
+		.data2_lane	= 3,
+		.data2_pol	= 0,
+		.ext_te		= true,
+		.ext_te_gpio	= 101,
+		.div		= {
+			.lck_div	= 1,
+			.pck_div	= 6,
+			.regm		= 200,
+			.regn		= 19,
+			.regm3		= 4,
+			.regm4		= 5,
+			.lp_clk_div	= 6,
+		},
+	},
+	.platform_enable	=	sdp4430_taal_enable,
+	.platform_disable	=	sdp4430_taal_disable,
+	.channel			=	OMAP_DSS_CHANNEL_LCD,
 };
 
-static struct platform_device *sdp4430_devices[] __initdata = {
+static struct omap_dss_device sdp4430_lcd2_device = {
+	.name			= "2lcd",
+	.driver_name		= "taal2",
+	.type			= OMAP_DISPLAY_TYPE_DSI,
+	.reset_gpio		= 102,
+	.phy.dsi		= {
+		.clk_lane	= 1,
+		.clk_pol	= 0,
+		.data1_lane	= 2,
+		.data1_pol	= 0,
+		.data2_lane	= 3,
+		.data2_pol	= 0,
+		.ext_te		= true,
+		.ext_te_gpio	= 103,
+		.div		= {
+			.lck_div	= 1,
+			.pck_div	= 6,
+			.regm		= 200,
+			.regn		= 19,
+			.regm3		= 4,
+			.regm4		= 5,
+			.lp_clk_div	= 6,
+		},
+	},
+	.platform_enable	=	sdp4430_taal_enable,
+	.platform_disable	=	sdp4430_taal_disable,
+	.channel			=	OMAP_DSS_CHANNEL_LCD2,
+ };
+
+static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
+{
+	gpio_request(HDMI_GPIO_60 , "hdmi_gpio_60");
+	gpio_request(HDMI_GPIO_41 , "hdmi_gpio_41");
+	gpio_direction_output(HDMI_GPIO_60, 0);
+	gpio_direction_output(HDMI_GPIO_41, 0);
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+	gpio_set_value(HDMI_GPIO_60, 0);
+	gpio_set_value(HDMI_GPIO_41, 0);
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+	return 0;
+}
+
+static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev)
+{
+	gpio_set_value(HDMI_GPIO_60, 1);
+	gpio_set_value(HDMI_GPIO_41, 1);
+
+}
+
+static __attribute__ ((unused)) void __init sdp4430_hdmi_init(void)
+{
+	return;
+}
+
+static struct omap_dss_device sdp4430_hdmi_device = {
+	.name = "hdmi",
+	.driver_name = "hdmi_panel",
+	.type = OMAP_DISPLAY_TYPE_HDMI,
+	.phy.dpi.data_lines = 24,
+	.platform_enable = sdp4430_panel_enable_hdmi,
+	.platform_disable = sdp4430_panel_disable_hdmi,
+};
+
+static int sdp4430_panel_enable_pico_DLP(struct omap_dss_device *dssdev)
+{
+	int i = 0;
+	gpio_request(DLP_4430_GPIO_59, "DLP DISPLAY SEL");
+	gpio_direction_output(DLP_4430_GPIO_59, 0);
+	gpio_request(DLP_4430_GPIO_45, "DLP PARK");
+	gpio_direction_output(DLP_4430_GPIO_45, 0);
+	gpio_request(DLP_4430_GPIO_40, "DLP PHY RESET");
+	gpio_direction_output(DLP_4430_GPIO_40, 0);
+	gpio_request(DLP_4430_GPIO_44, "DLP READY RESET");
+	gpio_direction_input(DLP_4430_GPIO_44);
+	mdelay(500);
+
+	gpio_set_value(DLP_4430_GPIO_59, 1);
+	gpio_set_value(DLP_4430_GPIO_45, 1);
+	mdelay(1000);
+
+	gpio_set_value(DLP_4430_GPIO_40, 1);
+	mdelay(1000);
+
+	/*FIXME with the MLO gpio changes , gpio read is not retuning correct value even though 		it is  set in hardware so the check is comment till the problem is fixed */
+	/*while(i == 0){
+	i=gpio_get_value(DLP_4430_GPIO_44);
+	printk("wait for ready bit %d\n",i);
+	}*/
+	printk("%d ready bit ", i);
+	mdelay(2000);
+	return 0;
+}
+
+static void sdp4430_panel_disable_pico_DLP(struct omap_dss_device *dssdev)
+{
+	gpio_set_value(DLP_4430_GPIO_40, 0);
+	gpio_set_value(DLP_4430_GPIO_45, 0);
+
+}
+
+static struct omap_dss_device sdp4430_picoDLP_device = {
+	.name			            = "pico_DLP",
+	.driver_name		        = "picoDLP_panel",
+	.type			            = OMAP_DISPLAY_TYPE_DPI,
+	.phy.dpi.data_lines	        = 24,
+	.platform_enable	        = sdp4430_panel_enable_pico_DLP,
+	.platform_disable	        = sdp4430_panel_disable_pico_DLP,
+	.channel			= OMAP_DSS_CHANNEL_LCD2,
+};
+
+static struct omap_dss_device *sdp4430_dss_devices[] = {
 	&sdp4430_lcd_device,
+	&sdp4430_lcd2_device,
+#ifdef CONFIG_OMAP2_DSS_HDMI
+	&sdp4430_hdmi_device,
+#endif
+#ifdef CONFIG_PANEL_PICO_DLP
+	&sdp4430_picoDLP_device,
+#endif
+};
+
+static struct omap_dss_board_info sdp4430_dss_data = {
+	.num_devices	=	ARRAY_SIZE(sdp4430_dss_devices),
+	.devices	=	sdp4430_dss_devices,
+	.default_device	=	&sdp4430_lcd_device,
+};
+
+static struct platform_device sdp4430_dss_device = {
+	.name	=	"omapdss",
+	.id	=	-1,
+	.dev	= {
+		.platform_data = &sdp4430_dss_data,
+	},
+};
+
+static struct platform_device *sdp4430_devices[] __initdata = {
+	&sdp4430_dss_device,
 	&sdp4430_keypad_device,
 	&sdp4430_proximity_device,
 	&sdp4430_leds_gpio,
@@ -716,6 +932,12 @@ static struct cma3000_platform_data cma3000_platform_data = {
 	.irqflags = IRQF_TRIGGER_HIGH,
 };
 
+static struct pico_platform_data picodlp_platform_data[] = {
+	[0] = { /* DLP Controller */
+		.gpio_intr = 40,
+	},
+};
+
 static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
 	{
 		I2C_BOARD_INFO("twl6030", 0x48),
@@ -734,6 +956,10 @@ static struct i2c_board_info __initdata sdp4430_i2c_2_boardinfo[] = {
 		I2C_BOARD_INFO("tm12xx_ts_primary", 0x4b),
 		.platform_data = &tm12xx_platform_data[0],
 	},
+    {
+		I2C_BOARD_INFO("picoDLP_i2c_driver", 0x1b),
+		.platform_data = &picodlp_platform_data[0],
+	},
 };
 
 static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@@ -836,11 +1062,22 @@ static void omap_cma3000accl_init(void)
 	gpio_direction_input(OMAP4_CMA3000ACCL_GPIO);
 }
 
+static void __init omap4_display_init(void)
+{
+	void __iomem *phymux_base = NULL;
+	unsigned int dsimux = 0xFFFFFFFF;
+	phymux_base = ioremap(0x4A100000, 0x1000);
+	/* Turning on DSI PHY Mux*/
+	__raw_writel(dsimux, phymux_base+0x618);
+	dsimux = __raw_readl(phymux_base+0x618);
+}
+
 static void __init omap_4430sdp_init(void)
 {
 	int status;
 
 	omap4_i2c_init();
+	omap4_display_init();
 	platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
 	omap_serial_init();
 	omap4_twl6030_hsmmc_init(mmc);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 944128df3972..6a24405da6b7 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -696,6 +696,58 @@ static inline void omap_hdq_init(void)
 static inline void omap_hdq_init(void) {}
 #endif
 
+/*---------------------------------------------------------------------------*/
+
+#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
+	defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
+#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
+#ifdef CONFIG_ARCH_OMAP4
+static struct resource omap_vout_resource[4 - CONFIG_FB_OMAP2_NUM_FBS] = {
+#else
+static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
+#endif
+};
+#else
+#ifdef CONFIG_ARCH_OMAP4
+static struct resource omap_vout_resource[3] = {
+#else
+static struct resource omap_vout_resource[2] = {
+#endif
+};
+#endif
+
+static struct platform_device omap_vout_device = {
+	.name		= "omap_vout",
+	.num_resources	= ARRAY_SIZE(omap_vout_resource),
+	.resource	= &omap_vout_resource[0],
+	.id		= -1,
+};
+static void omap_init_vout(void)
+{
+	if (platform_device_register(&omap_vout_device) < 0)
+		printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
+}
+
+static struct resource sdp4430_wb_resource[1] = {
+};
+
+static struct platform_device sdp4430_wb_device = {
+	.name		= "omap_wb",
+	.num_resources	= ARRAY_SIZE(sdp4430_wb_resource),
+	.resource	= &sdp4430_wb_resource[0],
+	.id		= -1,
+};
+
+static void omap_init_wb(void)
+{
+		(void) platform_device_register(&sdp4430_wb_device);
+}
+
+#else
+static inline void omap_init_vout(void) {}
+static void omap_init_wb(void) {}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -709,6 +761,9 @@ static int __init omap2_init_devices(void)
 	omap_hdq_init();
 	omap_init_sti();
 	omap_init_sha1_md5();
+	omap_init_vout();
+	if (cpu_is_omap44xx())
+		omap_init_wb();
 
 	return 0;
 }
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 28c8b950ef04..d5a38801cc08 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -349,6 +349,109 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+#define MAX_SECTIONS 4
+void __iomem *
+__arm_multi_strided_ioremap(int sections,
+			    unsigned long *phys_addr, size_t *phys_size,
+			    unsigned long *phys_stride,
+			    unsigned long *virt_stride,
+			    unsigned int mtype)
+{
+	unsigned long pfns[MAX_SECTIONS];
+	const struct mem_type *type;
+	unsigned long total_size = 0, j;
+	int err = 0, i;
+	unsigned long addr, addr_i, pstride, vstride;
+	struct vm_struct * area;
+
+	if (sections > MAX_SECTIONS)
+		return NULL;
+
+	for (i = 0; i < sections; i++) {
+		/* both physical and virtual strides must be both specified
+		   or neither specified */
+		pstride = ((phys_stride && phys_stride[i]) ?
+			   phys_stride[i] : phys_size[i]);
+		vstride = ((virt_stride && virt_stride[i]) ?
+			   virt_stride[i] : phys_size[i]);
+
+		if (!pstride ^ !vstride)
+			return NULL;
+
+		/*
+		* Don't allow wraparound or zero size.  Also, sections
+		* must end/begin on page boundary, and strides be page
+		* aligned
+		*
+		* For now, size must be multiple of physical stride.  This
+		* may be relaxed to contain only full virtual strides.  (E.g.
+		* not have to contain the waste after the last virtual block.)
+		*
+		*/
+		if (((phys_addr[i] | phys_size[i] |
+		      vstride | pstride) & ~PAGE_MASK) ||
+		    !phys_size[i] ||
+		    vstride > pstride ||
+		    (pstride && (phys_size[i] % pstride)) ||
+		    (phys_addr[i] + phys_size[i] - 1 < phys_addr[i]))
+			return NULL;
+
+		pfns[i] = __phys_to_pfn(phys_addr[i]);
+
+		/*
+		 * High mappings must be supersection aligned
+		 */
+		if (pfns[i] >= 0x100000 &&
+		    (__pfn_to_phys(pfns[i]) & ~SUPERSECTION_MASK))
+			return NULL;
+
+		total_size += phys_size[i] / pstride * vstride;
+	}
+
+	type = get_mem_type(mtype);
+	if (!type)
+		return NULL;
+
+	area = get_vm_area(total_size, VM_IOREMAP);
+	if (!area)
+		return NULL;
+	addr = addr_i = (unsigned long)area->addr;
+
+	for (i = 0; i < sections && !err; i++) {
+		printk(KERN_ERR "mapping %lx to %lx (%x)\n", __pfn_to_phys(pfns[i]), addr_i, phys_size[i]);
+		pstride = ((phys_stride && phys_stride[i]) ?
+			   phys_stride[i] : phys_size[i]);
+		vstride = ((virt_stride && virt_stride[i]) ?
+			   virt_stride[i] : phys_size[i]);
+		for (j = 0; j < phys_size[i]; j += pstride) {
+	#ifndef CONFIG_SMP
+			if (DOMAIN_IO == 0 &&
+			    (((cpu_architecture() >= CPU_ARCH_ARMv6) && (get_cr() & CR_XP)) ||
+			       cpu_is_xsc3()) && pfns[i] >= 0x100000 &&
+			       !((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~SUPERSECTION_MASK)) {
+				area->flags |= VM_ARM_SECTION_MAPPING;
+				err = remap_area_supersections(addr_i, pfns[i], size[i], type);
+			} else if (!((__pfn_to_phys(pfns[i]) | vstride | addr_i) & ~PMD_MASK)) {
+				area->flags |= VM_ARM_SECTION_MAPPING;
+				err = remap_area_sections(addr_i, pfns[i], vstride, type);
+			} else
+	#endif
+				err = remap_area_pages(addr_i, pfns[i], vstride, type);
+			pfns[i] += __phys_to_pfn(pstride);
+			addr_i += vstride;
+		}
+	}
+
+	if (err) {
+		vunmap((void *)addr);
+		return NULL;
+	}
+
+	flush_cache_vmap(addr, addr + total_size);
+	return (void __iomem *) addr;
+}
+EXPORT_SYMBOL(__arm_multi_strided_ioremap);
+
 void __iounmap(volatile void __iomem *io_addr)
 {
 	void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 4cd4ebd9dd01..5d3ff85dd753 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
-	 usb.o fb.o io.o
+	 usb.o fb.o io.o hdmi_lib.o
 obj-m :=
 obj-n :=
 obj-  :=
@@ -38,4 +38,4 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
 obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
 obj-$(CONFIG_OMAP_REMOTE_PROC) += remoteproc.o
 
-obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
\ No newline at end of file
+obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/hdmi_lib.c b/arch/arm/plat-omap/hdmi_lib.c
new file mode 100644
index 000000000000..efc409a35534
--- /dev/null
+++ b/arch/arm/plat-omap/hdmi_lib.c
@@ -0,0 +1,1482 @@
+/*
+ * hdmi_lib.c
+ *
+ * HDMI library support functions for TI OMAP processors.
+ *
+ * Copyright (C) 2010 Texas Instruments
+ * Author: Yong Zhi <y-zhi@ti.com>
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/* Rev history:
+ * Yong Zhi <y-zhi@ti.com>	changed SiVal macros
+ * 				added PLL/PHY code
+ *				added EDID code
+ * 				moved PLL/PHY code to hdmi panel driver
+ * 				cleanup 2/08/10
+ * MythriPk <mythripk@ti.com>	Apr 2010 Modified to read extended EDID partition
+ *				and handle checksum with and without extension
+ *				May 2010 Added support for Hot Plug Detect.
+ *
+ */
+
+#define DSS_SUBSYS_NAME "HDMI"
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+#include <plat/hdmi_lib.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+
+/* HDMI PHY */
+#define HDMI_TXPHY_TX_CTRL						0x0ul
+#define HDMI_TXPHY_DIGITAL_CTRL					0x4ul
+#define HDMI_TXPHY_POWER_CTRL					0x8ul
+
+/* HDMI Wrapper */
+#define HDMI_WP_REVISION						0x0ul
+#define HDMI_WP_SYSCONFIG						0x10ul
+#define HDMI_WP_IRQSTATUS_RAW					0x24ul
+#define HDMI_WP_IRQSTATUS						0x28ul
+#define HDMI_WP_PWR_CTRL						0x40ul
+#define HDMI_WP_IRQENABLE_SET					0x2Cul
+#define HDMI_WP_VIDEO_CFG						0x50ul
+#define HDMI_WP_VIDEO_SIZE						0x60ul
+#define HDMI_WP_VIDEO_TIMING_H					0x68ul
+#define HDMI_WP_VIDEO_TIMING_V					0x6Cul
+#define HDMI_WP_WP_CLK								0x70ul
+
+/* HDMI IP Core System */
+#define HDMI_CORE_SYS__VND_IDL					0x0ul
+#define HDMI_CORE_SYS__DEV_IDL					0x8ul
+#define HDMI_CORE_SYS__DEV_IDH					0xCul
+#define HDMI_CORE_SYS__DEV_REV					0x10ul
+#define HDMI_CORE_SYS__SRST						0x14ul
+#define HDMI_CORE_CTRL1							0x20ul
+#define HDMI_CORE_SYS__SYS_STAT					0x24ul
+#define HDMI_CORE_SYS__VID_ACEN					0x124ul
+#define HDMI_CORE_SYS__VID_MODE					0x128ul
+#define HDMI_CORE_SYS__INTR_STATE				0x1C0ul
+#define HDMI_CORE_SYS__INTR1					0x1C4ul
+#define HDMI_CORE_SYS__INTR2					0x1C8ul
+#define HDMI_CORE_SYS__INTR3					0x1CCul
+#define HDMI_CORE_SYS__INTR4					0x1D0ul
+#define HDMI_CORE_SYS__UMASK1					0x1D4ul
+#define HDMI_CORE_SYS__TMDS_CTRL				0x208ul
+#define HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC		0x1ul
+#define HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC		0x1ul
+#define HDMI_CORE_CTRL1_BSEL__24BITBUS			0x1ul
+#define HDMI_CORE_CTRL1_EDGE__RISINGEDGE		0x1ul
+
+#define HDMI_CORE_SYS__DE_DLY				0xC8ul
+#define HDMI_CORE_SYS__DE_CTRL				0xCCul
+#define HDMI_CORE_SYS__DE_TOP				0xD0ul
+#define HDMI_CORE_SYS__DE_CNTL				0xD8ul
+#define HDMI_CORE_SYS__DE_CNTH				0xDCul
+#define HDMI_CORE_SYS__DE_LINL				0xE0ul
+#define HDMI_CORE_SYS__DE_LINH__1			0xE4ul
+
+/* HDMI IP Core Audio Video */
+#define HDMI_CORE_AV_HDMI_CTRL				0xBCul
+#define HDMI_CORE_AV_DPD					0xF4ul
+#define HDMI_CORE_AV_PB_CTRL1				0xF8ul
+#define HDMI_CORE_AV_PB_CTRL2				0xFCul
+#define HDMI_CORE_AV_AVI_TYPE				0x100ul
+#define HDMI_CORE_AV_AVI_VERS				0x104ul
+#define HDMI_CORE_AV_AVI_LEN				0x108ul
+#define HDMI_CORE_AV_AVI_CHSUM				0x10Cul
+#define HDMI_CORE_AV_AVI_DBYTE				0x110ul
+#define HDMI_CORE_AV_AVI_DBYTE__ELSIZE		0x4ul
+
+/* HDMI DDC E-DID */
+#define HDMI_CORE_DDC_CMD				0x3CCul
+#define HDMI_CORE_DDC_STATUS			0x3C8ul
+#define HDMI_CORE_DDC_ADDR				0x3B4ul
+#define HDMI_CORE_DDC_OFFSET			0x3BCul
+#define HDMI_CORE_DDC_COUNT1			0x3C0ul
+#define HDMI_CORE_DDC_COUNT2			0x3C4ul
+#define HDMI_CORE_DDC_DATA				0x3D0ul
+#define HDMI_CORE_DDC_SEGM				0x3B8ul
+
+#define HDMI_WP_AUDIO_CFG                         0x80ul
+#define HDMI_WP_AUDIO_CFG2                        0x84ul
+#define HDMI_WP_AUDIO_CTRL                        0x88ul
+#define HDMI_WP_AUDIO_DATA                        0x8Cul
+
+#define HDMI_CORE_AV__AVI_DBYTE                0x110ul
+#define HDMI_CORE_AV__AVI_DBYTE__ELSIZE        0x4ul
+#define HDMI_IP_CORE_AV__AVI_DBYTE__NELEMS        15
+#define HDMI_CORE_AV__SPD_DBYTE                0x190ul
+#define HDMI_CORE_AV__SPD_DBYTE__ELSIZE        0x4ul
+#define HDMI_CORE_AV__SPD_DBYTE__NELEMS        27
+#define HDMI_CORE_AV__AUDIO_DBYTE              0x210ul
+#define HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE      0x4ul
+#define HDMI_CORE_AV__AUDIO_DBYTE__NELEMS      10
+#define HDMI_CORE_AV__MPEG_DBYTE               0x290ul
+#define HDMI_CORE_AV__MPEG_DBYTE__ELSIZE       0x4ul
+#define HDMI_CORE_AV__MPEG_DBYTE__NELEMS       27
+#define HDMI_CORE_AV__GEN_DBYTE                0x300ul
+#define HDMI_CORE_AV__GEN_DBYTE__ELSIZE        0x4ul
+#define HDMI_CORE_AV__GEN_DBYTE__NELEMS        31
+#define HDMI_CORE_AV__GEN2_DBYTE               0x380ul
+#define HDMI_CORE_AV__GEN2_DBYTE__ELSIZE       0x4ul
+#define HDMI_CORE_AV__GEN2_DBYTE__NELEMS       31
+#define HDMI_CORE_AV__ACR_CTRL                 0x4ul
+#define HDMI_CORE_AV__FREQ_SVAL                0x8ul
+#define HDMI_CORE_AV__N_SVAL1                  0xCul
+#define HDMI_CORE_AV__N_SVAL2                  0x10ul
+#define HDMI_CORE_AV__N_SVAL3                  0x14ul
+#define HDMI_CORE_AV__CTS_SVAL1                0x18ul
+#define HDMI_CORE_AV__CTS_SVAL2                0x1Cul
+#define HDMI_CORE_AV__CTS_SVAL3                0x20ul
+#define HDMI_CORE_AV__CTS_HVAL1                0x24ul
+#define HDMI_CORE_AV__CTS_HVAL2                0x28ul
+#define HDMI_CORE_AV__CTS_HVAL3                0x2Cul
+#define HDMI_CORE_AV__AUD_MODE                 0x50ul
+#define HDMI_CORE_AV__SPDIF_CTRL               0x54ul
+#define HDMI_CORE_AV__HW_SPDIF_FS              0x60ul
+#define HDMI_CORE_AV__SWAP_I2S                 0x64ul
+#define HDMI_CORE_AV__SPDIF_ERTH               0x6Cul
+#define HDMI_CORE_AV__I2S_IN_MAP               0x70ul
+#define HDMI_CORE_AV__I2S_IN_CTRL              0x74ul
+#define HDMI_CORE_AV__I2S_CHST0                0x78ul
+#define HDMI_CORE_AV__I2S_CHST1                0x7Cul
+#define HDMI_CORE_AV__I2S_CHST2                0x80ul
+#define HDMI_CORE_AV__I2S_CHST4                0x84ul
+#define HDMI_CORE_AV__I2S_CHST5                0x88ul
+#define HDMI_CORE_AV__ASRC                     0x8Cul
+#define HDMI_CORE_AV__I2S_IN_LEN               0x90ul
+#define HDMI_CORE_AV__HDMI_CTRL                0xBCul
+#define HDMI_CORE_AV__AUDO_TXSTAT              0xC0ul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_1         0xCCul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_2         0xD0ul
+#define HDMI_CORE_AV__AUD_PAR_BUSCLK_3         0xD4ul
+#define HDMI_CORE_AV__TEST_TXCTRL              0xF0ul
+#define HDMI_CORE_AV__DPD                      0xF4ul
+#define HDMI_CORE_AV__PB_CTRL1                 0xF8ul
+#define HDMI_CORE_AV__PB_CTRL2                 0xFCul
+#define HDMI_CORE_AV__AVI_TYPE                 0x100ul
+#define HDMI_CORE_AV__AVI_VERS                 0x104ul
+#define HDMI_CORE_AV__AVI_LEN                  0x108ul
+#define HDMI_CORE_AV__AVI_CHSUM                0x10Cul
+#define HDMI_CORE_AV__SPD_TYPE                 0x180ul
+#define HDMI_CORE_AV__SPD_VERS                 0x184ul
+#define HDMI_CORE_AV__SPD_LEN                  0x188ul
+#define HDMI_CORE_AV__SPD_CHSUM                0x18Cul
+#define HDMI_CORE_AV__AUDIO_TYPE               0x200ul
+#define HDMI_CORE_AV__AUDIO_VERS               0x204ul
+#define HDMI_CORE_AV__AUDIO_LEN                0x208ul
+#define HDMI_CORE_AV__AUDIO_CHSUM              0x20Cul
+#define HDMI_CORE_AV__MPEG_TYPE                0x280ul
+#define HDMI_CORE_AV__MPEG_VERS                0x284ul
+#define HDMI_CORE_AV__MPEG_LEN                 0x288ul
+#define HDMI_CORE_AV__MPEG_CHSUM               0x28Cul
+#define HDMI_CORE_AV__CP_BYTE1                 0x37Cul
+#define HDMI_CORE_AV__CEC_ADDR_ID              0x3FCul
+
+
+static struct {
+	void __iomem *base_core;     /*0*/
+	void __iomem *base_core_av;  /*1*/
+	void __iomem *base_wp;       /*2*/
+	struct mutex hdmi_lock;
+} hdmi;
+
+int count = 0, count_hpd = 0;
+
+static inline void hdmi_write_reg(u32 base, u16 idx, u32 val)
+{
+	void __iomem *b;
+
+	switch (base) {
+	case HDMI_CORE_SYS:
+	  b = hdmi.base_core;
+	  break;
+	case HDMI_CORE_AV:
+	  b = hdmi.base_core_av;
+	  break;
+	case HDMI_WP:
+	  b = hdmi.base_wp;
+	  break;
+	default:
+	  BUG();
+	}
+	__raw_writel(val, b + idx);
+	/* DBG("write = 0x%x idx =0x%x\r\n", val, idx); */
+}
+
+static inline u32 hdmi_read_reg(u32 base, u16 idx)
+{
+	void __iomem *b;
+	u32 l;
+
+	switch (base) {
+	case HDMI_CORE_SYS:
+	 b = hdmi.base_core;
+	 break;
+	case HDMI_CORE_AV:
+	 b = hdmi.base_core_av;
+	 break;
+	case HDMI_WP:
+	 b = hdmi.base_wp;
+	 break;
+	default:
+	 BUG();
+	}
+	l = __raw_readl(b + idx);
+
+	/* DBG("addr = 0x%p rd = 0x%x idx = 0x%x\r\n", (b+idx), l, idx); */
+	return l;
+}
+
+#define FLD_MASK(start, end)	(((1 << (start - end + 1)) - 1) << (end))
+#define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end))
+#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
+#define FLD_MOD(orig, val, start, end) \
+	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
+
+#define REG_FLD_MOD(base, idx, val, start, end) \
+	hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx), val, start, end))
+
+#define RD_REG_32(COMP, REG)            hdmi_read_reg(COMP, REG)
+#define WR_REG_32(COMP, REG, VAL)       hdmi_write_reg(COMP, REG, (u32)(VAL))
+
+u8 edid_backup[256];
+
+
+int hdmi_get_image_format(void)
+{
+	int offset = 0x4, i, current_byte, length, flag = 0, j = 0;
+	if (edid_backup[0x7e] != 0x00) {
+		printk(KERN_INFO"Extension block present");
+		offset = edid_backup[(0x80) + 2];
+		if (offset != 0x4) {
+			i = 0x80 + 4;
+			while (i < (0x80 + offset)) {
+				current_byte = edid_backup[i];
+				if ((current_byte >> 5) == 0x2) {
+					length = current_byte & 0x1F;
+					for (j = 1 ; j < length ; j++) {
+						current_byte = edid_backup[i+j];
+						printk(KERN_INFO"Image format supported is %d", current_byte & 0x7F);
+
+					}
+				flag = 1;
+				break;
+
+				} else {
+					length = (current_byte & 0x1F) + 1;
+					i += length;
+				}
+			}
+		}
+
+	} else if (edid_backup[0x7e] != 0x00 && flag == 0) {
+		printk(KERN_INFO "Video Information Data Not found");
+	} else {
+		printk(KERN_INFO "TV does not have Extension Block");
+	}
+	return 0 ;
+}
+EXPORT_SYMBOL(hdmi_get_image_format);
+
+int hdmi_get_audio_format(void)
+{
+	int offset = 0x4, i, current_byte, length, flag = 0, j = 0;
+	if (edid_backup[0x7e] != 0x00) {
+		printk(KERN_INFO"Extension block present");
+		offset = edid_backup[(0x80) + 2];
+		if (offset != 0x4) {
+			i = 0x80 + 4;
+			while (i < (0x80 + offset)) {
+				current_byte = edid_backup[i];
+				if ((current_byte >> 5) == 1) {
+					current_byte = edid_backup[i];
+					length = current_byte & 0x1F;
+					for (j = 1 ; j < length ; j++) {
+						if (j%3 == 1) {
+						current_byte = edid_backup[i+j];
+						printk(KERN_INFO"Audio format supported is %d", current_byte & 0x78);
+printk(KERN_INFO"Number of channels supported %d", (current_byte & 0x07) + 1);
+						}
+
+					}
+				flag = 1;
+				break;
+				} else {
+					length = (current_byte & 0x1F) + 1;
+					i += length;
+				}
+			}
+		}
+
+	} else if (edid_backup[0x7e] != 0x00 && flag == 0) {
+		printk(KERN_INFO "Audio Information Data Not found");
+	} else {
+		printk(KERN_INFO "TV does not have Extension Block");
+	}
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_audio_format);
+
+int hdmi_get_audio_video_latency(void)
+{
+	printk("This is yet to be implemented");
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_audio_video_latency);
+
+int hdmi_get_pixel_append_position(void)
+{
+	printk("This is yet to be implemented");
+	return 0;
+}
+EXPORT_SYMBOL(hdmi_get_pixel_append_position);
+
+int hdmi_core_ddc_edid(u8 *pEDID)
+{
+	u32 i, j, l;
+	char checksum = 0;
+	u32 sts = HDMI_CORE_DDC_STATUS;
+	u32 ins = HDMI_CORE_SYS;
+
+	/* Turn on CLK for DDC */
+	REG_FLD_MOD(HDMI_CORE_AV, HDMI_CORE_AV_DPD, 0x7, 2, 0);
+
+	/* Wait */
+	mdelay(10);
+
+	/* Clk SCL Devices */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
+
+	/* HDMI_CORE_DDC_STATUS__IN_PROG */
+	while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+
+	/* Clear FIFO */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
+
+	/* HDMI_CORE_DDC_STATUS__IN_PROG */
+	while (FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+
+	/* Load Slave Address Register */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
+
+	/* Load Offset Address Register */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_OFFSET, 0x0, 7, 0);
+	/* Load Byte Count */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT1, 0x100, 7, 0);
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_COUNT2, 0x100>>8, 1, 0);
+	/* Set DDC_CMD */
+	REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
+
+	/* Yong: do not optimize this part of the code, seems
+	DDC bus needs some time to get stabilized
+	*/
+	l = hdmi_read_reg(ins, sts);
+
+	/* HDMI_CORE_DDC_STATUS__BUS_LOW */
+	if (FLD_GET(l, 6, 6) == 1) {
+		printk("I2C Bus Low?\n\r");
+		return -1;
+	}
+	/* HDMI_CORE_DDC_STATUS__NO_ACK */
+	if (FLD_GET(l, 5, 5) == 1) {
+		printk("I2C No Ack\n\r");
+		return -1;
+	}
+
+	j = 100;
+	while (j--) {
+		l = hdmi_read_reg(ins, sts);
+		/* progress */
+		if (FLD_GET(l, 4, 4) == 1) {
+			/* HACK: Load Slave Address Register again */
+			REG_FLD_MOD(ins, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
+			REG_FLD_MOD(ins, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
+			break;
+		}
+		mdelay(20);
+	}
+
+	i = 0;
+	while (((FLD_GET(hdmi_read_reg(ins, sts), 4, 4) == 1)
+			| (FLD_GET(hdmi_read_reg(ins, sts), 2, 2) == 0)) && i < 256) {
+		if (FLD_GET(hdmi_read_reg(ins,
+			sts), 2, 2) == 0) {
+			/* FIFO not empty */
+			pEDID[i++] = FLD_GET(hdmi_read_reg(ins, HDMI_CORE_DDC_DATA), 7, 0);
+		}
+	}
+
+	if (pEDID[0x14] == 0x80) {/* Digital Display */
+		if (pEDID[0x7e] == 0x00) {/* No Extention Block */
+			for (j = 0; j < 128; j++)
+			checksum += pEDID[j];
+			DBG("No extension 128 bit checksum\n");
+		} else {
+			for (j = 0; j < 256; j++)
+			checksum += pEDID[j];
+			DBG("Extension present 256 bit checksum\n");
+			/* HDMI_CORE_DDC_READ_EXTBLOCK(); */
+		}
+	} else {
+		DBG("Analog Display\n");
+	}
+
+	DBG("EDID Content %d\n", i);
+	for (i = 0 ; i < 256 ; i++)
+		edid_backup[i] = pEDID[i];
+
+#ifdef DEBUG_EDID
+	DBG("Header:\n");
+	for (i = 0x00; i < 0x08; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Vendor & Product:\n");
+	for (i = 0x08; i < 0x12; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("EDID Structure:\n");
+	for (i = 0x12; i < 0x14; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Basic Display Parameter:\n");
+	for (i = 0x14; i < 0x19; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Color Characteristics:\n");
+	for (i = 0x19; i < 0x23; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Established timings:\n");
+	for (i = 0x23; i < 0x26; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Standart timings:\n");
+	for (i = 0x26; i < 0x36; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing1:\n");
+	for (i = 0x36; i < 0x48; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing2:\n");
+	for (i = 0x48; i < 0x5a; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing3:\n");
+	for (i = 0x5a; i < 0x6c; i++)
+		DBG("%02x\n", pEDID[i]);
+	DBG("Detailed timing4:\n");
+	for (i = 0x6c; i < 0x7e; i++)
+		DBG("%02x\n", pEDID[i]);
+#endif
+	if (checksum != 0) {
+		printk("E-EDID checksum failed!!");
+		return -1;
+	}
+	return 0;
+}
+
+static void hdmi_core_init(struct hdmi_core_video_config_t *v_cfg,
+	struct hdmi_core_audio_config *audio_cfg,
+	struct hdmi_core_infoframe_avi *avi,
+	struct hdmi_core_packet_enable_repeat *r_p)
+{
+	DBG("Enter HDMI_Core_GlobalInitVars()\n");
+
+	/*video core*/
+	v_cfg->CoreInputBusWide = HDMI_INPUT_8BIT;
+	v_cfg->CoreOutputDitherTruncation = HDMI_OUTPUTTRUNCATION_8BIT;
+	v_cfg->CoreDeepColorPacketED = HDMI_DEEPCOLORPACKECTDISABLE;
+	v_cfg->CorePacketMode = HDMI_PACKETMODERESERVEDVALUE;
+	v_cfg->CoreHdmiDvi = HDMI_DVI;
+	v_cfg->CoreTclkSelClkMult = FPLL10IDCK;
+
+	/*audio core*/
+	audio_cfg->fs = FS_44100;
+	audio_cfg->n = 0;
+	audio_cfg->cts = 0;
+	audio_cfg->layout = LAYOUT_2CH; /*2channel audio*/
+	audio_cfg->aud_par_busclk = 0;
+	audio_cfg->cts_mode = CTS_MODE_HW;
+
+	/*info frame*/
+	avi->db1y_rgb_yuv422_yuv444 = 0;
+	avi->db1a_active_format_off_on = 0;
+	avi->db1b_no_vert_hori_verthori = 0;
+	avi->db1s_0_1_2 = 0;
+	avi->db2c_no_itu601_itu709_extented = 0;
+	avi->db2m_no_43_169 = 0;
+	avi->db2r_same_43_169_149 = 0;
+	avi->db3itc_no_yes = 0;
+	avi->db3ec_xvyuv601_xvyuv709 = 0;
+	avi->db3q_default_lr_fr = 0;
+	avi->db3sc_no_hori_vert_horivert = 0;
+	avi->db4vic_videocode = 0;
+	avi->db5pr_no_2_3_4_5_6_7_8_9_10 = 0;
+	avi->db6_7_lineendoftop = 0 ;
+	avi->db8_9_linestartofbottom = 0;
+	avi->db10_11_pixelendofleft = 0;
+	avi->db12_13_pixelstartofright = 0;
+
+	/*packet enable and repeat*/
+	r_p->AudioPacketED = 0;
+	r_p->AudioPacketRepeat = 0;
+	r_p->AVIInfoFrameED = 0;
+	r_p->AVIInfoFrameRepeat = 0;
+	r_p->GeneralcontrolPacketED = 0;
+	r_p->GeneralcontrolPacketRepeat = 0;
+	r_p->GenericPacketED = 0;
+	r_p->GenericPacketRepeat = 0;
+}
+
+static void hdmi_core_powerdown_disable(void)
+{
+	DBG("Enter DSS_HDMI_CORE_POWER_DOWN_DISABLE()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x0, 0, 0);
+}
+
+/* todo: power off the core */
+static __attribute__ ((unused)) void hdmi_core_powerdown_enable(void)
+{
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_CTRL1, 0x1, 0, 0);
+}
+
+static void hdmi_core_swreset_release(void)
+{
+	DBG("Enter DSS_HDMI_CORE_SW_RESET_RELEASE()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x0, 0, 0);
+}
+
+static void hdmi_core_swreset_assert(void)
+{
+	DBG("Enter DSS_HDMI_CORE_SW_RESET_ASSERT ()\n");
+	REG_FLD_MOD(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST, 0x1, 0, 0);
+}
+
+/* DSS_HDMI_CORE_VIDEO_CONFIG */
+static int hdmi_core_video_config(
+	struct hdmi_core_video_config_t *cfg)
+{
+	u32 name = HDMI_CORE_SYS;
+	u32 av_name = HDMI_CORE_AV;
+	u32 r = 0;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	u32 ven;
+	u32 hen;
+	u32 bsel;
+	u32 edge;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	ven = HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC;
+	hen = HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC;
+	bsel = HDMI_CORE_CTRL1_BSEL__24BITBUS;
+	edge = HDMI_CORE_CTRL1_EDGE__RISINGEDGE;
+
+	/*sys_ctrl1 default configuration not tunable*/
+	r = hdmi_read_reg(name, HDMI_CORE_CTRL1);
+	r = FLD_MOD(r, ven, 5, 5);
+	r = FLD_MOD(r, hen, 4, 4);
+	r = FLD_MOD(r, bsel, 2, 2);
+	r = FLD_MOD(r, edge, 1, 1);
+	hdmi_write_reg(name, HDMI_CORE_CTRL1, r);
+
+	REG_FLD_MOD(name, HDMI_CORE_SYS__VID_ACEN, cfg->CoreInputBusWide, 7, 6);
+
+	/*Vid_Mode */
+	r = hdmi_read_reg(name, HDMI_CORE_SYS__VID_MODE);
+	/*dither truncation configuration*/
+	if (cfg->CoreOutputDitherTruncation >
+				HDMI_OUTPUTTRUNCATION_12BIT) {
+		r = FLD_MOD(r, cfg->CoreOutputDitherTruncation - 3, 7, 6);
+		r = FLD_MOD(r, 1, 5, 5);
+	} else {
+		r = FLD_MOD(r, cfg->CoreOutputDitherTruncation, 7, 6);
+		r = FLD_MOD(r, 0, 5, 5);
+	}
+	hdmi_write_reg(name, HDMI_CORE_SYS__VID_MODE, r);
+
+	/*HDMI_Ctrl*/
+	r = hdmi_read_reg(av_name, HDMI_CORE_AV_HDMI_CTRL);
+	r = FLD_MOD(r, cfg->CoreDeepColorPacketED, 6, 6);
+	r = FLD_MOD(r, cfg->CorePacketMode, 5, 3);
+	r = FLD_MOD(r, cfg->CoreHdmiDvi, 0, 0);
+	hdmi_write_reg(av_name, HDMI_CORE_AV_HDMI_CTRL, r);
+
+	/*TMDS_CTRL*/
+	REG_FLD_MOD(name, HDMI_CORE_SYS__TMDS_CTRL,
+		cfg->CoreTclkSelClkMult, 6, 5);
+
+	return 0;
+}
+
+static int hdmi_core_audio_mode_enable(u32  instanceName)
+{
+	REG_FLD_MOD(instanceName, HDMI_CORE_AV__AUD_MODE, 1, 0, 0);
+	return 0;
+}
+
+static int hdmi_core_audio_config(u32 name,
+		struct hdmi_core_audio_config *audio_cfg)
+{
+	int ret = 0;
+	u32 SD3_EN, SD2_EN, SD1_EN, SD0_EN;
+	u8 DBYTE1, DBYTE2, DBYTE4, CHSUM;
+	u8 size1;
+	u16 size0;
+
+	/*CTS_MODE*/
+	WR_REG_32(name, HDMI_CORE_AV__ACR_CTRL,
+		((0x0 << 2) | /* MCLK_EN (0: Mclk is not used)*/
+		(0x1 << 1) | /* CTS Request Enable (1:Packet Enable, 0:Disable) */
+		(audio_cfg->cts_mode << 0))); /* CTS Source Select  (1:SW, 0:HW)*/
+
+	REG_FLD_MOD(name, HDMI_CORE_AV__FREQ_SVAL, 0, 2, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL1, audio_cfg->n, 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL2, (audio_cfg->n >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__N_SVAL3, (audio_cfg->n >> 16), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL1, (audio_cfg->cts), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL2, (audio_cfg->cts >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__CTS_SVAL3, (audio_cfg->cts >> 16), 7, 0);
+
+	/*number of channel*/
+	REG_FLD_MOD(name, HDMI_CORE_AV__HDMI_CTRL, audio_cfg->layout, 2, 1);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_1,
+				audio_cfg->aud_par_busclk, 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_2,
+				(audio_cfg->aud_par_busclk >> 8), 7, 0);
+	REG_FLD_MOD(name, HDMI_CORE_AV__AUD_PAR_BUSCLK_3,
+				(audio_cfg->aud_par_busclk >> 16), 7, 0);
+	/* FS_OVERRIDE = 1 because // input is used*/
+	WR_REG_32(name, HDMI_CORE_AV__SPDIF_CTRL, 0x1);
+	 /* refer to table209 p192 in func core spec*/
+	WR_REG_32(name, HDMI_CORE_AV__I2S_CHST4, audio_cfg->fs);
+
+	/* audio config is mainly due to wrapper hardware connection
+	   and so are fixe (hardware) I2S deserializer is by-pass
+	   so I2S configuration is not needed (I2S don't care).
+	   Wrapper are directly connected at the I2S deserialiser
+	   output level so some register call I2S... need to be
+	   programm to configure this parallel bus, there configuration
+	   is also fixe and due to the hardware connection (I2S hardware)
+	*/
+	WR_REG_32(name, HDMI_CORE_AV__I2S_IN_CTRL,
+		(0 << 7) | /* HBRA_ON */
+		(1 << 6) | /* SCK_EDGE Sample clock is rising */
+		(0 << 5) | /* CBIT_ORDER */
+		(0 << 4) | /* VBit, 0x0=PCM, 0x1=compressed */
+		(0 << 3) | /* I2S_WS, 0xdon't care */
+		(0 << 2) | /* I2S_JUST, 0=left-justified 1=right-justified */
+		(0 << 1) | /* I2S_DIR, 0xdon't care */
+		(0)); /* I2S_SHIFT, 0x0 don't care*/
+
+	WR_REG_32(name, HDMI_CORE_AV__I2S_CHST5, /* mode only */
+		(0 << 4) | /* FS_ORIG */
+		(1 << 1) | /* I2S lenght 16bits (refer doc) */
+		(0));/* Audio sample lenght */
+
+	WR_REG_32(name, HDMI_CORE_AV__I2S_IN_LEN, /* mode only */
+		(0xb)); /* In lenght b=>24bits     i2s hardware */
+
+	/*channel enable depend of the layout*/
+	if (audio_cfg->layout == LAYOUT_2CH) {
+		SD3_EN = 0x0;
+		SD2_EN = 0x0;
+		SD1_EN = 0x0;
+		SD0_EN = 0x1;
+	}
+	if (audio_cfg->layout == LAYOUT_8CH) {
+		SD3_EN = 0x1;
+		SD2_EN = 0x1;
+		SD1_EN = 0x1;
+		SD0_EN = 0x1;
+	}
+
+	WR_REG_32(name, HDMI_CORE_AV__AUD_MODE,
+		(SD3_EN << 7) | /* SD3_EN */
+		(SD2_EN << 6) | /* SD2_EN */
+		(SD1_EN << 5) | /* SD1_EN */
+		(SD0_EN << 4) | /* SD0_EN */
+		(0 << 3) | /* DSD_EN */
+		(1 << 2) | /* AUD_PAR_EN*/
+		(0 << 1) | /* SPDIF_EN*/
+		(0)); /* AUD_EN*/
+
+	/* Audio info frame setting refer to CEA-861-d spec p75 */
+	/*0x10 because only PCM is supported / -1 because 1 is for 2 channel*/
+	DBYTE1 = 0x10 + (audio_cfg->if_channel_number - 1);
+	DBYTE2 = (audio_cfg->if_fs << 2) + audio_cfg->if_sample_size;
+	/*channel location according to CEA spec*/
+	DBYTE4 = audio_cfg->if_audio_channel_location;
+
+	CHSUM = 0x100-0x84-0x01-0x0A-DBYTE1-DBYTE2-DBYTE4;
+
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_TYPE, 0x084);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_VERS, 0x001);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_LEN, 0x00A);
+	WR_REG_32(name, HDMI_CORE_AV__AUDIO_CHSUM, CHSUM); /*don't care on VMP*/
+
+	size0 = HDMI_CORE_AV__AUDIO_DBYTE;
+	size1 = HDMI_CORE_AV__AUDIO_DBYTE__ELSIZE;
+	hdmi_write_reg(name, (size0 + 0 * size1), DBYTE1);
+	hdmi_write_reg(name, (size0 + 1 * size1), DBYTE2);
+	hdmi_write_reg(name, (size0 + 2 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 3 * size1), DBYTE4);
+	hdmi_write_reg(name, (size0 + 4 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 5 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 6 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 7 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 8 * size1), 0x000);
+	hdmi_write_reg(name, (size0 + 9 * size1), 0x000);
+
+	return ret;
+}
+
+static int hdmi_core_audio_infoframe_avi(u32 name,
+	struct hdmi_core_infoframe_avi info_avi)
+{
+	u16 offset;
+	int dbyte, dbyte_size;
+	u32 val;
+
+	dbyte = HDMI_CORE_AV_AVI_DBYTE;
+	dbyte_size = HDMI_CORE_AV_AVI_DBYTE__ELSIZE;
+	/*info frame video*/
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_TYPE, 0x082);
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_VERS, 0x002);
+	hdmi_write_reg(name, HDMI_CORE_AV_AVI_LEN, 0x00D);
+
+	offset = dbyte + (0 * dbyte_size);
+	val = (info_avi.db1y_rgb_yuv422_yuv444 << 5) |
+		(info_avi.db1a_active_format_off_on << 4) |
+		(info_avi.db1b_no_vert_hori_verthori << 2) |
+		(info_avi.db1s_0_1_2);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (1 * dbyte_size);
+	val = (info_avi.db2c_no_itu601_itu709_extented << 6) |
+		(info_avi.db2m_no_43_169 << 4) |
+		(info_avi.db2r_same_43_169_149);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (2 * dbyte_size);
+	val = (info_avi.db3itc_no_yes << 7) |
+		(info_avi.db3ec_xvyuv601_xvyuv709 << 4) |
+		(info_avi.db3q_default_lr_fr << 2) |
+		(info_avi.db3sc_no_hori_vert_horivert);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (3 * dbyte_size);
+	hdmi_write_reg(name, offset, info_avi.db4vic_videocode);
+
+	offset = dbyte + (4 * dbyte_size);
+	val = info_avi.db5pr_no_2_3_4_5_6_7_8_9_10;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (5 * dbyte_size);
+	val = info_avi.db6_7_lineendoftop & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (6 * dbyte_size);
+	val = ((info_avi.db6_7_lineendoftop >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (7 * dbyte_size);
+	val = info_avi.db8_9_linestartofbottom & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (8 * dbyte_size);
+	val = ((info_avi.db8_9_linestartofbottom >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (9 * dbyte_size);
+	val = info_avi.db10_11_pixelendofleft & 0x00FF;
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (10 * dbyte_size);
+	val = ((info_avi.db10_11_pixelendofleft >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	offset = dbyte + (11 * dbyte_size);
+	val = info_avi.db12_13_pixelstartofright & 0x00FF;
+	hdmi_write_reg(name, offset , val);
+
+	offset = dbyte + (12 * dbyte_size);
+	val = ((info_avi.db12_13_pixelstartofright >> 8) & 0x00FF);
+	hdmi_write_reg(name, offset, val);
+
+	return 0;
+}
+
+static int hdmi_core_av_packet_config(u32 name,
+	struct hdmi_core_packet_enable_repeat r_p)
+{
+	/*enable/repeat the infoframe*/
+	hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL1,
+		(r_p.AudioPacketED << 5)|
+		(r_p.AudioPacketRepeat << 4)|
+		(r_p.AVIInfoFrameED << 1)|
+		(r_p.AVIInfoFrameRepeat));
+
+	/*enable/repeat the packet*/
+	hdmi_write_reg(name, HDMI_CORE_AV_PB_CTRL2,
+		(r_p.GeneralcontrolPacketED << 3)|
+		(r_p.GeneralcontrolPacketRepeat << 2)|
+		(r_p.GenericPacketED << 1)|
+		(r_p.GenericPacketRepeat));
+	return 0;
+}
+
+static void hdmi_w1_init(struct hdmi_video_timing *t_p,
+	struct hdmi_video_format *f_p,
+	struct hdmi_video_interface *i_p,
+	struct hdmi_irq_vector *pIrqVectorEnable,
+	struct hdmi_audio_format *audio_fmt,
+	struct hdmi_audio_dma *audio_dma)
+{
+	DBG("Enter HDMI_W1_GlobalInitVars()\n");
+
+	t_p->horizontalBackPorch = 0;
+	t_p->horizontalFrontPorch = 0;
+	t_p->horizontalSyncPulse = 0;
+	t_p->verticalBackPorch = 0;
+	t_p->verticalFrontPorch = 0;
+	t_p->verticalSyncPulse = 0;
+
+	f_p->packingMode = HDMI_PACK_10b_RGB_YUV444;
+	f_p->linePerPanel = 0;
+	f_p->pixelPerLine = 0;
+
+	i_p->vSyncPolarity = 0;
+	i_p->hSyncPolarity = 0;
+
+	i_p->interlacing = 0;
+	i_p->timingMode = 0; /* HDMI_TIMING_SLAVE */
+
+	pIrqVectorEnable->pllRecal = 0;
+	pIrqVectorEnable->pllUnlock = 0;
+	pIrqVectorEnable->pllLock = 0;
+	pIrqVectorEnable->phyDisconnect = 1;
+	pIrqVectorEnable->phyConnect = 1;
+	pIrqVectorEnable->phyShort5v = 0;
+	pIrqVectorEnable->videoEndFrame = 0;
+	pIrqVectorEnable->videoVsync = 0;
+	pIrqVectorEnable->fifoSampleRequest = 0;
+	pIrqVectorEnable->fifoOverflow = 0;
+	pIrqVectorEnable->fifoUnderflow = 0;
+	pIrqVectorEnable->ocpTimeOut = 0;
+	pIrqVectorEnable->core = 1;
+
+	audio_fmt->stereo_channel_enable = HDMI_STEREO_ONECHANNELS;
+	audio_fmt->audio_channel_location = HDMI_CEA_CODE_03;
+	audio_fmt->iec = HDMI_AUDIO_FORMAT_LPCM;
+	audio_fmt->justify = HDMI_AUDIO_JUSTIFY_LEFT;
+	audio_fmt->left_before = HDMI_SAMPLE_LEFT_FIRST;
+	audio_fmt->sample_number = HDMI_ONEWORD_ONE_SAMPLE;
+	audio_fmt->sample_size = HDMI_SAMPLE_24BITS;
+
+	audio_dma->dma_transfer = 0x10;
+	audio_dma->block_size = 0xC0;
+	audio_dma->dma_or_irq = HDMI_THRESHOLD_DMA;
+	audio_dma->threshold_value = 0x10;
+	audio_dma->block_start_end = HDMI_BLOCK_STARTEND_ON;
+
+}
+
+
+static void hdmi_w1_irq_enable(struct hdmi_irq_vector *pIrqVectorEnable)
+{
+	u32 r = 0;
+
+	r = ((pIrqVectorEnable->pllRecal << 31) |
+		(pIrqVectorEnable->pllUnlock << 30) |
+		(pIrqVectorEnable->pllLock << 29) |
+		(pIrqVectorEnable->phyDisconnect << 26) |
+		(pIrqVectorEnable->phyConnect << 25) |
+		(pIrqVectorEnable->phyShort5v << 24) |
+		(pIrqVectorEnable->videoEndFrame << 17) |
+		(pIrqVectorEnable->videoVsync << 16) |
+		(pIrqVectorEnable->fifoSampleRequest << 10) |
+		(pIrqVectorEnable->fifoOverflow << 9) |
+		(pIrqVectorEnable->fifoUnderflow << 8) |
+		(pIrqVectorEnable->ocpTimeOut << 4) |
+		(pIrqVectorEnable->core << 0));
+
+	hdmi_write_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET, r);
+}
+
+static inline int hdmi_w1_wait_for_bit_change(const u32 ins,
+	u32 idx, int b2, int b1, int val)
+{
+	int t = 0;
+	while (val != FLD_GET(hdmi_read_reg(ins, idx), b2, b1)) {
+		udelay(1);
+		if (t++ > 1000)
+			return !val;
+	}
+	return val;
+}
+
+/* todo: add timeout value */
+int hdmi_w1_set_wait_srest(void)
+{
+	/* reset W1 */
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0);
+
+	/* wait till SOFTRESET == 0 */
+	while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0))
+		;
+
+	return 0;
+}
+
+/* PHY_PWR_CMD */
+int hdmi_w1_set_wait_phy_pwr(HDMI_PhyPwr_t val)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 7, 6);
+
+	if (hdmi_w1_wait_for_bit_change(HDMI_WP,
+		HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
+		ERR("Failed to set PHY power mode to %d\n", val);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+/* PLL_PWR_CMD */
+int hdmi_w1_set_wait_pll_pwr(HDMI_PllPwr_t val)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_PWR_CTRL, val, 3, 2);
+
+	/* wait till PHY_PWR_STATUS=ON */
+	if (hdmi_w1_wait_for_bit_change(HDMI_WP,
+		HDMI_WP_PWR_CTRL, 1, 0, val) != val) {
+		ERR("Failed to set PHY_PWR_STATUS to ON\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+void hdmi_w1_video_stop(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, 0, 31, 31);
+}
+
+void hdmi_w1_video_start(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, (u32)0x1, 31, 31);
+}
+
+static void hdmi_w1_video_init_format(struct hdmi_video_format *f_p,
+	struct hdmi_video_timing *t_p, struct hdmi_config *param)
+{
+	DBG("Enter HDMI_W1_ConfigVideoResolutionTiming()\n");
+
+	f_p->linePerPanel = param->lpp;
+	f_p->pixelPerLine = param->ppl;
+
+	t_p->horizontalBackPorch = param->hbp;
+	t_p->horizontalFrontPorch = param->hfp;
+	t_p->horizontalSyncPulse = param->hsw;
+	t_p->verticalBackPorch = param->vbp;
+	t_p->verticalFrontPorch = param->vfp;
+	t_p->verticalSyncPulse = param->vsw;
+}
+
+static void hdmi_w1_video_config_format(
+	struct hdmi_video_format *f_p)
+{
+	u32 l = 0;
+
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_VIDEO_CFG, f_p->packingMode, 10, 8);
+
+	l |= FLD_VAL(f_p->linePerPanel, 31, 16);
+	l |= FLD_VAL(f_p->pixelPerLine, 15, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, l);
+}
+
+static void hdmi_w1_video_config_interface(
+	struct hdmi_video_interface *i_p)
+{
+	u32 r;
+	DBG("Enter HDMI_W1_ConfigVideoInterface()\n");
+
+	r = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_CFG);
+	r = FLD_MOD(r, i_p->vSyncPolarity, 7, 7);
+	r = FLD_MOD(r, i_p->hSyncPolarity, 6, 6);
+	r = FLD_MOD(r, i_p->interlacing, 3, 3);
+	r = FLD_MOD(r, i_p->timingMode, 1, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_CFG, r);
+}
+
+static void hdmi_w1_video_config_timing(
+	struct hdmi_video_timing *t_p)
+{
+	u32 timing_h = 0;
+	u32 timing_v = 0;
+
+	DBG("Enter HDMI_W1_ConfigVideoTiming ()\n");
+
+	timing_h |= FLD_VAL(t_p->horizontalBackPorch, 31, 20);
+	timing_h |= FLD_VAL(t_p->horizontalFrontPorch, 19, 8);
+	timing_h |= FLD_VAL(t_p->horizontalSyncPulse, 7, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_H, timing_h);
+
+	timing_v |= FLD_VAL(t_p->verticalBackPorch, 31, 20);
+	timing_v |= FLD_VAL(t_p->verticalFrontPorch, 19, 8);
+	timing_v |= FLD_VAL(t_p->verticalSyncPulse, 7, 0);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_TIMING_V, timing_v);
+}
+
+static int hdmi_w1_audio_config_format(u32 name,
+			struct hdmi_audio_format *audio_fmt)
+{
+	int ret = 0;
+	u32 value = 0;
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG);
+	value &= 0xfffffff7;
+	value |= ((audio_fmt->justify) << 3);;
+	value &= 0xfffffffb;
+	value |= ((audio_fmt->left_before) << 2);
+	value &= 0xfffffffd;
+	value |= ((audio_fmt->sample_number) << 1);
+	value &= 0xfffffffe;
+	value |= ((audio_fmt->sample_size));
+	value &= 0xf8ffffff;
+	value |= ((audio_fmt->stereo_channel_enable) << 24);
+	value &= 0xff00ffff;
+	value |= ((audio_fmt->audio_channel_location) << 16);
+	value &= 0xffffffef;
+	value |= ((audio_fmt->iec) << 4);
+	/* Wakeup */
+	value = 0x1030022;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CFG, value);
+	DBG("HDMI_WP_AUDIO_CFG = 0x%x \n", value);
+
+	return ret;
+}
+
+static int hdmi_w1_audio_config_dma(u32 name, struct hdmi_audio_dma *audio_dma)
+
+{
+	int ret = 0;
+	u32 value = 0;
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CFG2);
+	value &= 0xffffff00;
+	value |= (audio_dma->block_size);
+	value &= 0xffff00ff;
+	value |= ((audio_dma->dma_transfer) << 8);
+	/*  Wakeup */
+	value = 0x20C0;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CFG2, value);
+	DBG("HDMI_WP_AUDIO_CFG2 = 0x%x \n", value);
+
+	value = hdmi_read_reg(name, HDMI_WP_AUDIO_CTRL);
+	value &= 0xfffffdff;
+	value |= ((audio_dma->dma_or_irq)<<9);
+	value &= 0xfffffe00;
+	value |= (audio_dma->threshold_value);
+	/*  Wakeup */
+	value = 0x020;
+	hdmi_write_reg(name, HDMI_WP_AUDIO_CTRL, value);
+	DBG("HDMI_WP_AUDIO_CTRL = 0x%x \n", value);
+
+	return ret;
+}
+
+static void hdmi_w1_audio_enable(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 31, 31);
+}
+
+static __attribute__ ((unused))__attribute__ ((unused)) void hdmi_w1_audio_disable(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 31, 31);
+}
+
+static void hdmi_w1_audio_start(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 1, 30, 30);
+}
+
+static void hdmi_w1_audio_stop(void)
+{
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_AUDIO_CTRL, 0, 30, 30);
+}
+
+static int hdmi_w1_audio_config(void)
+{
+	int ret;
+
+	struct hdmi_audio_format audio_fmt;
+	struct hdmi_audio_dma audio_dma;
+
+	audio_fmt.justify = HDMI_AUDIO_JUSTIFY_LEFT;
+	audio_fmt.sample_number = HDMI_ONEWORD_ONE_SAMPLE;
+	audio_fmt.sample_size = HDMI_SAMPLE_24BITS;
+	audio_fmt.stereo_channel_enable = HDMI_STEREO_ONECHANNELS;
+	audio_fmt.audio_channel_location = 0x03;
+
+	ret = hdmi_w1_audio_config_format(HDMI_WP, &audio_fmt);
+
+	audio_dma.dma_transfer = 0x20;
+	audio_dma.threshold_value = 0x60;
+	audio_dma.dma_or_irq = HDMI_THRESHOLD_DMA;
+
+	ret = hdmi_w1_audio_config_dma(HDMI_WP, &audio_dma);
+
+	return ret;
+}
+
+int hdmi_lib_enable(struct hdmi_config *cfg)
+{
+	u32 r, val;
+
+	u32 av_name = HDMI_CORE_AV;
+
+	/*HDMI*/
+	struct hdmi_video_timing VideoTimingParam;
+	struct hdmi_video_format VideoFormatParam;
+	struct hdmi_video_interface VideoInterfaceParam;
+	struct hdmi_irq_vector IrqHdmiVectorEnable;
+	struct hdmi_audio_format audio_fmt;
+	struct hdmi_audio_dma audio_dma;
+
+	/*HDMI core*/
+	struct hdmi_core_infoframe_avi avi_param;
+	struct hdmi_core_video_config_t v_core_cfg;
+	struct hdmi_core_audio_config audio_cfg;
+	struct hdmi_core_packet_enable_repeat repeat_param;
+
+	hdmi_w1_init(&VideoTimingParam, &VideoFormatParam,
+		&VideoInterfaceParam, &IrqHdmiVectorEnable,
+		&audio_fmt, &audio_dma);
+
+	hdmi_core_init(&v_core_cfg,
+		&audio_cfg,
+		&avi_param,
+		&repeat_param);
+
+	/* Enable PLL Lock and UnLock intrerrupts */
+	IrqHdmiVectorEnable.pllUnlock = 1;
+	IrqHdmiVectorEnable.pllLock = 1;
+
+	/***************** init DSS register **********************/
+	hdmi_w1_irq_enable(&IrqHdmiVectorEnable);
+
+	hdmi_w1_video_init_format(&VideoFormatParam,
+			&VideoTimingParam, cfg);
+
+	hdmi_w1_video_config_timing(&VideoTimingParam);
+
+	/*video config*/
+	VideoFormatParam.packingMode = HDMI_PACK_24b_RGB_YUV444_YUV422;
+
+	hdmi_w1_video_config_format(&VideoFormatParam);
+
+	/* FIXME */
+	VideoInterfaceParam.vSyncPolarity = cfg->v_pol;
+	VideoInterfaceParam.hSyncPolarity = cfg->h_pol;
+	VideoInterfaceParam.interlacing = cfg->interlace;
+	VideoInterfaceParam.timingMode = 1 ; /* HDMI_TIMING_MASTER_24BIT */
+
+	hdmi_w1_video_config_interface(&VideoInterfaceParam);
+
+#if 0
+	/* hnagalla */
+	val = hdmi_read_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE);
+
+	val &= 0x0FFFFFFF;
+	val |= ((0x1f) << 27); /* wakeup */
+	hdmi_write_reg(HDMI_WP, HDMI_WP_VIDEO_SIZE, val);
+
+	hdmi_w1_audio_config();
+#endif
+
+	/****************************** CORE *******************************/
+	/************* configure core video part ********************************/
+	/*set software reset in the core*/
+	hdmi_core_swreset_assert();
+
+	/*power down off*/
+	hdmi_core_powerdown_disable();
+
+	v_core_cfg.CorePacketMode = HDMI_PACKETMODE24BITPERPIXEL;
+	v_core_cfg.CoreHdmiDvi = HDMI_HDMI;
+
+	/* hnagalla */
+	audio_cfg.fs = 0x02;
+	audio_cfg.if_fs = 0x00;
+	audio_cfg.n = 6144;
+	audio_cfg.cts = 74250;
+
+	/* audio channel */
+	audio_cfg.if_sample_size = 0x0;
+	audio_cfg.layout = 0;
+	audio_cfg.if_channel_number = 2;
+	audio_cfg.if_audio_channel_location = 0x00;
+
+	/* TODO: Is this configuration correct? */
+	audio_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
+	audio_cfg.cts_mode = 0;
+
+	r = hdmi_core_video_config(&v_core_cfg);
+
+	/* hnagalla */
+	hdmi_core_audio_config(av_name, &audio_cfg);
+	hdmi_core_audio_mode_enable(av_name);
+
+	/*release software reset in the core*/
+	hdmi_core_swreset_release();
+
+	/*configure packet*/
+	/*info frame video see doc CEA861-D page 65*/
+	avi_param.db1y_rgb_yuv422_yuv444 = INFOFRAME_AVI_DB1Y_RGB;
+	avi_param.db1a_active_format_off_on =
+		INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
+	avi_param.db1b_no_vert_hori_verthori = INFOFRAME_AVI_DB1B_NO;
+	avi_param.db1s_0_1_2 = INFOFRAME_AVI_DB1S_0;
+	avi_param.db2c_no_itu601_itu709_extented = INFOFRAME_AVI_DB2C_NO;
+	avi_param.db2m_no_43_169 = INFOFRAME_AVI_DB2M_NO;
+	avi_param.db2r_same_43_169_149 = INFOFRAME_AVI_DB2R_SAME;
+	avi_param.db3itc_no_yes = INFOFRAME_AVI_DB3ITC_NO;
+	avi_param.db3ec_xvyuv601_xvyuv709 = INFOFRAME_AVI_DB3EC_XVYUV601;
+	avi_param.db3q_default_lr_fr = INFOFRAME_AVI_DB3Q_DEFAULT;
+	avi_param.db3sc_no_hori_vert_horivert = INFOFRAME_AVI_DB3SC_NO;
+	avi_param.db4vic_videocode = cfg->video_format;
+	avi_param.db5pr_no_2_3_4_5_6_7_8_9_10 = INFOFRAME_AVI_DB5PR_NO;
+	avi_param.db6_7_lineendoftop = 0;
+	avi_param.db8_9_linestartofbottom = 0;
+	avi_param.db10_11_pixelendofleft = 0;
+	avi_param.db12_13_pixelstartofright = 0;
+
+	r = hdmi_core_audio_infoframe_avi(av_name, avi_param);
+
+	/*enable/repeat the infoframe*/
+	repeat_param.AVIInfoFrameED = PACKETENABLE;
+	repeat_param.AVIInfoFrameRepeat = PACKETREPEATON;
+	/* wakeup */
+	repeat_param.AudioPacketED = PACKETENABLE;
+	repeat_param.AudioPacketRepeat = PACKETREPEATON;
+	r = hdmi_core_av_packet_config(av_name, repeat_param);
+
+	REG_FLD_MOD(av_name, HDMI_CORE_AV__HDMI_CTRL, cfg->hdmi_dvi, 0, 0);
+	return r;
+}
+
+int hdmi_lib_init(void){
+	u32 rev;
+
+	hdmi.base_wp = ioremap(HDMI_WP, (HDMI_HDCP - HDMI_WP));
+
+	if (!hdmi.base_wp) {
+		ERR("can't ioremap WP\n");
+		return -ENOMEM;
+	}
+
+	hdmi.base_core = hdmi.base_wp + 0x400;
+	hdmi.base_core_av = hdmi.base_wp + 0x900;
+
+	rev = hdmi_read_reg(HDMI_WP, HDMI_WP_REVISION);
+
+	printk(KERN_INFO "OMAP HDMI W1 rev %d.%d\n",
+		FLD_GET(rev, 10, 8), FLD_GET(rev, 5, 0));
+
+	return 0;
+}
+
+void hdmi_lib_exit(void){
+	iounmap(hdmi.base_wp);
+}
+
+void dump_regs(void){
+	DBG("W1 VIDEO_CFG = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x50ul));
+	DBG("Core CTRL1 = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x420ul));
+	DBG("Core VID_MODE = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x528ul));
+	DBG("Core AV_CTRL = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9bcul));
+	DBG("Core VID_ACEN = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x524ul));
+	DBG("Core PB_CTR2 packet buf = 0x%x\r\n", hdmi_read_reg(HDMI_WP, 0x9fcul));
+}
+
+int hdmi_set_irqs(void)
+{
+	u32 r = 0 , hpd = 0;
+	struct hdmi_irq_vector pIrqVectorEnable;
+
+	pIrqVectorEnable.pllRecal = 0;
+	pIrqVectorEnable.phyShort5v = 0;
+	pIrqVectorEnable.videoEndFrame = 0;
+	pIrqVectorEnable.videoVsync = 0;
+	pIrqVectorEnable.fifoSampleRequest = 0;
+	pIrqVectorEnable.fifoOverflow = 0;
+	pIrqVectorEnable.fifoUnderflow = 0;
+	pIrqVectorEnable.ocpTimeOut = 0;
+	pIrqVectorEnable.pllUnlock = 1;
+	pIrqVectorEnable.pllLock = 1;
+	pIrqVectorEnable.phyDisconnect = 1;
+	pIrqVectorEnable.phyConnect = 1;
+	pIrqVectorEnable.core = 1;
+
+	hdmi_w1_irq_enable(&pIrqVectorEnable);
+
+	r = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQENABLE_SET);
+	DBG("Irqenable %x \n", r);
+	hpd = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__UMASK1);
+	DBG("%x hpd\n", hpd);
+	return 0;
+}
+
+/* Interrupt handler*/
+void HDMI_W1_HPD_handler(int *r)
+{
+	u32 val, intr, set;
+	mdelay(30);
+	val = hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS);
+	DBG("%x hdmi_wp_irqstatus\n", val);
+	mdelay(30);
+	set = 0;
+	set = hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__SYS_STAT);
+	DBG("%x hdmi_core_sys_sys_stat\n", set);
+	mdelay(30);
+	hdmi_write_reg(HDMI_WP, HDMI_WP_IRQSTATUS, val);
+	/* flush posted write */
+	hdmi_read_reg(HDMI_WP, HDMI_WP_IRQSTATUS);
+	mdelay(30);
+	*r = 0;
+	if ((count == 0) && ((val & 0x02000000) == 0x02000000) &&
+		((set & 0x00000002) != 0x00000002)) {
+		*r = 2;
+		DBG("First interrupt physical attach but not HPD");
+		count_hpd = 0;
+	}
+	count++;
+	hdmi_set_irqs();
+	DBG("%d count and count_hpd %d", count, count_hpd);
+	if ((set & 0x00000002) == 0x00000002) {
+		if (count_hpd == 0) {
+			*r = 4;
+			count_hpd++;
+			goto end;
+		} else
+			*r = 1;
+		DBG("HPD is set you can read edid");
+	}
+	if (((val & 0x04000000) == 0x04000000) && ((set & 0x00000002) != 0x00000002)) {
+		*r = 3;
+		count = 0;
+		count_hpd = 0;
+	}
+	intr =  hdmi_read_reg(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR1);
+	DBG("%x hdmi_core_sys_sys_intr\n", intr);
+	end: /*Do nothing*/;
+}
+
+
+/* wrapper functions to be used until L24.5 release*/
+int HDMI_CORE_DDC_READEDID(u32 name, u8 *p)
+{
+	int r = hdmi_core_ddc_edid(p);
+	return r;
+}
+
+int HDMI_W1_StopVideoFrame(u32 name)
+{
+	DBG("Enter HDMI_W1_StopVideoFrame()\n");
+	hdmi_w1_video_stop();
+	return 0;
+}
+
+int HDMI_W1_StartVideoFrame(u32 name)
+{
+	DBG("Enter HDMI_W1_StartVideoFrame  ()\n");
+	hdmi_w1_video_start();
+	return 0;
+}
+
+/* PHY_PWR_CMD */
+int HDMI_W1_SetWaitPhyPwrState(u32 name,
+	HDMI_PhyPwr_t param)
+{
+	int r = hdmi_w1_set_wait_phy_pwr(param);
+	return r;
+}
+
+/* PLL_PWR_CMD */
+int HDMI_W1_SetWaitPllPwrState(u32 name,
+		HDMI_PllPwr_t param)
+{
+	int r = hdmi_w1_set_wait_pll_pwr(param);
+	return r;
+}
+
+int HDMI_W1_SetWaitSoftReset(void)
+{
+	/* reset W1 */
+	REG_FLD_MOD(HDMI_WP, HDMI_WP_SYSCONFIG, 0x1, 0, 0);
+
+	/* wait till SOFTRESET == 0 */
+	while (FLD_GET(hdmi_read_reg(HDMI_WP, HDMI_WP_SYSCONFIG), 0, 0))
+		;
+
+	return 0;
+}
+
+int hdmi_w1_wrapper_enable(u32 instanceName)
+{
+	printk(KERN_INFO "Wrapper Enabled...\n");
+	hdmi_w1_audio_enable();
+	return 0;
+}
+
+int hdmi_w1_wrapper_disable(u32 instanceName)
+{
+	hdmi_w1_audio_enable();
+	printk(KERN_INFO "Wrapper disabled...\n");
+	return 0;
+}
+
+int hdmi_w1_stop_audio_transfer(u32 instanceName)
+{
+	hdmi_w1_audio_stop();
+	return 0;
+}
+
+int hdmi_w1_start_audio_transfer(u32 instanceName)
+{
+	hdmi_w1_audio_start();
+	printk(KERN_INFO "Start audio transfer...\n");
+	return 0;
+}
+
+int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format,
+	u32 mode)
+{
+	int err;
+	struct hdmi_config data;
+
+	data.ppl = timings.pixelPerLine;
+	data.lpp = timings.linePerPanel;
+	data.pixel_clock = timings.pplclk;
+
+	data.hsw = timings.horizontalSyncPulse;
+	data.hfp = timings.horizontalFrontPorch;
+	data.hbp = timings.horizontalBackPorch;
+	data.vsw = timings.verticalSyncPulse;
+	data.vfp = timings.verticalFrontPorch;
+	data.vbp = timings.verticalBackPorch;
+
+	data.h_pol = 1;
+	data.v_pol = 1;
+	data.hdmi_dvi = mode;
+	data.video_format = video_format;
+
+	err = hdmi_lib_enable(&data);
+	return err;
+}
+
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 1c529ce9dc11..c5a54458d72a 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -42,6 +42,17 @@
 #define DISPC_IRQ_SYNC_LOST		(1 << 14)
 #define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
 #define DISPC_IRQ_WAKEUP		(1 << 16)
+#define DISPC_IRQ_SYNC_LOST_2  (1 << 17)
+#define DISPC_IRQ_VSYNC2               (1 << 18)
+#define DISPC_IRQ_VID3_END_WIN         (1 << 19)
+#define DISPC_IRQ_VID3_FIFO_UNDERFLOW  (1 << 20)
+					/* VID3_BUF_UNDERFLOW*/
+#define DISPC_IRQ_ACBIAS_COUNT_STAT2   (1 << 21)
+#define DISPC_IRQ_FRAMEDONE2           (1 << 22)
+#define DISPC_IRQ_FRAMEDONE_WB         (1 << 23)
+#define DISPC_IRQ_FRAMEDONE_DIG                (1 << 24) /* FRAMEDONE_TV*/
+#define DISPC_IRQ_WB_BUF_OVERFLOW      (1 << 25)
+
 
 struct omap_dss_device;
 struct omap_overlay_manager;
@@ -53,17 +64,21 @@ enum omap_display_type {
 	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
 	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
 	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
+	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
 };
 
 enum omap_plane {
 	OMAP_DSS_GFX	= 0,
 	OMAP_DSS_VIDEO1	= 1,
-	OMAP_DSS_VIDEO2	= 2
+	OMAP_DSS_VIDEO2	= 2,
+	OMAP_DSS_VIDEO3 = 3,
+	OMAP_DSS_WB = 4
 };
 
 enum omap_channel {
 	OMAP_DSS_CHANNEL_LCD	= 0,
 	OMAP_DSS_CHANNEL_DIGIT	= 1,
+	OMAP_DSS_CHANNEL_LCD2   = 2,
 };
 
 enum omap_color_mode {
@@ -81,6 +96,13 @@ enum omap_color_mode {
 	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
 	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
 	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
+	OMAP_DSS_COLOR_NV12     = 1 << 14, /* NV12 format: YUV 4:2:0 */
+	OMAP_DSS_COLOR_RGBA12   = 1 << 15, /* RGBA12 - 4444 */
+	OMAP_DSS_COLOR_XRGB12   = 1 << 16, /* xRGB12, 16-bit container */
+	OMAP_DSS_COLOR_ARGB16_1555      = 1 << 17, /* ARGB16-1555 */
+	OMAP_DSS_COLOR_RGBX24_32_ALGN   = 1 << 18, /* 32-msb aligned 24bit */
+	OMAP_DSS_COLOR_XRGB15   = 1 << 19, /* xRGB15: 1555*/
+
 
 	OMAP_DSS_COLOR_GFX_OMAP2 =
 		OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
@@ -102,16 +124,26 @@ enum omap_color_mode {
 		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 
 	OMAP_DSS_COLOR_VID1_OMAP3 =
+		OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 |
+		OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 |
+		OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 |
 		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
 		OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
-		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
+		OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY |
+		OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBA32 |
+		OMAP_DSS_COLOR_RGBX32,
 
 	OMAP_DSS_COLOR_VID2_OMAP3 =
+		OMAP_DSS_COLOR_NV12 | OMAP_DSS_COLOR_RGBA12 |
+		OMAP_DSS_COLOR_XRGB12 | OMAP_DSS_COLOR_ARGB16_1555 |
+		OMAP_DSS_COLOR_RGBX24_32_ALGN | OMAP_DSS_COLOR_XRGB15 |
 		OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
 		OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
 		OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
 		OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
 		OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
+
+	OMAP_DSS_COLOR_VID3_OMAP3 = OMAP_DSS_COLOR_VID2_OMAP3,
 };
 
 enum omap_lcd_display_type {
@@ -173,11 +205,13 @@ enum omap_dss_display_state {
 enum omap_dss_overlay_managers {
 	OMAP_DSS_OVL_MGR_LCD,
 	OMAP_DSS_OVL_MGR_TV,
+	OMAP_DSS_OVL_MGR_LCD2,
 };
 
 enum omap_dss_rotation_type {
 	OMAP_DSS_ROT_DMA = 0,
 	OMAP_DSS_ROT_VRFB = 1,
+	OMAP_DSS_ROT_TILER = 2,
 };
 
 /* clockwise rotation angle */
@@ -197,6 +231,34 @@ enum omap_overlay_manager_caps {
 	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
 };
 
+enum omap_overlay_zorder {
+	OMAP_DSS_OVL_ZORDER_0	= 0x0,
+	OMAP_DSS_OVL_ZORDER_1	= 0x1,
+	OMAP_DSS_OVL_ZORDER_2	= 0x2,
+	OMAP_DSS_OVL_ZORDER_3	= 0x3,
+};
+
+/* write back*/
+enum omap_writeback_source {
+	OMAP_WB_LCD_1_MANAGER		= 0,
+	OMAP_WB_LCD_2_MANAGER		= 1,
+	OMAP_WB_TV_MANAGER		= 2,
+	OMAP_WB_OVERLAY0			= 3,
+	OMAP_WB_OVERLAY1			= 4,
+	OMAP_WB_OVERLAY2			= 5,
+	OMAP_WB_OVERLAY3 			= 6
+};
+
+enum omap_writeback_capturemode {
+	OMAP_WB_CAPTURE_ALL = 0x0,
+	OMAP_WB_CAPTURE_1 = 0x1,
+	OMAP_WB_CAPTURE_1_OF_2 = 0x2,
+	OMAP_WB_CAPTURE_1_OF_3 = 0x3,
+	OMAP_WB_CAPTURE_1_OF_4 = 0x4,
+	OMAP_WB_CAPTURE_1_OF_5 = 0x5,
+	OMAP_WB_CAPTURE_1_OF_6 = 0x6,
+	OMAP_WB_CAPTURE_1_OF_7 = 0x7
+};
 /* RFBI */
 
 struct rfbi_timings {
@@ -230,20 +292,42 @@ int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
 			     int hs_pol_inv, int vs_pol_inv, int extif_div);
 
 /* DSI */
-void dsi_bus_lock(void);
-void dsi_bus_unlock(void);
-int dsi_vc_dcs_write(int channel, u8 *data, int len);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u16 *data);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-int dsi_vc_send_null(int channel);
-int dsi_vc_send_bta_sync(int channel);
+enum omap_dsi_index {
+	DSI1 = 0,
+	DSI2 = 1,
+};
+void dsi_bus_lock(enum omap_dsi_index ix);
+void dsi_bus_unlock(enum omap_dsi_index ix);
+int dsi_vc_dcs_write(enum omap_dsi_index ix, int channel,
+		u8 *data, int len);
+int dsi_vc_dcs_write_0(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd);
+int dsi_vc_dcs_write_1(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 param);
+int dsi_vc_dcs_write_nosync(enum omap_dsi_index ix, int channel,
+		u8 *data, int len);
+int dsi_vc_dcs_read(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 *buf, int buflen);
+int dsi_vc_dcs_read_1(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u8 *data);
+int dsi_vc_dcs_read_2(enum omap_dsi_index ix, int channel,
+		u8 dcs_cmd, u16 *data);
+int dsi_vc_set_max_rx_packet_size(enum omap_dsi_index ix,
+		int channel, u16 len);
+int dsi_vc_send_null(enum omap_dsi_index ix, int channel);
+int dsi_vc_send_bta_sync(enum omap_dsi_index ix, int channel);
 
 /* Board specific data */
+#define PWM2ON		0x03
+#define PWM2OFF		0x04
+#define TOGGLE3		0x92
+#define HDMI_GPIO_60 60
+#define HDMI_GPIO_41 41
+#define DLP_4430_GPIO_40	40
+#define DLP_4430_GPIO_44	44
+#define DLP_4430_GPIO_45	45
+#define DLP_4430_GPIO_59	59
+
 struct omap_dss_board_info {
 	int (*get_last_off_on_transaction_id)(struct device *dev);
 	int num_devices;
@@ -299,6 +383,8 @@ struct omap_overlay_info {
 	u16 out_width;	/* if 0, out_width == width */
 	u16 out_height;	/* if 0, out_height == height */
 	u8 global_alpha;
+	enum omap_overlay_zorder zorder;
+	u32 p_uv_addr; /* relevant for NV12 format only */
 };
 
 struct omap_overlay {
@@ -377,6 +463,43 @@ struct omap_overlay_manager {
 	int (*disable)(struct omap_overlay_manager *mgr);
 };
 
+enum omap_writeback_source_type {
+	OMAP_WB_SOURCE_OVERLAY	= 0,
+	OMAP_WB_SOURCE_MANAGER	= 1
+};
+
+
+struct omap_writeback_info {
+		bool					enabled;
+		bool					info_dirty;
+		enum omap_writeback_source		source;
+		enum omap_writeback_source_type 	source_type;
+		unsigned long				width;
+		unsigned long				height;
+		enum omap_color_mode			dss_mode;
+		enum omap_writeback_capturemode 	capturemode;
+		unsigned long				paddr;
+		/* NV12 support*/
+		unsigned long				puv_addr;
+
+};
+
+struct omap_writeback {
+	struct kobject kobj;
+	struct list_head list;
+	bool								enabled;
+	bool								info_dirty;
+	bool								first_time;
+	/* mutex to control access to wb data */
+	struct mutex lock;
+	struct omap_writeback_info info;
+	bool (*check_wb)(struct omap_writeback *wb);
+
+	int (*set_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info);
+	void (*get_wb_info)(struct omap_writeback *wb, struct omap_writeback_info *info);
+
+};
+
 struct omap_dss_device {
 	struct device dev;
 
@@ -460,8 +583,10 @@ struct omap_dss_device {
 	enum omap_display_caps caps;
 
 	struct omap_overlay_manager *manager;
+	struct omap_writeback *wb_manager;
 
 	enum omap_dss_display_state state;
+	enum omap_channel channel;
 
 	/* platform specific  */
 	int (*platform_enable)(struct omap_dss_device *dssdev);
@@ -494,6 +619,7 @@ struct omap_dss_driver {
 	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
 	int (*get_te)(struct omap_dss_device *dssdev);
 
+	int (*wait_for_te)(struct omap_dss_device *dssdev);
 	u8 (*get_rotate)(struct omap_dss_device *dssdev);
 	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
 
@@ -517,6 +643,15 @@ struct omap_dss_driver {
 
 	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
 	u32 (*get_wss)(struct omap_dss_device *dssdev);
+
+/*HDMI specific */
+	void (*get_edid)(struct omap_dss_device *dssdev);
+	void (*set_custom_edid_timing_code)(struct omap_dss_device *dssdev, int mode, int code);
+	int (*hpd_enable)(struct omap_dss_device *dssdev);
+};
+
+struct pico_platform_data {
+	u8 gpio_intr;
 };
 
 int omap_dss_register_driver(struct omap_dss_driver *);
@@ -540,11 +675,13 @@ struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
 
 int omap_dss_get_num_overlays(void);
 struct omap_overlay *omap_dss_get_overlay(int num);
+struct omap_writeback *omap_dss_get_wb(int num);
 
 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
 		u16 *xres, u16 *yres);
 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
-
+bool dispc_go_busy(enum omap_channel channel);
+void dispc_go(enum omap_channel channel);
 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
@@ -556,7 +693,8 @@ int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
 
-void omapdss_dsi_vc_enable_hs(int channel, bool enable);
+void omapdss_dsi_vc_enable_hs(enum omap_dsi_index ix, int channel,
+	bool enable);
 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
 
 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
diff --git a/arch/arm/plat-omap/include/plat/hdmi_lib.h b/arch/arm/plat-omap/include/plat/hdmi_lib.h
new file mode 100644
index 000000000000..bf45e025dc98
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hdmi_lib.h
@@ -0,0 +1,428 @@
+ /*
+ * hdmi_lib.h
+ *
+ * HDMI driver definition for TI OMAP processors.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef _HDMI_H_
+#define _HDMI_H_
+
+#include <linux/string.h>
+
+#define HDMI_WP				0x58006000
+#define HDMI_CORE_SYS		0x58006400
+#define HDMI_CORE_AV		0x58006900
+#define HDMI_HDCP			0x58007000
+
+#define HDMI_WP_AUDIO_DATA		0x8Cul
+
+#define DBG(format, ...) \
+		printk(KERN_DEBUG "hdmi: " format, ## __VA_ARGS__)
+#define ERR(format, ...) \
+	printk(KERN_ERR "hdmi error: " format, ## __VA_ARGS__)
+
+#define BITS_32(in_NbBits) \
+		((((u32)1 << in_NbBits) - 1) | ((u32)1 << in_NbBits))
+
+#define BITFIELD(in_UpBit, in_LowBit) \
+		(BITS_32(in_UpBit) & ~((BITS_32(in_LowBit)) >> 1))
+
+struct hdmi_irq_vector {
+	u8	pllRecal;
+	u8	pllUnlock;
+	u8	pllLock;
+	u8	phyDisconnect;
+	u8	phyConnect;
+	u8	phyShort5v;
+	u8	videoEndFrame;
+	u8	videoVsync;
+	u8	fifoSampleRequest;
+	u8	fifoOverflow;
+	u8	fifoUnderflow;
+	u8	ocpTimeOut;
+	u8	core;
+};
+
+typedef enum HDMI_PhyPwr_label {
+	HDMI_PHYPWRCMD_OFF = 0,
+	HDMI_PHYPWRCMD_LDOON = 1,
+	HDMI_PHYPWRCMD_TXON = 2
+} HDMI_PhyPwr_t, *pHDMI_PhyPwr_t;
+
+typedef enum HDMI_PllPwr_label {
+	HDMI_PLLPWRCMD_ALLOFF = 0,
+	HDMI_PLLPWRCMD_PLLONLY = 1,
+	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
+	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
+} HDMI_PllPwr_t, *pHDMI_PllPwr_t;
+
+enum hdmi_core_inputbus_width {
+	HDMI_INPUT_8BIT = 0,
+	HDMI_INPUT_10BIT = 1,
+	HDMI_INPUT_12BIT = 2
+};
+
+enum hdmi_core_dither_trunc {
+	HDMI_OUTPUTTRUNCATION_8BIT = 0,
+	HDMI_OUTPUTTRUNCATION_10BIT = 1,
+	HDMI_OUTPUTTRUNCATION_12BIT = 2,
+	HDMI_OUTPUTDITHER_8BIT = 3,
+	HDMI_OUTPUTDITHER_10BIT = 4,
+	HDMI_OUTPUTDITHER_12BIT = 5
+};
+
+enum hdmi_core_deepcolor_ed {
+	HDMI_DEEPCOLORPACKECTDISABLE = 0,
+	HDMI_DEEPCOLORPACKECTENABLE = 1
+};
+
+enum hdmi_core_packet_mode {
+	HDMI_PACKETMODERESERVEDVALUE = 0,
+	HDMI_PACKETMODE24BITPERPIXEL = 4,
+	HDMI_PACKETMODE30BITPERPIXEL = 5,
+	HDMI_PACKETMODE36BITPERPIXEL = 6,
+	HDMI_PACKETMODE48BITPERPIXEL = 7
+};
+
+enum hdmi_core_hdmi_dvi {
+	HDMI_DVI	= 0,
+	HDMI_HDMI	= 1
+};
+
+enum hdmi_core_tclkselclkmult {
+	FPLL05IDCK  = 0,
+	FPLL10IDCK  = 1,
+	FPLL20IDCK  = 2,
+	FPLL40IDCK  = 3
+};
+
+struct hdmi_core_video_config_t {
+	enum hdmi_core_inputbus_width	CoreInputBusWide;
+	enum hdmi_core_dither_trunc 	CoreOutputDitherTruncation;
+	enum hdmi_core_deepcolor_ed		CoreDeepColorPacketED;
+	enum hdmi_core_packet_mode		CorePacketMode;
+	enum hdmi_core_hdmi_dvi			CoreHdmiDvi;
+	enum hdmi_core_tclkselclkmult	CoreTclkSelClkMult;
+};
+
+enum hdmi_core_fs {
+	FS_32000 = 0,
+	FS_44100 = 1
+};
+
+enum hdmi_core_layout {
+	LAYOUT_2CH = 0,
+	LAYOUT_8CH = 1
+};
+
+enum hdmi_core_cts_mode {
+	CTS_MODE_HW = 0,
+	CTS_MODE_SW = 1
+};
+
+enum hdmi_core_packet_ctrl {
+	PACKETENABLE = 1,
+	PACKETDISABLE = 0,
+	PACKETREPEATON = 1,
+	PACKETREPEATOFF = 0
+};
+
+/* INFOFRAME_AVI_ definations */
+enum hdmi_core_infoframe {
+	INFOFRAME_AVI_DB1Y_RGB = 0,
+	INFOFRAME_AVI_DB1Y_YUV422 = 1,
+	INFOFRAME_AVI_DB1Y_YUV444 = 2,
+	INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
+	INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON =  1,
+	INFOFRAME_AVI_DB1B_NO = 0,
+	INFOFRAME_AVI_DB1B_VERT = 1,
+	INFOFRAME_AVI_DB1B_HORI = 2,
+	INFOFRAME_AVI_DB1B_VERTHORI = 3,
+	INFOFRAME_AVI_DB1S_0 = 0,
+	INFOFRAME_AVI_DB1S_1 = 1,
+	INFOFRAME_AVI_DB1S_2 = 2,
+	INFOFRAME_AVI_DB2C_NO = 0,
+	INFOFRAME_AVI_DB2C_ITU601 = 1,
+	INFOFRAME_AVI_DB2C_ITU709 = 2,
+	INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
+	INFOFRAME_AVI_DB2M_NO = 0,
+	INFOFRAME_AVI_DB2M_43 = 1,
+	INFOFRAME_AVI_DB2M_169 = 2,
+	INFOFRAME_AVI_DB2R_SAME = 8,
+	INFOFRAME_AVI_DB2R_43 = 9,
+	INFOFRAME_AVI_DB2R_169 = 10,
+	INFOFRAME_AVI_DB2R_149 = 11,
+	INFOFRAME_AVI_DB3ITC_NO = 0,
+	INFOFRAME_AVI_DB3ITC_YES = 1,
+	INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
+	INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
+	INFOFRAME_AVI_DB3Q_DEFAULT = 0,
+	INFOFRAME_AVI_DB3Q_LR = 1,
+	INFOFRAME_AVI_DB3Q_FR = 2,
+	INFOFRAME_AVI_DB3SC_NO = 0,
+	INFOFRAME_AVI_DB3SC_HORI = 1,
+	INFOFRAME_AVI_DB3SC_VERT = 2,
+	INFOFRAME_AVI_DB3SC_HORIVERT = 3,
+	INFOFRAME_AVI_DB5PR_NO = 0,
+	INFOFRAME_AVI_DB5PR_2 = 1,
+	INFOFRAME_AVI_DB5PR_3 = 2,
+	INFOFRAME_AVI_DB5PR_4 = 3,
+	INFOFRAME_AVI_DB5PR_5 = 4,
+	INFOFRAME_AVI_DB5PR_6 = 5,
+	INFOFRAME_AVI_DB5PR_7 = 6,
+	INFOFRAME_AVI_DB5PR_8 = 7,
+	INFOFRAME_AVI_DB5PR_9 = 8,
+	INFOFRAME_AVI_DB5PR_10 = 9
+};
+
+struct hdmi_core_infoframe_avi {
+	u8		db1y_rgb_yuv422_yuv444;
+	u8		db1a_active_format_off_on;
+	u8		db1b_no_vert_hori_verthori;
+	u8		db1s_0_1_2;
+	u8		db2c_no_itu601_itu709_extented;
+	u8		db2m_no_43_169;
+	u8		db2r_same_43_169_149;
+	u8		db3itc_no_yes;
+	u8		db3ec_xvyuv601_xvyuv709;
+	u8		db3q_default_lr_fr;
+	u8		db3sc_no_hori_vert_horivert;
+	u8		db4vic_videocode;
+	u8		db5pr_no_2_3_4_5_6_7_8_9_10;
+	u16		db6_7_lineendoftop;
+	u16		db8_9_linestartofbottom;
+	u16		db10_11_pixelendofleft;
+	u16		db12_13_pixelstartofright;
+};
+
+struct hdmi_core_packet_enable_repeat {
+	u32		AudioPacketED;
+	u32		AudioPacketRepeat;
+	u32		AVIInfoFrameED;
+	u32		AVIInfoFrameRepeat;
+	u32		GeneralcontrolPacketED;
+	u32		GeneralcontrolPacketRepeat;
+	u32		GenericPacketED;
+	u32		GenericPacketRepeat;
+};
+
+enum hdmi_stereo_channel {
+	HDMI_STEREO_NOCHANNEL = 0,
+	HDMI_STEREO_ONECHANNELS = 1,
+	HDMI_STEREO_TWOCHANNELS = 2,
+	HDMI_STEREO_THREECHANNELS = 3,
+	HDMI_STEREO_FOURCHANNELS = 4
+};
+
+enum hdmi_cea_code {
+	HDMI_CEA_CODE_00 = 0x0,
+	HDMI_CEA_CODE_01 = 0x1,
+	HDMI_CEA_CODE_02 = 0x2,
+	HDMI_CEA_CODE_03 = 0x3,
+	HDMI_CEA_CODE_04 = 0x4,
+	HDMI_CEA_CODE_05 = 0x5,
+	HDMI_CEA_CODE_06 = 0x6,
+	HDMI_CEA_CODE_07 = 0x7,
+	HDMI_CEA_CODE_08 = 0x8,
+	HDMI_CEA_CODE_09 = 0x9,
+	HDMI_CEA_CODE_0A = 0xA,
+	HDMI_CEA_CODE_0B = 0xB,
+	HDMI_CEA_CODE_0C = 0xC,
+	HDMI_CEA_CODE_0D = 0xD,
+	HDMI_CEA_CODE_0E = 0xE,
+	HDMI_CEA_CODE_0F = 0xF,
+	HDMI_CEA_CODE_10 = 0x10,
+	HDMI_CEA_CODE_11 = 0x11,
+	HDMI_CEA_CODE_12 = 0x12,
+	HDMI_CEA_CODE_13 = 0x13,
+	HDMI_CEA_CODE_14 = 0x14,
+	HDMI_CEA_CODE_15 = 0x15,
+	HDMI_CEA_CODE_16 = 0x16,
+	HDMI_CEA_CODE_17 = 0x17,
+	HDMI_CEA_CODE_18 = 0x18,
+	HDMI_CEA_CODE_19 = 0x19,
+	HDMI_CEA_CODE_1A = 0x1A,
+	HDMI_CEA_CODE_1B = 0x1B,
+	HDMI_CEA_CODE_1C = 0x1C,
+	HDMI_CEA_CODE_1D = 0x1D,
+	HDMI_CEA_CODE_1E = 0x1E,
+	HDMI_CEA_CODE_1F = 0x1F,
+	HDMI_CEA_CODE_20 = 0x20,
+	HDMI_CEA_CODE_21 = 0x21,
+	HDMI_CEA_CODE_22 = 0x22,
+	HDMI_CEA_CODE_23 = 0x23,
+	HDMI_CEA_CODE_24 = 0x24,
+	HDMI_CEA_CODE_25 = 0x25,
+	HDMI_CEA_CODE_26 = 0x26
+};
+
+enum hdmi_iec_format {
+	HDMI_AUDIO_FORMAT_LPCM = 0,
+	HDMI_AUDIO_FORMAT_IEC = 1
+};
+
+enum hdmi_audio_justify {
+	HDMI_AUDIO_JUSTIFY_LEFT = 0,
+	HDMI_AUDIO_JUSTIFY_RIGHT = 1
+};
+
+enum hdmi_sample_order {
+	HDMI_SAMPLE_RIGHT_FIRST = 0,
+	HDMI_SAMPLE_LEFT_FIRST = 1
+};
+
+enum hdmi_sample_perword {
+	HDMI_ONEWORD_ONE_SAMPLE = 0,
+	HDMI_ONEWORD_TWO_SAMPLES = 1
+};
+
+enum hdmi_sample_size {
+	HDMI_SAMPLE_16BITS = 0,
+	HDMI_SAMPLE_24BITS = 1
+};
+
+struct hdmi_audio_format {
+	enum hdmi_stereo_channel	stereo_channel_enable;
+	enum hdmi_cea_code		audio_channel_location;
+	enum hdmi_iec_format		iec;
+	enum hdmi_audio_justify		justify;
+	enum hdmi_sample_order		left_before;
+	enum hdmi_sample_perword	sample_number;
+	enum hdmi_sample_size		sample_size;
+};
+
+enum hdmi_dma_irq {
+	HDMI_THRESHOLD_DMA = 0,
+	HDMI_THRESHOLD_IRQ = 1
+};
+
+enum hdmi_block_start_end {
+	HDMI_BLOCK_STARTEND_ON = 0,
+	HDMI_BLOCK_STARTEND_OFF = 1
+};
+
+struct hdmi_audio_dma {
+	u8				dma_transfer;
+	u8				block_size;
+	enum hdmi_dma_irq		dma_or_irq;
+	u16				threshold_value;
+	enum hdmi_block_start_end	block_start_end;
+};
+
+enum hdmi_packing_mode {
+	HDMI_PACK_10b_RGB_YUV444 = 0,
+	HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
+	HDMI_PACK_20b_YUV422 = 2,
+	HDMI_PACK_ALREADYPACKED = 7
+};
+
+struct hdmi_video_format {
+	enum hdmi_packing_mode	packingMode;
+	u32	linePerPanel;
+	u32	pixelPerLine;
+};
+
+struct hdmi_video_interface {
+	int	vSyncPolarity;
+	int	hSyncPolarity;
+	int	interlacing;
+	int	timingMode;
+};
+
+struct hdmi_video_timing {
+	u32	horizontalBackPorch;
+	u32	horizontalFrontPorch;
+	u32	horizontalSyncPulse;
+	u32	verticalBackPorch;
+	u32	verticalFrontPorch;
+	u32	verticalSyncPulse;
+};
+
+typedef struct HDMI_Timing_label {
+	u32	pixelPerLine;
+	u32	linePerPanel;
+	u32	horizontalBackPorch;
+	u32	horizontalFrontPorch;
+	u32	horizontalSyncPulse;
+	u32	verticalBackPorch;
+	u32	verticalFrontPorch;
+	u32	verticalSyncPulse;
+	u32	pplclk;
+} HDMI_Timing_t, *pHDMI_Timing_t;
+
+struct hdmi_config {
+	u16 ppl;	/* pixel per line */
+	u16 lpp;	/* line per panel */
+	u32 pixel_clock;
+	u16 hsw;	/* Horizontal synchronization pulse width */
+	u16 hfp;	/* Horizontal front porch */
+	u16 hbp;	/* Horizontal back porch */
+	u16 vsw;	/* Vertical synchronization pulse width */
+	u16 vfp;	/* Vertical front porch */
+	u16 vbp;	/* Vertical back porch */
+	u16 interlace;
+	u16 h_pol;
+	u16 v_pol;
+	u16 hdmi_dvi;
+	u16 video_format;
+};
+
+enum hdmi_core_if_fs {
+	IF_FS_NO     = 0x0,
+	IF_FS_32000  = 0x1,
+	IF_FS_44100  = 0x2,
+	IF_FS_48000  = 0x3,
+	IF_FS_88200  = 0x4,
+	IF_FS_96000  = 0x5,
+	IF_FS_176400 = 0x6,
+	IF_FS_192000 = 0x7
+};
+
+enum hdmi_core_if_sample_size{
+	IF_NO_PER_SAMPLE = 0x0,
+	IF_16BIT_PER_SAMPLE = 0x1,
+	IF_20BIT_PER_SAMPLE = 0x2,
+	IF_24BIT_PER_SAMPLE = 0x3
+};
+
+struct hdmi_core_audio_config {
+	enum hdmi_core_fs		fs; /* 0=32KHz - 1=44.1KHz */
+	u32				n;
+	u32				cts;
+	u32				aud_par_busclk;
+	enum hdmi_core_layout		layout; /* 0: 2Ch - 1: 8Ch */
+	enum hdmi_core_cts_mode		cts_mode; /* 0: HW  - 1: SW*/
+	enum hdmi_core_if_fs		if_fs;
+	u32				if_channel_number;
+	enum hdmi_core_if_sample_size	if_sample_size;
+	enum hdmi_cea_code		if_audio_channel_location;
+ };
+
+/* Function prototype */
+int HDMI_W1_StopVideoFrame(u32);
+int HDMI_W1_StartVideoFrame(u32);
+int HDMI_W1_SetWaitPhyPwrState(u32 name, HDMI_PhyPwr_t param);
+int HDMI_W1_SetWaitPllPwrState(u32 name, HDMI_PllPwr_t param);
+int HDMI_W1_SetWaitSoftReset(void);
+int hdmi_w1_wrapper_disable(u32);
+int hdmi_w1_wrapper_enable(u32);
+int hdmi_w1_stop_audio_transfer(u32);
+int hdmi_w1_start_audio_transfer(u32);
+int HDMI_CORE_DDC_READEDID(u32 Core, u8 *data);
+int DSS_HDMI_CONFIG(HDMI_Timing_t timings, u32 video_format, u32 mode);
+void HDMI_W1_HPD_handler(int *r);
+int hdmi_lib_init(void);
+void hdmi_lib_exit(void);
+
+#endif
+
diff --git a/arch/arm/plat-omap/include/plat/vrfb.h b/arch/arm/plat-omap/include/plat/vrfb.h
index d8a03ced3b10..3792bdea2f6d 100644
--- a/arch/arm/plat-omap/include/plat/vrfb.h
+++ b/arch/arm/plat-omap/include/plat/vrfb.h
@@ -35,6 +35,7 @@ struct vrfb {
 	bool yuv_mode;
 };
 
+#ifdef CONFIG_OMAP2_VRFB
 extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
 extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
@@ -47,4 +48,19 @@ extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
 extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
 extern void omap_vrfb_restore_context(void);
 
+#else
+static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
+static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
+static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
+		u8 bytespp) {}
+static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
+		{ return 0; }
+static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
+		{ return 0; }
+static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
+		u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
+static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
+		{ return 0; }
+static inline void omap_vrfb_restore_context(void) {}
+#endif
 #endif /* __VRFB_H */