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authorArnd Bergmann <arnd@arndb.de>2022-08-02 16:09:12 +0200
committerArnd Bergmann <arnd@arndb.de>2022-08-02 16:09:13 +0200
commit0d98fbcf72f11b6a6fadcec16d4c7f317bf417ae (patch)
tree6018107f42bed383f7416e9d7309a92c737feb34 /arch/arm
parent87df0cecc269317def877ed05966781e4389d122 (diff)
parentb3cbbb58632fa6f9cebf3f5c3ba210f11a3bdeb8 (diff)
Merge tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late
SoCFPGA dts updates for v5.20, part 2 - Update EMAC AXI settings for Cyclone5 * tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: add EMAC AXI settings for Cyclone5 arm64: dts: altera: socfpga_stratix10: move clocks out of soc node arm64: dts: Add support for Stratix 10 Software Virtual Platform dt-bindings: altera: document Stratix 10 SWVP compatibles arm64: dts: altera: adjust whitespace around '=' arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC dt-bindings: altera: Add Chameleon v3 board ARM: dts: socfpga: Add Google Chameleon v3 devicetree ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Link: https://lore.kernel.org/r/20220728223237.3184243-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi8
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi10
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts90
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi (renamed from arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts)48
5 files changed, 117 insertions, 41 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..fff06ce4ad70 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1148,7 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
- socfpga_arria10_mercury_aa1.dtb \
+ socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index bfaef45bdd04..2459f3cd7dd9 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -561,6 +561,12 @@
interrupts = <0 175 4>;
};
+ socfpga_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ snps,blen = <0 0 0 0 16 0 0>;
+ };
+
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@@ -576,6 +582,7 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@@ -594,6 +601,7 @@
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
+ snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 26bda2557fe8..4370e3cbbb4b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -736,6 +736,16 @@
<37 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdmmca-ecc@ff8c2c00 {
+ compatible = "altr,socfpga-sdmmc-ecc";
+ reg = <0xff8c2c00 0x400>;
+ altr,ecc-parent = <&mmc>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <16 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 000000000000..422d00cd4c74
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+ model = "Google Chameleon V3";
+ compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
+ "altr,socfpga-arria10", "altr,socfpga";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ };
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ ssm2603: audio-codec@1a {
+ compatible = "adi,ssm2603";
+ reg = <0x1a>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ u80: gpio@21 {
+ compatible = "nxp,pca9535";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SOM_AUD_MUTE",
+ "DP1_OUT_CEC_EN",
+ "DP2_OUT_CEC_EN",
+ "DP1_SOM_PS8469_CAD",
+ "DPD_SOM_PS8469_CAD",
+ "DP_OUT_PWR_EN",
+ "STM32_RST_L",
+ "STM32_BOOT0",
+
+ "FPGA_PROT",
+ "STM32_FPGA_COMM0",
+ "TP119",
+ "TP120",
+ "TP121",
+ "TP122",
+ "TP123",
+ "TP124";
+ };
+};
+
+&mmc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
index a75c059b6727..ad7cd14de6b6 100644
--- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts
+++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
-/dts-v1/;
+/*
+ * Copyright 2022 Google LLC
+ */
#include "socfpga_arria10.dtsi"
@@ -11,8 +13,6 @@
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
};
memory@0 {
@@ -26,24 +26,11 @@
};
};
-&eccmgr {
- sdmmca-ecc@ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
-
&gmac0 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
max-frame-size = <3800>;
- status = "okay";
phy-handle = <&phy3>;
@@ -69,22 +56,13 @@
};
};
-&gpio0 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
&i2c1 {
- status = "okay";
+ atsha204a: crypto@64 {
+ compatible = "atmel,atsha204a";
+ reg = <0x64>;
+ };
+
isl12022: isl12022@6f {
- status = "okay";
compatible = "isil,isl12022";
reg = <0x6f>;
};
@@ -92,7 +70,6 @@
/* Following mappings are taken from arria10 socdk dts */
&mmc {
- status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
@@ -101,12 +78,3 @@
&osc1 {
clock-frequency = <33330000>;
};
-
-&uart1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- dr_mode = "host";
-};