diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2010-10-27 10:06:32 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-11-24 03:30:54 -0500 |
| commit | 4939c1a1e052291e6df220c0c68d452fd5e6a87f (patch) | |
| tree | bf8ed4a2ba4efa6ce025964bf25c24e36fbbd226 /arch/blackfin/mach-bf561 | |
| parent | f31e7e4cc4d4f25bcca12c516e42942117c6047f (diff) | |
Blackfin: bf561: update one more SIC_SYSCR rename
Looks like I missed a spot when renaming the SICA macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/smp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c index f540ed1257d6..be6083a7e42f 100644 --- a/arch/blackfin/mach-bf561/smp.c +++ b/arch/blackfin/mach-bf561/smp.c @@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle spin_lock(&boot_lock); - if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) { + if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) { /* CoreB already running, sending ipi to wakeup it */ platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0); } else { /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */ - bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT); + bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT); SSYNC(); } |