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authorGuo Ren <guoren@linux.alibaba.com>2020-01-22 11:15:14 +0800
committerGuo Ren <guoren@linux.alibaba.com>2020-02-21 15:43:24 +0800
commit761b4f694cb90b63ca2739ac8a8a176342636e5e (patch)
tree3af10af362b1feb39f151015ca4a96c537485745 /arch/csky/include/asm
parenta736fa1ed772e3640e1bfaab36032c5a285d6a7b (diff)
csky: Support icache flush without specific instructions
Some CPUs don't support icache specific instructions to flush icache lines in broadcast way. We use cpu control registers to flush local icache and use IPI to notify other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include/asm')
-rw-r--r--arch/csky/include/asm/cache.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/csky/include/asm/cache.h b/arch/csky/include/asm/cache.h
index 1d5fc2f78fd7..4b5c09bf1d25 100644
--- a/arch/csky/include/asm/cache.h
+++ b/arch/csky/include/asm/cache.h
@@ -16,6 +16,7 @@ void dcache_wb_line(unsigned long start);
void icache_inv_range(unsigned long start, unsigned long end);
void icache_inv_all(void);
+void local_icache_inv_all(void *priv);
void dcache_wb_range(unsigned long start, unsigned long end);
void dcache_wbinv_all(void);