diff options
| author | Huang Pei <huangpei@loongson.cn> | 2021-03-13 09:39:27 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-03-14 14:08:15 +0100 |
| commit | c6972fb9ba8aab384568665411015b7deb8a8609 (patch) | |
| tree | 6c28cfd26d67e3e5f9b12368e7dad65b0702a8b7 /arch/mips/Kconfig | |
| parent | c5a210453cf5c9140947533168077f518a01b4cd (diff) | |
MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling
+. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of
0xa8xx_xxxx_xxxx_xxxx
+. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit
+. cast CAC_BASE into u64 to silence warning on MIPS32
CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.
+. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53,
only save 53 - 12 = 41 bits, aka :
bit[63:59] | 0000 00 | bit[53:12] | 0000 0000 0000
+. for CKSEG0, only save 29 - 12 = 17 bits
when switching pgd, only need to save bit[53:12] or bit[28:12] into
CP0 Context's bit[63:23], see folling asm generated at run time
tlbmiss_handler_setup_pgd:
.set push
.set noreorder
dsra a2, a0, 29
move a3, a0
dins a0, zero, 29, 35
daddiu a2, a2, 4 //for CKSEG0, a2 from 0xfffffffffffffffc
//into 0
movn a0, a3, a2
dsll a0, a0, 11
jr ra
dmtc0 a0, CP0_CONTEXT
.set pop
when using it on page walking
dmfc0 k0, CP0_CONTEXT
dins k0, zero, 0, 23 // zero badv2
ori k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59]
drotr k0, k0, 11 // kick it in the right place
Signed-off-by: Huang Pei <huangpei@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b9ae8e7d95e0..160b3a890840 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2188,7 +2188,8 @@ config CPU_SUPPORTS_HUGEPAGES depends on !(32BIT && (ARCH_PHYS_ADDR_T_64BIT || EVA)) config MIPS_PGD_C0_CONTEXT bool - default y if 64BIT && (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP + depends on 64BIT + default y if (CPU_MIPSR2 || CPU_MIPSR6) && !CPU_XLP # # Set to y for ptrace access to watch registers. |