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authorAntony Pavlov <antonynpavlov@gmail.com>2016-03-17 06:34:15 +0300
committerRalf Baechle <ralf@linux-mips.org>2016-05-13 14:01:45 +0200
commit3bdf1071ba7de08c55a5cce54964ded7c0c8540d (patch)
tree8fa1452be032fd8c72d8adfcf6a55349a0d940f3 /arch/mips/boot
parentaf5ad0de22480a452049e0e942b10af77ef60530 (diff)
MIPS: ath79: update devicetree clock support for AR9132
Current ath79 clock.c code does not read reference clock and pll setup from devicetree. E.g. you can set any clock rate value in board DTS but it will have no effect on the real clk calculation. This patch fixes some AR9132 devicetree clock support defects: * clk initialization function ath79_clocks_init_dt_ng() is introduced; it actually gets pll block base register address and reference clock from devicetree; * pll register parsing code is moved to the separate ar724x_clk_init() function; this function can be called from platform code or from devicetree code. Also mips_hpt_frequency value is set from dt, so the appropriate clock parameter is added to the cpu@0 devicetree node. The same approach can be used for adding AR9331 devicetree support. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Alban Bedel <albeu@free.fr> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/boot')
-rw-r--r--arch/mips/boot/dts/qca/ar9132.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi
index 2f9a3eee9fe6..302f0a8d2988 100644
--- a/arch/mips/boot/dts/qca/ar9132.dtsi
+++ b/arch/mips/boot/dts/qca/ar9132.dtsi
@@ -13,6 +13,7 @@
cpu@0 {
device_type = "cpu";
compatible = "mips,mips24Kc";
+ clocks = <&pll ATH79_CLK_CPU>;
reg = <0>;
};
};