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authorIngo Molnar <mingo@elte.hu>2008-10-13 10:52:30 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-13 10:52:30 +0200
commitc493756e2a8a78bcaae30668317890dcfe86e7c3 (patch)
tree8fb40782e79472ed882ff2098d4dd295557278ee /arch/mips/include/asm/cachectl.h
parent0d15504f16f68725e4635aa85411015d1c573b0a (diff)
parent4480f15b3306f43bbb0310d461142b4e897ca45b (diff)
Merge branch 'linus' into oprofile
Conflicts: arch/x86/kernel/apic_32.c include/linux/pci_ids.h
Diffstat (limited to 'arch/mips/include/asm/cachectl.h')
-rw-r--r--arch/mips/include/asm/cachectl.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 000000000000..f3ce721861d3
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE (1<<0) /* flush instruction cache */
+#define DCACHE (1<<1) /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE 0 /* make pages cacheable */
+#define UNCACHEABLE 1 /* make pages uncacheable */
+
+#endif /* _ASM_CACHECTL */