diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2017-06-02 15:38:01 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2017-06-29 02:42:29 +0200 |
| commit | e7bc8557428f069eaa613b3676ea6931c0f7fe43 (patch) | |
| tree | c7f4f7a8b42f6c974159eef349eb041b5ea7b570 /arch/mips/kernel | |
| parent | fa7a3b4a7217b40bf58c4f38e5ee573b43a8aa2f (diff) | |
MIPS: Add CPU shared FTLB feature detection
Some systems share FTLB RAMs or entries between sibling CPUs (ie.
hardware threads, or VP(E)s, within a core). These properties require
kernel handling in various places. As a start this patch introduces
cpu_has_shared_ftlb_ram & cpu_has_shared_ftlb_entries feature macros
which we set appropriately for I6400 & I6500 CPUs. Further patches will
make use of these macros as appropriate.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16202/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 09462bba629f..3f0d43ce994a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1653,6 +1653,17 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) decode_configs(c); spram_config(); + + switch (__get_cpu_type(c->cputype)) { + case CPU_I6500: + c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; + /* fall-through */ + case CPU_I6400: + c->options |= MIPS_CPU_SHARED_FTLB_RAM; + /* fall-through */ + default: + break; + } } static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |