diff options
| author | Robert Richter <robert.richter@amd.com> | 2010-04-23 14:30:22 +0200 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2010-04-23 14:30:22 +0200 |
| commit | a36bf32e9e8a86f291f746b7f8292e042ee04a46 (patch) | |
| tree | c5c999baa4c214218e3adea9b336cbd9f23950ad /arch/mips/mm/c-octeon.c | |
| parent | bc078e4eab65f11bbaeed380593ab8151b30d703 (diff) | |
| parent | 01bf0b64579ead8a82e7cfc32ae44bc667e7ad0f (diff) | |
Merge commit 'v2.6.34-rc5' into oprofile/core
Diffstat (limited to 'arch/mips/mm/c-octeon.c')
| -rw-r--r-- | arch/mips/mm/c-octeon.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index e06f1af760a7..0f9c488044d1 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; @@ -305,4 +306,3 @@ asmlinkage void cache_parity_error_octeon_non_recoverable(void) { cache_parity_error_octeon(1); } - |