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authorMaciej W. Rozycki <macro@linux-mips.org>2015-04-03 23:27:06 +0100
committerBen Hutchings <ben@decadent.org.uk>2018-03-03 15:51:54 +0000
commit89d573ab001aca5b290ad627cb7e8afe1a88d9e3 (patch)
treee1abf2d0cd325d40362fa9e8cd3eced936da2346 /arch/mips
parenta4fba4e467e4150edf42a97a1641ab5c2cde354f (diff)
MIPS: Respect the FCSR exception mask for `si_code'
commit ed2d72c1eb3643b7c109bdf387563d9b9a30c279 upstream. Respect the FCSR exception mask when interpreting the IEEE 754 exception condition to report with SIGFPE in `si_code', so as not to use one that has been masked where a different one set in parallel caused the FPE hardware exception to trigger. As per the IEEE Std 754 the Inexact exception can happen together with Overflow or Underflow. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/traps.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e6a8e0d89b92..11c13e55a0cb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -12,6 +12,7 @@
* Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2014, Imagination Technologies Ltd.
*/
+#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/compiler.h>
#include <linux/context_tracking.h>
@@ -785,7 +786,15 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
process_fpemu_return(sig, fault_addr);
goto out;
- } else if (fcr31 & FPU_CSR_INV_X)
+ }
+
+ /*
+ * Inexact can happen together with Overflow or Underflow.
+ * Respect the mask to deliver the correct exception.
+ */
+ fcr31 &= (fcr31 & FPU_CSR_ALL_E) <<
+ (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E));
+ if (fcr31 & FPU_CSR_INV_X)
info.si_code = FPE_FLTINV;
else if (fcr31 & FPU_CSR_DIV_X)
info.si_code = FPE_FLTDIV;