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| author | Dan Williams <dan.j.williams@intel.com> | 2016-01-10 07:53:55 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2016-01-10 07:53:55 -0800 |
| commit | 8b63b6bfc1a551acf154061699028c7032d7890c (patch) | |
| tree | 16882e9bc9e35eacb870a6d8a71617e579c4ffdc /arch/parisc/kernel/pci.c | |
| parent | e07ecd76d4db7bda1e9495395b2110a3fe28845a (diff) | |
| parent | 55f5560d8c18fe33fc169f8d244a9247dcac7612 (diff) | |
Merge branch 'for-4.5/block-dax' into for-4.5/libnvdimmlibnvdimm-for-4.5
Diffstat (limited to 'arch/parisc/kernel/pci.c')
| -rw-r--r-- | arch/parisc/kernel/pci.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c index 64f2764a8cef..c99f3dde455c 100644 --- a/arch/parisc/kernel/pci.c +++ b/arch/parisc/kernel/pci.c @@ -171,24 +171,6 @@ void pcibios_set_master(struct pci_dev *dev) } -void __init pcibios_init_bus(struct pci_bus *bus) -{ - struct pci_dev *dev = bus->self; - unsigned short bridge_ctl; - - /* We deal only with pci controllers and pci-pci bridges. */ - if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) - return; - - /* PCI-PCI bridge - set the cache line and default latency - (32) for primary and secondary buses. */ - pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); - - pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); - bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; - pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); -} - /* * pcibios align resources() is called every time generic PCI code * wants to generate a new address. The process of looking for |