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authorBin Meng <bmeng@tinylab.org>2022-12-09 23:04:36 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2023-01-19 14:58:19 +0100
commitdb5489f4be000cbb7e7ce9cc1a264c5d3d25b56f (patch)
tree5750889ce8f55be25cbd33fc8419d7c95d3acbe9 /arch/riscv/include/asm/semihost.h
parent8890717526c8e13801f7e866329a2bfce3a62240 (diff)
riscv: Implement semihost.h for earlycon semihost driver
Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by: Bin Meng <bmeng@tinylab.org> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221209150437.795918-3-bmeng@tinylab.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/riscv/include/asm/semihost.h')
-rw-r--r--arch/riscv/include/asm/semihost.h26
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/semihost.h b/arch/riscv/include/asm/semihost.h
new file mode 100644
index 000000000000..557a34938193
--- /dev/null
+++ b/arch/riscv/include/asm/semihost.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
+ */
+
+#ifndef _RISCV_SEMIHOST_H_
+#define _RISCV_SEMIHOST_H_
+
+struct uart_port;
+
+static inline void smh_putc(struct uart_port *port, unsigned char c)
+{
+ asm volatile("addi a1, %0, 0\n"
+ "addi a0, zero, 3\n"
+ ".balign 16\n"
+ ".option push\n"
+ ".option norvc\n"
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 0x7\n"
+ ".option pop\n"
+ : : "r" (&c) : "a0", "a1", "memory");
+}
+
+#endif /* _RISCV_SEMIHOST_H_ */