diff options
| author | David S. Miller <davem@davemloft.net> | 2014-09-24 21:49:29 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-10-05 16:53:40 -0700 |
| commit | 7c0fa0f24bb76ce3d67be7f737b799846a04570f (patch) | |
| tree | 5383bc77f280dc29c5cc422cae89283c6fcb8690 /arch/sparc/include/asm/page_64.h | |
| parent | c06240c7f5c39c83dfd7849c0770775562441b96 (diff) | |
sparc64: Increase MAX_PHYS_ADDRESS_BITS to 53.
Make sure, at compile time, that the kernel can properly support
whatever MAX_PHYS_ADDRESS_BITS is defined to.
On M7 chips, use a max_phys_bits value of 49.
Based upon a patch by Bob Picco.
Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Bob Picco <bob.picco@oracle.com>
Diffstat (limited to 'arch/sparc/include/asm/page_64.h')
| -rw-r--r-- | arch/sparc/include/asm/page_64.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sparc/include/asm/page_64.h b/arch/sparc/include/asm/page_64.h index 732ba178a289..6784a3382826 100644 --- a/arch/sparc/include/asm/page_64.h +++ b/arch/sparc/include/asm/page_64.h @@ -122,11 +122,11 @@ extern unsigned long PAGE_OFFSET; #endif /* !(__ASSEMBLY__) */ -/* The maximum number of physical memory address bits we support, this - * is used to size various tables used to manage kernel TLB misses and - * also the sparsemem code. +/* The maximum number of physical memory address bits we support. The + * largest value we can support is whatever "KPGD_SHIFT + KPTE_BITS" + * evaluates to. */ -#define MAX_PHYS_ADDRESS_BITS 47 +#define MAX_PHYS_ADDRESS_BITS 53 #define ILOG2_4MB 22 #define ILOG2_256MB 28 |