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authorThomas Gleixner <tglx@linutronix.de>2018-05-09 23:01:01 +0200
committerThomas Gleixner <tglx@linutronix.de>2018-05-17 17:09:18 +0200
commitccbcd2674472a978b48c91c1fbfb66c0ff959f24 (patch)
tree2a163193b6db3cc4554f4a243782c5cf4893c758 /arch/x86/kernel/process.c
parent1f50ddb4f4189243c05926b842dc1a0332195f31 (diff)
x86/bugs, KVM: Extend speculation control for VIRT_SPEC_CTRL
AMD is proposing a VIRT_SPEC_CTRL MSR to handle the Speculative Store Bypass Disable via MSR_AMD64_LS_CFG so that guests do not have to care about the bit position of the SSBD bit and thus facilitate migration. Also, the sibling coordination on Family 17H CPUs can only be done on the host. Extend x86_spec_ctrl_set_guest() and x86_spec_ctrl_restore_host() with an extra argument for the VIRT_SPEC_CTRL MSR. Hand in 0 from VMX and in SVM add a new virt_spec_ctrl member to the CPU data structure which is going to be used in later patches for the actual implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@suse.de> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Diffstat (limited to 'arch/x86/kernel/process.c')
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