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authorRalf Baechle <ralf@linux-mips.org>2006-06-19 21:56:25 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-06-29 21:10:54 +0100
commitbeab375a48f0cd90eb08f04e2c1dad67b9e6d3f8 (patch)
treea95bf7f73a177a2590547a54759319fad758ecec /arch
parent92c7b62fd1a6898fbfaf1db790ba4e70e90f39d2 (diff)
[MIPS] Treat CPUs with AR bit as physically indexed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/mm/c-r4k.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a78355a44c41..33b1451a365d 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1009,10 +1009,15 @@ static void __init probe_pcache(void)
break;
case CPU_24K:
case CPU_34K:
- if (!(read_c0_config7() & (1 << 16)))
+ if ((read_c0_config7() & (1 << 16))) {
+ /* effectively physically indexed dcache,
+ thus no virtual aliases. */
+ c->dcache.flags |= MIPS_CACHE_PINDEX;
+ break;
+ }
default:
- if (c->dcache.waysize > PAGE_SIZE)
- c->dcache.flags |= MIPS_CACHE_ALIASES;
+ if (c->dcache.waysize > PAGE_SIZE)
+ c->dcache.flags |= MIPS_CACHE_ALIASES;
}
switch (c->cputype) {