diff options
| author | Mythri P K <mythripk@ti.com> | 2010-08-26 18:35:29 +0530 |
|---|---|---|
| committer | Sebastien Jan <s-jan@ti.com> | 2010-09-01 18:20:12 +0200 |
| commit | f79b0458af6df2d05e305c82fb442609e882aceb (patch) | |
| tree | 80f1d46fd2f3572d2a1f494c7097f05ca41fcbd0 /arch | |
| parent | a0116d2b4f0343730bb47bcb031c1e558e0139de (diff) | |
OMAP:DSS:HDMI:Patch to dump HDMI registers
Signed-off-by: Mythri P K <mythripk@ti.com>
checkpatch fixes
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/plat-omap/hdmi_lib.c | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/hdmi_lib.c b/arch/arm/plat-omap/hdmi_lib.c index 56b88c564bb6..36975ab46040 100644 --- a/arch/arm/plat-omap/hdmi_lib.c +++ b/arch/arm/plat-omap/hdmi_lib.c @@ -240,6 +240,70 @@ static inline u32 hdmi_read_reg(u32 base, u16 idx) return l; } +int hdmi_lib_dump_regs() +{ +#define DUMPREG(g, r) printk("%-35s %08x\n", #r, hdmi_read_reg(g, r)) + + /*wrapper registers*/ + DUMPREG(HDMI_WP, HDMI_WP_REVISION); + DUMPREG(HDMI_WP, HDMI_WP_SYSCONFIG); + DUMPREG(HDMI_WP, HDMI_WP_IRQSTATUS_RAW); + DUMPREG(HDMI_WP, HDMI_WP_IRQSTATUS); + DUMPREG(HDMI_WP, HDMI_WP_PWR_CTRL); + DUMPREG(HDMI_WP, HDMI_WP_IRQENABLE_SET); + DUMPREG(HDMI_WP, HDMI_WP_VIDEO_SIZE); + DUMPREG(HDMI_WP, HDMI_WP_VIDEO_TIMING_H); + DUMPREG(HDMI_WP, HDMI_WP_VIDEO_TIMING_V); + DUMPREG(HDMI_WP, HDMI_WP_WP_CLK); + + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__VND_IDL); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DEV_IDL); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DEV_IDH); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DEV_REV); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__SRST); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__SYS_STAT); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__VID_ACEN); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__VID_MODE); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR_STATE); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR1); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR2); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR3); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__INTR4); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__UMASK1); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__TMDS_CTRL); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_CTRL1_VEN__FOLLOWVSYNC); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_CTRL1_HEN__FOLLOWHSYNC); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_CTRL1_BSEL__24BITBUS); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_CTRL1_EDGE__RISINGEDGE); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_CTRL); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_TOP); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_CNTH); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_LINL); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_LINH__1); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_SYS__DE_DLY); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_CMD); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_STATUS); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_ADDR); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_OFFSET); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_COUNT1); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_COUNT2); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_DATA); + DUMPREG(HDMI_CORE_SYS, HDMI_CORE_DDC_SEGM); + + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_DBYTE); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__ACR_CTRL); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_TYPE); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_VERS); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_LEN); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_CHSUM); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__HDMI_CTRL); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_DBYTE); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_DBYTE); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_DBYTE); + DUMPREG(HDMI_CORE_AV, HDMI_CORE_AV__AVI_DBYTE); + return 0; +} + #define FLD_MASK(start, end) (((1 << (start - end + 1)) - 1) << (end)) #define FLD_VAL(val, start, end) (((val) << end) & FLD_MASK(start, end)) #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) |