diff options
| author | Hari Kanigeri <h-kanigeri2@ti.com> | 2010-08-20 08:41:43 -0500 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@canonical.com> | 2010-08-26 21:47:45 +0800 |
| commit | eae94e56ed9ede170571b290b8e9394f6eebe102 (patch) | |
| tree | df7c738056c0342a42c71b0e2d69cc7aea5383d2 /arch | |
| parent | ca31f4dc195d446a8deb8bf11fb64f60efec3263 (diff) | |
omap:iommu-load cam register before flushing the entry
The flush_iotlb_page is not loading the cam register before flushing
the cam entry. This causes wrong entry to be flushed out from the TLB, and
if the entry happens to be a locked TLB entry it would lead to MMU faults.
The fix is to load the cam register with the address to be flushed before
flushing the TLB entry.
Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/plat-omap/iommu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c index 9c6df1845c55..f9854ef3b6a4 100644 --- a/arch/arm/plat-omap/iommu.c +++ b/arch/arm/plat-omap/iommu.c @@ -303,6 +303,7 @@ void flush_iotlb_page(struct iommu *obj, u32 da) if ((start <= da) && (da < start + bytes)) { dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n", __func__, start, da, bytes); + iotlb_load_cr(obj, &cr); iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } |