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authorMichal Simek <monstr@monstr.eu>2010-03-22 20:37:23 +0100
committerMichal Simek <monstr@monstr.eu>2010-03-29 11:35:32 +0200
commit14e4e8373f3b399568053804d22cf3cf92c75a11 (patch)
treead806174810d54fcf58eed6929585d27ea9a2b8c /arch
parent210045c34bee6122f56368f3f3721318fe947469 (diff)
microblaze: Prepare work for optimization in exception code
Any sync branch must follow mts instructions not mfs. Signed-off-by: Michal Simek <monstr@monstr.eu>
Diffstat (limited to 'arch')
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S9
1 files changed, 3 insertions, 6 deletions
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 6651bb437db2..ad6dbf029e6b 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -562,7 +562,6 @@ ex_handler_done:
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop
/* If we are faulting a kernel address, we have to use the
@@ -679,18 +678,17 @@ ex_handler_done:
*/
handle_data_tlb_miss_exception:
/* Working registers already saved: R3, R4, R5, R6
- * R3 = ESR
+ * R3 = EAR, R4 = ESR
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop
/* If we are faulting a kernel address, we have to use the
* kernel page tables. */
- ori r4, r0, CONFIG_KERNEL_START
- cmpu r4, r3, r4
+ ori r6, r0, CONFIG_KERNEL_START
+ cmpu r4, r3, r6
bgti r4, ex5
ori r4, r0, swapper_pg_dir
mts rpid, r0 /* TLB will have 0 TID */
@@ -756,7 +754,6 @@ ex_handler_done:
*/
mfs r11, rpid
nop
- bri 4
mfs r3, rear /* Get faulting address */
nop