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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2010-07-10 02:48:52 +0530
committerSebastien Jan <s-jan@ti.com>2010-07-20 10:49:08 +0200
commit48a6317f1e7f71bfb99e7a6574881bf89c941e3c (patch)
tree5ef83c3222e0bf9ac6a9cba671107791945eb30d /arch
parentb4ee5684a5c6b18fb53841691aabce182dcd3908 (diff)
omap4: clocks: Keep GPT clock enabled all the time
Since the current clock framework code doesn't wait on idlest, the registers can gets accessed before the clock is being enabled and stable This leads to crashesh. One of the crash seen is with 1 GHz MPU speed Also reduce the boot noise by coverting WARN to printk Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c1
-rw-r--r--arch/arm/mach-omap2/dmtimers.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index ab4455dd0045..5e6e566a5840 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1515,6 +1515,7 @@ static struct clk gpt1_fck = {
.clksel = abe_dpll_bypass_clk_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ .flags = ENABLE_ON_INIT,
.clksel_mask = OMAP4430_CLKSEL_MASK,
.ops = &clkops_omap2_dflt,
.recalc = &omap2_clksel_recalc,
diff --git a/arch/arm/mach-omap2/dmtimers.c b/arch/arm/mach-omap2/dmtimers.c
index fd936eeb141d..368691e291bf 100644
--- a/arch/arm/mach-omap2/dmtimers.c
+++ b/arch/arm/mach-omap2/dmtimers.c
@@ -100,7 +100,8 @@ unsigned long omap2_dm_timer_set_clk(struct platform_device *pdev, int source)
clk_disable(odev->hwmods[0]->_clk);
ret = clk_set_parent(odev->hwmods[0]->_clk,
omap2_dm_source_clocks[source]);
- WARN(ret, " omap2 dmtimers: Not able to change the \
+ if (ret)
+ pr_err(" omap2 dmtimers: Not able to change the \
fclk source\n");
clk_enable(odev->hwmods[0]->_clk);
/*