diff options
author | Stephen Rothwell <sfr@canb.auug.org.au> | 2010-07-07 11:21:49 +1000 |
---|---|---|
committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2010-07-07 11:21:49 +1000 |
commit | 5b1d842e501079e477c2f187f152fc64c6d2f24c (patch) | |
tree | ddc864902f5a141fb43a7d4f7d648882dedcbfd2 /arch | |
parent | ec82535ae6d6d9e7043e2b1832a6d7c56818b102 (diff) | |
parent | a95a3727f46d2a8164e608eb3de7cb9cb514c5bd (diff) |
Merge remote branch 'davinci/davinci-next'
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/configs/tnetv107x_defconfig | 1741 | ||||
-rw-r--r-- | arch/arm/mach-davinci/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/mach-davinci/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-davinci/board-tnetv107x-evm.c | 174 | ||||
-rw-r--r-- | arch/arm/mach-davinci/devices-tnetv107x.c | 318 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm365.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-davinci/gpio-tnetv107x.c | 205 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/debug-macro.S | 50 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/gpio.h | 22 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/serial.h | 21 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/tnetv107x.h | 55 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/uncompress.h | 87 | ||||
-rw-r--r-- | arch/arm/mach-davinci/tnetv107x.c | 753 |
13 files changed, 3405 insertions, 40 deletions
diff --git a/arch/arm/configs/tnetv107x_defconfig b/arch/arm/configs/tnetv107x_defconfig new file mode 100644 index 000000000000..efc101f0f8b5 --- /dev/null +++ b/arch/arm/configs/tnetv107x_defconfig @@ -0,0 +1,1741 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.34-rc5 +# Sun May 2 15:05:52 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P6440 is not set +# CONFIG_ARCH_S5P6442 is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +CONFIG_ARCH_DAVINCI=y +# CONFIG_ARCH_OMAP is not set +CONFIG_CP_INTC=y + +# +# TI DaVinci Implementations +# + +# +# DaVinci Core Type +# +# CONFIG_ARCH_DAVINCI_DM644x is not set +# CONFIG_ARCH_DAVINCI_DM355 is not set +# CONFIG_ARCH_DAVINCI_DM646x is not set +# CONFIG_ARCH_DAVINCI_DA830 is not set +# CONFIG_ARCH_DAVINCI_DA850 is not set +# CONFIG_ARCH_DAVINCI_DM365 is not set +CONFIG_ARCH_DAVINCI_TNETV107X=y + +# +# DaVinci Board Type +# +CONFIG_MACH_TNETV107X=y +CONFIG_DAVINCI_MUX=y +CONFIG_DAVINCI_MUX_DEBUG=y +CONFIG_DAVINCI_MUX_WARNINGS=y +CONFIG_DAVINCI_RESET_CLOCKS=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +# CONFIG_CPU_32v6K is not set +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_LEDS=y +# CONFIG_LEDS_CPU is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +# CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=m +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +CONFIG_MTD_NAND_DAVINCI=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +CONFIG_TUN=m +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_TI_DAVINCI_EMAC is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NETPOLL_TRAP=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +CONFIG_INPUT_SPARSEKMAP=m + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_XTKBD=m +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +# CONFIG_VT_CONSOLE is not set +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_DAVINCI_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +CONFIG_SND_SOC=m +CONFIG_SND_DAVINCI_SOC=m +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=m +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +# CONFIG_HID_3M_PCT is not set +CONFIG_HID_A4TECH=m +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +# CONFIG_HID_DRAGONRISE is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KYE is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +CONFIG_HID_MICROSOFT=m +# CONFIG_HID_MOSART is not set +CONFIG_HID_MONTEREY=m +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +# CONFIG_HID_QUANTA is not set +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +# CONFIG_HID_STANTUM is not set +CONFIG_HID_SUNPLUS=m +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=m +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=m +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_SOC=y + +# +# DaVinci 35x and 644x USB support +# +# CONFIG_USB_MUSB_HOST is not set +CONFIG_USB_MUSB_PERIPHERAL=y +# CONFIG_USB_MUSB_OTG is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_MUSB_PIO_ONLY=y +# CONFIG_USB_MUSB_DEBUG is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +CONFIG_USB_GADGET_DEBUG_FILES=y +CONFIG_USB_GADGET_DEBUG_FS=y +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA27X is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +CONFIG_NOP_USB_XCEIV=m +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_DAVINCI=y +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LT3593 is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=m + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=m +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 0316e201ada0..71f90f864748 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -50,6 +50,11 @@ config ARCH_DAVINCI_DM365 select AINTC select ARCH_DAVINCI_DMx +config ARCH_DAVINCI_TNETV107X + select CPU_V6 + select CP_INTC + bool "TNETV107X based system" + comment "DaVinci Board Type" config MACH_DAVINCI_EVM @@ -173,6 +178,13 @@ config DA850_UI_RMII endchoice +config MACH_TNETV107X + bool "TI TNETV107X Reference Platform" + default ARCH_DAVINCI_TNETV107X + depends on ARCH_DAVINCI_TNETV107X + help + Say Y here to select the TI TNETV107X Evaluation Module. + config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 6aac880eb794..eab4c0fd667a 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o +obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o obj-$(CONFIG_AINTC) += irq.o obj-$(CONFIG_CP_INTC) += cp_intc.o @@ -30,6 +32,7 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o +obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o # Power Management obj-$(CONFIG_CPU_FREQ) += cpufreq.o diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c new file mode 100644 index 000000000000..fe2a9d9c8bb7 --- /dev/null +++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c @@ -0,0 +1,174 @@ +/* + * Texas Instruments TNETV107X EVM Board Support + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/console.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/ratelimit.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/mux.h> +#include <mach/cp_intc.h> +#include <mach/tnetv107x.h> + +#define EVM_MMC_WP_GPIO 21 +#define EVM_MMC_CD_GPIO 24 + +static int initialize_gpio(int gpio, char *desc) +{ + int ret; + + ret = gpio_request(gpio, desc); + if (ret < 0) { + pr_err_ratelimited("cannot open %s gpio\n", desc); + return -ENOSYS; + } + gpio_direction_input(gpio); + return gpio; +} + +static int mmc_get_cd(int index) +{ + static int gpio; + + if (!gpio) + gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect"); + + if (gpio < 0) + return gpio; + + return gpio_get_value(gpio) ? 0 : 1; +} + +static int mmc_get_ro(int index) +{ + static int gpio; + + if (!gpio) + gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect"); + + if (gpio < 0) + return gpio; + + return gpio_get_value(gpio) ? 1 : 0; +} + +static struct davinci_mmc_config mmc_config = { + .get_cd = mmc_get_cd, + .get_ro = mmc_get_ro, + .wires = 4, + .max_freq = 50000000, + .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, + .version = MMC_CTLR_VERSION_1, +}; + +static const short sdio1_pins[] __initdata = { + TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1, + TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1, + TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1, + TNETV107X_GPIO21, TNETV107X_GPIO24, + -1 +}; + +static const short uart1_pins[] __initdata = { + TNETV107X_UART1_RD, TNETV107X_UART1_TD, + -1 +}; + +static struct mtd_partition nand_partitions[] = { + /* bootloader (U-Boot, etc) in first 12 sectors */ + { + .name = "bootloader", + .offset = 0, + .size = (12*SZ_128K), + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* bootloader params in the next sector */ + { + .name = "params", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + /* kernel */ + { + .name = "kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M, + .mask_flags = 0, + }, + /* file system */ + { + .name = "filesystem", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } +}; + +static struct davinci_nand_pdata nand_config = { + .mask_cle = 0x4000, + .mask_ale = 0x2000, + .parts = nand_partitions, + .nr_parts = ARRAY_SIZE(nand_partitions), + .ecc_mode = NAND_ECC_HW, + .options = NAND_USE_FLASH_BBT, + .ecc_bits = 1, +}; + +static struct davinci_uart_config serial_config __initconst = { + .enabled_uarts = BIT(1), +}; + +static struct tnetv107x_device_info evm_device_info __initconst = { + .serial_config = &serial_config, + .mmc_config[1] = &mmc_config, /* controller 1 */ + .nand_config[0] = &nand_config, /* chip select 0 */ +}; + +static __init void tnetv107x_evm_board_init(void) +{ + davinci_cfg_reg_list(sdio1_pins); + davinci_cfg_reg_list(uart1_pins); + + tnetv107x_devices_init(&evm_device_info); +} + +#ifdef CONFIG_SERIAL_8250_CONSOLE +static int __init tnetv107x_evm_console_init(void) +{ + return add_preferred_console("ttyS", 0, "115200"); +} +console_initcall(tnetv107x_evm_console_init); +#endif + +MACHINE_START(TNETV107X, "TNETV107X EVM") + .phys_io = TNETV107X_IO_BASE, + .io_pg_offst = (TNETV107X_IO_VIRT >> 18) & 0xfffc, + .boot_params = (TNETV107X_DDR_BASE + 0x100), + .map_io = tnetv107x_init, + .init_irq = cp_intc_init, + .timer = &davinci_timer, + .init_machine = tnetv107x_evm_board_init, +MACHINE_END diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c new file mode 100644 index 000000000000..4eef6ccdc73e --- /dev/null +++ b/arch/arm/mach-davinci/devices-tnetv107x.c @@ -0,0 +1,318 @@ +/* + * Texas Instruments TNETV107X SoC devices + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> +#include <linux/clk.h> +#include <linux/slab.h> + +#include <mach/common.h> +#include <mach/irqs.h> +#include <mach/edma.h> +#include <mach/tnetv107x.h> + +#include "clock.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_TPCC_BASE 0x01c00000 +#define TNETV107X_TPTC0_BASE 0x01c10000 +#define TNETV107X_TPTC1_BASE 0x01c10400 +#define TNETV107X_WDOG_BASE 0x08086700 +#define TNETV107X_SDIO0_BASE 0x08088700 +#define TNETV107X_SDIO1_BASE 0x08088800 +#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 +#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 +#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 + +/* TNETV107X specific EDMA3 information */ +#define EDMA_TNETV107X_NUM_DMACH 64 +#define EDMA_TNETV107X_NUM_TCC 64 +#define EDMA_TNETV107X_NUM_PARAMENTRY 128 +#define EDMA_TNETV107X_NUM_EVQUE 2 +#define EDMA_TNETV107X_NUM_TC 2 +#define EDMA_TNETV107X_CHMAP_EXIST 0 +#define EDMA_TNETV107X_NUM_REGIONS 4 +#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u +#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu + +#define TNETV107X_DMACH_SDIO0_RX 26 +#define TNETV107X_DMACH_SDIO0_TX 27 +#define TNETV107X_DMACH_SDIO1_RX 28 +#define TNETV107X_DMACH_SDIO1_TX 29 + +static const s8 edma_tc_mapping[][2] = { + /* event queue no TC no */ + { 0, 0 }, + { 1, 1 }, + { -1, -1 } +}; + +static const s8 edma_priority_mapping[][2] = { + /* event queue no Prio */ + { 0, 3 }, + { 1, 7 }, + { -1, -1 } +}; + +static struct edma_soc_info edma_info[] = { + { + .n_channel = EDMA_TNETV107X_NUM_DMACH, + .n_region = EDMA_TNETV107X_NUM_REGIONS, + .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY, + .n_tc = EDMA_TNETV107X_NUM_TC, + .n_cc = 1, + .queue_tc_mapping = edma_tc_mapping, + .queue_priority_mapping = edma_priority_mapping, + }, +}; + +static struct resource edma_resources[] = { + { + .name = "edma_cc0", + .start = TNETV107X_TPCC_BASE, + .end = TNETV107X_TPCC_BASE + SZ_32K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc0", + .start = TNETV107X_TPTC0_BASE, + .end = TNETV107X_TPTC0_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma_tc1", + .start = TNETV107X_TPTC1_BASE, + .end = TNETV107X_TPTC1_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "edma0", + .start = IRQ_TNETV107X_TPCC, + .flags = IORESOURCE_IRQ, + }, + { + .name = "edma0_err", + .start = IRQ_TNETV107X_TPCC_ERR, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device edma_device = { + .name = "edma", + .id = -1, + .num_resources = ARRAY_SIZE(edma_resources), + .resource = edma_resources, + .dev.platform_data = edma_info, +}; + +static struct plat_serial8250_port serial_data[] = { + { + .mapbase = TNETV107X_UART0_BASE, + .irq = IRQ_TNETV107X_UART0, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = TNETV107X_UART1_BASE, + .irq = IRQ_TNETV107X_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .mapbase = TNETV107X_UART2_BASE, + .irq = IRQ_TNETV107X_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_FIXED_TYPE | UPF_IOREMAP, + .type = PORT_AR7, + .iotype = UPIO_MEM32, + .regshift = 2, + }, + { + .flags = 0, + }, +}; + +struct platform_device tnetv107x_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = serial_data, +}; + +static struct resource mmc0_resources[] = { + { /* Memory mapped registers */ + .start = TNETV107X_SDIO0_BASE, + .end = TNETV107X_SDIO0_BASE + 0x0ff, + .flags = IORESOURCE_MEM + }, + { /* MMC interrupt */ + .start = IRQ_TNETV107X_MMC0, + .flags = IORESOURCE_IRQ + }, + { /* SDIO interrupt */ + .start = IRQ_TNETV107X_SDIO0, + .flags = IORESOURCE_IRQ + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX), + .flags = IORESOURCE_DMA + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX), + .flags = IORESOURCE_DMA + }, +}; + +static struct resource mmc1_resources[] = { + { /* Memory mapped registers */ + .start = TNETV107X_SDIO1_BASE, + .end = TNETV107X_SDIO1_BASE + 0x0ff, + .flags = IORESOURCE_MEM + }, + { /* MMC interrupt */ + .start = IRQ_TNETV107X_MMC1, + .flags = IORESOURCE_IRQ + }, + { /* SDIO interrupt */ + .start = IRQ_TNETV107X_SDIO1, + .flags = IORESOURCE_IRQ + }, + { /* DMA RX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX), + .flags = IORESOURCE_DMA + }, + { /* DMA TX */ + .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX), + .flags = IORESOURCE_DMA + }, +}; + +static u64 mmc0_dma_mask = DMA_BIT_MASK(32); +static u64 mmc1_dma_mask = DMA_BIT_MASK(32); + +static struct platform_device mmc_devices[2] = { + { + .name = "davinci_mmc", + .id = 0, + .dev = { + .dma_mask = &mmc0_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmc0_resources), + .resource = mmc0_resources + }, + { + .name = "davinci_mmc", + .id = 1, + .dev = { + .dma_mask = &mmc1_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(mmc1_resources), + .resource = mmc1_resources + }, +}; + +static const u32 emif_windows[] = { + TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE, + TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE, +}; + +static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M }; + +static struct resource wdt_resources[] = { + { + .start = TNETV107X_WDOG_BASE, + .end = TNETV107X_WDOG_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device tnetv107x_wdt_device = { + .name = "tnetv107x_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +static int __init nand_init(int chipsel, struct davinci_nand_pdata *data) +{ + struct resource res[2]; + struct platform_device *pdev; + u32 range; + int ret; + + /* Figure out the resource range from the ale/cle masks */ + range = max(data->mask_cle, data->mask_ale); + range = PAGE_ALIGN(range + 4) - 1; + + if (range >= emif_window_sizes[chipsel]) + return -EINVAL; + + pdev = kzalloc(sizeof(*pdev), GFP_KERNEL); + if (!pdev) + return -ENOMEM; + + pdev->name = "davinci_nand"; + pdev->id = chipsel; + pdev->dev.platform_data = data; + + memset(res, 0, sizeof(res)); + + res[0].start = emif_windows[chipsel]; + res[0].end = res[0].start + range; + res[0].flags = IORESOURCE_MEM; + + res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE; + res[1].end = res[1].start + SZ_4K - 1; + res[1].flags = IORESOURCE_MEM; + + ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); + if (ret < 0) { + kfree(pdev); + return ret; + } + + return platform_device_register(pdev); +} + +void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) +{ + int i; + + platform_device_register(&edma_device); + platform_device_register(&tnetv107x_wdt_device); + + if (info->serial_config) + davinci_serial_init(info->serial_config); + + for (i = 0; i < 2; i++) + if (info->mmc_config[i]) { + mmc_devices[i].dev.platform_data = info->mmc_config[i]; + platform_device_register(&mmc_devices[i]); + } + + for (i = 0; i < 4; i++) + if (info->nand_config[i]) + nand_init(i, info->nand_config[i]); +} diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c index a146849d78f0..652f4b6ee1cd 100644 --- a/arch/arm/mach-davinci/dm365.c +++ b/arch/arm/mach-davinci/dm365.c @@ -1020,6 +1020,8 @@ static struct davinci_timer_info dm365_timer_info = { .clocksource_id = T0_TOP, }; +#define DM365_UART1_BASE (IO_PHYS + 0x106000) + static struct plat_serial8250_port dm365_serial_platform_data[] = { { .mapbase = DAVINCI_UART0_BASE, @@ -1030,7 +1032,7 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = { .regshift = 2, }, { - .mapbase = DAVINCI_UART1_BASE, + .mapbase = DM365_UART1_BASE, .irq = IRQ_UARTINT1, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, diff --git a/arch/arm/mach-davinci/gpio-tnetv107x.c b/arch/arm/mach-davinci/gpio-tnetv107x.c new file mode 100644 index 000000000000..d10298620e2c --- /dev/null +++ b/arch/arm/mach-davinci/gpio-tnetv107x.c @@ -0,0 +1,205 @@ +/* + * Texas Instruments TNETV107X GPIO Controller + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> + +#include <mach/common.h> +#include <mach/tnetv107x.h> + +struct tnetv107x_gpio_regs { + u32 idver; + u32 data_in[3]; + u32 data_out[3]; + u32 direction[3]; + u32 enable[3]; +}; + +#define gpio_reg_index(gpio) ((gpio) >> 5) +#define gpio_reg_bit(gpio) BIT((gpio) & 0x1f) + +#define gpio_reg_rmw(reg, mask, val) \ + __raw_writel((__raw_readl(reg) & ~(mask)) | (val), (reg)) + +#define gpio_reg_set_bit(reg, gpio) \ + gpio_reg_rmw((reg) + gpio_reg_index(gpio), 0, gpio_reg_bit(gpio)) + +#define gpio_reg_clear_bit(reg, gpio) \ + gpio_reg_rmw((reg) + gpio_reg_index(gpio), gpio_reg_bit(gpio), 0) + +#define gpio_reg_get_bit(reg, gpio) \ + (__raw_readl((reg) + gpio_reg_index(gpio)) & gpio_reg_bit(gpio)) + +#define chip2controller(chip) \ + container_of(chip, struct davinci_gpio_controller, chip) + +#define TNETV107X_GPIO_CTLRS DIV_ROUND_UP(TNETV107X_N_GPIO, 32) + +static struct davinci_gpio_controller chips[TNETV107X_GPIO_CTLRS]; + +static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_set_bit(®s->enable, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_clear_bit(®s->enable, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); +} + +static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + gpio_reg_set_bit(®s->direction, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static int tnetv107x_gpio_dir_out(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + if (value) + gpio_reg_set_bit(®s->data_out, gpio); + else + gpio_reg_clear_bit(®s->data_out, gpio); + + gpio_reg_clear_bit(®s->direction, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); + + return 0; +} + +static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + int ret; + + ret = gpio_reg_get_bit(®s->data_in, gpio); + + return ret ? 1 : 0; +} + +static void tnetv107x_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct davinci_gpio_controller *ctlr = chip2controller(chip); + struct tnetv107x_gpio_regs __iomem *regs = ctlr->regs; + unsigned gpio = chip->base + offset; + unsigned long flags; + + spin_lock_irqsave(&ctlr->lock, flags); + + if (value) + gpio_reg_set_bit(®s->data_out, gpio); + else + gpio_reg_clear_bit(®s->data_out, gpio); + + spin_unlock_irqrestore(&ctlr->lock, flags); +} + +static int __init tnetv107x_gpio_setup(void) +{ + int i, base; + unsigned ngpio; + struct davinci_soc_info *soc_info = &davinci_soc_info; + struct tnetv107x_gpio_regs *regs; + struct davinci_gpio_controller *ctlr; + + if (soc_info->gpio_type != GPIO_TYPE_TNETV107X) + return 0; + + ngpio = soc_info->gpio_num; + if (ngpio == 0) { + pr_err("GPIO setup: how many GPIOs?\n"); + return -EINVAL; + } + + if (WARN_ON(TNETV107X_N_GPIO < ngpio)) + ngpio = TNETV107X_N_GPIO; + + regs = ioremap(soc_info->gpio_base, SZ_4K); + if (WARN_ON(!regs)) + return -EINVAL; + + for (i = 0, base = 0; base < ngpio; i++, base += 32) { + ctlr = &chips[i]; + + ctlr->chip.label = "tnetv107x"; + ctlr->chip.can_sleep = 0; + ctlr->chip.base = base; + ctlr->chip.ngpio = ngpio - base; + if (ctlr->chip.ngpio > 32) + ctlr->chip.ngpio = 32; + + ctlr->chip.request = tnetv107x_gpio_request; + ctlr->chip.free = tnetv107x_gpio_free; + ctlr->chip.direction_input = tnetv107x_gpio_dir_in; + ctlr->chip.get = tnetv107x_gpio_get; + ctlr->chip.direction_output = tnetv107x_gpio_dir_out; + ctlr->chip.set = tnetv107x_gpio_set; + + spin_lock_init(&ctlr->lock); + + ctlr->regs = regs; + ctlr->set_data = ®s->data_out[i]; + ctlr->clr_data = ®s->data_out[i]; + ctlr->in_data = ®s->data_in[i]; + + gpiochip_add(&ctlr->chip); + } + + soc_info->gpio_ctlrs = chips; + soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); + return 0; +} +pure_initcall(tnetv107x_gpio_setup); diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S index 3cd93a801d9b..f761dfdb8689 100644 --- a/arch/arm/mach-davinci/include/mach/debug-macro.S +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S @@ -17,22 +17,50 @@ */ #include <linux/serial_reg.h> + +#include <asm/memory.h> + +#include <mach/serial.h> + #define UART_SHIFT 2 + .pushsection .data +davinci_uart_phys: .word 0 +davinci_uart_virt: .word 0 + .popsection + .macro addruart, rx, tmp + + /* Use davinci_uart_phys/virt if already configured */ +10: mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =__virt_to_phys(davinci_uart_phys) + ldrne \rx, =davinci_uart_virt + ldr \rx, [\rx] + cmp \rx, #0 @ is port configured? + bne 99f @ already configured + mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? - moveq \rx, #0x01000000 @ physical base address - movne \rx, #0xfe000000 @ virtual base -#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx) -#error Cannot enable DaVinci and DA8XX platforms concurrently -#elif defined(CONFIG_MACH_DAVINCI_DA830_EVM) || \ - defined(CONFIG_MACH_DAVINCI_DA850_EVM) - orr \rx, \rx, #0x00d00000 @ physical base address - orr \rx, \rx, #0x0000d000 @ of UART 2 -#else - orr \rx, \rx, #0x00c20000 @ UART 0 -#endif + + /* Copy uart phys address from decompressor uart info */ + ldreq \tmp, =__virt_to_phys(davinci_uart_phys) + ldrne \tmp, =davinci_uart_phys + ldreq \rx, =DAVINCI_UART_INFO + ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) + ldr \rx, [\rx, #0] + str \rx, [\tmp] + + /* Copy uart virt address from decompressor uart info */ + ldreq \tmp, =__virt_to_phys(davinci_uart_virt) + ldrne \tmp, =davinci_uart_virt + ldreq \rx, =DAVINCI_UART_INFO + ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) + ldr \rx, [\rx, #4] + str \rx, [\tmp] + + b 10b +99: .endm .macro senduart,rd,rx diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 504cc180a60b..fbece126c2bf 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -25,6 +25,7 @@ enum davinci_gpio_type { GPIO_TYPE_DAVINCI = 0, + GPIO_TYPE_TNETV107X, }; /* @@ -87,9 +88,13 @@ static inline u32 __gpio_mask(unsigned gpio) return 1 << (gpio % 32); } -/* The get/set/clear functions will inline when called with constant +/* + * The get/set/clear functions will inline when called with constant * parameters referencing built-in GPIOs, for low-overhead bitbanging. * + * gpio_set_value() will inline only on traditional Davinci style controllers + * with distinct set/clear registers. + * * Otherwise, calls with variable parameters or referencing external * GPIOs (e.g. on GPIO expander chips) use outlined functions. */ @@ -100,12 +105,15 @@ static inline void gpio_set_value(unsigned gpio, int value) u32 mask; ctlr = __gpio_to_controller(gpio); - mask = __gpio_mask(gpio); - if (value) - __raw_writel(mask, ctlr->set_data); - else - __raw_writel(mask, ctlr->clr_data); - return; + + if (ctlr->set_data != ctlr->clr_data) { + mask = __gpio_mask(gpio); + if (value) + __raw_writel(mask, ctlr->set_data); + else + __raw_writel(mask, ctlr->clr_data); + return; + } } __gpio_set_value(gpio, value); diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h index f6c4f34909a2..8051110b8ac3 100644 --- a/arch/arm/mach-davinci/include/mach/serial.h +++ b/arch/arm/mach-davinci/include/mach/serial.h @@ -11,8 +11,19 @@ #ifndef __ASM_ARCH_SERIAL_H #define __ASM_ARCH_SERIAL_H +#include <asm/memory.h> + #include <mach/hardware.h> +/* + * Stolen area that contains debug uart physical and virtual addresses. These + * addresses are filled in by the uncompress.h code, and are used by the debug + * macros in debug-macro.S. + * + * This area sits just below the page tables (see arch/arm/kernel/head.S). + */ +#define DAVINCI_UART_INFO (PHYS_OFFSET + 0x3ff8) + #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) @@ -21,16 +32,26 @@ #define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) #define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) +#define TNETV107X_UART0_BASE 0x08108100 +#define TNETV107X_UART1_BASE 0x08088400 +#define TNETV107X_UART2_BASE 0x08108300 + +#define TNETV107X_UART0_VIRT IOMEM(0xfee08100) +#define TNETV107X_UART1_VIRT IOMEM(0xfed88400) +#define TNETV107X_UART2_VIRT IOMEM(0xfee08300) + /* DaVinci UART register offsets */ #define UART_DAVINCI_PWREMU 0x0c #define UART_DM646X_SCR 0x10 #define UART_DM646X_SCR_TX_WATERMARK 0x08 +#ifndef __ASSEMBLY__ struct davinci_uart_config { /* Bit field of UARTs present; bit 0 --> UART1 */ unsigned int enabled_uarts; }; extern int davinci_serial_init(struct davinci_uart_config *); +#endif #endif /* __ASM_ARCH_SERIAL_H */ diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h new file mode 100644 index 000000000000..c72064733123 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h @@ -0,0 +1,55 @@ +/* + * Texas Instruments TNETV107X SoC Specific Defines + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H +#define __ASM_ARCH_DAVINCI_TNETV107X_H + +#include <asm/sizes.h> + +#define TNETV107X_DDR_BASE 0x80000000 + +/* + * Fixed mapping for early init starts here. If low-level debug is enabled, + * this area also gets mapped via io_pg_offset and io_phys by the boot code. + * To fit in with the io_pg_offset calculation, the io base address selected + * here _must_ be a multiple of 2^20. + */ +#define TNETV107X_IO_BASE 0x08000000 +#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M) + +#define TNETV107X_N_GPIO 65 + +#ifndef __ASSEMBLY__ + +#include <linux/serial_8250.h> +#include <mach/mmc.h> +#include <mach/nand.h> +#include <mach/serial.h> + +struct tnetv107x_device_info { + struct davinci_uart_config *serial_config; + struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ + struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ +}; + +extern struct platform_device tnetv107x_wdt_device; +extern struct platform_device tnetv107x_serial_device; + +extern void __init tnetv107x_init(void); +extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *); +extern void __init tnetv107x_irq_init(void); + +#endif + +#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */ diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h index 33796b4db17f..15a6192ad6eb 100644 --- a/arch/arm/mach-davinci/include/mach/uncompress.h +++ b/arch/arm/mach-davinci/include/mach/uncompress.h @@ -1,8 +1,17 @@ /* * Serial port stubs for kernel decompress status messages * - * Author: Anant Gole - * (C) Copyright (C) 2006, Texas Instruments, Inc + * Initially based on: + * arch/arm/plat-omap/include/mach/uncompress.h + * + * Original copyrights follow. + * + * Copyright (C) 2000 RidgeRun, Inc. + * Author: Greg Lonnon <glonnon@ridgerun.com> + * + * Rewritten by: + * Author: <source@mvista.com> + * 2004 (c) MontaVista Software, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -11,30 +20,17 @@ #include <linux/types.h> #include <linux/serial_reg.h> -#include <mach/serial.h> #include <asm/mach-types.h> -extern unsigned int __machine_arch_type; +#include <mach/serial.h> static u32 *uart; - -static u32 *get_uart_base(void) -{ - if (__machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM || - __machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) - return (u32 *)DA8XX_UART2_BASE; - else - return (u32 *)DAVINCI_UART0_BASE; -} +static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); /* PORT_16C550A, in polled non-fifo mode */ - static void putc(char c) { - if (!uart) - uart = get_uart_base(); - while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); uart[UART_TX] = c; @@ -42,12 +38,61 @@ static void putc(char c) static inline void flush(void) { - if (!uart) - uart = get_uart_base(); - while (!(uart[UART_LSR] & UART_LSR_THRE)) barrier(); } -#define arch_decomp_setup() +static inline void set_uart_info(u32 phys, void * __iomem virt) +{ + uart = (u32 *)phys; + uart_info[0] = phys; + uart_info[1] = (u32)virt; +} + +#define _DEBUG_LL_ENTRY(machine, phys, virt) \ + if (machine_is_##machine()) { \ + set_uart_info(phys, virt); \ + break; \ + } + +#define DEBUG_LL_DAVINCI(machine, port) \ + _DEBUG_LL_ENTRY(machine, DAVINCI_UART##port##_BASE, \ + IO_ADDRESS(DAVINCI_UART##port##_BASE)) + +#define DEBUG_LL_DA8XX(machine, port) \ + _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE, \ + IO_ADDRESS(DA8XX_UART##port##_BASE)) + +#define DEBUG_LL_TNETV107X(machine, port) \ + _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE, \ + TNETV107X_UART##port##_VIRT) + +static inline void __arch_decomp_setup(unsigned long arch_id) +{ + /* + * Initialize the port based on the machine ID from the bootloader. + * Note that we're using macros here instead of switch statement + * as machine_is functions are optimized out for the boards that + * are not selected. + */ + do { + /* Davinci boards */ + DEBUG_LL_DAVINCI(davinci_evm, 0); + DEBUG_LL_DAVINCI(sffsdr, 0); + DEBUG_LL_DAVINCI(neuros_osd2, 0); + DEBUG_LL_DAVINCI(davinci_dm355_evm, 0); + DEBUG_LL_DAVINCI(dm355_leopard, 0); + DEBUG_LL_DAVINCI(davinci_dm6467_evm, 0); + DEBUG_LL_DAVINCI(davinci_dm365_evm, 0); + + /* DA8xx boards */ + DEBUG_LL_DA8XX(davinci_da830_evm, 2); + DEBUG_LL_DA8XX(davinci_da850_evm, 2); + + /* TNETV107x boards */ + DEBUG_LL_TNETV107X(tnetv107x, 1); + } while (0); +} + +#define arch_decomp_setup() __arch_decomp_setup(arch_id) #define arch_decomp_wdog() diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c new file mode 100644 index 000000000000..864e60482c53 --- /dev/null +++ b/arch/arm/mach-davinci/tnetv107x.c @@ -0,0 +1,753 @@ +/* + * Texas Instruments TNETV107X SoC Support + * + * Copyright (C) 2010 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/platform_device.h> + +#include <asm/mach/map.h> + +#include <mach/common.h> +#include <mach/time.h> +#include <mach/cputype.h> +#include <mach/psc.h> +#include <mach/cp_intc.h> +#include <mach/irqs.h> +#include <mach/gpio.h> +#include <mach/hardware.h> +#include <mach/tnetv107x.h> + +#include "clock.h" +#include "mux.h" + +/* Base addresses for on-chip devices */ +#define TNETV107X_INTC_BASE 0x03000000 +#define TNETV107X_TIMER0_BASE 0x08086500 +#define TNETV107X_TIMER1_BASE 0x08086600 +#define TNETV107X_CHIP_CFG_BASE 0x08087000 +#define TNETV107X_GPIO_BASE 0x08088000 +#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000 +#define TNETV107X_PSC_BASE 0x0808b000 + +/* Reference clock frequencies */ +#define OSC_FREQ_ONCHIP (24000 * 1000) +#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000) +#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000) +#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000) + +#define N_PLLS 3 + +/* Clock Control Registers */ +struct clk_ctrl_regs { + u32 pll_bypass; + u32 _reserved0; + u32 gem_lrst; + u32 _reserved1; + u32 pll_unlock_stat; + u32 sys_unlock; + u32 eth_unlock; + u32 tdm_unlock; +}; + +/* SSPLL Registers */ +struct sspll_regs { + u32 modes; + u32 post_div; + u32 pre_div; + u32 mult_factor; + u32 divider_range; + u32 bw_divider; + u32 spr_amount; + u32 spr_rate_div; + u32 diag; +}; + +/* Watchdog Timer Registers */ +struct wdt_regs { + u32 kick_lock; + u32 kick; + u32 change_lock; + u32 change ; + u32 disable_lock; + u32 disable; + u32 prescale_lock; + u32 prescale; +}; + +static struct clk_ctrl_regs __iomem *clk_ctrl_regs; + +static struct sspll_regs __iomem *sspll_regs[N_PLLS]; +static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 }; + +/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */ +static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) }; + +/* offchip (external) reference clock frequencies */ +static u32 pll_ext_freq[] = { + OSC_FREQ_OFFCHIP_SYS, + OSC_FREQ_OFFCHIP_TDM, + OSC_FREQ_OFFCHIP_ETH +}; + +/* PSC control registers */ +static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE }; + +/* Host map for interrupt controller */ +static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 }; + +static unsigned long clk_sspll_recalc(struct clk *clk); + +/* Level 1 - the PLLs */ +#define define_pll_clk(cname, pll, divmask, base) \ + static struct pll_data pll_##cname##_data = { \ + .num = pll, \ + .div_ratio_mask = divmask, \ + .phys_base = base + \ + TNETV107X_CLOCK_CONTROL_BASE, \ + }; \ + static struct clk pll_##cname##_clk = { \ + .name = "pll_" #cname "_clk", \ + .pll_data = &pll_##cname##_data, \ + .flags = CLK_PLL, \ + .recalc = clk_sspll_recalc, \ + } + +define_pll_clk(sys, 0, 0x1ff, 0x600); +define_pll_clk(tdm, 1, 0x0ff, 0x200); +define_pll_clk(eth, 2, 0x0ff, 0x400); + +/* Level 2 - divided outputs from the PLLs */ +#define define_pll_div_clk(pll, cname, div) \ + static struct clk pll##_##cname##_clk = { \ + .name = #pll "_" #cname "_clk",\ + .parent = &pll_##pll##_clk, \ + .flags = CLK_PLL, \ + .div_reg = PLLDIV##div, \ + } + +define_pll_div_clk(sys, arm1176, 1); +define_pll_div_clk(sys, dsp, 2); +define_pll_div_clk(sys, ddr, 3); +define_pll_div_clk(sys, full, 4); +define_pll_div_clk(sys, lcd, 5); +define_pll_div_clk(sys, vlynq_ref, 6); +define_pll_div_clk(sys, tsc, 7); +define_pll_div_clk(sys, half, 8); + +define_pll_div_clk(eth, 5mhz, 1); +define_pll_div_clk(eth, 50mhz, 2); +define_pll_div_clk(eth, 125mhz, 3); +define_pll_div_clk(eth, 250mhz, 4); +define_pll_div_clk(eth, 25mhz, 5); + +define_pll_div_clk(tdm, 0, 1); +define_pll_div_clk(tdm, extra, 2); +define_pll_div_clk(tdm, 1, 3); + + +/* Level 3 - LPSC gated clocks */ +#define __lpsc_clk(cname, _parent, mod, flg) \ + static struct clk clk_##cname = { \ + .name = #cname, \ + .parent = &_parent, \ + .lpsc = TNETV107X_LPSC_##mod,\ + .flags = flg, \ + } + +#define lpsc_clk_enabled(cname, parent, mod) \ + __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED) + +#define lpsc_clk(cname, parent, mod) \ + __lpsc_clk(cname, parent, mod, 0) + +lpsc_clk_enabled(arm, sys_arm1176_clk, ARM); +lpsc_clk_enabled(gem, sys_dsp_clk, GEM); +lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY); +lpsc_clk_enabled(tpcc, sys_full_clk, TPCC); +lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0); +lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1); +lpsc_clk_enabled(ram, sys_full_clk, RAM); +lpsc_clk_enabled(aemif, sys_full_clk, AEMIF); +lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG); +lpsc_clk_enabled(rom, sys_half_clk, ROM); +lpsc_clk_enabled(secctl, sys_half_clk, SECCTL); +lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR); +lpsc_clk_enabled(gpio, sys_half_clk, GPIO); +lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS); +lpsc_clk_enabled(system, sys_half_clk, SYSTEM); +lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST); +lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST); +lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM); + +lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE); +lpsc_clk(ethss, eth_125mhz_clk, ETHSS); +lpsc_clk(tsc, sys_tsc_clk, TSC); +lpsc_clk(uart0, sys_half_clk, UART0); +lpsc_clk(uart1, sys_half_clk, UART1); +lpsc_clk(uart2, sys_half_clk, UART2); +lpsc_clk(pktsec, sys_half_clk, PKTSEC); +lpsc_clk(keypad, sys_half_clk, KEYPAD); +lpsc_clk(mdio, sys_half_clk, MDIO); +lpsc_clk(sdio0, sys_half_clk, SDIO0); +lpsc_clk(sdio1, sys_half_clk, SDIO1); +lpsc_clk(timer0, sys_half_clk, TIMER0); +lpsc_clk(timer1, sys_half_clk, TIMER1); +lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP); +lpsc_clk(ssp, sys_half_clk, SSP); +lpsc_clk(tdm0, tdm_0_clk, TDM0); +lpsc_clk(tdm1, tdm_1_clk, TDM1); +lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ); +lpsc_clk(mcdma, sys_half_clk, MCDMA); +lpsc_clk(usb0, sys_half_clk, USB0); +lpsc_clk(usb1, sys_half_clk, USB1); +lpsc_clk(usbss, sys_half_clk, USBSS); +lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII); +lpsc_clk(imcop, sys_dsp_clk, IMCOP); +lpsc_clk(spare, sys_half_clk, SPARE); + +/* LCD needs a full power down to clear controller state */ +__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE); + + +/* Level 4 - leaf clocks for LPSC modules shared across drivers */ +static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec }; +static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec }; + +static struct clk_lookup clks[] = { + CLK(NULL, "pll_sys_clk", &pll_sys_clk), + CLK(NULL, "pll_eth_clk", &pll_eth_clk), + CLK(NULL, "pll_tdm_clk", &pll_tdm_clk), + CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk), + CLK(NULL, "sys_dsp_clk", &sys_dsp_clk), + CLK(NULL, "sys_ddr_clk", &sys_ddr_clk), + CLK(NULL, "sys_full_clk", &sys_full_clk), + CLK(NULL, "sys_lcd_clk", &sys_lcd_clk), + CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk), + CLK(NULL, "sys_tsc_clk", &sys_tsc_clk), + CLK(NULL, "sys_half_clk", &sys_half_clk), + CLK(NULL, "eth_5mhz_clk", ð_5mhz_clk), + CLK(NULL, "eth_50mhz_clk", ð_50mhz_clk), + CLK(NULL, "eth_125mhz_clk", ð_125mhz_clk), + CLK(NULL, "eth_250mhz_clk", ð_250mhz_clk), + CLK(NULL, "eth_25mhz_clk", ð_25mhz_clk), + CLK(NULL, "tdm_0_clk", &tdm_0_clk), + CLK(NULL, "tdm_extra_clk", &tdm_extra_clk), + CLK(NULL, "tdm_1_clk", &tdm_1_clk), + CLK(NULL, "clk_arm", &clk_arm), + CLK(NULL, "clk_gem", &clk_gem), + CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy), + CLK(NULL, "clk_tpcc", &clk_tpcc), + CLK(NULL, "clk_tptc0", &clk_tptc0), + CLK(NULL, "clk_tptc1", &clk_tptc1), + CLK(NULL, "clk_ram", &clk_ram), + CLK(NULL, "clk_mbx_lite", &clk_mbx_lite), + CLK("tnetv107x-fb.0", NULL, &clk_lcd), + CLK(NULL, "clk_ethss", &clk_ethss), + CLK(NULL, "aemif", &clk_aemif), + CLK(NULL, "clk_chipcfg", &clk_chipcfg), + CLK("tnetv107x-ts.0", NULL, &clk_tsc), + CLK(NULL, "clk_rom", &clk_rom), + CLK(NULL, "uart2", &clk_uart2), + CLK(NULL, "clk_pktsec", &clk_pktsec), + CLK("tnetv107x-rng.0", NULL, &clk_rng), + CLK("tnetv107x-pka.0", NULL, &clk_pka), + CLK(NULL, "clk_secctl", &clk_secctl), + CLK(NULL, "clk_keymgr", &clk_keymgr), + CLK("tnetv107x-keypad.0", NULL, &clk_keypad), + CLK(NULL, "clk_gpio", &clk_gpio), + CLK(NULL, "clk_mdio", &clk_mdio), + CLK("davinci_mmc.0", NULL, &clk_sdio0), + CLK(NULL, "uart0", &clk_uart0), + CLK(NULL, "uart1", &clk_uart1), + CLK(NULL, "timer0", &clk_timer0), + CLK(NULL, "timer1", &clk_timer1), + CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), + CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp), + CLK("ti-ssp.0", NULL, &clk_ssp), + CLK(NULL, "clk_tdm0", &clk_tdm0), + CLK(NULL, "clk_vlynq", &clk_vlynq), + CLK(NULL, "clk_mcdma", &clk_mcdma), + CLK(NULL, "clk_usb0", &clk_usb0), + CLK(NULL, "clk_tdm1", &clk_tdm1), + CLK(NULL, "clk_debugss", &clk_debugss), + CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii), + CLK(NULL, "clk_system", &clk_system), + CLK(NULL, "clk_imcop", &clk_imcop), + CLK(NULL, "clk_spare", &clk_spare), + CLK("davinci_mmc.1", NULL, &clk_sdio1), + CLK(NULL, "clk_usb1", &clk_usb1), + CLK(NULL, "clk_usbss", &clk_usbss), + CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst), + CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst), + CLK(NULL, NULL, NULL), +}; + +static const struct mux_config pins[] = { +#ifdef CONFIG_DAVINCI_MUX + MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false) + MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false) + MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false) + MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false) + MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false) +#endif +}; + +/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ +static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = { + /* fill in default priority 7 */ + [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7, + /* now override as needed, e.g. [xxx] = 5 */ +}; + +/* Contents of JTAG ID register used to identify exact cpu type */ +static struct davinci_id ids[] = { + { + .variant = 0x0, + .part_no = 0xb8a1, + .manufacturer = 0x017, + .cpu_id = DAVINCI_CPU_ID_TNETV107X, + .name = "tnetv107x rev1.0", + }, +}; + +static struct davinci_timer_instance timer_instance[2] = { + { + .base = TNETV107X_TIMER0_BASE, + .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_0_TINT34, + }, + { + .base = TNETV107X_TIMER1_BASE, + .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12, + .top_irq = IRQ_TNETV107X_TIMER_1_TINT34, + }, +}; + +static struct davinci_timer_info timer_info = { + .timers = timer_instance, + .clockevent_id = T0_BOT, + .clocksource_id = T0_TOP, +}; + +/* + * TNETV107X platforms do not use the static mappings from Davinci + * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses, + * and changing IO_PHYS would break away from existing Davinci SOCs. + * + * The primary impact of the current model is that IO_ADDRESS() is not to be + * used to map registers on TNETV107X. + * + * 1. The first chunk is for INTC: This needs to be mapped in via iotable + * because ioremap() does not seem to be operational at the time when + * irqs are initialized. Without this, consistent dma init bombs. + * + * 2. The second chunk maps in register areas that need to be populated into + * davinci_soc_info. Note that alignment restrictions come into play if + * low-level debug is enabled (see note in <mach/tnetv107x.h>). + */ +static struct map_desc io_desc[] = { + { /* INTC */ + .virtual = IO_VIRT, + .pfn = __phys_to_pfn(TNETV107X_INTC_BASE), + .length = SZ_16K, + .type = MT_DEVICE + }, + { /* Most of the rest */ + .virtual = TNETV107X_IO_VIRT, + .pfn = __phys_to_pfn(TNETV107X_IO_BASE), + .length = IO_SIZE - SZ_1M, + .type = MT_DEVICE + }, +}; + +static unsigned long clk_sspll_recalc(struct clk *clk) +{ + int pll; + unsigned long mult = 0, prediv = 1, postdiv = 1; + unsigned long ref = OSC_FREQ_ONCHIP, ret; + u32 tmp; + + if (WARN_ON(!clk->pll_data)) + return clk->rate; + + if (!clk_ctrl_regs) { + void __iomem *tmp; + + tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K); + + if (WARN(!tmp, "failed ioremap for clock control regs\n")) + return clk->parent ? clk->parent->rate : 0; + + for (pll = 0; pll < N_PLLS; pll++) + sspll_regs[pll] = tmp + sspll_regs_base[pll]; + + clk_ctrl_regs = tmp; + } + + pll = clk->pll_data->num; + + tmp = __raw_readl(&clk_ctrl_regs->pll_bypass); + if (!(tmp & bypass_mask[pll])) { + mult = __raw_readl(&sspll_regs[pll]->mult_factor); + prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1; + postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1; + } + + tmp = __raw_readl(clk->pll_data->base + PLLCTL); + if (tmp & PLLCTL_CLKMODE) + ref = pll_ext_freq[pll]; + + clk->pll_data->input_rate = ref; + + tmp = __raw_readl(clk->pll_data->base + PLLCTL); + if (!(tmp & PLLCTL_PLLEN)) + return ref; + + ret = ref; + if (mult) + ret += ((unsigned long long)ref * mult) / 256; + + ret /= (prediv * postdiv); + + return ret; +} + +static void tnetv107x_watchdog_reset(struct platform_device *pdev) +{ + struct wdt_regs __iomem *regs; + + regs = ioremap(pdev->resource[0].start, SZ_4K); + + /* disable watchdog */ + __raw_writel(0x7777, ®s->disable_lock); + __raw_writel(0xcccc, ®s->disable_lock); + __raw_writel(0xdddd, ®s->disable_lock); + __raw_writel(0, ®s->disable); + + /* program prescale */ + __raw_writel(0x5a5a, ®s->prescale_lock); + __raw_writel(0xa5a5, ®s->prescale_lock); + __raw_writel(0, ®s->prescale); + + /* program countdown */ + __raw_writel(0x6666, ®s->change_lock); + __raw_writel(0xbbbb, ®s->change_lock); + __raw_writel(1, ®s->change); + + /* enable watchdog */ + __raw_writel(0x7777, ®s->disable_lock); + __raw_writel(0xcccc, ®s->disable_lock); + __raw_writel(0xdddd, ®s->disable_lock); + __raw_writel(1, ®s->disable); + + /* kick */ + __raw_writel(0x5555, ®s->kick_lock); + __raw_writel(0xaaaa, ®s->kick_lock); + __raw_writel(1, ®s->kick); +} + +static struct davinci_soc_info tnetv107x_soc_info = { + .io_desc = io_desc, + .io_desc_num = ARRAY_SIZE(io_desc), + .ids = ids, + .ids_num = ARRAY_SIZE(ids), + .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018, + .cpu_clks = clks, + .psc_bases = psc_regs, + .psc_bases_num = ARRAY_SIZE(psc_regs), + .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150, + .pinmux_pins = pins, + .pinmux_pins_num = ARRAY_SIZE(pins), + .intc_type = DAVINCI_INTC_TYPE_CP_INTC, + .intc_base = TNETV107X_INTC_BASE, + .intc_irq_prios = irq_prios, + .intc_irq_num = TNETV107X_N_CP_INTC_IRQ, + .intc_host_map = intc_host_map, + .gpio_base = TNETV107X_GPIO_BASE, + .gpio_type = GPIO_TYPE_TNETV107X, + .gpio_num = TNETV107X_N_GPIO, + .timer_info = &timer_info, + .serial_dev = &tnetv107x_serial_device, + .reset = tnetv107x_watchdog_reset, + .reset_device = &tnetv107x_wdt_device, +}; + +void __init tnetv107x_init(void) +{ + davinci_common_init(&tnetv107x_soc_info); +} |