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authorPiyush Mehta <piyush.mehta@xilinx.com>2021-09-22 19:23:19 +0530
committerBartosz Golaszewski <brgl@bgdev.pl>2021-09-23 10:09:58 +0200
commit7687a5b0ee9358c96d85db58bad2a3aebee562b7 (patch)
tree317f202a3d0ac30f4df7df9dbcbdf316fdf56e23 /drivers/gpio/Kconfig
parentd7f4a65cdf4f671296fab1e5b331fd3f5ab776e5 (diff)
gpio: modepin: Add driver support for modepin GPIO controller
This patch adds driver support for the zynqmp modepin GPIO controller. GPIO modepin driver set and get the value and status of the PS_MODE pin, based on device-tree pin configuration. These four mode pins are configurable as input/output. The mode pin has a control register, which have lower four-bits [0:3] are configurable as input/output, next four-bits can be used for reading the data as input[4:7], and next setting the output pin state output[8:11]. By default value of mode pin register is 0. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Diffstat (limited to 'drivers/gpio/Kconfig')
-rw-r--r--drivers/gpio/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fae5141251e5..37a6f77c86fe 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -763,6 +763,18 @@ config GPIO_ZYNQ
help
Say yes here to support Xilinx Zynq GPIO controller.
+config GPIO_ZYNQMP_MODEPIN
+ tristate "ZynqMP ps-mode pin gpio configuration driver"
+ depends on ZYNQMP_FIRMWARE
+ default ZYNQMP_FIRMWARE
+ help
+ Say yes here to support the ZynqMP ps-mode pin gpio configuration
+ driver.
+
+ This ps-mode pin gpio driver is based on GPIO framework, PS_MODE
+ is 4-bits boot mode pins. It sets and gets the status of
+ the ps-mode pin. Every pin can be configured as input/output.
+
config GPIO_LOONGSON1
tristate "Loongson1 GPIO support"
depends on MACH_LOONGSON32