diff options
| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2023-12-19 12:35:44 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-01-15 18:35:39 -0500 |
| commit | e6f82bd44b401049367fcdee3328c7c720351419 (patch) | |
| tree | 8ebe912c554d541a37a9bc3f6f2060130bd51fe2 /drivers/gpu/drm/amd/display/dc/core/dc.c | |
| parent | 5950efe25ee02df4983864b3bc1f460ad5c8d862 (diff) | |
drm/amd/display: Rework DC Z10 restore
[Why]
The call currently does two things:
1. Exits DMCUB from idle optimization if it was in
2. Checks DMCUB scratch register to determine if we need to call
DMCUB to do deferred HW restore and then sends the command if it's
ready for it.
By doing (1) we prevent driver idle from being renotified in the cases
where driver had previously allowed DC level idle optimizations via
dc_allow_idle_optimizations since it thinks:
allow == dc->idle_optimizations_allowed
...and that the operation is a no-op.
We want driver idle to be resent at the next opprotunity to do so
for video playback cases.
[How]
Migrate all usecases of dc_z10_restore to only perform (2).
Add extra calls to dc_allow_idle_optimizations to handle (1) and also
keep SW state matching with when we requested enter/exit of DMCUB
idle optimizations.
Ensure cursor idle optimizations false always get called when IPS
is supported.
Further rework/redesign is needed to decide whether we need a separate
level of DM allow vs DC allow and when to attempt re-entry.
Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index aa7c02ba948e..af83ec23f3a0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1836,8 +1836,8 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c struct dc_state *old_state; bool subvp_prev_use = false; - dc_z10_restore(dc); dc_allow_idle_optimizations(dc, false); + dc_z10_restore(dc); for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; @@ -3376,6 +3376,9 @@ static void commit_planes_for_stream_fast(struct dc *dc, int i, j; struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; + if (dc->caps.ips_support) + dc_allow_idle_optimizations(dc, false); + dc_z10_restore(dc); top_pipe_to_program = resource_get_otg_master_for_stream( @@ -3503,6 +3506,9 @@ static void commit_planes_for_stream(struct dc *dc, // dc->current_state anymore, so we have to cache it before we apply // the new SubVP context subvp_prev_use = false; + if (dc->caps.ips_support) + dc_allow_idle_optimizations(dc, false); + dc_z10_restore(dc); if (update_type == UPDATE_TYPE_FULL) wait_for_outstanding_hw_updates(dc, context); @@ -4686,6 +4692,9 @@ void dc_set_power_state( case DC_ACPI_CM_POWER_STATE_D0: dc_state_construct(dc, dc->current_state); + if (dc->caps.ips_support) + dc_allow_idle_optimizations(dc, false); + dc_z10_restore(dc); dc->hwss.init_hw(dc); |