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authorYang Jihong <yangjihong1@huawei.com>2022-09-02 16:29:18 +0800
committerPeter Zijlstra <peterz@infradead.org>2022-09-06 11:33:00 +0200
commit6b959ba22d34ca793ffdb15b5715457c78e38b1a (patch)
treeee0db65396154d2268b05e09c443a66b355ce7e6 /drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
parentf2aeea57504cbbc58da3c59b939fc16150087648 (diff)
perf/core: Fix reentry problem in perf_output_read_group()
perf_output_read_group may respond to IPI request of other cores and invoke __perf_install_in_context function. As a result, hwc configuration is modified. causing inconsistency and unexpected consequences. Interrupts are not disabled when perf_output_read_group reads PMU counter. In this case, IPI request may be received from other cores. As a result, PMU configuration is modified and an error occurs when reading PMU counter: CPU0 CPU1 __se_sys_perf_event_open perf_install_in_context perf_output_read_group smp_call_function_single for_each_sibling_event(sub, leader) { generic_exec_single if ((sub != event) && remote_function (sub->state == PERF_EVENT_STATE_ACTIVE)) | <enter IPI handler: __perf_install_in_context> <----RAISE IPI-----+ __perf_install_in_context ctx_resched event_sched_out armpmu_del ... hwc->idx = -1; // event->hwc.idx is set to -1 ... <exit IPI> sub->pmu->read(sub); armpmu_read armv8pmu_read_counter armv8pmu_read_hw_counter int idx = event->hw.idx; // idx = -1 u64 val = armv8pmu_read_evcntr(idx); u32 counter = ARMV8_IDX_TO_COUNTER(idx); // invalid counter = 30 read_pmevcntrn(counter) // undefined instruction Signed-off-by: Yang Jihong <yangjihong1@huawei.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220902082918.179248-1-yangjihong1@huawei.com
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c')
0 files changed, 0 insertions, 0 deletions