diff options
| author | Eric Huang <JinHuiEric.Huang@amd.com> | 2016-04-12 14:57:23 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:29:47 -0400 |
| commit | 5632708f4452eb9afb985b245b98dac9a5feeac2 (patch) | |
| tree | cd46c6074e2869548d735b77f17fe0d1be3953b6 /drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | |
| parent | 51224389543ebd7307e09f0f46e5c5cac417d940 (diff) | |
drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)
Allows you to force multiple levels rather than just one via the new
sysfs interrface.
v2: squash in:
drm/amd/powerplay: ensure clock level set by user is valid.
From Rex.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index dc836d3e92b5..f8d49f1b44f5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -5113,7 +5113,7 @@ static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t siz } static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, int level) + enum pp_clock_type type, uint32_t mask) { struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); @@ -5125,20 +5125,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr, if (!data->sclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); break; + case PP_MCLK: if (!data->mclk_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_MCLKDPM_SetEnabledMask, - (1 << level)); + data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); break; + case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; + uint32_t level = 0; + + while (tmp >>= 1) + level++; + if (!data->pcie_dpm_key_disabled) smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_PCIeDPM_ForceLevel, - (1 << level)); + level); break; + } default: break; } |