diff options
author | Rex Zhu <Rex.Zhu@amd.com> | 2016-01-06 16:38:48 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-01-08 15:39:22 -0500 |
commit | 75ac63dbc3b0f4d3af67a5857790749e954e2ba6 (patch) | |
tree | 20bd5ccb1fb294cbc3034422e517ebe708c27c82 /drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | |
parent | 53d3de140b668d37e1ebfe01c94ec36d369edcbf (diff) |
drm/amd/powerplay: fix Smatch static checker warnings with indenting (v2)
v2: AGD: rebase on upstream
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c')
-rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 51 |
1 files changed, 26 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index 94f404c121b7..6dba5bf73e52 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -941,8 +941,9 @@ static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr, memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table)); kfree(table); - return 0; + return 0; } + static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr, phm_ppt_v1_clock_voltage_dependency_table *dep_table) { @@ -1112,7 +1113,7 @@ static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr) fiji_trim_voltage_table_to_fit_state_table(hwmgr, SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table))); - return 0; + return 0; } static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) @@ -1158,7 +1159,7 @@ static int fiji_program_static_screen_threshold_parameters( CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, data->static_screen_threshold); - return 0; + return 0; } /** @@ -1295,7 +1296,7 @@ static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - return error ? -1 : 0; + return error ? -1 : 0; } /* Copy one arb setting to another and then switch the active set. @@ -1339,12 +1340,12 @@ static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, return -EINVAL; } - mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); - mc_cg_config |= 0x0000000F; - cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); - PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); + mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); + mc_cg_config |= 0x0000000F; + cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); + PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); - return 0; + return 0; } /** @@ -1927,17 +1928,17 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, threshold = clock * data->fast_watermark_threshold / 100; - /* - * TODO: get minimum clocks from dal configaration - * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); - */ - /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ + /* + * TODO: get minimum clocks from dal configaration + * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks); + */ + /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */ - /* get level->DeepSleepDivId - if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) - { - level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); - } */ + /* get level->DeepSleepDivId + if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) + { + level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); + } */ /* Default to slow, highest DPM level will be * set to PPSMC_DISPLAY_WATERMARK_LOW later. @@ -2756,7 +2757,7 @@ static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) SclkFrequency) / 100); if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 && - fiji_clock_stretcher_lookup_table[stretch_amount2][1] > + fiji_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; @@ -3172,9 +3173,9 @@ static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) /* enable SCLK dpm */ if(!data->sclk_dpm_key_disabled) PP_ASSERT_WITH_CODE( - (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), - "Failed to enable SCLK DPM during DPM Start Function!", - return -1); + (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)), + "Failed to enable SCLK DPM during DPM Start Function!", + return -1); /* enable MCLK dpm */ if(0 == data->mclk_dpm_key_disabled) { @@ -3320,7 +3321,7 @@ static int fiji_start_dpm(struct pp_hwmgr *hwmgr) return -1); } - return 0; + return 0; } static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr, @@ -3378,7 +3379,7 @@ static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) { - return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); + return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); } static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr) |