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| author | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-01-27 17:48:30 +0100 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-01-27 17:48:30 +0100 |
| commit | 701ddf0bbfc761b8bdc974ce9c4e05f9833683e3 (patch) | |
| tree | 1009975aacf14d36cc280dfeef1a9a816fa16ef8 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 0dcf2572710d68c305e58946c435ddf67ea16bf3 (diff) | |
| parent | ccfb9299a0b63da4fde607c822e1470472a46177 (diff) | |
Merge tag 'spi-nor/for-5.6' into mtd/next
SPI NOR core changes:
- Add support for TB selection using SR bit 6,
- Add support for few flashes.
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 809bff955b5a..75ae6f495161 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4291,8 +4291,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state, &crtc_state->wm.skl.optimal.planes[plane_id]; if (plane_id == PLANE_CURSOR) { - if (WARN_ON(wm->wm[level].min_ddb_alloc > - total[PLANE_CURSOR])) { + if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) { + WARN_ON(wm->wm[level].min_ddb_alloc != U16_MAX); blocks = U32_MAX; break; } |