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authorYong Wu <yong.wu@mediatek.com>2023-04-11 17:31:33 +0800
committerJoerg Roedel <jroedel@suse.de>2023-04-13 11:59:24 +0200
commitae6693453ac665015929d2b05104d5a2951375af (patch)
treedb3d8813799c5210ee1cb354e2f19e2069b60638 /drivers/iommu/mtk_iommu.c
parent559549b1f250a1b5bec3c6c3a9354deead371bde (diff)
iommu/mediatek: Improve comment for the current region/bank
No functional change. Just add more comment about the current region/bank in the code. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230411093144.2690-4-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/mtk_iommu.c')
-rw-r--r--drivers/iommu/mtk_iommu.c31
1 files changed, 26 insertions, 5 deletions
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 6a00ce208dc2..efc247a3989e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -197,12 +197,33 @@ struct mtk_iommu_plat_data {
char *pericfg_comp_str;
struct list_head *hw_list;
- unsigned int iova_region_nr;
- const struct mtk_iommu_iova_region *iova_region;
- u8 banks_num;
- bool banks_enable[MTK_IOMMU_BANK_MAX];
- unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
+ /*
+ * The IOMMU HW may support 16GB iova. In order to balance the IOVA ranges,
+ * different masters will be put in different iova ranges, for example vcodec
+ * is in 4G-8G and cam is in 8G-12G. Meanwhile, some masters may have the
+ * special IOVA range requirement, like CCU can only support the address
+ * 0x40000000-0x44000000.
+ * Here list the iova ranges this SoC supports and which larbs/ports are in
+ * which region.
+ *
+ * 16GB iova all use one pgtable, but each a region is a iommu group.
+ */
+ struct {
+ unsigned int iova_region_nr;
+ const struct mtk_iommu_iova_region *iova_region;
+ };
+
+ /*
+ * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
+ * Here list how many banks this SoC supports/enables and which ports are in which bank.
+ */
+ struct {
+ u8 banks_num;
+ bool banks_enable[MTK_IOMMU_BANK_MAX];
+ unsigned int banks_portmsk[MTK_IOMMU_BANK_MAX];
+ };
+
unsigned char larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
};