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| author | Dan Williams <dan.j.williams@intel.com> | 2023-04-03 16:01:32 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-04-04 15:34:34 -0700 |
| commit | 24b18197184ac39bb8566fb82c0bf788bcd0d45b (patch) | |
| tree | 6cd1946fc5af84f051cbb44d10bd7ef82c6f7fac /drivers/net/ethernet/intel/i40e/i40e_main.c | |
| parent | 52cc48ad2a76a5fe82d239044d67944bbb928de6 (diff) | |
cxl/hdm: Extend DVSEC range register emulation for region enumeration
One motivation for mapping range registers to decoder objects is
to use those settings for region autodiscovery.
The need to map a region for devices programmed to use range registers
is especially urgent now that the kernel no longer routes "Soft
Reserved" ranges in the memory map to device-dax by default. The CXL
memory range loses all access mechanisms.
Complete the implementation by marking the DPA reservation and setting
the endpoint-decoder state to signal autodiscovery. Note that the
default settings of ways=1 and granularity=4096 set in cxl_decode_init()
do not need to be updated.
Fixes: 09d09e04d2fc ("cxl/dax: Create dax devices for CXL RAM regions")
Tested-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Gregory Price <gregory.price@memverge.com>
Link: https://lore.kernel.org/r/168012575521.221280.14177293493678527326.stgit@dwillia2-xfh.jf.intel.com
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/i40e/i40e_main.c')
0 files changed, 0 insertions, 0 deletions