diff options
| author | Balsam CHIHI <bchihi@baylibre.com> | 2022-10-21 10:47:08 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-11-07 15:42:53 +0100 |
| commit | cdb6f424e93cec2c9d19d59c56ee448d63cb0146 (patch) | |
| tree | 13fcb7aaddc09111d73f736c43d1c481cdd25348 /drivers/pinctrl/mediatek | |
| parent | d459a2352211bf01c532def4f85eb8c2545c610a (diff) | |
pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback
On MT8365, the SET/CLR of the mode is broken and some pin modes won't
be set correctly.
Use the mt8365_set_clr_mode() callback to fix the issue.
Co-developed-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mediatek')
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 57f37a294063..42b48136ab77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,6 +416,23 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -431,6 +448,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode = mt8365_set_clr_mode, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000, |