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authorJianqun Xu <jay.xu@rock-chips.com>2021-08-16 09:21:11 +0800
committerLinus Walleij <linus.walleij@linaro.org>2021-08-17 01:01:49 +0200
commitff96a8c21cdbf4a36fbad341af3a41db44bbf878 (patch)
treefee7f997dfe059658b195d2e3f86b82e0138edbe /drivers/pinctrl
parent936ee2675eee1faca0dcdfa79165c7990422e0fc (diff)
gpio/rockchip: use struct rockchip_gpio_regs for gpio controller
Store register offsets in the struct rockchip_gpio_regs, this patch prepare for the driver update for new gpio controller. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210816012111.1119125-1-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 4aa3d2f1fa67..1b774b6bbc3e 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -33,6 +33,42 @@ enum rockchip_pinctrl_type {
};
/**
+ * struct rockchip_gpio_regs
+ * @port_dr: data register
+ * @port_ddr: data direction register
+ * @int_en: interrupt enable
+ * @int_mask: interrupt mask
+ * @int_type: interrupt trigger type, such as high, low, edge trriger type.
+ * @int_polarity: interrupt polarity enable register
+ * @int_bothedge: interrupt bothedge enable register
+ * @int_status: interrupt status register
+ * @int_rawstatus: int_status = int_rawstatus & int_mask
+ * @debounce: enable debounce for interrupt signal
+ * @dbclk_div_en: enable divider for debounce clock
+ * @dbclk_div_con: setting for divider of debounce clock
+ * @port_eoi: end of interrupt of the port
+ * @ext_port: port data from external
+ * @version_id: controller version register
+ */
+struct rockchip_gpio_regs {
+ u32 port_dr;
+ u32 port_ddr;
+ u32 int_en;
+ u32 int_mask;
+ u32 int_type;
+ u32 int_polarity;
+ u32 int_bothedge;
+ u32 int_status;
+ u32 int_rawstatus;
+ u32 debounce;
+ u32 dbclk_div_en;
+ u32 dbclk_div_con;
+ u32 port_eoi;
+ u32 ext_port;
+ u32 version_id;
+};
+
+/**
* struct rockchip_iomux
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -126,6 +162,8 @@ struct rockchip_pin_bank {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range grange;
raw_spinlock_t slock;
+ const struct rockchip_gpio_regs *gpio_regs;
+ u32 gpio_type;
u32 toggle_edge_mode;
u32 recalced_mask;
u32 route_mask;