diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-07 16:12:17 +0100 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-08-15 22:30:01 +0100 |
| commit | 48a1319164d9339ad50a25085cad6b879fef9fbe (patch) | |
| tree | 84589864d17e7a607ce8e0938bd62205918e6d7a /drivers/staging/iio | |
| parent | e48668a38bf420c660b07851985e6922fcf4b194 (diff) | |
staging: iio: meter: ade7854: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org
Diffstat (limited to 'drivers/staging/iio')
| -rw-r--r-- | drivers/staging/iio/meter/ade7854.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/staging/iio/meter/ade7854.h b/drivers/staging/iio/meter/ade7854.h index a51e6e3183d3..7a49f8f1016f 100644 --- a/drivers/staging/iio/meter/ade7854.h +++ b/drivers/staging/iio/meter/ade7854.h @@ -162,7 +162,7 @@ struct ade7854_state { int bits); int irq; struct mutex buf_lock; - u8 tx[ADE7854_MAX_TX] ____cacheline_aligned; + u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN); u8 rx[ADE7854_MAX_RX]; }; |