diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2020-11-23 10:36:37 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-11-26 09:12:18 +0100 |
| commit | 1de16e38f1fdbfd9d842a06919098813ed93abf7 (patch) | |
| tree | 02363bd63d1bfd504c09923d7e483438d27a2082 /drivers/staging/mt7621-pci | |
| parent | 108b2f2a9724548ffa64274731034d9723665c71 (diff) | |
staging: mt7621-pci: remove 'RALINK_PCI_IMBASEBAR0_ADDR' register
Register 'RALINK_PCI_IMBASEBAR0_ADDR' contains internal memory
base address for BAR0. We don't really need to write anything
there at all since its initial value contains always a desired
valid value. Hence remove register definition and related code.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20201123093637.8300-8-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-pci')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index 4cdaccbcc97c..c3532bc138fb 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -68,7 +68,6 @@ #define MT7621_NEXT_PORT 0x1000 #define RALINK_PCI_BAR0SETUP_ADDR 0x0010 -#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018 #define RALINK_PCI_ID 0x0030 #define RALINK_PCI_CLASS 0x0034 #define RALINK_PCI_SUBID 0x0038 @@ -83,7 +82,6 @@ #define PCIE_PORT_CLK_EN(x) BIT(24 + (x)) #define PCIE_PORT_LINKUP BIT(0) -#define MEMORY_BASE 0x0 #define PERST_MODE_MASK GENMASK(11, 10) #define PERST_MODE_GPIO BIT(10) #define PERST_DELAY_MS 100 @@ -543,8 +541,6 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) /* map 2G DDR region */ pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, offset + RALINK_PCI_BAR0SETUP_ADDR); - pcie_write(pcie, MEMORY_BASE, - offset + RALINK_PCI_IMBASEBAR0_ADDR); /* configure class code and revision ID */ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, |