diff options
| author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-04-26 16:06:18 +0200 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2009-05-05 10:04:16 +1000 |
| commit | 6f6fb48026d811d763f51a458e97e9d1a5133642 (patch) | |
| tree | 7a21994ae1ce7315342f16c188397f646b06c7b7 /drivers/staging/rt2870/rt28xx.h | |
| parent | c0da96eb83db8409a55059e43308bde6ed347729 (diff) | |
Staging: rt2870: prepare for rt{28,30}70/*.[ch] merge
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/rt2870/rt28xx.h')
| -rw-r--r-- | drivers/staging/rt2870/rt28xx.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/staging/rt2870/rt28xx.h b/drivers/staging/rt2870/rt28xx.h index 1a8a641f2d0f..f03b0f5deefb 100644 --- a/drivers/staging/rt2870/rt28xx.h +++ b/drivers/staging/rt2870/rt28xx.h @@ -47,6 +47,15 @@ #define PCI_EECTRL 0x0004 #define PCI_MCUCTRL 0x0008 +#ifdef RT30xx +#define OPT_14 0x114 + +typedef int NTSTATUS; +#define RETRY_LIMIT 10 +#define STATUS_SUCCESS 0x00 +#define STATUS_UNSUCCESSFUL 0x01 +#endif + // // SCH/DMA registers - base address 0x0200 // @@ -282,6 +291,36 @@ typedef union _USB_DMA_CFG_STRUC { #define PBF_DBG 0x043c #define PBF_CAP_CTRL 0x0440 +#ifdef RT30xx +// eFuse registers +#define EFUSE_CTRL 0x0580 +#define EFUSE_DATA0 0x0590 +#define EFUSE_DATA1 0x0594 +#define EFUSE_DATA2 0x0598 +#define EFUSE_DATA3 0x059c +#define EFUSE_USAGE_MAP_START 0x2d0 +#define EFUSE_USAGE_MAP_END 0x2fc +#define EFUSE_TAG 0x2fe +#define EFUSE_USAGE_MAP_SIZE 45 + +typedef union _EFUSE_CTRL_STRUC { + struct { + UINT32 EFSROM_AOUT:6; + UINT32 EFSROM_MODE:2; + UINT32 EFSROM_LDO_OFF_TIME:6; + UINT32 EFSROM_LDO_ON_TIME:2; + UINT32 EFSROM_AIN:10; + UINT32 RESERVED:4; + UINT32 EFSROM_KICK:1; + UINT32 SEL_EFUSE:1; + } field; + UINT32 word; +} EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC; + +#define LDO_CFG0 0x05d4 +#define GPIO_SWITCH 0x05dc +#endif /* RT30xx */ + // // 4 MAC registers // @@ -1093,6 +1132,9 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry #define BBP_R22 22 #define BBP_R24 24 #define BBP_R25 25 +#ifdef RT30xx +#define BBP_R31 31 +#endif #define BBP_R49 49 //TSSI #define BBP_R50 50 #define BBP_R51 51 @@ -1110,6 +1152,10 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry #define BBP_R73 73 #define BBP_R75 75 #define BBP_R77 77 +#ifdef RT30xx +#define BBP_R79 79 +#define BBP_R80 80 +#endif #define BBP_R81 81 #define BBP_R82 82 #define BBP_R83 83 @@ -1131,6 +1177,9 @@ typedef struct _HW_WCID_ENTRY { // 8-byte per entry #define BBP_R121 121 #define BBP_R122 122 #define BBP_R123 123 +#ifdef RT30xx +#define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control +#endif // RT30xx // #define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db @@ -1519,7 +1568,15 @@ typedef union _EEPROM_NIC_CINFIG2_STRUC { USHORT EnableWPSPBC:1; // WPS PBC Control bit USHORT BW40MAvailForG:1; // 0:enable, 1:disable USHORT BW40MAvailForA:1; // 0:enable, 1:disable +#ifndef RT30xx USHORT Rsv2:6; // must be 0 +#endif +#ifdef RT30xx + USHORT Rsv1:1; // must be 0 + USHORT AntDiversity:1; // Antenna diversity + USHORT Rsv2:3; // must be 0 + USHORT DACTestBit:1; // control if driver should patch the DAC issue +#endif } field; USHORT word; } EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC; |