DSS2 Warning fixes This patch ,makes necessary changes in display related files for reducing number of warnings observed while building the kernel

Signed-off-by: Mayuresh Janorkar <mayur@ti.com>

7 files changed, 4228 insertions, 4222 deletions

diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index 8f28019535bb..1f1ef5eef8d2 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -252,12 +252,12 @@ static int taal_set_addr_mode(u8 rotate, bool mirror)
 
 static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)
 {
-	int r;
+	int r = 0;
+#if 0 //sv no need of column addr
 	u16 x1 = x;
 	u16 x2 = x + w - 1;
 	u16 y1 = y;
 	u16 y2 = y + h - 1;
-#if 0 //sv no need of column addr
 	u8 buf[5];
 	buf[0] = DCS_COLUMN_ADDR;
 	buf[1] = (x1 >> 8) & 0xff;
@@ -625,7 +625,7 @@ static void taal_remove(struct omap_dss_device *dssdev)
 static int taal_enable(struct omap_dss_device *dssdev)
 {
 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);
-	u8 id1, id2, id3;
+	u8 id1 = 0, id2 = 0, id3 = 0;
 	int r;
 
 	DBG("enable\n");
diff --git a/drivers/video/omap2/displays/panel-taal2.c b/drivers/video/omap2/displays/panel-taal2.c
index c840c2b2f84d..a710f12515aa 100644
--- a/drivers/video/omap2/displays/panel-taal2.c
+++ b/drivers/video/omap2/displays/panel-taal2.c
@@ -252,12 +252,12 @@ static int taal_set_addr_mode(u8 rotate, bool mirror)
 

 static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h)

 {

-	int r;

+	int r = 0;

+#if 0 //sv no need of column addr

 	u16 x1 = x;

 	u16 x2 = x + w - 1;

 	u16 y1 = y;

 	u16 y2 = y + h - 1;

-#if 0 //sv no need of column addr

 	u8 buf[5];

 	buf[0] = DCS_COLUMN_ADDR;

 	buf[1] = (x1 >> 8) & 0xff;

@@ -627,7 +627,7 @@ static void taal_remove(struct omap_dss_device *dssdev)
 static int taal_enable(struct omap_dss_device *dssdev)

 {

 	struct taal_data *td = dev_get_drvdata(&dssdev->dev);

-	u8 id1, id2, id3;

+	u8 id1 = 0, id2 = 0, id3 = 0;

 	int r;

 

 	DBG("enable\n");

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 49d12f26ef05..bddf909947e2 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -53,7 +53,7 @@
 		#define DISPC_BASE              0x58001000
 #endif
 
-#define DISPC_SZ_REGS			SZ_1K
+#define DISPC_SZ_REGS			2000//SZ_1K
 
 struct dispc_reg { u16 idx; };
 
@@ -386,6 +386,7 @@ void dispc_save_context(void)
 	SR(TIMING_V);
 	SR(POL_FREQ);
 	SR(DIVISOR);
+
 	SR(GLOBAL_ALPHA);
 	SR(SIZE_DIG);
 	SR(SIZE_LCD);
@@ -706,14 +707,15 @@ void dispc_go(enum omap_channel channel)
 		bit = 1; /* DIGITALENABLE */
 
 #ifdef CONFIG_ARCH_OMAP4
-	if (channel == OMAP_DSS_CHANNEL_LCD2)
+	if (channel == OMAP_DSS_CHANNEL_LCD2) {
 		if (REG_GET(DISPC_CONTROL2, bit, bit) == 0)
 			goto end;
-	else
+	} else
 #endif
+	{
 		if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
                         goto end;
-
+	}
 #ifdef CONFIG_ARCH_OMAP4
 	if (channel != OMAP_DSS_CHANNEL_DIGIT)
 #else
@@ -1074,7 +1076,6 @@ static void _dispc_set_plane_ba_uv0(enum omap_plane plane, u32 paddr)
 				DISPC_VID_BA_UV0(2) /* VID 3 pipeline*/
 	};
 
-	u32 val = 0;
 	BUG_ON(plane == OMAP_DSS_GFX);
 
 	dispc_write_reg(ba_uv0_reg[plane - 1], paddr);
@@ -1277,7 +1278,7 @@ static void _dispc_set_channel_out(enum omap_plane plane,
 	int shift;
 	u32 val;
 #ifdef CONFIG_ARCH_OMAP4
-	int chan, chan2;
+	int chan = 0, chan2 = 0;
 #endif
 
 	switch (plane) {
@@ -1841,7 +1842,8 @@ static void _dispc_set_scaling_uv(enum omap_plane plane,
 		if (check_h)
 			hv2_coef_mod = NULL;
 		else
-			hv2_coef_mod = coef_hv2_greater;
+		/* TODO: Need to check this */
+			*hv2_coef_mod = *coef_hv2_greater;
 	} else {
 		v2_coef = coef_v2_greater;
 		hv2_coef = coef_hv2_greater;
@@ -1980,6 +1982,7 @@ static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
 #endif
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static s32 pixinc(int pixels, u8 ps)
 {
 	if (pixels == 1)
@@ -1991,6 +1994,7 @@ static s32 pixinc(int pixels, u8 ps)
 	else
 		BUG();
 }
+#endif
 
 static void calc_tiler_row_rotation(u8 rotation,
 		u16 width, u16 height,
@@ -2055,7 +2059,7 @@ static void calc_tiler_row_rotation(u8 rotation,
 */
 	return;
 }
-
+#ifndef CONFIG_ARCH_OMAP4
 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
 		u16 screen_width,
 		u16 width, u16 height,
@@ -2299,6 +2303,7 @@ static void calc_dma_rotation_offset(u8 rotation, bool mirror,
 		BUG();
 	}
 }
+#endif
 
 static unsigned long calc_fclk_five_taps(enum omap_channel channel,
 		u16 width, u16 height, u16 out_width, u16 out_height,
@@ -2399,9 +2404,9 @@ static int _dispc_setup_plane(enum omap_plane plane,
 
 	u8 orientation = 0;
 	struct dmmViewOrientT orient;
-	unsigned long r, mir_x, mir_y;
+	unsigned long mir_x = 0, mir_y = 0;
 	unsigned long tiler_width, tiler_height;
-	void __iomem *reg = NULL;
+//	void __iomem *reg = NULL;
 
 	if (paddr == 0)
 		return -EINVAL;
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index 1af6444d79e8..6dbbbfd654a8 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -314,7 +314,6 @@ void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 		u32 fifo_size, enum omap_burst_size *burst_size,
 		u32 *fifo_low, u32 *fifo_high)
 {
-	unsigned low, high, size;
 	unsigned burst_size_bytes;
 
 #if 0
@@ -468,8 +467,8 @@ void dss_init_device(struct platform_device *pdev,
 #endif
 #ifdef CONFIG_OMAP2_DSS_DSI
 	case OMAP_DISPLAY_TYPE_DSI:
-		if(dssdev->name == "lcd")
-		r = dsi_init_display(dssdev);
+		if(!strcmp(dssdev->name, "lcd"))
+			r = dsi_init_display(dssdev);
 		else
 			r = dsi2_init_display(dssdev);
 		break;
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index d8a0926ba72a..361ed37a601a 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -618,7 +618,7 @@ void dsi_irq_handler(void)
 	dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 }
 
-
+#ifndef CONFIG_ARCH_OMAP4
 static void _dsi_initialize_irq(void)
 {
 	u32 l;
@@ -656,6 +656,7 @@ static void _dsi_initialize_irq(void)
 	dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
 			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
 }
+#endif
 
 static u32 dsi_get_errors(void)
 {
@@ -710,7 +711,7 @@ static inline void dsi_enable_pll_clock(bool enable)
 			DSSERR("cannot lock PLL when enabling clocks\n");
 	}
 }
-
+#ifndef CONFIG_ARCH_OMAP4
 #ifdef DEBUG
 static void _dsi_print_reset_status(void)
 {
@@ -742,7 +743,7 @@ static void _dsi_print_reset_status(void)
 #else
 #define _dsi_print_reset_status()
 #endif
-
+#endif
 static inline int dsi_if_enable(bool enable)
 {
 	DSSDBG("dsi_if_enable(%d)\n", enable);
@@ -758,6 +759,7 @@ static inline int dsi_if_enable(bool enable)
 	return 0;
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static unsigned long dsi_fclk_rate(void)
 {
 	unsigned long r;
@@ -803,7 +805,7 @@ static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
 
 	return 0;
 }
-
+#endif
 
 enum dsi_pll_power_state {
 	DSI_PLL_POWER_OFF	= 0x0,
@@ -963,6 +965,7 @@ found:
 	return 0;
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static int dsi_pll_calc_ddrfreq(unsigned long clk_freq,
 		struct dsi_clock_info *cinfo)
 {
@@ -1064,11 +1067,11 @@ found:
 
 	return 0;
 }
+#endif
 
 int dsi_pll_program(struct dsi_clock_info *cinfo)
 {
 	int r = 0;
-	u32 l;
 
 	DSSDBG("dsi_pll_program\n");
 
@@ -1413,8 +1416,8 @@ enum dsi_complexio_power_state {
 
 static int dsi_complexio_power(enum dsi_complexio_power_state state)
 {
-	int t = 0;
 #if 0 //sv3
+	int t = 0;
 	/* PWR_CMD */
 	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
 
@@ -1439,6 +1442,7 @@ static int dsi_complexio_power(enum dsi_complexio_power_state state)
 	return 0;
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static void dsi_complexio_config(struct omap_dss_device *dssdev)
 {
 	u32 r;
@@ -1477,6 +1481,7 @@ static void dsi_complexio_config(struct omap_dss_device *dssdev)
 	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
 	*/
 }
+#endif
 
 static inline unsigned ns2ddr(unsigned ns)
 {
@@ -1489,6 +1494,7 @@ static inline unsigned ddr2ns(unsigned ddr)
 	return ddr * 1000 * 1000 / (dsi.ddr_clk / 1000);
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static void dsi_complexio_timings(void)
 {
 	u32 r;
@@ -1559,11 +1565,10 @@ static void dsi_complexio_timings(void)
 	dsi_write_reg(DSI_DSIPHY_CFG2, 0xB8000007); //sv3
 }
 
-
 static int dsi_complexio_init(struct omap_dss_device *dssdev)
 {
 	int r = 0,t = 0;
-
+	u32 val;
 	DSSDBG("dsi_complexio_init\n");
 #if 0 //sv3
 	/* CIO_CLK_ICG, enable L3 clk to CIO */
@@ -1648,7 +1653,6 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
 
 
 	dsi_complexio_config(dssdev);
-	u32 val = 0;
 
     	//To do a read of any of the DSIPHY to have a dummy access
 	dsi_read_reg(DSI_DSIPHY_CFG8); 
@@ -1686,9 +1690,9 @@ static int dsi_complexio_init(struct omap_dss_device *dssdev)
 
 #endif
 	DSSDBG("CIO init done\n");
-err:
 	return r;
 }
+#endif
 
 static void dsi_complexio_uninit(void)
 {
@@ -1717,7 +1721,7 @@ static int _dsi_reset(void)
 	return _dsi_wait_reset();
 }
 
-
+#ifndef CONFIG_ARCH_OMAP4
 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
 		enum fifo_size size3, enum fifo_size size4)
 {
@@ -1777,6 +1781,7 @@ static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
 
 	dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
 }
+#endif
 
 static int dsi_force_tx_stop_mode_io(void)
 {
@@ -1830,6 +1835,7 @@ static int dsi_vc_enable(int channel, bool enable)
 	return 0;
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static void dsi_vc_initial_config(int channel)
 {
 	u32 r;
@@ -1857,6 +1863,7 @@ static void dsi_vc_initial_config(int channel)
 	dsi_write_reg(DSI_VC_CTRL(channel), r);
 	dsi.vc[channel].mode = DSI_VC_MODE_L4;
 }
+#endif
 
 static void dsi_vc_config_l4(int channel)
 {
@@ -1877,6 +1884,7 @@ static void dsi_vc_config_l4(int channel)
 	dsi.vc[channel].mode = DSI_VC_MODE_L4;
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static void dsi_vc_config_vp(int channel)
 {
 	if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
@@ -1895,7 +1903,7 @@ static void dsi_vc_config_vp(int channel)
 
 	dsi.vc[channel].mode = DSI_VC_MODE_VP;
 }
-
+#endif
 
 static void dsi_vc_enable_hs(int channel, bool enable)
 {
@@ -2276,8 +2284,7 @@ EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
 int dsi_vc_dcs_write(int channel, u8 *data, int len)
 {
 	int r =0;
-	u32 val;
-	
+
 	r = dsi_vc_dcs_write_nosync(channel, data, len);
 #if 0
 	val = dsi_read_reg(DSI_VC_IRQSTATUS(channel));
@@ -2397,7 +2404,7 @@ int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
 }
 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
 
-
+#ifndef CONFIG_ARCH_OMAP4
 static int dsi_set_lp_rx_timeout(int ns, int x4, int x16)
 {
 	u32 r;
@@ -2526,6 +2533,7 @@ static int dsi_set_hs_tx_timeout(int ns, int x4, int x16)
 
 	return 0;
 }
+
 static int dsi_proto_config(struct omap_dss_device *dssdev)
 {
 	u32 r;
@@ -2674,7 +2682,7 @@ static void dsi_proto_timings(struct omap_dss_device *dssdev)
 	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
 			enter_hs_mode_lat, exit_hs_mode_lat);
 }
-
+#endif
 
 #define DSI_DECL_VARS \
 	int __dsi_cb = 0; u32 __dsi_cv = 0;
@@ -2963,11 +2971,10 @@ static void dsi_start_auto_update(struct omap_dss_device *dssdev)
 
 static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
 {
-	dssdev->driver->enable_te(dssdev, enable);
 	int r;
-	printk(KERN_INFO "\n dsi_set_te ");
+
+	dssdev->driver->enable_te(dssdev, enable);
 	r = dssdev->driver->enable_te(dssdev, enable);
-	printk(KERN_INFO "\n dsi_set_te DONE ");
 	/* XXX for some reason, DSI TE breaks if we don't wait here.
 	 * Panel bug? Needs more studying */
 	msleep(100);
@@ -2976,8 +2983,6 @@ static int dsi_set_te(struct omap_dss_device *dssdev, bool enable)
 
 static void dsi_handle_framedone(void)
 {
-	int r;
-	const int channel = 0;
 	bool use_te_trigger;
 
 	use_te_trigger = dsi.te_enabled && !dsi.use_ext_te;
@@ -3196,13 +3201,12 @@ static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
 
 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 {
-	struct dsi_clock_info cinfo;
 	int r;
-
-	u32 val,l;
-	u32 control_core_base;
 #if 0 //comment everything
 #if 0 //sv3
+	struct dsi_clock_info cinfo;
+	u32 val,l;
+	u32 control_core_base;
 	val = dsi_read_reg(DSI_CLK_CTRL);
 	printk(KERN_INFO "\n DSI_CLK_CONTROL = 0x%X (bit 14 should be 1 ", val);
 	val = val |(1<<14);
@@ -3402,12 +3406,14 @@ static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
 	return 0;
 	// MJ
 err3:
-//	dsi_if_enable(0);
+#if 0
+	dsi_if_enable(0);
 err2:
-//	dsi_complexio_uninit();
+	dsi_complexio_uninit();
 err1:
-//	dsi_pll_uninit();
+	dsi_pll_uninit();
 err0:
+#endif
 	return r;
 }
 
@@ -3420,6 +3426,7 @@ static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
 	dsi_pll_uninit();
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static int dsi_core_init(void)
 {
 	
@@ -3436,6 +3443,7 @@ static int dsi_core_init(void)
 
 	return 0;
 }
+#endif
 
 #define GPIO_OE		0x134
 #define GPIO_DATAOUT	0x13C
@@ -3949,8 +3957,7 @@ int dsi_init_display(struct omap_dss_device *dssdev)
 
 int dsi_init(struct platform_device *pdev)
 {
-	u8 rd_reg;
-	int res, ret;
+	int ret;
 	u32 rev;
 
 	struct sched_param param = {
@@ -3982,7 +3989,6 @@ int dsi_init(struct platform_device *pdev)
 	dsi.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
 
 	dsi_base = dsi.base = ioremap(DSI_BASE, 2000);// MJ DSI_SZ_REGS);
-	printk("dss_base = 0x%x, dispc_base = 0x%x, dsi_base = 0x%x",dss_base,dispc_base,dsi_base);
 	if (!dsi.base) {
 		DSSERR("can't ioremap DSI\n");
 		return -ENOMEM;
diff --git a/drivers/video/omap2/dss/dsi2.c b/drivers/video/omap2/dss/dsi2.c
index 3dff73e428a9..bd5138c50f21 100644
--- a/drivers/video/omap2/dss/dsi2.c
+++ b/drivers/video/omap2/dss/dsi2.c
@@ -1,4172 +1,4165 @@
-/*

- * linux/drivers/video/omap2/dss/dsi2.c

- *

- * Copyright (C) 2009 Nokia Corporation

- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>

- *

- * This program is free software; you can redistribute it and/or modify it

- * under the terms of the GNU General Public License version 2 as published by

- * the Free Software Foundation.

- *

- * This program is distributed in the hope that it will be useful, but WITHOUT

- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

- * more details.

- *

- * You should have received a copy of the GNU General Public License along with

- * this program.  If not, see <http://www.gnu.org/licenses/>.

- */

-

-#define __raw_dumpl(n, x) printk(KERN_ERR "(x%08x) = x%08x { " #n ":" #x "\n", x, __raw_readl(x))

-

-#define DSS_SUBSYS_NAME "DSI"

-

-#include <linux/kernel.h>

-#include <linux/io.h>

-#include <linux/clk.h>

-#include <linux/device.h>

-#include <linux/err.h>

-#include <linux/interrupt.h>

-#include <linux/delay.h>

-#include <linux/mutex.h>

-#include <linux/seq_file.h>

-#include <linux/platform_device.h>

-#include <linux/regulator/consumer.h>

-#include <linux/kthread.h>

-#include <linux/wait.h>

-

-#include <mach/board.h>

-#include <mach/display.h>

-#include <mach/clock.h>

-

-#include <linux/i2c/twl.h>

-

-#include "dss.h"

-

-/*#define VERBOSE_IRQ*/

-

-#define DSI2_BASE		0x58005000

-

-struct dsi2_reg { u16 idx; };

-

-#define DSI_REG(idx)		((const struct dsi2_reg) { idx })

-

-#define DSI_SZ_REGS		SZ_1K

-/* DSI Protocol Engine */

-

-#define DSI_REVISION			DSI_REG(0x0000)

-#define DSI_SYSCONFIG			DSI_REG(0x0010)

-#define DSI_SYSSTATUS			DSI_REG(0x0014)

-#define DSI_IRQSTATUS			DSI_REG(0x0018)

-#define DSI_IRQENABLE			DSI_REG(0x001C)

-#define DSI_CTRL			DSI_REG(0x0040)

-#define DSI_GNQ					DSI_REG(0x0044) // MJ

-#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)

-#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)

-#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)

-#define DSI_CLK_CTRL			DSI_REG(0x0054)

-#define DSI_TIMING1			DSI_REG(0x0058)

-#define DSI_TIMING2			DSI_REG(0x005C)

-#define DSI_VM_TIMING1			DSI_REG(0x0060)

-#define DSI_VM_TIMING2			DSI_REG(0x0064)

-#define DSI_VM_TIMING3			DSI_REG(0x0068)

-#define DSI_CLK_TIMING			DSI_REG(0x006C)

-#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)

-#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)

-#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)

-#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)

-#define DSI_VM_TIMING4			DSI_REG(0x0080)

-#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)

-#define DSI_VM_TIMING5			DSI_REG(0x0088)

-#define DSI_VM_TIMING6			DSI_REG(0x008C)

-#define DSI_VM_TIMING7			DSI_REG(0x0090)

-#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)

-#ifdef CONFIG_ARCH_OMAP4

-#define DSI_CTRL2						DSI_REG(0x0098) // MJ

-#define DSI_VM_TIMING8					DSI_REG(0x009C) // MJ

-

-#define DSI_TE_HSYNC_WIDTH(n)			DSI_REG(0x00A0 + (n *0xC)) // MJ

-#define DSI_TE_VSYNC_WIDTH(n)			DSI_REG(0x00A4 + (n *0xC)) // MJ

-

-#define DSI_TE_HSYNC_NUMBER(n)			DSI_REG(0x00A8 + (n *0xC)) // MJ

-#endif

-#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))

-#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))

-#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))

-#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))

-#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))

-#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))

-#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))

-

-/* DSIPHY_SCP */

-

-#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)

-#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)

-#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)

-#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)

-

-#ifdef CONFIG_ARCH_OMAP4

-#define DSI_DSIPHY_CFG12			DSI_REG(0x200 + 0x0030)

-#define DSI_DSIPHY_CFG14			DSI_REG(0x200 + 0x0038)

-#define DSI_DSIPHY_CFG8			DSI_REG(0x200 + 0x0020)

-#define DSI_DSIPHY_CFG9			DSI_REG(0x200 + 0x0024)

-#endif

-/* DSI_PLL_CTRL_SCP */

-

-#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)

-#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)

-#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)

-#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)

-#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)

-#ifdef CONFIG_ARCH_OMAP4

-#define DSI_PLL_CONFIGURATION3		DSI_REG(0x300 + 0x0014)

-#define DSI_SSC_CONFIGURATION1		DSI_REG(0x300 + 0x0018)

-#define DSI_SSC_CONFIGURATION2		DSI_REG(0x300 + 0x001C)

-#define DSI_SSC_CONFIGURATION4		DSI_REG(0x300 + 0x0020)

-#endif

-

-#define REG_GET(idx, start, end) \

-	FLD_GET(dsi2_read_reg(idx), start, end)

-

-#define REG_FLD_MOD(idx, val, start, end) \

-	dsi2_write_reg(idx, FLD_MOD(dsi2_read_reg(idx), val, start, end))

-

-/* Global interrupts */

-#define DSI_IRQ_VC0		(1 << 0)

-#define DSI_IRQ_VC1		(1 << 1)

-#define DSI_IRQ_VC2		(1 << 2)

-#define DSI_IRQ_VC3		(1 << 3)

-#define DSI_IRQ_WAKEUP		(1 << 4)

-#define DSI_IRQ_RESYNC		(1 << 5)

-#define DSI_IRQ_PLL_LOCK	(1 << 7)

-#define DSI_IRQ_PLL_UNLOCK	(1 << 8)

-#define DSI_IRQ_PLL_RECALL	(1 << 9)

-#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)

-#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)

-#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)

-#define DSI_IRQ_TE_TRIGGER	(1 << 16)

-#define DSI_IRQ_ACK_TRIGGER	(1 << 17)

-#define DSI_IRQ_SYNC_LOST	(1 << 18)

-#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)

-#define DSI_IRQ_TA_TIMEOUT	(1 << 20)

-#define DSI_IRQ_ERROR_MASK \

-	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \

-	DSI_IRQ_TA_TIMEOUT)

-#define DSI_IRQ_CHANNEL_MASK	0xf

-

-/* Virtual channel interrupts */

-#define DSI_VC_IRQ_CS		(1 << 0)

-#define DSI_VC_IRQ_ECC_CORR	(1 << 1)

-#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)

-#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)

-#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)

-#define DSI_VC_IRQ_BTA		(1 << 5)

-#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)

-#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)

-#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)

-#define DSI_VC_IRQ_ERROR_MASK \

-	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \

-	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \

-	DSI_VC_IRQ_FIFO_TX_UDF)

-

-/* ComplexIO interrupts */

-#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)

-#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)

-#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)

-#define DSI_CIO_IRQ_ERRESC1		(1 << 5)

-#define DSI_CIO_IRQ_ERRESC2		(1 << 6)

-#define DSI_CIO_IRQ_ERRESC3		(1 << 7)

-#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)

-#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)

-#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)

-#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)

-#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)

-#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)

-#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)

-#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)

-#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)

-

-#define DSI_DT_DCS_SHORT_WRITE_0	0x05

-#define DSI_DT_DCS_SHORT_WRITE_1	0x15

-#define DSI_DT_DCS_READ			0x06

-#define DSI_DT_SET_MAX_RET_PKG_SIZE	0x37

-#define DSI_DT_NULL_PACKET		0x09

-#define DSI_DT_DCS_LONG_WRITE		0x39

-

-#define DSI_DT_RX_ACK_WITH_ERR		0x02

-#define DSI_DT_RX_DCS_LONG_READ		0x1c

-#define DSI_DT_RX_SHORT_READ_1		0x21

-#define DSI_DT_RX_SHORT_READ_2		0x22

-

-#define FINT_MAX 2100000

-#define FINT_MIN 750000

-#define REGN_MAX (1 << 7)

-#define REGM_MAX ((1 << 11) - 1)

-#define REGM3_MAX (1 << 4)

-#define REGM4_MAX (1 << 4)

-

-#ifdef CONFIG_ARCH_OMAP4

-extern void __iomem  *dss_base;

-extern void __iomem  *dispc_base;

-

-void __iomem  *dsi2_base;

-#define PWM2ON		3

-#define PWM2OFF		4

-#define TOGGLE3		2

-#define PWDNSTATUS2	4

-#endif

-enum fifo_size {

-	DSI_FIFO_SIZE_0		= 0,

-	DSI_FIFO_SIZE_32	= 1,

-	DSI_FIFO_SIZE_64	= 2,

-	DSI_FIFO_SIZE_96	= 3,

-	DSI_FIFO_SIZE_128	= 4,

-};

-

-enum dsi2_vc_mode {

-	DSI_VC_MODE_L4 = 0,

-	DSI_VC_MODE_VP,

-};

-

-struct dsi2_update_region {

-	bool dirty;

-	u16 x, y, w, h;

-	struct omap_dss_device *device;

-};

-

-static struct

-{

-	void __iomem	*base;

-

-	unsigned long	dsi1_pll_fclk;	/* Hz */

-	unsigned long	dsi2_pll_fclk;	/* Hz */

-	unsigned long	dsiphy;		/* Hz */

-	unsigned long	ddr_clk;	/* Hz */

-

-//	struct regulator *vdds_dsi_reg;

-

-	struct {

-		enum dsi2_vc_mode mode;

-		struct omap_dss_device *dssdev;

-		enum fifo_size fifo_size;

-		int dest_per;	/* destination peripheral 0-3 */

-	} vc[4];

-

-	struct mutex lock;

-	struct mutex bus_lock;

-

-	unsigned pll_locked;

-

-	struct completion bta_completion;

-

-	struct task_struct *thread;

-	wait_queue_head_t waitqueue;

-

-	spinlock_t update_lock;

-	bool framedone_received;

-	struct dsi2_update_region update_region;

-	struct dsi2_update_region active_update_region;

-	struct completion update_completion;

-

-	enum omap_dss_update_mode user_update_mode;

-	enum omap_dss_update_mode update_mode;

-	bool te_enabled;

-	bool use_ext_te;

-

-	unsigned long cache_req_pck;

-	unsigned long cache_clk_freq;

-	struct dsi_clock_info cache_cinfo;

-

-	u32		errors;

-	spinlock_t	errors_lock;

-#ifdef DEBUG

-	ktime_t perf_setup_time;

-	ktime_t perf_start_time;

-	ktime_t perf_start_time_auto;

-	int perf_measure_frames;

-#endif

-	int debug_read;

-	int debug_write;

-} dsi2;

-

-#ifdef DEBUG

-static unsigned int dsi2_perf;

-module_param_named(dsi2_perf, dsi2_perf, bool, 0644);

-#endif

-

-extern void Setup_SDP(void *, int);

-

-static inline void dsi2_write_reg(const struct dsi2_reg idx, u32 val)

-{

-	__raw_writel(val, dsi2.base + idx.idx);

-	__raw_readl(dsi2.base + 0x00);	//sv5

-}

-

-static inline u32 dsi2_read_reg(const struct dsi2_reg idx)

-{

-	return __raw_readl(dsi2.base + idx.idx);

-}

-

-

-void dsi2_save_context(void)

-{

-}

-

-void dsi2_restore_context(void)

-{

-}

-

-void dsi2_bus_lock(void)

-{

-	mutex_lock(&dsi2.bus_lock);

-}

-EXPORT_SYMBOL(dsi2_bus_lock);

-

-void dsi2_bus_unlock(void)

-{

-	mutex_unlock(&dsi2.bus_lock);

-}

-EXPORT_SYMBOL(dsi2_bus_unlock);

-

-static inline int wait_for_bit_change_delay(const struct dsi2_reg idx, int bitnum,

-		int value,int delay)

-{

-	int t = 100000;

-

-	while (REG_GET(idx, bitnum, bitnum) != value) {

-		udelay(delay);

-		if (--t == 0)

-			return !value;

-	}

-

-	return value;

-}

-

-static inline int wait_for_bit_change(const struct dsi2_reg idx, int bitnum,

-		int value)

-{

-	int t = 100000;

-

-	while (REG_GET(idx, bitnum, bitnum) != value) {

-		if (--t == 0)

-			return !value;

-	}

-

-	return value;

-}

-

-#ifdef DEBUG

-static void dsi2_perf_mark_setup(void)

-{

-	dsi2.perf_setup_time = ktime_get();

-}

-

-static void dsi2_perf_mark_start(void)

-{

-	dsi2.perf_start_time = ktime_get();

-}

-

-static void dsi2_perf_mark_start_auto(void)

-{

-	dsi2.perf_measure_frames = 0;

-	dsi2.perf_start_time_auto = ktime_get();

-}

-

-static void dsi2_perf_show(const char *name)

-{

-	ktime_t t, setup_time, trans_time;

-	u32 total_bytes;

-	u32 setup_us, trans_us, total_us;

-

-	if (!dsi2_perf)

-		return;

-

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_DISABLED)

-		return;

-

-	t = ktime_get();

-

-	setup_time = ktime_sub(dsi2.perf_start_time, dsi2.perf_setup_time);

-	setup_us = (u32)ktime_to_us(setup_time);

-	if (setup_us == 0)

-		setup_us = 1;

-

-	trans_time = ktime_sub(t, dsi2.perf_start_time);

-	trans_us = (u32)ktime_to_us(trans_time);

-	if (trans_us == 0)

-		trans_us = 1;

-

-	total_us = setup_us + trans_us;

-

-	total_bytes = dsi2.active_update_region.w *

-		dsi2.active_update_region.h *

-		dsi2.active_update_region.device->ctrl.pixel_size / 8;

-

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO) {

-		static u32 s_total_trans_us, s_total_setup_us;

-		static u32 s_min_trans_us = 0xffffffff, s_min_setup_us;

-		static u32 s_max_trans_us, s_max_setup_us;

-		const int numframes = 100;

-		ktime_t total_time_auto;

-		u32 total_time_auto_us;

-

-		dsi2.perf_measure_frames++;

-

-		if (setup_us < s_min_setup_us)

-			s_min_setup_us = setup_us;

-

-		if (setup_us > s_max_setup_us)

-			s_max_setup_us = setup_us;

-

-		s_total_setup_us += setup_us;

-

-		if (trans_us < s_min_trans_us)

-			s_min_trans_us = trans_us;

-

-		if (trans_us > s_max_trans_us)

-			s_max_trans_us = trans_us;

-

-		s_total_trans_us += trans_us;

-

-		if (dsi2.perf_measure_frames < numframes)

-			return;

-

-		total_time_auto = ktime_sub(t, dsi2.perf_start_time_auto);

-		total_time_auto_us = (u32)ktime_to_us(total_time_auto);

-

-		printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, "

-				"trans %u/%u/%u\n",

-				name,

-				1000 * 1000 * numframes / total_time_auto_us,

-				s_min_setup_us,

-				s_max_setup_us,

-				s_total_setup_us / numframes,

-				s_min_trans_us,

-				s_max_trans_us,

-				s_total_trans_us / numframes);

-

-		s_total_setup_us = 0;

-		s_min_setup_us = 0xffffffff;

-		s_max_setup_us = 0;

-		s_total_trans_us = 0;

-		s_min_trans_us = 0xffffffff;

-		s_max_trans_us = 0;

-		dsi2_perf_mark_start_auto();

-	} else {

-		printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "

-				"%u bytes, %u kbytes/sec\n",

-				name,

-				setup_us,

-				trans_us,

-				total_us,

-				1000*1000 / total_us,

-				total_bytes,

-				total_bytes * 1000 / total_us);

-	}

-}

-#else

-#define dsi2_perf_mark_setup()

-#define dsi2_perf_mark_start()

-#define dsi2_perf_mark_start_auto()

-#define dsi2_perf_show(x)

-#endif

-

-static void print_irq_status(u32 status)

-{

-#ifndef VERBOSE_IRQ

-	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)

-		return;

-#endif

-	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);

-

-#define PIS(x) \

-	if (status & DSI_IRQ_##x) \

-		printk(#x " ");

-#ifdef VERBOSE_IRQ

-	PIS(VC0);

-	PIS(VC1);

-	PIS(VC2);

-	PIS(VC3);

-#endif

-	PIS(WAKEUP);

-	PIS(RESYNC);

-	PIS(PLL_LOCK);

-	PIS(PLL_UNLOCK);

-	PIS(PLL_RECALL);

-	PIS(COMPLEXIO_ERR);

-	PIS(HS_TX_TIMEOUT);

-	PIS(LP_RX_TIMEOUT);

-	PIS(TE_TRIGGER);

-	PIS(ACK_TRIGGER);

-	PIS(SYNC_LOST);

-	PIS(LDO_POWER_GOOD);

-	PIS(TA_TIMEOUT);

-#undef PIS

-

-	printk("\n");

-}

-

-static void print_irq_status_vc(int channel, u32 status)

-{

-#ifndef VERBOSE_IRQ

-	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)

-		return;

-#endif

-	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);

-

-#define PIS(x) \

-	if (status & DSI_VC_IRQ_##x) \

-		printk(#x " ");

-	PIS(CS);

-	PIS(ECC_CORR);

-#ifdef VERBOSE_IRQ

-	PIS(PACKET_SENT);

-#endif

-	PIS(FIFO_TX_OVF);

-	PIS(FIFO_RX_OVF);

-	PIS(BTA);

-	PIS(ECC_NO_CORR);

-	PIS(FIFO_TX_UDF);

-	PIS(PP_BUSY_CHANGE);

-#undef PIS

-	printk("\n");

-}

-

-static void print_irq_status_cio(u32 status)

-{

-	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);

-

-#define PIS(x) \

-	if (status & DSI_CIO_IRQ_##x) \

-		printk(#x " ");

-	PIS(ERRSYNCESC1);

-	PIS(ERRSYNCESC2);

-	PIS(ERRSYNCESC3);

-	PIS(ERRESC1);

-	PIS(ERRESC2);

-	PIS(ERRESC3);

-	PIS(ERRCONTROL1);

-	PIS(ERRCONTROL2);

-	PIS(ERRCONTROL3);

-	PIS(STATEULPS1);

-	PIS(STATEULPS2);

-	PIS(STATEULPS3);

-	PIS(ERRCONTENTIONLP0_1);

-	PIS(ERRCONTENTIONLP1_1);

-	PIS(ERRCONTENTIONLP0_2);

-	PIS(ERRCONTENTIONLP1_2);

-	PIS(ERRCONTENTIONLP0_3);

-	PIS(ERRCONTENTIONLP1_3);

-	PIS(ULPSACTIVENOT_ALL0);

-	PIS(ULPSACTIVENOT_ALL1);

-#undef PIS

-

-	printk("\n");

-}

-

-static int debug_irq;

-

-/* called from dss */

-void dsi2_irq_handler(void)

-{

-	u32 irqstatus, vcstatus, ciostatus;

-	int i;

-#if 1 //sv3 debugging

-	irqstatus = dsi2_read_reg(DSI_IRQSTATUS);

-

-	if (irqstatus & DSI_IRQ_ERROR_MASK) {

-		DSSERR("DSI error, irqstatus %x\n", irqstatus);

-		print_irq_status(irqstatus);

-		spin_lock(&dsi2.errors_lock);

-		dsi2.errors |= irqstatus & DSI_IRQ_ERROR_MASK;

-		spin_unlock(&dsi2.errors_lock);

-	} else if (debug_irq) {

-		print_irq_status(irqstatus);

-	}

-

-	for (i = 0; i < 4; ++i) {

-		if ((irqstatus & (1<<i)) == 0)

-			continue;

-

-		vcstatus = dsi2_read_reg(DSI_VC_IRQSTATUS(i));

-

-		if (vcstatus & DSI_VC_IRQ_BTA)

-			complete(&dsi2.bta_completion);

-

-		if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {

-			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",

-				       i, vcstatus);

-			print_irq_status_vc(i, vcstatus);

-		} else if (debug_irq) {

-			print_irq_status_vc(i, vcstatus);

-		}

-

-		dsi2_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);

-	}

-

-	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {

-		ciostatus = dsi2_read_reg(DSI_COMPLEXIO_IRQ_STATUS);

-

-		dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);

-

-		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);

-		print_irq_status_cio(ciostatus);

-	}

-

-	dsi2_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);

-#endif

-}

-

-

-static void _dsi2_initialize_irq(void)

-{

-	u32 l;

-	int i;

-

-	/* disable all interrupts */

-	dsi2_write_reg(DSI_IRQENABLE, 0);

-	for (i = 0; i < 4; ++i)

-		dsi2_write_reg(DSI_VC_IRQENABLE(i), 0);

-	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);

-

-	/* clear interrupt status */

-	l = dsi2_read_reg(DSI_IRQSTATUS);

-	dsi2_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);

-

-	for (i = 0; i < 4; ++i) {

-		l = dsi2_read_reg(DSI_VC_IRQSTATUS(i));

-		dsi2_write_reg(DSI_VC_IRQSTATUS(i), l);

-	}

-

-	l = dsi2_read_reg(DSI_COMPLEXIO_IRQ_STATUS);

-	dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);

-

-	/* enable error irqs */

-	l = DSI_IRQ_ERROR_MASK;

-	dsi2_write_reg(DSI_IRQENABLE, l);

-

-	l = DSI_VC_IRQ_ERROR_MASK;

-	for (i = 0; i < 4; ++i)

-		dsi2_write_reg(DSI_VC_IRQENABLE(i), l);

-

-	/* XXX zonda responds incorrectly, causing control error:

-	   Exit from LP-ESC mode to LP11 uses wrong transition states on the

-	   data lines LP0 and LN0. */

-	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,

-			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));

-}

-

-static u32 dsi2_get_errors(void)

-{

-	unsigned long flags;

-	u32 e;

-	spin_lock_irqsave(&dsi2.errors_lock, flags);

-	e = dsi2.errors;

-	dsi2.errors = 0;

-	spin_unlock_irqrestore(&dsi2.errors_lock, flags);

-	return e;

-}

-

-static void dsi2_vc_enable_bta_irq(int channel)

-{

-	u32 l;

-

-	dsi2_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);

-

-	l = dsi2_read_reg(DSI_VC_IRQENABLE(channel));

-	l |= DSI_VC_IRQ_BTA;

-	dsi2_write_reg(DSI_VC_IRQENABLE(channel), l);

-}

-

-static void dsi2_vc_disable_bta_irq(int channel)

-{

-	u32 l;

-

-	l = dsi2_read_reg(DSI_VC_IRQENABLE(channel));

-	l &= ~DSI_VC_IRQ_BTA;

-	dsi2_write_reg(DSI_VC_IRQENABLE(channel), l);

-}

-

-/* DSI func clock. this could also be DSI2_PLL_FCLK */

-static inline void enable_clocks(bool enable)

-{

-	if (enable)

-		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);

-	else

-		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);

-}

-

-/* source clock for DSI PLL. this could also be PCLKFREE */

-static inline void dsi2_enable_pll_clock(bool enable)

-{

-	if (enable)

-		dss_clk_enable(DSS_CLK_FCK2);

-	else

-		dss_clk_disable(DSS_CLK_FCK2);

-

-	if (enable && dsi2.pll_locked) {

-		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)

-			DSSERR("cannot lock PLL when enabling clocks\n");

-	}

-}

-

-#ifdef DEBUG

-static void _dsi2_print_reset_status(void)

-{

-	u32 l;

-

-	if (!dss_debug)

-		return;

-

-	/* A dummy read using the SCP interface to any DSIPHY register is

-	 * required after DSIPHY reset to complete the reset of the DSI complex

-	 * I/O. */

-	l = dsi2_read_reg(DSI_DSIPHY_CFG5);

-

-	printk(KERN_DEBUG "DSI resets: ");

-

-	l = dsi2_read_reg(DSI_PLL_STATUS);

-	printk("PLL (%d) ", FLD_GET(l, 0, 0));

-

-	l = dsi2_read_reg(DSI_COMPLEXIO_CFG1);

-	printk("CIO (%d) ", FLD_GET(l, 29, 29));

-

-	l = dsi2_read_reg(DSI_DSIPHY_CFG5);

-	printk("PHY (%x, %d, %d, %d)\n",

-			FLD_GET(l, 28, 26),

-			FLD_GET(l, 29, 29),

-			FLD_GET(l, 30, 30),

-			FLD_GET(l, 31, 31));

-}

-#else

-#define _dsi2_print_reset_status()

-#endif

-

-static inline int dsi2_if_enable(bool enable)

-{

-	DSSDBG("dsi2_if_enable(%d)\n", enable);

-

-	enable = enable ? 1 : 0;

-	REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */

-

-	if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {

-			DSSERR("Failed to set dsi2_if_enable to %d\n", enable);

-			return -EIO;

-	}

-

-	return 0;

-}

-

-static unsigned long dsi2_fclk_rate(void)

-{

-	unsigned long r;

-

-	if (dss_get_dsi_clk_source() == 0) {

-		/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */

-		r = dss_clk_get_rate(DSS_CLK_FCK1);

-	} else {

-		/* DSI FCLK source is DSI2_PLL_FCLK */

-		r = dsi2.dsi2_pll_fclk;

-	}

-

-	return r;

-}

-

-static int dsi2_set_lp_clk_divisor(struct omap_dss_device *dssdev)

-{

-	unsigned n;

-	unsigned long dsi2_fclk;

-	unsigned long lp_clk, lp_clk_req;

-

-	dsi2_fclk = dsi2_fclk_rate();

-

-	lp_clk_req = dssdev->phy.dsi.lp_clk_hz;

-

-	for (n = 1; n < (1 << 13) - 1; ++n) {

-		lp_clk = dsi2_fclk / 2 / n;

-		if (lp_clk <= lp_clk_req)

-			break;

-	}

-

-	if (n == (1 << 13) - 1) {

-		DSSERR("Failed to find LP_CLK_DIVISOR\n");

-		return -EINVAL;

-	}

-

-	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu (req %lu)\n", n, lp_clk, lp_clk_req);

-

-//sv5 	REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0);	/* LP_CLK_DIVISOR */

-	REG_FLD_MOD(DSI_CLK_CTRL, 6, 12, 0);	/* LP_CLK_DIVISOR */

-	if (dsi2_fclk > 30*1000*1000)

-		REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */

-

-	return 0;

-}

-

-

-enum dsi2_pll_power_state {

-	DSI_PLL_POWER_OFF	= 0x0,

-	DSI_PLL_POWER_ON_HSCLK	= 0x1,

-	DSI_PLL_POWER_ON_ALL	= 0x2,

-	DSI_PLL_POWER_ON_DIV	= 0x3,

-};

-

-static int dsi2_pll_power(enum dsi2_pll_power_state state)

-{

-	int t = 0;

-

-	REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */

-

-	/* PLL_PWR_STATUS */

-	while (FLD_GET(dsi2_read_reg(DSI_CLK_CTRL), 29, 28) != state) {

-		udelay(1);

-		if (t++ > 1000) {

-			DSSERR("Failed to set DSI PLL power mode to %d\n",

-					state);

-			return -ENODEV;

-		}

-	}

-

-	return 0;

-}

-

-int dsi2_pll_calc_pck(bool is_tft, unsigned long req_pck,

-		struct dsi_clock_info *cinfo)

-{

-	struct dsi_clock_info cur, best;

-	int min_fck_per_pck;

-	int match = 0;

-	unsigned long dss_clk_fck2;

-

-	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);

-

-	if (req_pck == dsi2.cache_req_pck &&

-			dsi2.cache_cinfo.clkin == dss_clk_fck2) {

-		DSSDBG("DSI clock info found from cache\n");

-		*cinfo = dsi2.cache_cinfo;

-		return 0;

-	}

-

-	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;

-

-	if (min_fck_per_pck &&

-		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {

-		DSSERR("Requested pixel clock not possible with the current "

-				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "

-				"the constraint off.\n");

-		min_fck_per_pck = 0;

-	}

-

-	DSSDBG("dsi2_pll_calc\n");

-

-retry:

-	memset(&best, 0, sizeof(best));

-

-	memset(&cur, 0, sizeof(cur));

-	cur.clkin = dss_clk_fck2;

-	cur.use_dss2_fck = 1;

-	cur.highfreq = 0;

-

-	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */

-	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */

-	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */

-	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {

-		if (cur.highfreq == 0)

-			cur.fint = cur.clkin / cur.regn;

-		else

-			cur.fint = cur.clkin / (2 * cur.regn);

-

-		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)

-			continue;

-

-		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */

-		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {

-			unsigned long a, b;

-

-			a = 2 * cur.regm * (cur.clkin/1000);

-			b = cur.regn * (cur.highfreq + 1);

-			cur.dsiphy = a / b * 1000;

-

-			if (cur.dsiphy > 1800 * 1000 * 1000)

-				break;

-

-			/* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */

-			for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;

-					++cur.regm3) {

-				cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;

-

-				/* this will narrow down the search a bit,

-				 * but still give pixclocks below what was

-				 * requested */

-				if (cur.dsi1_pll_fclk  < req_pck)

-					break;

-

-				if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)

-					continue;

-

-				if (min_fck_per_pck &&

-					cur.dsi1_pll_fclk <

-						req_pck * min_fck_per_pck)

-					continue;

-

-				match = 1;

-

-				find_lck_pck_divs(is_tft, req_pck,

-						cur.dsi1_pll_fclk,

-						&cur.lck_div,

-						&cur.pck_div);

-

-				cur.lck = cur.dsi1_pll_fclk / cur.lck_div;

-				cur.pck = cur.lck / cur.pck_div;

-

-				if (abs(cur.pck - req_pck) <

-						abs(best.pck - req_pck)) {

-					best = cur;

-

-					if (cur.pck == req_pck)

-						goto found;

-				}

-			}

-		}

-	}

-found:

-	if (!match) {

-		if (min_fck_per_pck) {

-			DSSERR("Could not find suitable clock settings.\n"

-					"Turning FCK/PCK constraint off and"

-					"trying again.\n");

-			min_fck_per_pck = 0;

-			goto retry;

-		}

-

-		DSSERR("Could not find suitable clock settings.\n");

-

-		return -EINVAL;

-	}

-

-	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */

-	best.regm4 = best.dsiphy / 48000000;

-	if (best.regm4 > REGM4_MAX)

-		best.regm4 = REGM4_MAX;

-	else if (best.regm4 == 0)

-		best.regm4 = 1;

-	best.dsi2_pll_fclk = best.dsiphy / best.regm4;

-

-	if (cinfo)

-		*cinfo = best;

-

-	dsi2.cache_req_pck = req_pck;

-	dsi2.cache_clk_freq = 0;

-	dsi2.cache_cinfo = best;

-

-	return 0;

-}

-

-static int dsi2_pll_calc_ddrfreq(unsigned long clk_freq,

-		struct dsi_clock_info *cinfo)

-{

-	struct dsi_clock_info cur, best;

-	const bool use_dss2_fck = 1;

-	unsigned long datafreq;

-	unsigned long dss_clk_fck2;

-

-	DSSDBG("dsi2_pll_calc_ddrfreq\n");

-

-	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);

-

-	if (clk_freq == dsi2.cache_clk_freq &&

-			dsi2.cache_cinfo.clkin == dss_clk_fck2) {

-		DSSDBG("DSI clock info found from cache\n");

-		*cinfo = dsi2.cache_cinfo;

-		return 0;

-	}

-

-	datafreq = clk_freq * 4;

-

-	memset(&best, 0, sizeof(best));

-

-	memset(&cur, 0, sizeof(cur));

-	if(cpu_is_omap44xx()){

-		cur.use_dss2_fck = 0;

-		cur.clkin = 38400000;

-		cur.highfreq = 1;

-	}else if(cpu_is_omap34xx()){

-		cur.use_dss2_fck = use_dss2_fck;

-		if (use_dss2_fck) {

-			cur.clkin = dss_clk_fck2;

-			cur.highfreq = 0;

-		} else  {

-			/* TODO: Add support for LCD2 */

-			cur.clkin = dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2);

-			if (cur.clkin < 32000000)

-				cur.highfreq = 0;

-			else	

-				cur.highfreq = 1;

-		}

-	}

-	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */

-	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */

-	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */

-	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {

-		if (cur.highfreq == 0)

-			cur.fint = cur.clkin / cur.regn;

-		else

-			cur.fint = cur.clkin / (2 * cur.regn);

-

-		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)

-			continue;

-

-		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */

-		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {

-			unsigned long a, b;

-

-			a = 2 * cur.regm * (cur.clkin/1000);

-			b = cur.regn * (cur.highfreq + 1);

-			cur.dsiphy = a / b * 1000;

-

-			if (cur.dsiphy > 1800 * 1000 * 1000)

-				break;

-

-			if (abs(cur.dsiphy - datafreq) <

-					abs(best.dsiphy - datafreq)) {

-				best = cur;

-				/* DSSDBG("best %ld\n", best.dsiphy); */

-			}

-

-			if (cur.dsiphy == datafreq)

-				goto found;

-		}

-	}

-found:

-	/* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */

-	best.regm3 = best.dsiphy / 48000000;

-	if (best.regm3 > REGM3_MAX)

-		best.regm3 = REGM3_MAX;

-	else if (best.regm3 == 0)

-		best.regm3 = 1;

-	best.dsi1_pll_fclk = best.dsiphy / best.regm3;

-

-	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */

-	best.regm4 = best.dsiphy / 48000000;

-	if (best.regm4 > REGM4_MAX)

-		best.regm4 = REGM4_MAX;

-	else if (best.regm4 == 0)

-		best.regm4 = 1;

-	best.dsi2_pll_fclk = best.dsiphy / best.regm4;

-

-	if (cinfo)

-		*cinfo = best;

-

-	dsi2.cache_clk_freq = clk_freq;

-	dsi2.cache_req_pck = 0;

-	dsi2.cache_cinfo = best;

-

-	return 0;

-}

-

-int dsi2_pll_program(struct dsi_clock_info *cinfo)

-{

-	int r = 0;

-	u32 l;

-

-	DSSDBG("dsi2_pll_program\n");

-

-	dsi2.dsiphy = cinfo->dsiphy;

-	dsi2.ddr_clk = dsi2.dsiphy / 4;

-	dsi2.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;

-	dsi2.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;

-

-	DSSDBG("DSI Fint %ld\n", cinfo->fint);

-

-	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",

-			cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",

-			cinfo->clkin,

-			cinfo->highfreq);

-

-	/* DSIPHY == CLKIN4DDR */

-	DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",

-			cinfo->regm,

-			cinfo->regn,

-			cinfo->clkin,

-			cinfo->highfreq + 1,

-			cinfo->dsiphy);

-

-	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",

-			dsi2.dsiphy / 1000 / 1000 / 2);

-

-	DSSDBG("Clock lane freq %ld Hz\n", dsi2.ddr_clk);

-

-	DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",

-			cinfo->regm3, cinfo->dsi1_pll_fclk);

-	DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",

-			cinfo->regm4, cinfo->dsi2_pll_fclk);

-#if 0//sv3

-	REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */

-

-	l = dsi2_read_reg(DSI_PLL_CONFIGURATION1);

-	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */

-	l = FLD_MOD(l, cinfo->regn - 1, 7, 1);	/* DSI_PLL_REGN */

-	l = FLD_MOD(l, cinfo->regm, 18, 8);	/* DSI_PLL_REGM */

-	l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19);	/* DSI_CLOCK_DIV */

-	l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23);	/* DSIPROTO_CLOCK_DIV */

-	dsi2_write_reg(DSI_PLL_CONFIGURATION1, l);

-

-	l = dsi2_read_reg(DSI_PLL_CONFIGURATION2);

-	l = FLD_MOD(l, 7, 4, 1);		/* DSI_PLL_FREQSEL */

-	/* DSI_PLL_CLKSEL */

-	l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);

-	l = FLD_MOD(l, cinfo->highfreq, 12, 12);	/* DSI_PLL_HIGHFREQ */

-	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */

-	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */

-	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */

-	dsi2_write_reg(DSI_PLL_CONFIGURATION2, l);

-#else

-/*

-	REG_FLD_MOD(DSI_PLL_CONTROL, 0,0,0);

-	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,14,14);

-	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 1,20,20);

-	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,11,11);

-	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,12,12);

-

-	REG_FLD_MOD(DSI_PLL_CONFIGURATION1, 0,12,12);

-

-	l = dsi2_read_reg(DSI_PLL_CONFIGURATION1);

-

-	l = 	FLD_MOD(l, 3,26,30);

-	l = 	FLD_MOD(l, 3,21,25);

-	l = 	FLD_MOD(l, 102,9,20);

-	l = 	FLD_MOD(l, 18,1,8);	

-	l = 	FLD_MOD(l, 1,0,0);	

-	dsi2_write_reg(DSI_PLL_CONFIGURATION1, l);

-*/	

-//	regm4 = 3; 	regm3 = 3;

-//	regn = 18; regm = 102;

-	

-#endif

-

-	dsi2_write_reg(DSI_PLL_CONFIGURATION1, 0x0C60CC25);

-	dsi2_write_reg(DSI_PLL_CONFIGURATION2, 0x0065600C);

-

-	REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */

-

-	if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {

-		DSSERR("dsi pll go bit not going down.\n");

-		r = -EIO;

-		goto err;

-	}

-

-	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {

-		DSSERR("cannot lock PLL\n");

-		r = -EIO;

-		goto err;

-	}

-	printk(KERN_INFO "\n PLL is locked ");

-	printk(KERN_INFO "\n DSI_PLL_STATUS = 0x%X ", dsi2_read_reg(DSI_PLL_STATUS));

-	dsi2.pll_locked = 1;

-

-#if 0

-	l = dsi2_read_reg(DSI_PLL_CONFIGURATION2);

-	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */

-	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */

-	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */

-	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */

-	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */

-	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */

-	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */

-	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */

-	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */

-	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */

-	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */

-	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */

-	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */

-	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */

-	dsi2_write_reg(DSI_PLL_CONFIGURATION2, l);

-#endif

-	DSSDBG("PLL config done\n");

-err:

-	return r;

-}

-

-int dsi2_pll_init(bool enable_hsclk, bool enable_hsdiv)

-{

-	int r = 0;

-	enum dsi2_pll_power_state pwstate;

-	struct dispc_clock_info cinfo;

-

-	DSSDBG("PLL init\n");

-

-//sv3 	enable_clocks(1);

-//sv3	dsi2_enable_pll_clock(1);

-

-	/* XXX this should be calculated depending on the screen size,

-	 * required framerate and DSI speed.

-	 * For now 48MHz is enough for 864x480@60 with 360Mbps/lane

-	 * with two lanes */

-	r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);

-	if (r)

-		goto err0;

-

-/*sv3	r = dispc_set_clock_div(&cinfo);

-	if (r) {

-		DSSERR("Failed to set basic clocks\n");

-		goto err0;

-	}

-

-	r = regulator_enable(dsi2.vdds_dsi2_reg);

-	if (r)

-		goto err0;

-*/

-	/* CIO_CLK_ICG, enable L3 clk to CIO */

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); //sv3

-

-	pwstate = DSI_PLL_POWER_ON_ALL;

-	r = dsi2_pll_power(pwstate);

-	if (r)

-		goto err1;

-

-	/* XXX PLL does not come out of reset without this... */

-//sv3 	dispc_pck_free_enable(1);

-

-	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {

-		DSSERR("PLL not coming out of reset.\n");

-		r = -ENODEV;

-		goto err1;

-	}

-

-	/* XXX ... but if left on, we get problems when planes do not

-	 * fill the whole display. No idea about this */

-//sv3	dispc_pck_free_enable(0); 

-

-	if (enable_hsclk && enable_hsdiv)

-		pwstate = DSI_PLL_POWER_ON_ALL;

-	else if (enable_hsclk)

-		pwstate = DSI_PLL_POWER_ON_HSCLK;

-	else if (enable_hsdiv)

-		pwstate = DSI_PLL_POWER_ON_DIV;

-	else

-		pwstate = DSI_PLL_POWER_OFF;

-

-	pwstate = DSI_PLL_POWER_ON_ALL;

-	r = dsi2_pll_power(pwstate);

-

-	if (r)

-		goto err1;

-

-	DSSDBG("PLL init done\n");

-

-	return 0;

-err1:

-//sv3	regulator_disable(dsi2.vdds_dsi2_reg);

-err0:

-//sv3 	enable_clocks(0);

-//sv3	dsi2_enable_pll_clock(0);

-	return r;

-}

-

-void dsi2_pll_uninit(void)

-{

-	enable_clocks(0);

-	dsi2_enable_pll_clock(0);

-

-	dsi2.pll_locked = 0;

-	dsi2_pll_power(DSI_PLL_POWER_OFF);

-	//regulator_disable(dsi2.vdds_dsi2_reg);

-	DSSDBG("PLL uninit done\n");

-}

-

-unsigned long dsi2_get_dsi1_pll_rate(void)

-{

-	return dsi2.dsi1_pll_fclk;

-}

-

-unsigned long dsi2_get_dsi2_pll_rate(void)

-{

-	return dsi2.dsi2_pll_fclk;

-}

-

-void dsi2_dump_clocks(struct seq_file *s)

-{

-	int clksel;

-

-	enable_clocks(1);

-

-	clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);

-

-	seq_printf(s, "- dsi -\n");

-

-	seq_printf(s, "dsi fclk source = %s\n",

-			dss_get_dsi_clk_source() == 0 ?

-			"dss1_alwon_fclk" : "dsi2_pll_fclk");

-

-	seq_printf(s, "dsi pll source = %s\n",

-			clksel == 0 ?

-			"dss2_alwon_fclk" : "pclkfree");

-

-	seq_printf(s,	"DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",

-			dsi2.dsiphy, dsi2.ddr_clk);

-

-	seq_printf(s,	"dsi1_pll_fck\t%lu (%s)\n"

-			"dsi2_pll_fck\t%lu (%s)\n",

-			dsi2.dsi1_pll_fclk,

-			dss_get_dispc_clk_source() == 0 ? "off" : "on",

-			dsi2.dsi2_pll_fclk,

-			dss_get_dsi_clk_source() == 0 ? "off" : "on");

-

-	enable_clocks(0);

-}

-

-void dsi2_dump_regs(struct seq_file *s)

-{

-#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi2_read_reg(r))

-

-	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);

-

-	DUMPREG(DSI_REVISION);

-	DUMPREG(DSI_SYSCONFIG);

-	DUMPREG(DSI_SYSSTATUS);

-	DUMPREG(DSI_IRQSTATUS);

-	DUMPREG(DSI_IRQENABLE);

-	DUMPREG(DSI_CTRL);

-	DUMPREG(DSI_COMPLEXIO_CFG1);

-	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);

-	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);

-	DUMPREG(DSI_CLK_CTRL);

-	DUMPREG(DSI_TIMING1);

-	DUMPREG(DSI_TIMING2);

-	DUMPREG(DSI_VM_TIMING1);

-	DUMPREG(DSI_VM_TIMING2);

-	DUMPREG(DSI_VM_TIMING3);

-	DUMPREG(DSI_CLK_TIMING);

-	DUMPREG(DSI_TX_FIFO_VC_SIZE);

-	DUMPREG(DSI_RX_FIFO_VC_SIZE);

-	DUMPREG(DSI_COMPLEXIO_CFG2);

-	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);

-	DUMPREG(DSI_VM_TIMING4);

-	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);

-	DUMPREG(DSI_VM_TIMING5);

-	DUMPREG(DSI_VM_TIMING6);

-	DUMPREG(DSI_VM_TIMING7);

-	DUMPREG(DSI_STOPCLK_TIMING);

-

-	DUMPREG(DSI_VC_CTRL(0));

-	DUMPREG(DSI_VC_TE(0));

-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));

-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));

-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));

-	DUMPREG(DSI_VC_IRQSTATUS(0));

-	DUMPREG(DSI_VC_IRQENABLE(0));

-

-	DUMPREG(DSI_VC_CTRL(1));

-	DUMPREG(DSI_VC_TE(1));

-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));

-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));

-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));

-	DUMPREG(DSI_VC_IRQSTATUS(1));

-	DUMPREG(DSI_VC_IRQENABLE(1));

-

-	DUMPREG(DSI_VC_CTRL(2));

-	DUMPREG(DSI_VC_TE(2));

-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));

-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));

-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));

-	DUMPREG(DSI_VC_IRQSTATUS(2));

-	DUMPREG(DSI_VC_IRQENABLE(2));

-

-	DUMPREG(DSI_VC_CTRL(3));

-	DUMPREG(DSI_VC_TE(3));

-	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));

-	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));

-	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));

-	DUMPREG(DSI_VC_IRQSTATUS(3));

-	DUMPREG(DSI_VC_IRQENABLE(3));

-

-	DUMPREG(DSI_DSIPHY_CFG0);

-	DUMPREG(DSI_DSIPHY_CFG1);

-	DUMPREG(DSI_DSIPHY_CFG2);

-	DUMPREG(DSI_DSIPHY_CFG5);

-

-	DUMPREG(DSI_PLL_CONTROL);

-	DUMPREG(DSI_PLL_STATUS);

-	DUMPREG(DSI_PLL_GO);

-	DUMPREG(DSI_PLL_CONFIGURATION1);

-	DUMPREG(DSI_PLL_CONFIGURATION2);

-

-	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);

-#undef DUMPREG

-}

-

-enum dsi2_complexio_power_state {

-	DSI_COMPLEXIO_POWER_OFF		= 0x0,

-	DSI_COMPLEXIO_POWER_ON		= 0x1,

-	DSI_COMPLEXIO_POWER_ULPS	= 0x2,

-};

-

-static int dsi2_complexio_power(enum dsi2_complexio_power_state state)

-{

-	int t = 0;

-#if 0 //sv3

-	/* PWR_CMD */

-	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);

-

-	/* PWR_STATUS */

-	while (FLD_GET(dsi2_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {

-		udelay(1);

-		if (t++ > 1000) {

-			DSSERR("failed to set complexio power state to "

-					"%d\n", state);

-			return -ENODEV;

-		}

-	}

-#else

-	/* CIO_CLK_ICG, enable L3 clk to CIO */

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); //sv3

-	/* PWR_CMD */

-	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);	

-	udelay(100);

-	

-

-#endif

-	return 0;

-}

-

-static void dsi2_complexio_config(struct omap_dss_device *dssdev)

-{

-	u32 r;

-

-	int clk_lane   = dssdev->phy.dsi.clk_lane;

-	int data1_lane = dssdev->phy.dsi.data1_lane;

-	int data2_lane = dssdev->phy.dsi.data2_lane;

-	int clk_pol    = dssdev->phy.dsi.clk_pol;

-	int data1_pol  = dssdev->phy.dsi.data1_pol;

-	int data2_pol  = dssdev->phy.dsi.data2_pol;

-

-	r = dsi2_read_reg(DSI_COMPLEXIO_CFG1);

-	r = FLD_MOD(r, clk_lane, 2, 0);

-	r = FLD_MOD(r, clk_pol, 3, 3);

-	r = FLD_MOD(r, data1_lane, 6, 4);

-	r = FLD_MOD(r, data1_pol, 7, 7);

-	r = FLD_MOD(r, data2_lane, 10, 8);

-	r = FLD_MOD(r, data2_pol, 11, 11);

-	dsi2_write_reg(DSI_COMPLEXIO_CFG1, r);

-

-	/* The configuration of the DSI complex I/O (number of data lanes,

-	   position, differential order) should not be changed while

-	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for

-	   the hardware to take into account a new configuration of the complex

-	   I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to

-	   follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,

-	   then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set

-	   DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the

-	   DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the

-	   DSI complex I/O configuration is unknown. */

-

-	/*

-	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);

-	REG_FLD_MOD(DSI_CTRL, 0, 0, 0);

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);

-	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);

-	*/

-}

-

-static inline unsigned ns2ddr(unsigned ns)

-{

-	/* convert time in ns to ddr ticks, rounding up */

-	return (ns * (dsi2.ddr_clk/1000/1000) + 999) / 1000;

-}

-

-static inline unsigned ddr2ns(unsigned ddr)

-{

-	return ddr * 1000 * 1000 / (dsi2.ddr_clk / 1000);

-}

-

-static void dsi2_complexio_timings(void)

-{

-	u32 r;

-	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;

-	u32 tlpx_half, tclk_trail, tclk_zero;

-	u32 tclk_prepare;

-

-	/* calculate timings */

-

-	/* 1 * DDR_CLK = 2 * UI */

-

-	/* min 40ns + 4*UI	max 85ns + 6*UI */

-	ths_prepare = ns2ddr(70) + 2;

-

-	/* min 145ns + 10*UI */

-	ths_prepare_ths_zero = ns2ddr(175) + 2;

-

-	/* min max(8*UI, 60ns+4*UI) */

-	ths_trail = ns2ddr(60) + 5;

-

-	/* min 100ns */

-	ths_exit = ns2ddr(145);

-

-	/* tlpx min 50n */

-	tlpx_half = ns2ddr(25);

-

-	/* min 60ns */

-	tclk_trail = ns2ddr(60) + 2;

-

-	/* min 38ns, max 95ns */

-	tclk_prepare = ns2ddr(65);

-

-	/* min tclk-prepare + tclk-zero = 300ns */

-	tclk_zero = ns2ddr(260);

-

-	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",

-		ths_prepare, ddr2ns(ths_prepare),

-		ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));

-	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",

-			ths_trail, ddr2ns(ths_trail),

-			ths_exit, ddr2ns(ths_exit));

-

-	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "

-			"tclk_zero %u (%uns)\n",

-			tlpx_half, ddr2ns(tlpx_half),

-			tclk_trail, ddr2ns(tclk_trail),

-			tclk_zero, ddr2ns(tclk_zero));

-	DSSDBG("tclk_prepare %u (%uns)\n",

-			tclk_prepare, ddr2ns(tclk_prepare));

-

-	/* program timings */

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG0);

-	r = FLD_MOD(r, ths_prepare, 31, 24);

-	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);

-	r = FLD_MOD(r, ths_trail, 15, 8);

-	r = FLD_MOD(r, ths_exit, 7, 0);

-	dsi2_write_reg(DSI_DSIPHY_CFG0, 0x0914060F); //sv3

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG1);

-	r = FLD_MOD(r, tlpx_half, 22, 16);

-	r = FLD_MOD(r, tclk_trail, 15, 8);

-	r = FLD_MOD(r, tclk_zero, 7, 0);

-	dsi2_write_reg(DSI_DSIPHY_CFG1, 0x4203061A); //sv3

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG2);

-	r = FLD_MOD(r, tclk_prepare, 7, 0);

-	dsi2_write_reg(DSI_DSIPHY_CFG2, 0xB8000007); //sv3

-}

-

-

-static int dsi2_complexio_init(struct omap_dss_device *dssdev)

-{

-	int r = 0,t = 0;

-

-	DSSDBG("dsi2_complexio_init\n");

-#if 0 //sv3

-	/* CIO_CLK_ICG, enable L3 clk to CIO */

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);

-

-	/* A dummy read using the SCP interface to any DSIPHY register is

-	 * required after DSIPHY reset to complete the reset of the DSI complex

-	 * I/O. */

-	dsi2_read_reg(DSI_DSIPHY_CFG5);

-

-	if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {

-		DSSERR("ComplexIO PHY not coming out of reset.\n");

-		r = -ENODEV;

-		goto err;

-	}

-

-	dsi2_complexio_config(dssdev);

-

-//sv5

-	u32 val = 0;

-

-        // Register 12

-        val = val | (0x58 << 0);

-       dsi2_write_reg(DSI_DSIPHY_CFG12,val);

-

-        // Register 14

-        val = 0;

-        val = val | (1 << 31) |  (0x54 << 23) |  (0x7 << 14);

-	val = FLD_MOD(val,1,31,31);

-	val = FLD_MOD(val,1,11,11);

-	val = FLD_MOD(val,1,19,19);

-	val = FLD_MOD(val,1,18,18);

-	

-       dsi2_write_reg(DSI_DSIPHY_CFG14,val);

-

- 

-        // Register 8

-        val = 0;

-        val = val | (1 << 11) | (16 << 6) | (0xE << 0);

-	val = FLD_MOD(val,1,5,5);

-	dsi2_write_reg(DSI_DSIPHY_CFG8,val);

-//sv5

-	r = dsi2_complexio_power(DSI_COMPLEXIO_POWER_ON);

-

-	if (r)

-		goto err;

-

-	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {

-		DSSERR("ComplexIO not coming out of reset.\n");

-		r = -ENODEV;

-		goto err;

-	}

-//sv5

-#if 0

-	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {

-		DSSERR("ComplexIO LDO power down.\n");

-		r = -ENODEV;

-		goto err;

-	}

-#endif

-//sv5

-	dsi2_complexio_timings();

-

-	/*

-	   The configuration of the DSI complex I/O (number of data lanes,

-	   position, differential order) should not be changed while

-	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the

-	   hardware to recognize a new configuration of the complex I/O (done

-	   in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow

-	   this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next

-	   reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]

-	   LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN

-	   bit to 1. If the sequence is not followed, the DSi complex I/O

-	   configuration is undetermined.

-	   */

-	dsi2_if_enable(1);

-	dsi2_if_enable(0);

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */

-	dsi2_if_enable(1);

-	dsi2_if_enable(0);

-#else

-

-

-	dsi2_complexio_config(dssdev);

-	u32 val = 0;

-

-    	//To do a read of any of the DSIPHY to have a dummy access

-	dsi2_read_reg(DSI_DSIPHY_CFG8); 

-

-	dsi2_complexio_timings();

-

-	/*Set Go bit */

-	REG_FLD_MOD(DSI_COMPLEXIO_CFG1,1,30,30);

-	mdelay(1);

-	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 30, 1) != 1) {

-		DSSERR("ComplexIO PHY not coming out of reset.\n");

-	}

-	mdelay(1);

-

-	dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, 0xFFFFFFFF);

-	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0x0);

-	

-	r = dsi2_complexio_power(DSI_COMPLEXIO_POWER_ON);

-	if (r)

-		DSSERR("ComplexIO PWR ON cmd fail \n");

-

-	/*Set Go bit */

-	REG_FLD_MOD(DSI_COMPLEXIO_CFG1,1,30,30);

-	udelay(100);

-	/* PLL_PWR_STATUS */

-	t = 0;

-	while (FLD_GET(dsi2_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != DSI_COMPLEXIO_POWER_ON) {

-		udelay(100);

-		if (t++ > 1000) {

-			DSSERR("Failed to set DSI PLL power mode to %d\n",

-					DSI_COMPLEXIO_POWER_ON);

-			return -ENODEV;

-		}

-	}

-

-#endif

-	DSSDBG("CIO init done\n");

-err:

-	return r;

-}

-

-static void dsi2_complexio_uninit(void)

-{

-	dsi2_complexio_power(DSI_COMPLEXIO_POWER_OFF);

-}

-

-static int _dsi2_wait_reset(void)

-{

-	int i = 0;

-

-	while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {

-		if (i++ > 5) {

-			DSSERR("soft reset failed\n");

-			return -ENODEV;

-		}

-		udelay(1);

-	}

-

-	return 0;

-}

-

-static int _dsi2_reset(void)

-{

-	/* Soft reset */

-	REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);

-	return _dsi2_wait_reset();

-}

-

-

-static void dsi2_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,

-		enum fifo_size size3, enum fifo_size size4)

-{

-	u32 r = 0;

-	int add = 0;

-	int i;

-

-	dsi2.vc[0].fifo_size = size1;

-	dsi2.vc[1].fifo_size = size2;

-	dsi2.vc[2].fifo_size = size3;

-	dsi2.vc[3].fifo_size = size4;

-

-	for (i = 0; i < 4; i++) {

-		u8 v;

-		int size = dsi2.vc[i].fifo_size;

-

-		if (add + size > 4) {

-			DSSERR("Illegal FIFO configuration\n");

-			BUG();

-		}

-

-		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);

-		r |= v << (8 * i);

-		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */

-		add += size;

-	}

-

-	dsi2_write_reg(DSI_TX_FIFO_VC_SIZE, r);

-}

-

-static void dsi2_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,

-		enum fifo_size size3, enum fifo_size size4)

-{

-	u32 r = 0;

-	int add = 0;

-	int i;

-

-	dsi2.vc[0].fifo_size = size1;

-	dsi2.vc[1].fifo_size = size2;

-	dsi2.vc[2].fifo_size = size3;

-	dsi2.vc[3].fifo_size = size4;

-

-	for (i = 0; i < 4; i++) {

-		u8 v;

-		int size = dsi2.vc[i].fifo_size;

-

-		if (add + size > 4) {

-			DSSERR("Illegal FIFO configuration\n");

-			BUG();

-		}

-

-		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);

-		r |= v << (8 * i);

-		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */

-		add += size;

-	}

-

-	dsi2_write_reg(DSI_RX_FIFO_VC_SIZE, r);

-}

-

-static int dsi2_force_tx_stop_mode_io(void)

-{

-	u32 r;

-

-	r = dsi2_read_reg(DSI_TIMING1);

-	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */

-	dsi2_write_reg(DSI_TIMING1, r);

-

-	if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {

-		DSSERR("TX_STOP bit not going down\n");

-		return -EIO;

-	}

-

-	return 0;

-}

-

-static void dsi2_vc_print_status(int channel)

-{

-	u32 r;

-

-	r = dsi2_read_reg(DSI_VC_CTRL(channel));

-	DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "

-			"TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",

-			channel,

-			FLD_GET(r, 5, 5),

-			FLD_GET(r, 6, 6),

-			FLD_GET(r, 15, 15),

-			FLD_GET(r, 16, 16),

-			FLD_GET(r, 20, 20));

-

-	r = dsi2_read_reg(DSI_TX_FIFO_VC_EMPTINESS);

-	DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);

-}

-

-static int dsi2_vc_enable(int channel, bool enable)

-{

-//sv 	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)

-//sv		DSSDBG("dsi2_vc_enable channel %d, enable %d\n",

-//sv				channel, enable);

-

-	enable = enable ? 1 : 0;

-

-	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);

-#if 0

-	if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {

-			DSSERR("Failed to set dsi2_vc_enable to %d\n", enable);

-			return -EIO;

-	}

-#endif

-	return 0;

-}

-

-static void dsi2_vc_initial_config(int channel)

-{

-	u32 r;

-

-	DSSDBGF("%d", channel);

-

-	r = dsi2_read_reg(DSI_VC_CTRL(channel));

-

-	if (FLD_GET(r, 15, 15)) /* VC_BUSY */

-		DSSERR("VC(%d) busy when trying to configure it!\n",

-				channel);

-

-	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */

-	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */

-	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */

-	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */

-	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */

-	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */

-	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */

-	r = FLD_MOD(r, 3, 11, 10);  //sv5

-	r = FLD_MOD(r, 3, 18, 17);  //sv5

-	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */

-	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */

-

-	dsi2_write_reg(DSI_VC_CTRL(channel), r);

-	dsi2.vc[channel].mode = DSI_VC_MODE_L4;

-}

-

-static void dsi2_vc_config_l4(int channel)

-{

-	if (dsi2.vc[channel].mode == DSI_VC_MODE_L4)

-		return;

-

-	DSSDBGF("%d", channel);

-

-	dsi2_vc_enable(channel, 0);

-

-	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */

-		DSSERR("vc(%d) busy when trying to config for L4\n", channel);

-

-	REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */

-

-	dsi2_vc_enable(channel, 1);

-

-	dsi2.vc[channel].mode = DSI_VC_MODE_L4;

-}

-

-static void dsi2_vc_config_vp(int channel)

-{

-	if (dsi2.vc[channel].mode == DSI_VC_MODE_VP)

-		return;

-

-	DSSDBGF("%d", channel);

-

-	dsi2_vc_enable(channel, 0);

-

-	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */

-		DSSERR("vc(%d) busy when trying to config for VP\n", channel);

-

-	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */

-

-	dsi2_vc_enable(channel, 1);

-

-	dsi2.vc[channel].mode = DSI_VC_MODE_VP;

-}

-

-

-static void dsi2_vc_enable_hs(int channel, bool enable)

-{

-	DSSDBG("dsi2_vc_enable_hs(%d, %d)\n", channel, enable);

-

-	dsi2_vc_enable(channel, 0);

-	dsi2_if_enable(0);

-

-	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);

-

-	dsi2_vc_enable(channel, 1);

-	dsi2_if_enable(1);

-

-	dsi2_force_tx_stop_mode_io();

-}

-

-static void dsi2_vc_flush_long_data(int channel)

-{

-	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {

-		u32 val;

-		val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));

-		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",

-				(val >> 0) & 0xff,

-				(val >> 8) & 0xff,

-				(val >> 16) & 0xff,

-				(val >> 24) & 0xff);

-	}

-}

-

-static void dsi2_show_rx_ack_with_err(u16 err)

-{

-	DSSERR("\tACK with ERROR (%#x):\n", err);

-	if (err & (1 << 0))

-		DSSERR("\t\tSoT Error\n");

-	if (err & (1 << 1))

-		DSSERR("\t\tSoT Sync Error\n");

-	if (err & (1 << 2))

-		DSSERR("\t\tEoT Sync Error\n");

-	if (err & (1 << 3))

-		DSSERR("\t\tEscape Mode Entry Command Error\n");

-	if (err & (1 << 4))

-		DSSERR("\t\tLP Transmit Sync Error\n");

-	if (err & (1 << 5))

-		DSSERR("\t\tHS Receive Timeout Error\n");

-	if (err & (1 << 6))

-		DSSERR("\t\tFalse Control Error\n");

-	if (err & (1 << 7))

-		DSSERR("\t\t(reserved7)\n");

-	if (err & (1 << 8))

-		DSSERR("\t\tECC Error, single-bit (corrected)\n");

-	if (err & (1 << 9))

-		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");

-	if (err & (1 << 10))

-		DSSERR("\t\tChecksum Error\n");

-	if (err & (1 << 11))

-		DSSERR("\t\tData type not recognized\n");

-	if (err & (1 << 12))

-		DSSERR("\t\tInvalid VC ID\n");

-	if (err & (1 << 13))

-		DSSERR("\t\tInvalid Transmission Length\n");

-	if (err & (1 << 14))

-		DSSERR("\t\t(reserved14)\n");

-	if (err & (1 << 15))

-		DSSERR("\t\tDSI Protocol Violation\n");

-}

-

-static u16 dsi2_vc_flush_receive_data(int channel)

-{

-	/* RX_FIFO_NOT_EMPTY */

-	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {

-		u32 val;

-		u8 dt;

-		val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));

-		DSSDBG("\trawval %#08x\n", val);

-		dt = FLD_GET(val, 5, 0);

-		if (dt == DSI_DT_RX_ACK_WITH_ERR) {

-			u16 err = FLD_GET(val, 23, 8);

-			dsi2_show_rx_ack_with_err(err);

-		} else if (dt == DSI_DT_RX_SHORT_READ_1) {

-			DSSDBG("\tDCS short response, 1 byte: %#x\n",

-					FLD_GET(val, 23, 8));

-		} else if (dt == DSI_DT_RX_SHORT_READ_2) {

-			DSSDBG("\tDCS short response, 2 byte: %#x\n",

-					FLD_GET(val, 23, 8));

-		} else if (dt == DSI_DT_RX_DCS_LONG_READ) {

-			DSSDBG("\tDCS long response, len %d\n",

-					FLD_GET(val, 23, 8));

-			dsi2_vc_flush_long_data(channel);

-		} else {

-			DSSERR("\tunknown datatype 0x%02x\n", dt);

-		}

-	}

-	return 0;

-}

-

-static int dsi2_vc_send_bta(int channel)

-{

-	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO &&

-			(dsi2.debug_write || dsi2.debug_read))

-		DSSDBG("dsi2_vc_send_bta %d\n", channel);

-

-	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));

-

-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {	/* RX_FIFO_NOT_EMPTY */

-		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");

-		dsi2_vc_flush_receive_data(channel);

-	}

-

-	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */

-

-	return 0;

-}

-

-int dsi2_vc_send_bta_sync(int channel)

-{

-	int r = 0;

-	u32 err;

-

-	INIT_COMPLETION(dsi2.bta_completion);

-

-	dsi2_vc_enable_bta_irq(channel);

-

-	r = dsi2_vc_send_bta(channel);

-	if (r)

-		goto err;

-

-	if (wait_for_completion_timeout(&dsi2.bta_completion,

-				msecs_to_jiffies(500)) == 0) {

-		DSSERR("Failed to receive BTA\n");

-		r = -EIO;

-		goto err;

-	}

-

-	err = dsi2_get_errors();

-	if (err) {

-		DSSERR("Error while sending BTA: %x\n", err);

-		r = -EIO;

-		goto err;

-	}

-err:

-	dsi2_vc_disable_bta_irq(channel);

-

-	return r;

-}

-EXPORT_SYMBOL(dsi2_vc_send_bta_sync);

-

-static inline void dsi2_vc_write_long_header(int channel, u8 data_type,

-		u16 len, u8 ecc)

-{

-	u32 val;

-	u8 data_id;

-	ecc = 0; //sv5

-	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));

-

-	/*data_id = data_type | channel << 6; */

-	data_id = data_type | dsi2.vc[channel].dest_per << 6;

-

-	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |

-		FLD_VAL(ecc, 31, 24);

-

-	dsi2_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);

-}

-

-static inline void dsi2_vc_write_long_payload(int channel,

-		u8 b1, u8 b2, u8 b3, u8 b4)

-{

-	u32 val;

-

-	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;

-

-/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",

-			b1, b2, b3, b4, val); */

-

-	dsi2_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);

-}

-

-static int dsi2_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,

-		u8 ecc)

-{

-	/*u32 val; */

-	int i;

-	u8 *p;

-	int r = 0;

-	u8 b1, b2, b3, b4;

-	ecc = 0; //sv5

-	

-	if (dsi2.debug_write)

-		DSSDBG("dsi2_vc_send_long, %d bytes\n", len);

-

-

-//sv HS mode

-	printk("we need not come here for send long");

-	/* len + header */

-	if (dsi2.vc[channel].fifo_size * 32 * 4 < len + 4) {

-		DSSERR("unable to send long packet: packet too long.\n");

-		return -EINVAL;

-	}

-	dsi2_vc_config_l4(channel);

-

-	mdelay(2+1);

-	dsi2_vc_write_long_header(channel, data_type, len, ecc);

-

-	/*dsi2_vc_print_status(0); */

-

-	p = data;

-	for (i = 0; i < len >> 2; i++) {

-		if (dsi2.debug_write)

-			DSSDBG("\tsending full packet %d\n", i);

-		/*dsi2_vc_print_status(0); */

-

-		b1 = *p++;

-		b2 = *p++;

-		b3 = *p++;

-		b4 = *p++;

-

-		mdelay(2+1);

-		dsi2_vc_write_long_payload(channel, b1, b2, b3, b4);

-	}

-

-	i = len % 4;

-	if (i) {

-		b1 = 0; b2 = 0; b3 = 0;

-

-		if (dsi2.debug_write)

-			DSSDBG("\tsending remainder bytes %d\n", i);

-

-		switch (i) {

-		case 3:

-			b1 = *p++;

-			b2 = *p++;

-			b3 = *p++;

-			break;

-		case 2:

-			b1 = *p++;

-			b2 = *p++;

-			break;

-		case 1:

-			b1 = *p++;

-			break;

-		}

-

-		mdelay(2+1);

-		dsi2_vc_write_long_payload(channel, b1, b2, b3, 0);

-	}

-

-	return r;

-}

-

-

-#if 0

-int send_short_packet(u8 data_type,u8 vc,u8 data0,u8 data1,bool mode, bool ecc)

-{	u32 val,header=0,count=10000;	

-

-	/* Configure the Virtual Channel */	

-	dsi2_vc_enable(vc,0);

-	/* speed selection (HS or LPS) */	

-	val = dsi2_read_reg(DSI_VC_CTRL(vc));

-	if(mode == 1) //HS MODE

-		{		

-		val = val | (1<<9);	

-		}	

-	else if(mode == 0)	 //LP MODE

-		{		

-		val = val & ~(1<<9);	

-		}	

-	dsi2_write_reg(DSI_VC_CTRL(vc),val);

-	/*TODO: can be do the below step before itself, do we need to disable the DSI interface before configuring the 	 * VCs */

-	//	enable_omap_dsi2_interface();	

-	dsi2_vc_enable(vc,1);

-	/* Send Short packet */	

-	header = (0<<24)|

-			(data1<<16)|		 

-			(data0<<8)|		 

-			(0<<6) |		 

-			(data_type<<0);	

-	dsi2_write_reg(DSI_VC_SHORT_PACKET_HEADER(0),header);

-

-	printk("Header = 0x%x",header);

-

-	do	{		

-		val = dsi2_read_reg(DSI_VC_IRQSTATUS(vc));

-		}while ( (!(val & 0x00000004)) && (--count));	

-	if(count)	{		

-		printk("Short packet  success!!! \n\r");	

-		/*TODO: this need to be cross check, whether we need to reset the bit */		

-		dsi2_write_reg(DSI_VC_IRQSTATUS(vc),0x00000004);

-		return 0;	

-		}	

-	else	{		

-		printk("Failed to send Short packet !!! \n\r");		

-		return -1;	

-		}

-}

-#endif

-

-static int dsi2_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)

-{

-	u32 r;

-	u8 data_id;

-	u32 val, u, count;

-	ecc = 0; //sv5

-	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));

-

-	if (dsi2.debug_write)

-		DSSDBG("dsi2_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",

-				channel,

-				data_type, data & 0xff, (data >> 8) & 0xff);

-

-	dsi2_vc_config_l4(channel);

-

-#if 0 //sv3

-	if (FLD_GET(dsi2_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {

-		DSSERR("ERROR FIFO FULL, aborting transfer\n");

-		return -EINVAL;

-	}

-#endif

-	data_id = data_type | 0 << 6;

-

-	r = (data_id << 0) | (data << 8) | (0 << 16) | (ecc << 24);

-

-	mdelay(2);

-	

-	dsi2_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);

-

-	count = 10000;

-

-	do

-	{

-		val = dsi2_read_reg(DSI_VC_IRQSTATUS(channel));

-		for (u=0;u<100000;u++);

-	}while ( (!(val & 0x4)) && (--count));

-

-

-	if(count)

-	{

-		dsi2_write_reg(DSI_VC_IRQSTATUS(channel),val);

-		printk("short Packet  success");

-		return 0;

-	}

-	else

-	{

-		printk("short Packet sent fail");

-	}

-	

-

-	return 0;

-}

-

-int dsi2_vc_send_null(int channel)

-{

-	u8 nullpkg[] = {0, 0, 0, 0};

-	return dsi2_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);

-}

-EXPORT_SYMBOL(dsi2_vc_send_null);

-

-int dsi2_vc_dcs_write_nosync(int channel, u8 *data, int len)

-{

-	int r = 0;

-

-	BUG_ON(len == 0);

-

-	if (len == 1) {

-		r = dsi2_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,

-				data[0], 0);

-	} else if (len == 2) {

-		r = dsi2_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,

-				data[0] | (data[1] << 8), 0);

-	} else {

-		/* 0x39 = DCS Long Write */

-		r = dsi2_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,

-				data, len, 0);

-	}

-

-	return r;

-}

-EXPORT_SYMBOL(dsi2_vc_dcs_write_nosync);

-

-int dsi2_vc_dcs_write(int channel, u8 *data, int len)

-{

-	int r =0;

-	u32 val;

-	

-	r = dsi2_vc_dcs_write_nosync(channel, data, len);

-#if 0

-	val = dsi2_read_reg(DSI_VC_IRQSTATUS(channel));

-

-	printk(KERN_ERR "Packet IRQ 0x%x",	val);

-	if(val & 0x4)

-		printk(KERN_ERR "Sent", (val&0x4));		

-	if (r)

-		return r;

-#endif

-	/* Some devices need time to process the msg in low power mode.

-	   This also makes the write synchronous, and checks that

-	   the peripheral is still alive */

-//sv3	r = dsi2_vc_send_bta_sync(channel);

-

-	return r;

-}

-EXPORT_SYMBOL(dsi2_vc_dcs_write);

-

-int dsi2_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)

-{

-	u32 val;

-	u8 dt;

-	int r;

-

-	if (dsi2.debug_read)

-		DSSDBG("dsi2_vc_dcs_read(ch%d, dcs_cmd %u)\n", channel, dcs_cmd);

-

-	r = dsi2_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);

-	if (r)

-		return r;

-

-	r = dsi2_vc_send_bta_sync(channel);

-	if (r)

-		return r;

-

-	/* RX_FIFO_NOT_EMPTY */

-	if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {

-		DSSERR("RX fifo empty when trying to read.\n");

-		return -EIO;

-	}

-

-	val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));

-	if (dsi2.debug_read)

-		DSSDBG("\theader: %08x\n", val);

-	dt = FLD_GET(val, 5, 0);

-	if (dt == DSI_DT_RX_ACK_WITH_ERR) {

-		u16 err = FLD_GET(val, 23, 8);

-		dsi2_show_rx_ack_with_err(err);

-		return -EIO;

-

-	} else if (dt == DSI_DT_RX_SHORT_READ_1) {

-		u8 data = FLD_GET(val, 15, 8);

-		if (dsi2.debug_read)

-			DSSDBG("\tDCS short response, 1 byte: %02x\n", data);

-

-		if (buflen < 1)

-			return -EIO;

-

-		buf[0] = data;

-

-		return 1;

-	} else if (dt == DSI_DT_RX_SHORT_READ_2) {

-		u16 data = FLD_GET(val, 23, 8);

-		if (dsi2.debug_read)

-			DSSDBG("\tDCS short response, 2 byte: %04x\n", data);

-

-		if (buflen < 2)

-			return -EIO;

-

-		buf[0] = data & 0xff;

-		buf[1] = (data >> 8) & 0xff;

-

-		return 2;

-	} else if (dt == DSI_DT_RX_DCS_LONG_READ) {

-		int w;

-		int len = FLD_GET(val, 23, 8);

-		if (dsi2.debug_read)

-			DSSDBG("\tDCS long response, len %d\n", len);

-

-		if (len > buflen)

-			return -EIO;

-

-		/* two byte checksum ends the packet, not included in len */

-		for (w = 0; w < len + 2;) {

-			int b;

-			val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));

-			if (dsi2.debug_read)

-				DSSDBG("\t\t%02x %02x %02x %02x\n",

-						(val >> 0) & 0xff,

-						(val >> 8) & 0xff,

-						(val >> 16) & 0xff,

-						(val >> 24) & 0xff);

-

-			for (b = 0; b < 4; ++b) {

-				if (w < len)

-					buf[w] = (val >> (b * 8)) & 0xff;

-				/* we discard the 2 byte checksum */

-				++w;

-			}

-		}

-

-		return len;

-

-	} else {

-		DSSERR("\tunknown datatype 0x%02x\n", dt);

-		return -EIO;

-	}

-}

-EXPORT_SYMBOL(dsi2_vc_dcs_read);

-

-

-int dsi2_vc_set_max_rx_packet_size(int channel, u16 len)

-{

-	return dsi2_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,

-			len, 0);

-}

-EXPORT_SYMBOL(dsi2_vc_set_max_rx_packet_size);

-

-

-static int dsi2_set_lp_rx_timeout(int ns, int x4, int x16)

-{

-	u32 r;

-	unsigned long fck;

-	int ticks;

-

-	/* ticks in DSI_FCK */

-

-	fck = dsi2_fclk_rate();

-	ticks = (fck / 1000 / 1000) * ns / 1000;

-

-	if (ticks > 0x1fff) {

-		DSSERR("LP_TX_TO too high\n");

-		return -EINVAL;

-	}

-

-	r = dsi2_read_reg(DSI_TIMING2);

-	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */

-	r = FLD_MOD(r, x16, 14, 14);	/* LP_RX_TO_X16 */

-	r = FLD_MOD(r, x4, 13, 13);	/* LP_RX_TO_X4 */

-	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */

-	dsi2_write_reg(DSI_TIMING2, r);

-

-	DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",

-			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /

-			(fck / 1000 / 1000),

-			ticks);

-

-	return 0;

-}

-

-static int dsi2_set_ta_timeout(int ns, int x8, int x16)

-{

-	u32 r;

-	unsigned long fck;

-	int ticks;

-

-	/* ticks in DSI_FCK */

-

-	fck = dsi2_fclk_rate();

-	ticks = (fck / 1000 / 1000) * ns / 1000;

-

-	if (ticks > 0x1fff) {

-		DSSERR("TA_TO too high\n");

-		return -EINVAL;

-	}

-

-	r = dsi2_read_reg(DSI_TIMING1);

-	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */

-	r = FLD_MOD(r, x16, 30, 30);	/* TA_TO_X16 */

-	r = FLD_MOD(r, x8, 29, 29);	/* TA_TO_X8 */

-	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */

-	dsi2_write_reg(DSI_TIMING1, r);

-

-//sv3

-	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);

-

-	DSSDBG("TA_TO %ld ns (%#x ticks)\n",

-			(ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /

-			(fck / 1000 / 1000),

-			ticks);

-

-	return 0;

-}

-

-static int dsi2_set_stop_state_counter(int ns, int x4, int x16)

-{

-	u32 r;

-	unsigned long fck;

-	int ticks;

-

-	/* ticks in DSI_FCK */

-

-	fck = dsi2_fclk_rate();

-	ticks = (fck / 1000 / 1000) * ns / 1000;

-

-	if (ticks > 0x1fff) {

-		DSSERR("STOP_STATE_COUNTER_IO too high\n");

-		return -EINVAL;

-	}

-

-	r = dsi2_read_reg(DSI_TIMING1);

-	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */

-	r = FLD_MOD(r, x16, 14, 14);	/* STOP_STATE_X16_IO */

-	r = FLD_MOD(r, x4, 13, 13);	/* STOP_STATE_X4_IO */

-	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */

-	dsi2_write_reg(DSI_TIMING1, r);

-//sv3

-	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);

-

-	DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",

-			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /

-			(fck / 1000 / 1000),

-			ticks);

-

-	return 0;

-}

-

-static int dsi2_set_hs_tx_timeout(int ns, int x4, int x16)

-{

-	u32 r;

-	unsigned long fck;

-	int ticks;

-

-	/* ticks in TxByteClkHS */

-

-	fck = dsi2.ddr_clk / 4;

-	ticks = (fck / 1000 / 1000) * ns / 1000;

-

-	if (ticks > 0x1fff) {

-		DSSERR("HS_TX_TO too high\n");

-		return -EINVAL;

-	}

-

-	r = dsi2_read_reg(DSI_TIMING2);

-	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */

-	r = FLD_MOD(r, x16, 30, 30);	/* HS_TX_TO_X16 */

-	r = FLD_MOD(r, x4, 29, 29);	/* HS_TX_TO_X8 (4 really) */

-	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */

-	dsi2_write_reg(DSI_TIMING2, r);

-

-	DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",

-			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /

-			(fck / 1000 / 1000),

-			ticks);

-

-	return 0;

-}

-static int dsi2_proto_config(struct omap_dss_device *dssdev)

-{

-	u32 r;

-	int buswidth = 0;

-	int div;

-

-	dsi2_config_tx_fifo(DSI_FIFO_SIZE_128,

-			DSI_FIFO_SIZE_0,

-			DSI_FIFO_SIZE_0,

-			DSI_FIFO_SIZE_0);

-

-	dsi2_config_rx_fifo(DSI_FIFO_SIZE_128,

-			DSI_FIFO_SIZE_0,

-			DSI_FIFO_SIZE_0,

-			DSI_FIFO_SIZE_0);

-

-	/* XXX what values for the timeouts? */

-	dsi2_set_stop_state_counter(1000, 0, 0);

-

-	dsi2_set_ta_timeout(50000, 1, 1);

-

-	/* 3000ns * 16 */

-//sv3 	dsi2_set_lp_rx_timeout(3000, 0, 1);

-

-	/* 10000ns * 4 */

-//sv3 	dsi2_set_hs_tx_timeout(10000, 1, 0);

-	dsi2_write_reg(DSI_TIMING2, 0x7FFF7FFF); //sv3

-

-	switch (dssdev->ctrl.pixel_size) {

-	case 16:

-		buswidth = 0;

-		break;

-	case 18:

-		buswidth = 1;

-		break;

-	case 24:

-		buswidth = 2;

-		break;

-	default:

-		BUG();

-	}

-

-	r = dsi2_read_reg(DSI_CTRL);

-//sv3	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */

-//sv3	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */

-	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */

-

-	r = FLD_MOD(r, 1, 11, 11); /*VP_VSYNC_POL */ //sv3

- 	r = FLD_MOD(r, 1, 9, 9); /*VP_DE_POL */ //sv3

-

-

-	/* TODO: Change for LCD2 support */

-	

-	//sv3 div = dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD) /

-		//sv3		dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD);

-	div = 1; //sv3

-	r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4);	/* VP_CLK_RATIO */

-	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */

-	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */

-	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */

-	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */

-//sv3 	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */

-//sv3	r = FLD_MOD(r, 1, 24, 24);	/* DISPC_UPDATE_SYNC*/

-	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */

-

-	dsi2_write_reg(DSI_CTRL, r);

-

-	dsi2_vc_initial_config(0);

-

-	/* set all vc targets to peripheral 0 */

-	dsi2.vc[0].dest_per = 0;

-	dsi2.vc[1].dest_per = 0;

-	dsi2.vc[2].dest_per = 0;

-	dsi2.vc[3].dest_per = 0;

-

-	return 0;

-}

-

-static void dsi2_proto_timings(struct omap_dss_device *dssdev)

-{

-	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;

-	unsigned tclk_pre, tclk_post;

-	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;

-	unsigned ths_trail, ths_exit;

-	unsigned ddr_clk_pre, ddr_clk_post;

-	unsigned enter_hs_mode_lat, exit_hs_mode_lat;

-	unsigned ths_eot;

-	u32 r;

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG0);

-	ths_prepare = FLD_GET(r, 31, 24);

-	ths_prepare_ths_zero = FLD_GET(r, 23, 16);

-	ths_zero = ths_prepare_ths_zero - ths_prepare;

-	ths_trail = FLD_GET(r, 15, 8);

-	ths_exit = FLD_GET(r, 7, 0);

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG1);

-	tlpx = FLD_GET(r, 22, 16) * 2;

-	tclk_trail = FLD_GET(r, 15, 8);

-	tclk_zero = FLD_GET(r, 7, 0);

-

-	r = dsi2_read_reg(DSI_DSIPHY_CFG2);

-	tclk_prepare = FLD_GET(r, 7, 0);

-

-	/* min 8*UI */

-	tclk_pre = 20;

-	/* min 60ns + 52*UI */

-	tclk_post = ns2ddr(60) + 26;

-

-	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */

-	if (dssdev->phy.dsi.data1_lane != 0 &&

-			dssdev->phy.dsi.data2_lane != 0)

-		ths_eot = 2;

-	else

-		ths_eot = 4;

-

-	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,

-			4);

-	ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot;

-

-	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);

-	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);

-

-	ddr_clk_pre = 0xA; 	//sv3

-	ddr_clk_post = 0x9;	//sv3

-	r = dsi2_read_reg(DSI_CLK_TIMING);

-	r = FLD_MOD(r, ddr_clk_pre, 15, 8);

-	r = FLD_MOD(r, ddr_clk_post, 7, 0);

-	dsi2_write_reg(DSI_CLK_TIMING, r);

-

-	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",

-			ddr_clk_pre,

-			ddr_clk_post);

-

-	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +

-		DIV_ROUND_UP(ths_prepare, 4) +

-		DIV_ROUND_UP(ths_zero + 3, 4);

-

-	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;

-	enter_hs_mode_lat = 7; //sv3

-	exit_hs_mode_lat = 9; //sv3

-	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |

-		FLD_VAL(exit_hs_mode_lat, 15, 0);

-	dsi2_write_reg(DSI_VM_TIMING7, r);

-

-	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",

-			enter_hs_mode_lat, exit_hs_mode_lat);

-}

-

-

-#define DSI_DECL_VARS \

-	int __dsi2_cb = 0; u32 __dsi2_cv = 0;

-

-#define DSI_FLUSH(ch) \

-	if (__dsi2_cb > 0) { \

-		/*DSSDBG("sending long packet %#010x\n", __dsi2_cv);*/ \

-		dsi2_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi2_cv); \

-		__dsi2_cb = __dsi2_cv = 0; \

-	}

-

-#define DSI_PUSH(ch, data) \

-	do { \

-		__dsi2_cv |= (data) << (__dsi2_cb * 8); \

-		/*DSSDBG("cv = %#010x, cb = %d\n", __dsi2_cv, __dsi2_cb);*/ \

-		if (++__dsi2_cb > 3) \

-			DSI_FLUSH(ch); \

-	} while (0)

-

-static int dsi2_update_screen_l4(struct omap_dss_device *dssdev,

-			int x, int y, int w, int h)

-{

-	/* Note: supports only 24bit colors in 32bit container */

-	int first = 1;

-	int fifo_stalls = 0;

-	int max_dsi2_packet_size;

-	int max_data_per_packet;

-	int max_pixels_per_packet;

-	int pixels_left;

-	int bytespp = dssdev->ctrl.pixel_size / 8;

-	int scr_width;

-	u32 __iomem *data;

-	int start_offset;

-	int horiz_inc;

-	int current_x;

-	struct omap_overlay *ovl;

-

-	debug_irq = 0;

-

-	DSSDBG("dsi2_update_screen_l4 (%d,%d %dx%d)\n",

-			x, y, w, h);

-

-    int i;

-	ovl = dssdev->manager->overlays[0]; //sv hardcoding of overlays[0] here

-

-	if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)

-		return -EINVAL;

-

-	if (dssdev->ctrl.pixel_size != 24)

-		return -EINVAL;

-

-	scr_width = ovl->info.screen_width;

-	data = ovl->info.vaddr;

-

-	start_offset = scr_width * y + x;

-	horiz_inc = scr_width - w;

-	current_x = x;

-

-	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes

-	 * in fifo */

-

-	/* When using CPU, max long packet size is TX buffer size */

-	max_dsi2_packet_size = dsi2.vc[0].fifo_size * 32 * 4;

-

-	/* we seem to get better perf if we divide the tx fifo to half,

-	   and while the other half is being sent, we fill the other half

-	   max_dsi2_packet_size /= 2; */

-

-	max_data_per_packet = max_dsi2_packet_size - 4 - 1;

-

-	max_pixels_per_packet = max_data_per_packet / bytespp;

-

-	DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);

-

-	pixels_left = w * h;

-

-	DSSDBG("total pixels %d\n", pixels_left);

-

-	data += start_offset;

-

-	while (pixels_left > 0) {

-		/* 0x2c = write_memory_start */

-		/* 0x3c = write_memory_continue */

-		u8 dcs_cmd = first ? 0x2c : 0x3c;

-		int pixels;

-		DSI_DECL_VARS;

-		first = 0;

-

-#if 1

-		/* using fifo not empty */

-		/* TX_FIFO_NOT_EMPTY */

-		while (FLD_GET(dsi2_read_reg(DSI_VC_CTRL(0)), 5, 5)) {

-			udelay(1);

-			fifo_stalls++;

-			if (fifo_stalls > 0xfffff) {

-				DSSERR("fifo stalls overflow, pixels left %d\n",

-						pixels_left);

-				dsi2_if_enable(0);

-				return -EIO;

-			}

-		}

-#elif 1

-		/* using fifo emptiness */

-		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <

-				max_dsi2_packet_size) {

-			fifo_stalls++;

-			if (fifo_stalls > 0xfffff) {

-				DSSERR("fifo stalls overflow, pixels left %d\n",

-					       pixels_left);

-				dsi2_if_enable(0);

-				return -EIO;

-			}

-		}

-#else

-		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {

-			fifo_stalls++;

-			if (fifo_stalls > 0xfffff) {

-				DSSERR("fifo stalls overflow, pixels left %d\n",

-					       pixels_left);

-				dsi2_if_enable(0);

-				return -EIO;

-			}

-		}

-#endif

-		pixels = min(max_pixels_per_packet, pixels_left);

-

-		pixels_left -= pixels;

-

-		dsi2_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,

-				1 + pixels * bytespp, 0);

-

-		DSI_PUSH(0, dcs_cmd);

-

-		while (pixels-- > 0) {

-			u32 pix = __raw_readl(data++);

-

-			DSI_PUSH(0, (pix >> 16) & 0xff);

-			DSI_PUSH(0, (pix >> 8) & 0xff);

-			DSI_PUSH(0, (pix >> 0) & 0xff);

-

-			current_x++;

-			if (current_x == x+w) {

-				current_x = x;

-				data += horiz_inc;

-			}

-		}

-

-		DSI_FLUSH(0);

-	}

-

-	return 0;

-}

-

-static void dsi2_update_screen_dispc(struct omap_dss_device *dssdev,

-		u16 x, u16 y, u16 w, u16 h)

-{

-	int bytespp = dssdev->ctrl.pixel_size / 8;

-	int len;

-	int total_len;

-	int packet_payload;

-	int packet_len;

-	u32 l;

-	bool use_te_trigger;

-	const int channel = 0+1;  //HS mode //sv

-

-	use_te_trigger = dsi2.te_enabled && !dsi2.use_ext_te;

-	if(use_te_trigger)

-		use_te_trigger = 0; //sv HS mode

-

-	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)

-		DSSDBG("dsi2_update_screen_dispc(%d,%d %dx%d)\n",

-				x, y, w, h);

-

-	len = w * h * bytespp;

-

-	/* XXX: one packet could be longer, I think? Line buffer is

-	 * 1024 x 24bits, but we have to put DCS cmd there also.

-	 * 1023 * 3 should work, but causes strange color effects. */

-	packet_payload = min(w, (u16)1020) * bytespp;

-

-	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */

-	total_len = (len / packet_payload) * packet_len;

-

-	if (len % packet_payload)

-		total_len += (len % packet_payload) + 1;

-

-	if (0)

-		dsi2_vc_print_status(1);

-

-	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */

-	dsi2_write_reg(DSI_VC_TE(channel), l);

-

-	dsi2_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);

-

-	if (use_te_trigger)

-		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */

-	else

-		l = FLD_MOD(l, 1, 31, 31); /* TE_START */

-	dsi2_write_reg(DSI_VC_TE(channel), l);

-

-	/* We put SIDLEMODE to no-idle for the duration of the transfer,

-	 * because DSS interrupts are not capable of waking up the CPU and the

-	 * framedone interrupt could be delayed for quite a long time. I think

-	 * the same goes for any DSS interrupts, but for some reason I have not

-	 * seen the problem anywhere else than here.

-	 */

-	dispc_disable_sidle();

-

-	dss_start_update(dssdev);

-

-	if (use_te_trigger) {

-		/* disable LP_RX_TO, so that we can receive TE.  Time to wait

-		 * for TE is longer than the timer allows */

-		REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */

-

-		dsi2_vc_send_bta(channel);

-	}

-}

-

-static void dsi2_framedone_irq_callback(void *data, u32 mask)

-{

-	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and

-	 * turns itself off. However, DSI still has the pixels in its buffers,

-	 * and is sending the data.

-	 */

-

-	/* SIDLEMODE back to smart-idle */

-	dispc_enable_sidle();

-	//sv HS MODE	printk("Framedone IRQ");  

-	udelay(100);

-	dsi2.framedone_received = true;

-	wake_up(&dsi2.waitqueue);

-}

-

-static void dsi2_set_update_region(struct omap_dss_device *dssdev,

-		u16 x, u16 y, u16 w, u16 h)

-{

-	spin_lock(&dsi2.update_lock);

-	if (dsi2.update_region.dirty) {

-		dsi2.update_region.x = min(x, dsi2.update_region.x);

-		dsi2.update_region.y = min(y, dsi2.update_region.y);

-		dsi2.update_region.w = max(w, dsi2.update_region.w);

-		dsi2.update_region.h = max(h, dsi2.update_region.h);

-	} else {

-		dsi2.update_region.x = x;

-		dsi2.update_region.y = y;

-		dsi2.update_region.w = w;

-		dsi2.update_region.h = h;

-	}

-

-	dsi2.update_region.device = dssdev;

-	dsi2.update_region.dirty = true;

-

-	spin_unlock(&dsi2.update_lock);

-

-}

-

-static void dsi2_start_auto_update(struct omap_dss_device *dssdev)

-{

-	u16 w, h;

-	int i;

-

-	DSSDBG("starting auto update\n");

-

-	//sv HS mode set the GFX threshold there properly before apply

-

-	/* In automatic mode the overlay settings are applied like on DPI/SDI.

-	 * Mark the overlays dirty, so that we get the overlays configured, as

-	 * manual mode has left them in bad shape after config partia planes */

-	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {

-		struct omap_overlay *ovl;

-		ovl = omap_dss_get_overlay(i);

-		if (ovl->manager == dssdev->manager)

-			ovl->info_dirty = true;

-		printk(KERN_ERR "ovl[%d]->manager = %s", i, ovl->manager->name);

-	}

-

-	printk(KERN_ERR "dssdev->manager->device->driver_name = %s",dssdev->manager->device->driver_name);	

-	

-	dssdev->manager->apply(dssdev->manager);

-

-	dssdev->get_resolution(dssdev, &w, &h);

-

-	dsi2_set_update_region(dssdev, 0, 0, w, h);

-

-	//sv HS MODE

-//sv	__raw_writel(0x03FC03BC, dispc_base + 0xA4); //DISPC_GFX_THRESHOLD

-

-	dsi2_perf_mark_start_auto();

-

-	wake_up(&dsi2.waitqueue);

-}

-

-static int dsi2_set_te(struct omap_dss_device *dssdev, bool enable)

-{

-	dssdev->driver->enable_te(dssdev, enable);

-	int r;

-	printk(KERN_INFO "\n dsi2_set_te ");

-	r = dssdev->driver->enable_te(dssdev, enable);

-	printk(KERN_INFO "\n dsi2_set_te DONE ");

-	/* XXX for some reason, DSI TE breaks if we don't wait here.

-	 * Panel bug? Needs more studying */

-	msleep(100);

-	return r;

-}

-

-static void dsi2_handle_framedone(void)

-{

-	int r;

-	const int channel = 0;

-	bool use_te_trigger;

-

-	use_te_trigger = dsi2.te_enabled && !dsi2.use_ext_te;

-	if(use_te_trigger)

-		use_te_trigger = 0; //sv HS mode

-

-	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)

-		DSSDBG("FRAMEDONE\n");

-

-	if (use_te_trigger) {

-		/* enable LP_RX_TO again after the TE */

-		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */

-	}

-

-	/* Send BTA after the frame. We need this for the TE to work, as TE

-	 * trigger is only sent for BTAs without preceding packet. Thus we need

-	 * to BTA after the pixel packets so that next BTA will cause TE

-	 * trigger.

-	 *

-	 * This is not needed when TE is not in use, but we do it anyway to

-	 * make sure that the transfer has been completed. It would be more

-	 * optimal, but more complex, to wait only just before starting next

-	 * transfer. */

-#if 0

-	r = dsi2_vc_send_bta_sync(channel);

-	if (r)

-		DSSERR("BTA after framedone failed\n");

-#endif

-#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC

-	dispc_fake_vsync_irq();

-#endif

-}

-

-static int dsi2_update_thread(void *data)

- {

-	unsigned long timeout;

-	struct omap_dss_device *device;

-	u16 x, y, w, h;

-

-	while (1) {

-		bool sched;

-

-		wait_event_interruptible(dsi2.waitqueue,

-				dsi2.update_mode == OMAP_DSS_UPDATE_AUTO ||

-				(dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL &&

-				 dsi2.update_region.dirty == true) ||

-				kthread_should_stop());

-

-		if (kthread_should_stop())

-			break;

-

-		dsi2_bus_lock();

-

-		if (dsi2.update_mode == OMAP_DSS_UPDATE_DISABLED ||

-			kthread_should_stop()) {

-			dsi2_bus_unlock();

-			break;

-		}

-

-		dsi2_perf_mark_setup();

-

-		if (dsi2.update_region.dirty) {

-			spin_lock(&dsi2.update_lock);

-			dsi2.active_update_region = dsi2.update_region;

-			dsi2.update_region.dirty = false;

-			spin_unlock(&dsi2.update_lock);

-		}

-

-		device = dsi2.active_update_region.device;

-		x = dsi2.active_update_region.x;

-		y = dsi2.active_update_region.y;

-		w = dsi2.active_update_region.w;

-		h = dsi2.active_update_region.h;

-

-		if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {

-

-			if (dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL) {

-				dss_setup_partial_planes(device,

-						&x, &y, &w, &h);

-#if 1

-				/* XXX there seems to be a bug in this driver

-				 * or OMAP hardware.  Some updates with certain

-				 * widths and x coordinates fail. These widths

-				 * are always odd, so "fix" it here for now */

-				if (w & 1) {

-					u16 dw, dh;

-					device->get_resolution(device,

-						&dw, &dh);

-					if (x + w == dw)

-						x &= ~1;

-					++w;

-					dss_setup_partial_planes(device,

-							&x, &y, &w, &h);

-				}

-#endif

-			}

-

-			dispc_set_lcd_size(OMAP_DSS_CHANNEL_LCD2, w, h);

-			/* TODO: Correct this while adding support for LCD2 */

-		}

-

-		if (dsi2.active_update_region.dirty) {

-			dsi2.active_update_region.dirty = false;

-			/* XXX TODO we don't need to send the coords, if they

-			 * are the same that are already programmed to the

-			 * panel. That should speed up manual update a bit */

-			device->driver->setup_update(device, x, y, w, h);

-		}

-

-		dsi2_perf_mark_start();

-

-		if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {

-			 //sv HS mode dsi2_vc_config_vp(0+1); //Video mode use channel1 

-			 /*Since we have already configured the VC Ctrl of Video channel */

-

-			if (dsi2.te_enabled && dsi2.use_ext_te)

-				device->driver->wait_for_te(device);

-

-			dsi2.framedone_received = false;

-

-			dsi2_update_screen_dispc(device, x, y, w, h);

-

-			/* wait for framedone */

-			timeout = msecs_to_jiffies(1000);

-			timeout = wait_event_timeout(dsi2.waitqueue,

-					dsi2.framedone_received == true,

-					timeout);

-

-			if (timeout == 0) {

-				DSSERR("dsi2 framedone timeout\n"); //svov3

-				printk("DSS_CONTROL = 0x%x", __raw_readl(dss_base + 0x40) );

-				//svov3 DSSERR("failed update %d,%d %dx%d\n",

-						//svov3 x, y, w, h);

-

-				dispc_enable_sidle();

-				/* TODO: update for LCD2 support */

-				dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 0);

-			} else {

-				dsi2_handle_framedone();

-				dsi2_perf_show("DISPC");

-			}

-		} else {

-			dsi2_update_screen_l4(device, x, y, w, h);

-			dsi2_perf_show("L4");

-		}

-

-		sched = atomic_read(&dsi2.bus_lock.count) < 0;

-

-		complete_all(&dsi2.update_completion);

-

-		dsi2_bus_unlock();

-

-		/* XXX We need to give others chance to get the bus lock. Is

-		 * there a better way for this? */

-	 	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO && sched)

-			schedule_timeout_interruptible(1);

-	}

-

-	DSSDBG("update thread exiting\n");

-

-	return 0;

- }

-

-

-/* Display funcs */

-

-static int dsi2_display_init_dispc(struct omap_dss_device *dssdev)

-{

-	int r;

-

-	r = omap_dispc_register_isr(dsi2_framedone_irq_callback, NULL,

-			DISPC_IRQ_FRAMEDONE);

-	if (r) {

-		DSSERR("can't get FRAMEDONE irq\n");

-		return r;

-	}

-#if 1 //sv3

-	/* TODO: Change here for LCD2 support*/

-	dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD2,

-					OMAP_DSS_LCD_DISPLAY_TFT);

-

-	dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD2,

-					OMAP_DSS_PARALLELMODE_DSI);

-//sv	dispc_enable_fifohandcheck(1);

-

-	dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD2, dssdev->ctrl.pixel_size);

-

-//sv HS mode

-	{

-		struct omap_video_timings timings = {

-			.hsw		= 4+1,

-			.hfp		= 4+1,

-			.hbp		= 4+1,

-			.vsw		= 0+1, //before writing to the register it subtracts 1

-			.vfp		= 0,

-			.vbp		= 1,

-			.x_res	= 864,

-			.y_res	= 480,

-		};

-

-		dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD2, &timings);

-	}

-	dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD2, dssdev->panel.config,

-			dssdev->panel.acbi, dssdev->panel.acb);

-

-	dispc_set_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, 1/*lck_div*/,

-							0x6/*pck_div*/);

-#else

-	/*DISPC_CONTROL = 0x18B48; */

-	/*DISPC_CONFIG = 0x4; */

-	/*DISPC_DIVISOR = 0x10006; */

-

-	__raw_writel(0xb28, dispc_base + 0x238); //DISPC_CONTROL2

-	__raw_readl( dispc_base + 0x00);  //sv

-

-	// __raw_writel(0x0, dispc_base + 0x620); //DISPC_CONFIG2

-	// __raw_readl( dispc_base + 0x00);  //sv

-

-	__raw_writel(0x3fc03bc, dispc_base + 0x38c); //VID3_THRESH

-	__raw_readl( dispc_base + 0x00);  //sv

-

-	__raw_writel(0x1df035f, dispc_base + 0x394); //VID3_PICT_SIZE

-	__raw_readl( dispc_base + 0x00);  //sv

-

-	__raw_writel(0x1df035f, dispc_base + 0x3a8); //VID3_SIZE

-	__raw_readl( dispc_base + 0x00);  //sv

-

-//	__raw_writel(0x1df035f, dispc_base + 0x3cc); //SIZE_LCD2

-//	__raw_readl( dispc_base + 0x00);  //sv

-	

-	__raw_writel(0x40008411, dispc_base + 0x62c); //DISPC_VID3_ATTRIBUTES

-	__raw_readl( dispc_base + 0x00);  //sv

-

-	__raw_writel(0x10006, dispc_base + 0x40c); //DISPC_DIVISOR2

-	__raw_readl( dispc_base + 0x00);  //sv	

-

-	__raw_writel(0x00400404  , dispc_base + 0x400); //DISPC_H2_TIMING

-	__raw_readl( dispc_base + 0x00);  //sv	

-	__raw_writel(0x00100000  , dispc_base + 0x404); //DISPC_V2_TIMING

-	__raw_readl( dispc_base + 0x00);  //sv	

-	__raw_writel(0x30000    , dispc_base + 0x408); //DISPC_V_TIMIPOL_FREQ2

-	__raw_readl( dispc_base + 0x00);  //sv	

-//sv	__raw_writel(0x01DF035F    , dispc_base + 0x7C); //DISPC_SIZE_LCD1

-//sv	__raw_readl( dispc_base + 0x00);  //sv	

-

-	//__raw_writel(0x03FC03BC, dispc_base + 0xA4); //DISPC_GFX_THRESHOLD

-  	__raw_writel(0x1F, dispc_base + 0x3aC); //DISPC_DEF_COLOR2

-

-	__raw_dumpl(DISPC_CONTROL2, dispc_base + 0x238); 

-	__raw_dumpl(VID3_THRESH, dispc_base + 0x38c); 

-	__raw_dumpl(VID3_PICT_SIZE, dispc_base + 0x394); 

-	__raw_dumpl(VID3_SIZE, dispc_base + 0x3a8); 

-	__raw_dumpl(DISPC_VID3_ATTRIBUTES, dispc_base + 0x62c); 

-	__raw_dumpl(DISPC_DIVISOR2, dispc_base + 0x40c); 

-	__raw_dumpl(DISPC_H2_TIMING, dispc_base + 0x400); 

-	__raw_dumpl(DISPC_V2_TIMING, dispc_base + 0x404); 

-	__raw_dumpl(DISPC_V_TIMIPOL_FREQ2, dispc_base + 0x408); 

-	__raw_dumpl(DISPC_DEF_COLOR2, dispc_base + 0x3aC); 

-#endif

-	return 0;

-}

-

-static void dsi2_display_uninit_dispc(struct omap_dss_device *dssdev)

-{

-	omap_dispc_unregister_isr(dsi2_framedone_irq_callback, NULL,

-			DISPC_IRQ_FRAMEDONE);

-}

-

-static int dsi2_display_init_dsi(struct omap_dss_device *dssdev)

-{

-	struct dsi_clock_info cinfo;

-	int r;

-

-	u32 val,l;

-	u32 control_core_base;

-

-	DSSDBG("dsi2_display_init_dsi\n");

-#if 0 //comment everything

-#if 0 //sv3

-	val = dsi2_read_reg(DSI_CLK_CTRL);

-	printk(KERN_INFO "\n DSI_CLK_CONTROL = 0x%X (bit 14 should be 1 ", val);

-	val = val |(1<<14);

-	dsi2_write_reg(DSI_CLK_CTRL, val);

-	val = dsi2_read_reg(DSI_CLK_CTRL);

-	printk(KERN_INFO "\n DSI_CLK_CONTROL = 0x%X (bit 14 should be 1 ", val);

-

-	_dsi2_print_reset_status();

-#else

-

-	omap_writel(0xFFFF0000, 0x4A100618);

-	printk(KERN_INFO "\n CONTROL_DSIPHY = 0x%X ", omap_readl(0x4A100618));

-

-

-	dsi2_if_enable(0);

-	dsi2_vc_enable(0,0); //videochannel

-	dsi2_vc_enable(1,0); //cmdchannel

-

-/*************SIVAL ***************/

-

-	l = dsi2_read_reg(DSI_CLK_CTRL);

-	l = ( l | 

-		(0x2 << 30) | 

-		(0x1 << 21) |

-		(0x1 << 20) |

-		(0x1 << 18));

-	dsi2_write_reg(DSI_CLK_CTRL, l);

-	l = dsi2_read_reg(DSI_CLK_CTRL);

-	l = (l & (~(0x3 << 15)) );

-	dsi2_write_reg(DSI_CLK_CTRL, l);		

-	l = dsi2_read_reg(DSI_CLK_CTRL);

-	l = ( l | 

-		(0x1 << 14) | 

-		(0x1 << 13));

-	dsi2_write_reg(DSI_CLK_CTRL, l);

-

-	printk(KERN_INFO "Checking pll pwr status");

-	/* PLL_PWR_STATUS */

-	while (FLD_GET(dsi2_read_reg(DSI_CLK_CTRL), 29, 28) != 0x2) ;

-

-/***************************************/		

-

-#if 1 //Sival

-

-	/*Config Video port */

-	dsi2_write_reg(DSI_CTRL,0x00006A18);

-

-	/*Config VideoMode Timing */

-	dsi2_write_reg(DSI_CLK_CTRL,0x00346006);

-	dsi2_write_reg(DSI_VM_TIMING1,0x02004006);

-	dsi2_write_reg(DSI_VM_TIMING2,0x04010001);

-	dsi2_write_reg(DSI_VM_TIMING3,0x036F01E0);

-	dsi2_write_reg(DSI_VM_TIMING4,0x00487296);

-	dsi2_write_reg(DSI_VM_TIMING5,0x0082DF3B);

-	dsi2_write_reg(DSI_VM_TIMING6,0x7A6731D1);

-	dsi2_write_reg(DSI_VM_TIMING7,0x00090007);

-

-	/*Config VC channel */

-	dsi2_write_reg(DSI_VC_CTRL(0),0x60809382);  //video channel

-	dsi2_write_reg(DSI_VC_CTRL(1),0x20868D80); //cmd channel

-

-	//Clear all IRQ

-	dsi2_write_reg(DSI_VC_IRQSTATUS(0), 0xFF);

-	dsi2_write_reg(DSI_VC_IRQENABLE(0), 0x0);

-	

-	//Clear all IRQ

-	dsi2_write_reg(DSI_VC_IRQSTATUS(1), 0xFF);

-	dsi2_write_reg(DSI_VC_IRQENABLE(1), 0x0);

-

-	/* Config FIfo size */

-	dsi2_write_reg(DSI_TX_FIFO_VC_SIZE,0x00004040);	

-	dsi2_write_reg(DSI_RX_FIFO_VC_SIZE,0x00001010);

-

-	dsi2_write_reg(DSI_IRQSTATUS, 0x1FFFFF);

-#endif	

-#endif	

-

-	r = dsi2_pll_init(1, 0);

-	if (r)

-		goto err0;

-

-	r = dsi2_pll_calc_ddrfreq(dssdev->phy.dsi.ddr_clk_hz, &cinfo);

-	if (r)

-		goto err1;

-

-	r = dsi2_pll_program(&cinfo);

-	if (r)

-		goto err1;

-

-	DSSDBG("PLL OK\n");

-

-

-//sv3	/*Switch to dsi2 pll DSS_CONTROL Func switch to pll1 for lcd1,dsi1 */

-	val = __raw_readl(dss_base + 0x0040); //DSS_CONTROL

-	val = val | (1<<1) | (1<<0);

-	__raw_writel(val, dss_base + 0x0040); //DSS_CONTROL

-	__raw_readl( dss_base + 0x00);  //sv	

-

-//sv3	/*Switch to dsi2 pll DSS_CONTROL  Func switch to pll1 for dispc */

-	val = __raw_readl(dss_base + 0x0040); //DSS_CONTROL

-	val = val | (1<<8);

-	val = val & (~(1<<9));

-	__raw_writel(val, dss_base + 0x0040); //DSS_CONTROL

-	__raw_readl( dss_base + 0x00);  //sv		

-

-//sv3  /*GO Digital or GO LCd bit to be updated */

-	__raw_writel(0x18B69, dispc_base + 0x0040); //DISPC_CONTROL - Go LCD bit 5

-	__raw_readl( dispc_base + 0x00);  //sv		

-	

-	udelay(100);

-

-	

-	r = dsi2_complexio_init(dssdev);

-	if (r)

-		goto err1;

-#if 0 //sv3

-	_dsi2_print_reset_status();

-

-	dsi2_proto_timings(dssdev);

-

-//sv3

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 13, 13); /* DDR_CLK_ALWAYS_ON*/

-	REG_FLD_MOD(DSI_CLK_CTRL, 1, 18, 18); /* HS_AUTO_STOP_ENABLE*/

-//sv3

-

-	dsi2_set_lp_clk_divisor(dssdev);

-

-	if (1)

-		_dsi2_print_reset_status();

-

-	r = dsi2_proto_config(dssdev);

-	if (r)

-		goto err2;

-#else

-	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);

-	dsi2_vc_enable(1,0);

-	dsi2_vc_enable(1,1);

-	dsi2_write_reg(DSI_TIMING2, 0x7FFF7FFF);

-	dsi2_write_reg(DSI_CLK_TIMING, 0xA09);	

-	udelay(100); //added for trial

-#endif

-	/* enable interface */

-	dsi2_if_enable(1);

-	dsi2_vc_enable(1, 1); //cmd channel

-	dsi2_vc_enable(0, 1);  //video channel

-	dsi2_force_tx_stop_mode_io();

-

-

-	udelay(100); //added for trial

-

-    // Register 12

-    	val = 0;

-       val = val | (0x58 << 0);

-       dsi2_write_reg(DSI_DSIPHY_CFG12,val);

-

-        // Register 14

-        val = 0;

-        val = val | (1 << 31) |  (0x54 << 23) |  (0x7 << 14);

-	val = FLD_MOD(val,1,31,31);

-	val = FLD_MOD(val,1,11,11);

-	val = FLD_MOD(val,1,19,19);

-	val = FLD_MOD(val,1,18,18);

-	

-       dsi2_write_reg(DSI_DSIPHY_CFG14,val);

-

- 

-        // Register 8

-        val = 0;

-        val = val | (1 << 11) | (16 << 6) | (0xE << 0);

-	val = FLD_MOD(val,1,5,5);

-	dsi2_write_reg(DSI_DSIPHY_CFG8,val);

-

-

-

-#if 1 //testing

-	mdelay(100);

-	{

-	volatile int i = 1;

-	while(i){	

-	send_short_packet(0x5,1,0x1,0,0,0);

-	}

-	}

-#endif

-#endif	

-

-	dsi2.vc[0].fifo_size = DSI_FIFO_SIZE_96;

-	dsi2.vc[1].fifo_size = DSI_FIFO_SIZE_128;

-	dsi2.vc[2].fifo_size = DSI_FIFO_SIZE_0;

-	dsi2.vc[3].fifo_size = DSI_FIFO_SIZE_0;

-	

-	Setup_SDP((void *)dsi2.base, 1);

-	if (dssdev->driver->enable) {

-		r = dssdev->driver->enable(dssdev);

-		if (r)

-			goto err3;

-	}

-#if 0 //svov3	

-//sv	/*Enable Lcd interface */

-	val = __raw_readl( dispc_base + 0x238);  //sv

-	val |= (0x1 << 0) | (1 << 5);

-	__raw_writel(val, dispc_base + 0x238); //DISPC_CONTROL  should be 0x18B29 now

-#endif	

-	/* enable high-speed after initial config */

-//sv3	dsi2_vc_enable_hs(0, 1);

-

-	return 0;

-	// MJ

-err3:

-//	dsi2_if_enable(0);

-err2:

-//	dsi2_complexio_uninit();

-err1:

-//	dsi2_pll_uninit();

-err0:

-	return r;

-}

-

-static void dsi2_display_uninit_dsi(struct omap_dss_device *dssdev)

-{

-	if (dssdev->driver->disable)

-		dssdev->driver->disable(dssdev);

-

-	dsi2_complexio_uninit();

-	dsi2_pll_uninit();

-}

-

-static int dsi2_core_init(void)

-{

-	

-	REG_FLD_MOD(DSI_SYSCONFIG, 0, 0, 0);

-

-#if 0

-	/* ENWAKEUP */

-	REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);

-

-	/* SIDLEMODE smart-idle */

-	REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);

-#endif

-	_dsi2_initialize_irq();

-

-	return 0;

-}

-

-#define GPIO_OE		0x134

-#define GPIO_DATAOUT	0x13C

-#define OMAP24XX_GPIO_CLEARDATAOUT	0x190

-#define OMAP24XX_GPIO_SETDATAOUT	0x194

-

-static int dsi2_display_enable(struct omap_dss_device *dssdev)

-{

-	int r = 0, val = 0;

-	

-

-	DSSDBG("dsi2_display_enable\n");

-

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	r = omap_dss_start_device(dssdev);

-	if (r) {

-		DSSERR("failed to start device\n");

-		goto err0;

-	}

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {

-		DSSERR("dssdev already enabled\n");

-		r = -EINVAL;

-		goto err1;

-	}

-

-	

-//sv	enable_clocks(1);

-//sv	dsi2_enable_pll_clock(1);

-

-	omap_writel(0x00030007  , 0x4A307100);  //DSS_PWR_DSS_DSS_CTRL

-

-//sv3  /*GO Digital or GO LCd bit to be updated */

-//sv3  	__raw_writel(0x18B29, dispc_base + 0x0040); //DISPC_CONTROL - LCD en Bit 0

-//sv3  	__raw_writel(0x18B29, dispc_base + 0x0040); //DISPC_CONTROL - Go LCD bit 5

-//sv3  	mdelay(10);

-

-	r = _dsi2_reset();

-	if (r)

-		goto err2;

-/*

-	{

-	volatile int i =1;

-	printk("Doing GPIO reset");

-	while(i)

-	{*/

-#if 0

-	gpio_base_dsi2=ioremap(0x48059000,0x1000);

-

-

-	val = __raw_readl(gpio_base_dsi2+GPIO_OE);

-	val &= ~0x140;

-	__raw_writel(val, gpio_base_dsi2+GPIO_OE);

-

-	mdelay(120);

-

-	/* To output signal high */

-	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);

-	val |= 0x140;

-	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);

-	mdelay(120);

-

-	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_CLEARDATAOUT);

-	val |= 0x140;

-	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_CLEARDATAOUT);

-	mdelay(120);

-

-	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);

-	val |= 0x140;

-	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);

-

-	mdelay(120);

-//		}

-//		}

-	printk("GPIO 104 reset done ");

-	

-#endif	

-#if 0

-	*(volatile int*)(GPIO_OE) = (*(volatile int*)(GPIO_OE) & ~0x40);

-	/* To output signal high */

-	*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) =

-			(*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) | 0x40);

-	mdelay(10);

-	/* To output signal low */

-	*(volatile int*)(OMAP24XX_GPIO_CLEARDATAOUT) =

-			(*(volatile int*)(OMAP24XX_GPIO_CLEARDATAOUT) | 0x40);

-	mdelay(10);

-	/* To output signal high */

-	*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) =

-			(*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) | 0x40);

-	mdelay(10);

-#endif

-	

-#if 0 //comment everything	

-	dsi2_core_init();

-#if 0

-	dsi2_write_reg(DSI_SYSCONFIG, 0x10);

-#endif

-#endif

-#if 1

-	r = dsi2_display_init_dispc(dssdev);

-	if (r)

-		goto err2;

-

-	r = dsi2_display_init_dsi(dssdev);

-	if (r)

-		goto err3;

-

-

-	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;

-

-	dsi2.use_ext_te = dssdev->phy.dsi.ext_te;

-	r = dsi2_set_te(dssdev, dsi2.te_enabled);

-	if (r)

-		goto err3;

-

-	dsi2.user_update_mode = OMAP_DSS_UPDATE_AUTO; //svov3

-	dsi2.update_mode = dsi2.user_update_mode;

-	

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO)

-		dsi2_start_auto_update(dssdev);

-

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-#endif

-

-#if 0 //svov3 not a good one

-	printk("DSI2_PLL %x\n", __raw_readl(dsi2_base+0x304));

-	//printk("DSI_PLL %x\n", __raw_readl(dsi2_base+0x304));

-

-	val = __raw_readl(dss_base+0x40);

-	val |= 0x1503;

-	__raw_writel(val, dss_base+0x40);

-	printk("DSS_STATUS %x\n", __raw_readl(dss_base+0x5c));

-#endif

-	return 0;

-// MJ

-err3:

-//	dsi2_display_uninit_dispc(dssdev);

-err2:

-//	enable_clocks(0);

-//	dsi2_enable_pll_clock(0);

-err1:

-//	omap_dss_stop_device(dssdev);

-err0:

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-	DSSDBG("dsi2_display_enable FAILED\n");

-	return 0; //r

-

-

-}

-

-static void dsi2_display_disable(struct omap_dss_device *dssdev)

-{

-	DSSDBG("dsi2_display_disable\n");

-

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||

-			dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)

-		goto end;

-

-	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;

-	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;

-

-	dsi2_display_uninit_dispc(dssdev);

-

-	dsi2_display_uninit_dsi(dssdev);

-

-	enable_clocks(0);

-	dsi2_enable_pll_clock(0);

-

-	omap_dss_stop_device(dssdev);

-end:

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-}

-

-static int dsi2_display_suspend(struct omap_dss_device *dssdev)

-{

-	DSSDBG("dsi2_display_suspend\n");

-#if 0 //svov3

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||

-			dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)

-		goto end;

-

-	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;

-	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;

-

-	dsi2_display_uninit_dispc(dssdev);

-

-	dsi2_display_uninit_dsi(dssdev);

-

-	enable_clocks(0);

-	dsi2_enable_pll_clock(0);

-end:

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-#endif

-	return 0;

-}

-

-static int dsi2_display_resume(struct omap_dss_device *dssdev)

-{

-	int r = 0;

-

-	DSSDBG("dsi2_display_resume\n");

-#if 0 //svov3

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {

-		DSSERR("dssdev not suspended\n");

-		r = -EINVAL;

-		goto err0;

-	}

-

-	enable_clocks(1);

-	dsi2_enable_pll_clock(1);

-

-	r = _dsi2_reset();

-	if (r)

-		goto err1;

-

-	dsi2_core_init();

-

-	r = dsi2_display_init_dispc(dssdev);

-	if (r)

-		goto err1;

-

-	r = dsi2_display_init_dsi(dssdev);

-	if (r)

-		goto err2;

-

-	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;

-

-	r = dsi2_set_te(dssdev, dsi2.te_enabled);

-	if (r)

-		goto err2;

-

-	dsi2.update_mode = dsi2.user_update_mode;

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO)

-		dsi2_start_auto_update(dssdev);

-

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-

-	return 0;

-

-err2:

-	dsi2_display_uninit_dispc(dssdev);

-err1:

-	enable_clocks(0);

-	dsi2_enable_pll_clock(0);

-err0:

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-	DSSDBG("dsi2_display_resume FAILED\n");

-#endif

-	return r;

-}

-

-static int dsi2_display_update(struct omap_dss_device *dssdev,

-			u16 x, u16 y, u16 w, u16 h)

-{

-	int r = 0;

-	u16 dw, dh;

-

-	DSSDBG("dsi2_display_update(%d,%d %dx%d)\n", x, y, w, h);

-

-	mutex_lock(&dsi2.lock);

-

-	if (dsi2.update_mode != OMAP_DSS_UPDATE_MANUAL)

-		goto end;

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)

-		goto end;

-

-	dssdev->get_resolution(dssdev, &dw, &dh);

-

-	if  (x > dw || y > dh)

-		goto end;

-

-	if (x + w > dw)

-		w = dw - x;

-

-	if (y + h > dh)

-		h = dh - y;

-

-	if (w == 0 || h == 0)

-		goto end;

-

-	dsi2_set_update_region(dssdev, x, y, w, h);

-

-	wake_up(&dsi2.waitqueue);

-

-end:

-	mutex_unlock(&dsi2.lock);

-

-	return r;

-}

-

-static int dsi2_display_sync(struct omap_dss_device *dssdev)

-{

-	bool wait;

-

-	DSSDBG("dsi2_display_sync()\n");

-

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL &&

-			dsi2.update_region.dirty) {

-		INIT_COMPLETION(dsi2.update_completion);

-		wait = true;

-	} else {

-		wait = false;

-	}

-

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-

-	if (wait)

-		wait_for_completion_interruptible(&dsi2.update_completion);

-

-	DSSDBG("dsi2_display_sync() done\n");

-	return 0;

-}

-

-static int dsi2_display_set_update_mode(struct omap_dss_device *dssdev,

-		enum omap_dss_update_mode mode)

-{

-	DSSDBGF("%d", mode);

-	

-	mutex_lock(&dsi2.lock);

-	dsi2_bus_lock();

-

-	if (dsi2.update_mode != mode) {

-		dsi2.user_update_mode = mode;

-		dsi2.update_mode = mode;

-

-		if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&

-				mode == OMAP_DSS_UPDATE_AUTO)

-			dsi2_start_auto_update(dssdev);

-	}

-

-	dsi2_bus_unlock();

-	mutex_unlock(&dsi2.lock);

-

-	return 0;

-}

-

-static enum omap_dss_update_mode dsi2_display_get_update_mode(

-		struct omap_dss_device *dssdev)

-{

-	return dsi2.update_mode;

-}

-

-

-static int dsi2_display_enable_te(struct omap_dss_device *dssdev, bool enable)

-{

-	int r = 0;

-	DSSDBGF("%d", enable);

-

-	if (!dssdev->driver->enable_te)

-		return -ENOENT;

-

-	dsi2_bus_lock();

-

-	dsi2.te_enabled = enable;

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)

-		goto end;

-

-	r = dsi2_set_te(dssdev, enable);

-end:

-	dsi2_bus_unlock();

-

-	return r;

-}

-

-static int dsi2_display_get_te(struct omap_dss_device *dssdev)

-{

-	return dsi2.te_enabled;

-}

-

-static int dsi2_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)

-{

-

-	DSSDBGF("%d", rotate);

-

-	if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)

-		return -EINVAL;

-

-	dsi2_bus_lock();

-	dssdev->driver->set_rotate(dssdev, rotate);

-	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO) {

-		u16 w, h;

-		/* the display dimensions may have changed, so set a new

-		 * update region */

-		dssdev->get_resolution(dssdev, &w, &h);

-		dsi2_set_update_region(dssdev, 0, 0, w, h);

-	}

-	dsi2_bus_unlock();

-

-	return 0;

-}

-

-static u8 dsi2_display_get_rotate(struct omap_dss_device *dssdev)

-{

-	if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)

-		return 0;

-

-	return dssdev->driver->get_rotate(dssdev);

-}

-

-static int dsi2_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)

-{

-	DSSDBGF("%d", mirror);

-

-	if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)

-		return -EINVAL;

-

-	dsi2_bus_lock();

-	dssdev->driver->set_mirror(dssdev, mirror);

-	dsi2_bus_unlock();

-

-	return 0;

-}

-

-static bool dsi2_display_get_mirror(struct omap_dss_device *dssdev)

-{

-	if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)

-		return 0;

-

-	return dssdev->driver->get_mirror(dssdev);

-}

-

-static int dsi2_display_run_test(struct omap_dss_device *dssdev, int test_num)

-{

-	int r;

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)

-		return -EIO;

-

-	DSSDBGF("%d", test_num);

-

-	dsi2_bus_lock();

-

-	/* run test first in low speed mode */

-	dsi2_vc_enable_hs(0, 0);

-

-	if (dssdev->driver->run_test) {

-		r = dssdev->driver->run_test(dssdev, test_num);

-		if (r)

-			goto end;

-	}

-

-	/* then in high speed */

-	dsi2_vc_enable_hs(0, 1);

-

-	if (dssdev->driver->run_test) {

-		r = dssdev->driver->run_test(dssdev, test_num);

-		if (r)

-			goto end;

-	}

-

-end:

-	dsi2_vc_enable_hs(0, 1);

-

-	dsi2_bus_unlock();

-

-	return r;

-}

-

-static int dsi2_display_memory_read(struct omap_dss_device *dssdev,

-		void *buf, size_t size,

-		u16 x, u16 y, u16 w, u16 h)

-{

-	int r;

-

-	DSSDBGF("");

-

-	if (!dssdev->driver->memory_read)

-		return -EINVAL;

-

-	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)

-		return -EIO;

-

-	dsi2_bus_lock();

-

-	r = dssdev->driver->memory_read(dssdev, buf, size,

-			x, y, w, h);

-

-	dsi2_bus_unlock();

-

-	return r;

-}

-

-void dsi2_get_overlay_fifo_thresholds(enum omap_plane plane,

-		u32 fifo_size, enum omap_burst_size *burst_size,

-		u32 *fifo_low, u32 *fifo_high)

-{

-	unsigned burst_size_bytes;

-#ifndef CONFIG_ARCH_OMAP4

-	*burst_size = OMAP_DSS_BURST_16x32;

-	burst_size_bytes = 16 * 32 / 8;

-	*fifo_high = fifo_size - burst_size_bytes;

-	*fifo_low = 0;

-#else

-	*burst_size = OMAP_DSS_BURST_4x32; /* OMAP4: same as 2x128*/

-	burst_size_bytes = 2 * 128 / 8;

-	*fifo_high = 1020; /* check SV comment*/

-	*fifo_low = 956;

-#endif

-}

-

-int dsi2_init_display(struct omap_dss_device *dssdev)

-{

-	DSSDBG("DSI2 init\n");

-

-	dssdev->enable = dsi2_display_enable;

-	dssdev->disable = dsi2_display_disable;

-	dssdev->suspend = dsi2_display_suspend;

-	dssdev->resume = dsi2_display_resume;

-	dssdev->update = dsi2_display_update;

-	dssdev->sync = dsi2_display_sync;

-	dssdev->set_update_mode = dsi2_display_set_update_mode;

-	dssdev->get_update_mode = dsi2_display_get_update_mode;

-	dssdev->enable_te = dsi2_display_enable_te;

-	dssdev->get_te = dsi2_display_get_te;

-

-	dssdev->get_rotate = dsi2_display_get_rotate;

-	dssdev->set_rotate = dsi2_display_set_rotate;

-

-	dssdev->get_mirror = dsi2_display_get_mirror;

-	dssdev->set_mirror = dsi2_display_set_mirror;

-

-	dssdev->run_test = dsi2_display_run_test;

-	dssdev->memory_read = dsi2_display_memory_read;

-

-	dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;

-

-	dsi2.vc[0].dssdev = dssdev;

-	dsi2.vc[1].dssdev = dssdev;

-

-	return 0;

-}

-

-int dsi2_init(struct platform_device *pdev)

-{

-	u32 rev,ret, val;

-	void __iomem  *gpio1_base, *gpio2_base;

-    struct sched_param param = {

-		.sched_priority = MAX_USER_RT_PRIO-1

-	};

-

-	spin_lock_init(&dsi2.errors_lock);

-	dsi2.errors = 0;

-

-	/* XXX fail properly */

-

-	init_completion(&dsi2.bta_completion);

-	init_completion(&dsi2.update_completion);

-

-	dsi2.thread = kthread_create(dsi2_update_thread, NULL, "dsi2");

-	if (IS_ERR(dsi2.thread)) {

-		DSSERR("cannot create kthread\n");

-		return PTR_ERR(dsi2.thread);

-	}

-	sched_setscheduler(dsi2.thread, SCHED_FIFO, &param);

-

-	init_waitqueue_head(&dsi2.waitqueue);

-	spin_lock_init(&dsi2.update_lock);

-

-	mutex_init(&dsi2.lock);

-	mutex_init(&dsi2.bus_lock);

-

-	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;

-	dsi2.user_update_mode = OMAP_DSS_UPDATE_DISABLED;

-

-	dsi2_base = dsi2.base = ioremap(DSI2_BASE, 2000);// MJ DSI_SZ_REGS);

-	printk("dsi2 dss_base = 0x%x, dispc_base = 0x%x, dsi2_base = 0x%x",dss_base,dispc_base,dsi2_base);

-	if (!dsi2.base) {

-		DSSERR("can't ioremap DSI\n");

-		return -ENOMEM;

-	}

-#if 0

-	ret = twl_i2c_write_u8(TWL6030_MODULE_PWM, 0xFF, PWM2ON); //0xBD = 0xFF

-	ret = twl_i2c_write_u8(TWL6030_MODULE_PWM, 0x7F, PWM2OFF); //0xBE = 0x7F

-	ret = twl_i2c_write_u8(TWL6030_MODULE_AUX, 0x30, TOGGLE3);

-/*

-	dsi2.vdds_dsi2_reg = regulator_get(&pdev->dev, "vdds_dsi");

-	if (IS_ERR(dsi2.vdds_dsi2_reg)) {

-		iounmap(dsi2.base);

-		DSSERR("can't get VDDS_DSI regulator\n");

-		return PTR_ERR(dsi2.vdds_dsi2_reg);

-	}

-*/

-

-	gpio1_base=ioremap(0x4a310000,0x1000);

-	gpio2_base=ioremap(0x48055000,0x1000);

-	rev = __raw_readl(gpio2_base+GPIO_OE);	

-	rev &= ~(1<<27);	

-	__raw_writel(rev, gpio2_base+GPIO_OE);	

-	/* To output signal low */	

-	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);

-	rev |= (1<<27);

-	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);

-	mdelay(120);	

-	/* To output signal high */	

-	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_SETDATAOUT);	

-	rev |= (1<<27);	

-	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_SETDATAOUT);	

-	mdelay(120);	

-	/* To output signal low */	

-	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);

-	rev |= (1<<27);

-	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);	

-	mdelay(120);	

-	rev = __raw_readl(gpio1_base+GPIO_OE);	rev &= ~(1<<27);

-	__raw_writel(rev, gpio1_base+GPIO_OE);	mdelay(120);	

-	/* To output signal high */

-	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_SETDATAOUT);

-	rev |= (1<<27);	

-	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_SETDATAOUT);

-	mdelay(120);	

-	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_CLEARDATAOUT);

-	rev |= (1<<27);

-	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_CLEARDATAOUT);

-	mdelay(120);

-	/* To output signal high */	

-	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_SETDATAOUT);

-	rev |= (1<<27);	

-	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_SETDATAOUT);

-	mdelay(120);

-#endif

-

-	enable_clocks(1);

-

-	rev = dsi2_read_reg(DSI_REVISION);

-	printk(KERN_INFO "OMAP DSI2 rev %d.%d\n",

-	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

-

-	enable_clocks(0);

-

-	wake_up_process(dsi2.thread);

-

-	return 0;

-}

-

-void dsi2_exit(void)

-{

-	kthread_stop(dsi2.thread);

-

-	//regulator_put(dsi.vdds_dsi_reg);

-

-	iounmap(dsi2.base);

-

-	DSSDBG("omap_dsi2_exit\n");

-}

-

+/*
+ * linux/drivers/video/omap2/dss/dsi2.c
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define __raw_dumpl(n, x) printk(KERN_ERR "(x%08x) = x%08x { " #n ":" #x "\n", x, __raw_readl(x))
+
+#define DSS_SUBSYS_NAME "DSI"
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/seq_file.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/kthread.h>
+#include <linux/wait.h>
+
+#include <mach/board.h>
+#include <mach/display.h>
+#include <mach/clock.h>
+
+#include <linux/i2c/twl.h>
+
+#include "dss.h"
+
+/*#define VERBOSE_IRQ*/
+
+#define DSI2_BASE		0x58005000
+
+struct dsi2_reg { u16 idx; };
+
+#define DSI_REG(idx)		((const struct dsi2_reg) { idx })
+
+#define DSI_SZ_REGS		SZ_1K
+/* DSI Protocol Engine */
+
+#define DSI_REVISION			DSI_REG(0x0000)
+#define DSI_SYSCONFIG			DSI_REG(0x0010)
+#define DSI_SYSSTATUS			DSI_REG(0x0014)
+#define DSI_IRQSTATUS			DSI_REG(0x0018)
+#define DSI_IRQENABLE			DSI_REG(0x001C)
+#define DSI_CTRL			DSI_REG(0x0040)
+#define DSI_GNQ					DSI_REG(0x0044) // MJ
+#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)
+#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)
+#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)
+#define DSI_CLK_CTRL			DSI_REG(0x0054)
+#define DSI_TIMING1			DSI_REG(0x0058)
+#define DSI_TIMING2			DSI_REG(0x005C)
+#define DSI_VM_TIMING1			DSI_REG(0x0060)
+#define DSI_VM_TIMING2			DSI_REG(0x0064)
+#define DSI_VM_TIMING3			DSI_REG(0x0068)
+#define DSI_CLK_TIMING			DSI_REG(0x006C)
+#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)
+#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)
+#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)
+#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)
+#define DSI_VM_TIMING4			DSI_REG(0x0080)
+#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)
+#define DSI_VM_TIMING5			DSI_REG(0x0088)
+#define DSI_VM_TIMING6			DSI_REG(0x008C)
+#define DSI_VM_TIMING7			DSI_REG(0x0090)
+#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)
+#ifdef CONFIG_ARCH_OMAP4
+#define DSI_CTRL2						DSI_REG(0x0098) // MJ
+#define DSI_VM_TIMING8					DSI_REG(0x009C) // MJ
+
+#define DSI_TE_HSYNC_WIDTH(n)			DSI_REG(0x00A0 + (n * 0xC)) // MJ
+#define DSI_TE_VSYNC_WIDTH(n)			DSI_REG(0x00A4 + (n * 0xC)) // MJ
+
+#define DSI_TE_HSYNC_NUMBER(n)			DSI_REG(0x00A8 + (n * 0xC)) // MJ
+#endif
+#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))
+#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))
+#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))
+#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))
+#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))
+#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))
+#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))
+
+/* DSIPHY_SCP */
+
+#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)
+#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)
+#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
+#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
+
+#ifdef CONFIG_ARCH_OMAP4
+#define DSI_DSIPHY_CFG12			DSI_REG(0x200 + 0x0030)
+#define DSI_DSIPHY_CFG14			DSI_REG(0x200 + 0x0038)
+#define DSI_DSIPHY_CFG8			DSI_REG(0x200 + 0x0020)
+#define DSI_DSIPHY_CFG9			DSI_REG(0x200 + 0x0024)
+#endif
+/* DSI_PLL_CTRL_SCP */
+
+#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
+#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)
+#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)
+#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
+#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)
+#ifdef CONFIG_ARCH_OMAP4
+#define DSI_PLL_CONFIGURATION3		DSI_REG(0x300 + 0x0014)
+#define DSI_SSC_CONFIGURATION1		DSI_REG(0x300 + 0x0018)
+#define DSI_SSC_CONFIGURATION2		DSI_REG(0x300 + 0x001C)
+#define DSI_SSC_CONFIGURATION4		DSI_REG(0x300 + 0x0020)
+#endif
+
+#define REG_GET(idx, start, end) \
+	FLD_GET(dsi2_read_reg(idx), start, end)
+
+#define REG_FLD_MOD(idx, val, start, end) \
+	dsi2_write_reg(idx, FLD_MOD(dsi2_read_reg(idx), val, start, end))
+
+/* Global interrupts */
+#define DSI_IRQ_VC0		(1 << 0)
+#define DSI_IRQ_VC1		(1 << 1)
+#define DSI_IRQ_VC2		(1 << 2)
+#define DSI_IRQ_VC3		(1 << 3)
+#define DSI_IRQ_WAKEUP		(1 << 4)
+#define DSI_IRQ_RESYNC		(1 << 5)
+#define DSI_IRQ_PLL_LOCK	(1 << 7)
+#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
+#define DSI_IRQ_PLL_RECALL	(1 << 9)
+#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
+#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
+#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
+#define DSI_IRQ_TE_TRIGGER	(1 << 16)
+#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
+#define DSI_IRQ_SYNC_LOST	(1 << 18)
+#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
+#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
+#define DSI_IRQ_ERROR_MASK \
+	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
+	DSI_IRQ_TA_TIMEOUT)
+#define DSI_IRQ_CHANNEL_MASK	0xf
+
+/* Virtual channel interrupts */
+#define DSI_VC_IRQ_CS		(1 << 0)
+#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
+#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
+#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
+#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
+#define DSI_VC_IRQ_BTA		(1 << 5)
+#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
+#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
+#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
+#define DSI_VC_IRQ_ERROR_MASK \
+	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
+	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
+	DSI_VC_IRQ_FIFO_TX_UDF)
+
+/* ComplexIO interrupts */
+#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
+#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
+#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
+#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
+#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
+#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
+#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
+#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
+#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
+#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
+#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
+#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
+#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
+
+#define DSI_DT_DCS_SHORT_WRITE_0	0x05
+#define DSI_DT_DCS_SHORT_WRITE_1	0x15
+#define DSI_DT_DCS_READ			0x06
+#define DSI_DT_SET_MAX_RET_PKG_SIZE	0x37
+#define DSI_DT_NULL_PACKET		0x09
+#define DSI_DT_DCS_LONG_WRITE		0x39
+
+#define DSI_DT_RX_ACK_WITH_ERR		0x02
+#define DSI_DT_RX_DCS_LONG_READ		0x1c
+#define DSI_DT_RX_SHORT_READ_1		0x21
+#define DSI_DT_RX_SHORT_READ_2		0x22
+
+#define FINT_MAX 2100000
+#define FINT_MIN 750000
+#define REGN_MAX (1 << 7)
+#define REGM_MAX ((1 << 11) - 1)
+#define REGM3_MAX (1 << 4)
+#define REGM4_MAX (1 << 4)
+
+#ifdef CONFIG_ARCH_OMAP4
+extern void __iomem  *dss_base;
+extern void __iomem  *dispc_base;
+
+void __iomem  *dsi2_base;
+#define PWM2ON		3
+#define PWM2OFF		4
+#define TOGGLE3		2
+#define PWDNSTATUS2	4
+#endif
+enum fifo_size {
+	DSI_FIFO_SIZE_0		= 0,
+	DSI_FIFO_SIZE_32	= 1,
+	DSI_FIFO_SIZE_64	= 2,
+	DSI_FIFO_SIZE_96	= 3,
+	DSI_FIFO_SIZE_128	= 4,
+};
+
+enum dsi2_vc_mode {
+	DSI_VC_MODE_L4 = 0,
+	DSI_VC_MODE_VP,
+};
+
+struct dsi2_update_region {
+	bool dirty;
+	u16 x, y, w, h;
+	struct omap_dss_device *device;
+};
+
+static struct
+{
+	void __iomem	*base;
+
+	unsigned long	dsi1_pll_fclk;	/* Hz */
+	unsigned long	dsi2_pll_fclk;	/* Hz */
+	unsigned long	dsiphy;		/* Hz */
+	unsigned long	ddr_clk;	/* Hz */
+
+/*	struct regulator *vdds_dsi_reg; */
+
+	struct {
+		enum dsi2_vc_mode mode;
+		struct omap_dss_device *dssdev;
+		enum fifo_size fifo_size;
+		int dest_per;	/* destination peripheral 0-3 */
+	} vc[4];
+
+	struct mutex lock;
+	struct mutex bus_lock;
+
+	unsigned pll_locked;
+
+	struct completion bta_completion;
+
+	struct task_struct *thread;
+	wait_queue_head_t waitqueue;
+
+	spinlock_t update_lock;
+	bool framedone_received;
+	struct dsi2_update_region update_region;
+	struct dsi2_update_region active_update_region;
+	struct completion update_completion;
+
+	enum omap_dss_update_mode user_update_mode;
+	enum omap_dss_update_mode update_mode;
+	bool te_enabled;
+	bool use_ext_te;
+
+	unsigned long cache_req_pck;
+	unsigned long cache_clk_freq;
+	struct dsi_clock_info cache_cinfo;
+
+	u32		errors;
+	spinlock_t	errors_lock;
+#ifdef DEBUG
+	ktime_t perf_setup_time;
+	ktime_t perf_start_time;
+	ktime_t perf_start_time_auto;
+	int perf_measure_frames;
+#endif
+	int debug_read;
+	int debug_write;
+} dsi2;
+
+#ifdef DEBUG
+static unsigned int dsi2_perf;
+module_param_named(dsi2_perf, dsi2_perf, bool, 0644);
+#endif
+
+extern void Setup_SDP(void *, int);
+
+static inline void dsi2_write_reg(const struct dsi2_reg idx, u32 val)
+{
+	__raw_writel(val, dsi2.base + idx.idx);
+	__raw_readl(dsi2.base + 0x00);	//sv5
+}
+
+static inline u32 dsi2_read_reg(const struct dsi2_reg idx)
+{
+	return __raw_readl(dsi2.base + idx.idx);
+}
+
+
+void dsi2_save_context(void)
+{
+}
+
+void dsi2_restore_context(void)
+{
+}
+
+void dsi2_bus_lock(void)
+{
+	mutex_lock(&dsi2.bus_lock);
+}
+EXPORT_SYMBOL(dsi2_bus_lock);
+
+void dsi2_bus_unlock(void)
+{
+	mutex_unlock(&dsi2.bus_lock);
+}
+EXPORT_SYMBOL(dsi2_bus_unlock);
+
+static inline int wait_for_bit_change_delay(const struct dsi2_reg idx, int bitnum,
+		int value,int delay)
+{
+	int t = 100000;
+
+	while (REG_GET(idx, bitnum, bitnum) != value) {
+		udelay(delay);
+		if (--t == 0)
+			return !value;
+	}
+
+	return value;
+}
+
+static inline int wait_for_bit_change(const struct dsi2_reg idx, int bitnum,
+		int value)
+{
+	int t = 100000;
+
+	while (REG_GET(idx, bitnum, bitnum) != value) {
+		if (--t == 0)
+			return !value;
+	}
+
+	return value;
+}
+
+#ifdef DEBUG
+static void dsi2_perf_mark_setup(void)
+{
+	dsi2.perf_setup_time = ktime_get();
+}
+
+static void dsi2_perf_mark_start(void)
+{
+	dsi2.perf_start_time = ktime_get();
+}
+
+static void dsi2_perf_mark_start_auto(void)
+{
+	dsi2.perf_measure_frames = 0;
+	dsi2.perf_start_time_auto = ktime_get();
+}
+
+static void dsi2_perf_show(const char *name)
+{
+	ktime_t t, setup_time, trans_time;
+	u32 total_bytes;
+	u32 setup_us, trans_us, total_us;
+
+	if (!dsi2_perf)
+		return;
+
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_DISABLED)
+		return;
+
+	t = ktime_get();
+
+	setup_time = ktime_sub(dsi2.perf_start_time, dsi2.perf_setup_time);
+	setup_us = (u32)ktime_to_us(setup_time);
+	if (setup_us == 0)
+		setup_us = 1;
+
+	trans_time = ktime_sub(t, dsi2.perf_start_time);
+	trans_us = (u32)ktime_to_us(trans_time);
+	if (trans_us == 0)
+		trans_us = 1;
+
+	total_us = setup_us + trans_us;
+
+	total_bytes = dsi2.active_update_region.w *
+		dsi2.active_update_region.h *
+		dsi2.active_update_region.device->ctrl.pixel_size / 8;
+
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO) {
+		static u32 s_total_trans_us, s_total_setup_us;
+		static u32 s_min_trans_us = 0xffffffff, s_min_setup_us;
+		static u32 s_max_trans_us, s_max_setup_us;
+		const int numframes = 100;
+		ktime_t total_time_auto;
+		u32 total_time_auto_us;
+
+		dsi2.perf_measure_frames++;
+
+		if (setup_us < s_min_setup_us)
+			s_min_setup_us = setup_us;
+
+		if (setup_us > s_max_setup_us)
+			s_max_setup_us = setup_us;
+
+		s_total_setup_us += setup_us;
+
+		if (trans_us < s_min_trans_us)
+			s_min_trans_us = trans_us;
+
+		if (trans_us > s_max_trans_us)
+			s_max_trans_us = trans_us;
+
+		s_total_trans_us += trans_us;
+
+		if (dsi2.perf_measure_frames < numframes)
+			return;
+
+		total_time_auto = ktime_sub(t, dsi2.perf_start_time_auto);
+		total_time_auto_us = (u32)ktime_to_us(total_time_auto);
+
+		printk(KERN_INFO "DSI(%s): %u fps, setup %u/%u/%u, "
+				"trans %u/%u/%u\n",
+				name,
+				1000 * 1000 * numframes / total_time_auto_us,
+				s_min_setup_us,
+				s_max_setup_us,
+				s_total_setup_us / numframes,
+				s_min_trans_us,
+				s_max_trans_us,
+				s_total_trans_us / numframes);
+
+		s_total_setup_us = 0;
+		s_min_setup_us = 0xffffffff;
+		s_max_setup_us = 0;
+		s_total_trans_us = 0;
+		s_min_trans_us = 0xffffffff;
+		s_max_trans_us = 0;
+		dsi2_perf_mark_start_auto();
+	} else {
+		printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
+				"%u bytes, %u kbytes/sec\n",
+				name,
+				setup_us,
+				trans_us,
+				total_us,
+				1000*1000 / total_us,
+				total_bytes,
+				total_bytes * 1000 / total_us);
+	}
+}
+#else
+#define dsi2_perf_mark_setup()
+#define dsi2_perf_mark_start()
+#define dsi2_perf_mark_start_auto()
+#define dsi2_perf_show(x)
+#endif
+
+static void print_irq_status(u32 status)
+{
+#ifndef VERBOSE_IRQ
+	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
+		return;
+#endif
+	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
+
+#define PIS(x) \
+	if (status & DSI_IRQ_##x) \
+		printk(#x " ");
+#ifdef VERBOSE_IRQ
+	PIS(VC0);
+	PIS(VC1);
+	PIS(VC2);
+	PIS(VC3);
+#endif
+	PIS(WAKEUP);
+	PIS(RESYNC);
+	PIS(PLL_LOCK);
+	PIS(PLL_UNLOCK);
+	PIS(PLL_RECALL);
+	PIS(COMPLEXIO_ERR);
+	PIS(HS_TX_TIMEOUT);
+	PIS(LP_RX_TIMEOUT);
+	PIS(TE_TRIGGER);
+	PIS(ACK_TRIGGER);
+	PIS(SYNC_LOST);
+	PIS(LDO_POWER_GOOD);
+	PIS(TA_TIMEOUT);
+#undef PIS
+
+	printk("\n");
+}
+
+static void print_irq_status_vc(int channel, u32 status)
+{
+#ifndef VERBOSE_IRQ
+	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
+		return;
+#endif
+	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
+
+#define PIS(x) \
+	if (status & DSI_VC_IRQ_##x) \
+		printk(#x " ");
+	PIS(CS);
+	PIS(ECC_CORR);
+#ifdef VERBOSE_IRQ
+	PIS(PACKET_SENT);
+#endif
+	PIS(FIFO_TX_OVF);
+	PIS(FIFO_RX_OVF);
+	PIS(BTA);
+	PIS(ECC_NO_CORR);
+	PIS(FIFO_TX_UDF);
+	PIS(PP_BUSY_CHANGE);
+#undef PIS
+	printk("\n");
+}
+
+static void print_irq_status_cio(u32 status)
+{
+	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
+
+#define PIS(x) \
+	if (status & DSI_CIO_IRQ_##x) \
+		printk(#x " ");
+	PIS(ERRSYNCESC1);
+	PIS(ERRSYNCESC2);
+	PIS(ERRSYNCESC3);
+	PIS(ERRESC1);
+	PIS(ERRESC2);
+	PIS(ERRESC3);
+	PIS(ERRCONTROL1);
+	PIS(ERRCONTROL2);
+	PIS(ERRCONTROL3);
+	PIS(STATEULPS1);
+	PIS(STATEULPS2);
+	PIS(STATEULPS3);
+	PIS(ERRCONTENTIONLP0_1);
+	PIS(ERRCONTENTIONLP1_1);
+	PIS(ERRCONTENTIONLP0_2);
+	PIS(ERRCONTENTIONLP1_2);
+	PIS(ERRCONTENTIONLP0_3);
+	PIS(ERRCONTENTIONLP1_3);
+	PIS(ULPSACTIVENOT_ALL0);
+	PIS(ULPSACTIVENOT_ALL1);
+#undef PIS
+
+	printk("\n");
+}
+
+static int debug_irq;
+
+/* called from dss */
+void dsi2_irq_handler(void)
+{
+	u32 irqstatus, vcstatus, ciostatus;
+	int i;
+#if 1 //sv3 debugging
+	irqstatus = dsi2_read_reg(DSI_IRQSTATUS);
+
+	if (irqstatus & DSI_IRQ_ERROR_MASK) {
+		DSSERR("DSI error, irqstatus %x\n", irqstatus);
+		print_irq_status(irqstatus);
+		spin_lock(&dsi2.errors_lock);
+		dsi2.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
+		spin_unlock(&dsi2.errors_lock);
+	} else if (debug_irq) {
+		print_irq_status(irqstatus);
+	}
+
+	for (i = 0; i < 4; ++i) {
+		if ((irqstatus & (1<<i)) == 0)
+			continue;
+
+		vcstatus = dsi2_read_reg(DSI_VC_IRQSTATUS(i));
+
+		if (vcstatus & DSI_VC_IRQ_BTA)
+			complete(&dsi2.bta_completion);
+
+		if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
+			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
+				       i, vcstatus);
+			print_irq_status_vc(i, vcstatus);
+		} else if (debug_irq) {
+			print_irq_status_vc(i, vcstatus);
+		}
+
+		dsi2_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
+	}
+
+	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
+		ciostatus = dsi2_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+
+		dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
+
+		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
+		print_irq_status_cio(ciostatus);
+	}
+
+	dsi2_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
+#endif
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void _dsi2_initialize_irq(void)
+{
+	u32 l;
+	int i;
+
+	/* disable all interrupts */
+	dsi2_write_reg(DSI_IRQENABLE, 0);
+	for (i = 0; i < 4; ++i)
+		dsi2_write_reg(DSI_VC_IRQENABLE(i), 0);
+	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
+
+	/* clear interrupt status */
+	l = dsi2_read_reg(DSI_IRQSTATUS);
+	dsi2_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
+
+	for (i = 0; i < 4; ++i) {
+		l = dsi2_read_reg(DSI_VC_IRQSTATUS(i));
+		dsi2_write_reg(DSI_VC_IRQSTATUS(i), l);
+	}
+
+	l = dsi2_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+	dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
+
+	/* enable error irqs */
+	l = DSI_IRQ_ERROR_MASK;
+	dsi2_write_reg(DSI_IRQENABLE, l);
+
+	l = DSI_VC_IRQ_ERROR_MASK;
+	for (i = 0; i < 4; ++i)
+		dsi2_write_reg(DSI_VC_IRQENABLE(i), l);
+
+	/* XXX zonda responds incorrectly, causing control error:
+	   Exit from LP-ESC mode to LP11 uses wrong transition states on the
+	   data lines LP0 and LN0. */
+	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE,
+			-1 & (~DSI_CIO_IRQ_ERRCONTROL2));
+}
+#endif
+
+static u32 dsi2_get_errors(void)
+{
+	unsigned long flags;
+	u32 e;
+	spin_lock_irqsave(&dsi2.errors_lock, flags);
+	e = dsi2.errors;
+	dsi2.errors = 0;
+	spin_unlock_irqrestore(&dsi2.errors_lock, flags);
+	return e;
+}
+
+static void dsi2_vc_enable_bta_irq(int channel)
+{
+	u32 l;
+
+	dsi2_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
+
+	l = dsi2_read_reg(DSI_VC_IRQENABLE(channel));
+	l |= DSI_VC_IRQ_BTA;
+	dsi2_write_reg(DSI_VC_IRQENABLE(channel), l);
+}
+
+static void dsi2_vc_disable_bta_irq(int channel)
+{
+	u32 l;
+
+	l = dsi2_read_reg(DSI_VC_IRQENABLE(channel));
+	l &= ~DSI_VC_IRQ_BTA;
+	dsi2_write_reg(DSI_VC_IRQENABLE(channel), l);
+}
+
+/* DSI func clock. this could also be DSI2_PLL_FCLK */
+static inline void enable_clocks(bool enable)
+{
+	if (enable)
+		dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+	else
+		dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+}
+
+/* source clock for DSI PLL. this could also be PCLKFREE */
+static inline void dsi2_enable_pll_clock(bool enable)
+{
+	if (enable)
+		dss_clk_enable(DSS_CLK_FCK2);
+	else
+		dss_clk_disable(DSS_CLK_FCK2);
+
+	if (enable && dsi2.pll_locked) {
+		if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
+			DSSERR("cannot lock PLL when enabling clocks\n");
+	}
+}
+#ifndef CONFIG_ARCH_OMAP4
+#ifdef DEBUG
+static void _dsi2_print_reset_status(void)
+{
+	u32 l;
+
+	if (!dss_debug)
+		return;
+
+	/* A dummy read using the SCP interface to any DSIPHY register is
+	 * required after DSIPHY reset to complete the reset of the DSI complex
+	 * I/O. */
+	l = dsi2_read_reg(DSI_DSIPHY_CFG5);
+
+	printk(KERN_DEBUG "DSI resets: ");
+
+	l = dsi2_read_reg(DSI_PLL_STATUS);
+	printk("PLL (%d) ", FLD_GET(l, 0, 0));
+
+	l = dsi2_read_reg(DSI_COMPLEXIO_CFG1);
+	printk("CIO (%d) ", FLD_GET(l, 29, 29));
+
+	l = dsi2_read_reg(DSI_DSIPHY_CFG5);
+	printk("PHY (%x, %d, %d, %d)\n",
+			FLD_GET(l, 28, 26),
+			FLD_GET(l, 29, 29),
+			FLD_GET(l, 30, 30),
+			FLD_GET(l, 31, 31));
+}
+#else
+#define _dsi2_print_reset_status()
+#endif
+#endif
+static inline int dsi2_if_enable(bool enable)
+{
+	DSSDBG("dsi2_if_enable(%d)\n", enable);
+
+	enable = enable ? 1 : 0;
+	REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
+
+	if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
+			DSSERR("Failed to set dsi2_if_enable to %d\n", enable);
+			return -EIO;
+	}
+
+	return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static unsigned long dsi2_fclk_rate(void)
+{
+	unsigned long r;
+
+	if (dss_get_dsi_clk_source() == 0) {
+		/* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
+		r = dss_clk_get_rate(DSS_CLK_FCK1);
+	} else {
+		/* DSI FCLK source is DSI2_PLL_FCLK */
+		r = dsi2.dsi2_pll_fclk;
+	}
+
+	return r;
+}
+
+static int dsi2_set_lp_clk_divisor(struct omap_dss_device *dssdev)
+{
+	unsigned n;
+	unsigned long dsi2_fclk;
+	unsigned long lp_clk, lp_clk_req;
+
+	dsi2_fclk = dsi2_fclk_rate();
+
+	lp_clk_req = dssdev->phy.dsi.lp_clk_hz;
+
+	for (n = 1; n < (1 << 13) - 1; ++n) {
+		lp_clk = dsi2_fclk / 2 / n;
+		if (lp_clk <= lp_clk_req)
+			break;
+	}
+
+	if (n == (1 << 13) - 1) {
+		DSSERR("Failed to find LP_CLK_DIVISOR\n");
+		return -EINVAL;
+	}
+
+	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu (req %lu)\n", n, lp_clk, lp_clk_req);
+
+//sv5 	REG_FLD_MOD(DSI_CLK_CTRL, n, 12, 0);	/* LP_CLK_DIVISOR */
+	REG_FLD_MOD(DSI_CLK_CTRL, 6, 12, 0);	/* LP_CLK_DIVISOR */
+	if (dsi2_fclk > 30*1000*1000)
+		REG_FLD_MOD(DSI_CLK_CTRL, 1, 21, 21); /* LP_RX_SYNCHRO_ENABLE */
+
+	return 0;
+}
+#endif
+
+enum dsi2_pll_power_state {
+	DSI_PLL_POWER_OFF	= 0x0,
+	DSI_PLL_POWER_ON_HSCLK	= 0x1,
+	DSI_PLL_POWER_ON_ALL	= 0x2,
+	DSI_PLL_POWER_ON_DIV	= 0x3,
+};
+
+static int dsi2_pll_power(enum dsi2_pll_power_state state)
+{
+	int t = 0;
+
+	REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30);	/* PLL_PWR_CMD */
+
+	/* PLL_PWR_STATUS */
+	while (FLD_GET(dsi2_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
+		udelay(1);
+		if (t++ > 1000) {
+			DSSERR("Failed to set DSI PLL power mode to %d\n",
+					state);
+			return -ENODEV;
+		}
+	}
+
+	return 0;
+}
+
+int dsi2_pll_calc_pck(bool is_tft, unsigned long req_pck,
+		struct dsi_clock_info *cinfo)
+{
+	struct dsi_clock_info cur, best;
+	int min_fck_per_pck;
+	int match = 0;
+	unsigned long dss_clk_fck2;
+
+	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
+
+	if (req_pck == dsi2.cache_req_pck &&
+			dsi2.cache_cinfo.clkin == dss_clk_fck2) {
+		DSSDBG("DSI clock info found from cache\n");
+		*cinfo = dsi2.cache_cinfo;
+		return 0;
+	}
+
+	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
+
+	if (min_fck_per_pck &&
+		req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
+		DSSERR("Requested pixel clock not possible with the current "
+				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
+				"the constraint off.\n");
+		min_fck_per_pck = 0;
+	}
+
+	DSSDBG("dsi2_pll_calc\n");
+
+retry:
+	memset(&best, 0, sizeof(best));
+
+	memset(&cur, 0, sizeof(cur));
+	cur.clkin = dss_clk_fck2;
+	cur.use_dss2_fck = 1;
+	cur.highfreq = 0;
+
+	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
+	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
+	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
+	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
+		if (cur.highfreq == 0)
+			cur.fint = cur.clkin / cur.regn;
+		else
+			cur.fint = cur.clkin / (2 * cur.regn);
+
+		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
+			continue;
+
+		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
+		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
+			unsigned long a, b;
+
+			a = 2 * cur.regm * (cur.clkin/1000);
+			b = cur.regn * (cur.highfreq + 1);
+			cur.dsiphy = a / b * 1000;
+
+			if (cur.dsiphy > 1800 * 1000 * 1000)
+				break;
+
+			/* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3  < 173MHz */
+			for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
+					++cur.regm3) {
+				cur.dsi1_pll_fclk = cur.dsiphy / cur.regm3;
+
+				/* this will narrow down the search a bit,
+				 * but still give pixclocks below what was
+				 * requested */
+				if (cur.dsi1_pll_fclk  < req_pck)
+					break;
+
+				if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
+					continue;
+
+				if (min_fck_per_pck &&
+					cur.dsi1_pll_fclk <
+						req_pck * min_fck_per_pck)
+					continue;
+
+				match = 1;
+
+				find_lck_pck_divs(is_tft, req_pck,
+						cur.dsi1_pll_fclk,
+						&cur.lck_div,
+						&cur.pck_div);
+
+				cur.lck = cur.dsi1_pll_fclk / cur.lck_div;
+				cur.pck = cur.lck / cur.pck_div;
+
+				if (abs(cur.pck - req_pck) <
+						abs(best.pck - req_pck)) {
+					best = cur;
+
+					if (cur.pck == req_pck)
+						goto found;
+				}
+			}
+		}
+	}
+found:
+	if (!match) {
+		if (min_fck_per_pck) {
+			DSSERR("Could not find suitable clock settings.\n"
+					"Turning FCK/PCK constraint off and"
+					"trying again.\n");
+			min_fck_per_pck = 0;
+			goto retry;
+		}
+
+		DSSERR("Could not find suitable clock settings.\n");
+
+		return -EINVAL;
+	}
+
+	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
+	best.regm4 = best.dsiphy / 48000000;
+	if (best.regm4 > REGM4_MAX)
+		best.regm4 = REGM4_MAX;
+	else if (best.regm4 == 0)
+		best.regm4 = 1;
+	best.dsi2_pll_fclk = best.dsiphy / best.regm4;
+
+	if (cinfo)
+		*cinfo = best;
+
+	dsi2.cache_req_pck = req_pck;
+	dsi2.cache_clk_freq = 0;
+	dsi2.cache_cinfo = best;
+
+	return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static int dsi2_pll_calc_ddrfreq(unsigned long clk_freq,
+		struct dsi_clock_info *cinfo)
+{
+	struct dsi_clock_info cur, best;
+	const bool use_dss2_fck = 1;
+	unsigned long datafreq;
+	unsigned long dss_clk_fck2;
+
+	DSSDBG("dsi2_pll_calc_ddrfreq\n");
+
+	dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
+
+	if (clk_freq == dsi2.cache_clk_freq &&
+			dsi2.cache_cinfo.clkin == dss_clk_fck2) {
+		DSSDBG("DSI clock info found from cache\n");
+		*cinfo = dsi2.cache_cinfo;
+		return 0;
+	}
+
+	datafreq = clk_freq * 4;
+
+	memset(&best, 0, sizeof(best));
+
+	memset(&cur, 0, sizeof(cur));
+	if(cpu_is_omap44xx()){
+		cur.use_dss2_fck = 0;
+		cur.clkin = 38400000;
+		cur.highfreq = 1;
+	}else if(cpu_is_omap34xx()){
+		cur.use_dss2_fck = use_dss2_fck;
+		if (use_dss2_fck) {
+			cur.clkin = dss_clk_fck2;
+			cur.highfreq = 0;
+		} else  {
+			/* TODO: Add support for LCD2 */
+			cur.clkin = dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2);
+			if (cur.clkin < 32000000)
+				cur.highfreq = 0;
+			else
+				cur.highfreq = 1;
+		}
+	}
+	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
+	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
+	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
+	for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
+		if (cur.highfreq == 0)
+			cur.fint = cur.clkin / cur.regn;
+		else
+			cur.fint = cur.clkin / (2 * cur.regn);
+
+		if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
+			continue;
+
+		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
+		for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
+			unsigned long a, b;
+
+			a = 2 * cur.regm * (cur.clkin/1000);
+			b = cur.regn * (cur.highfreq + 1);
+			cur.dsiphy = a / b * 1000;
+
+			if (cur.dsiphy > 1800 * 1000 * 1000)
+				break;
+
+			if (abs(cur.dsiphy - datafreq) <
+					abs(best.dsiphy - datafreq)) {
+				best = cur;
+				/* DSSDBG("best %ld\n", best.dsiphy); */
+			}
+
+			if (cur.dsiphy == datafreq)
+				goto found;
+		}
+	}
+found:
+	/* DSI1_PLL_FCLK (regm3) is not used. Set it to something sane. */
+	best.regm3 = best.dsiphy / 48000000;
+	if (best.regm3 > REGM3_MAX)
+		best.regm3 = REGM3_MAX;
+	else if (best.regm3 == 0)
+		best.regm3 = 1;
+	best.dsi1_pll_fclk = best.dsiphy / best.regm3;
+
+	/* DSI2_PLL_FCLK (regm4) is not used. Set it to something sane. */
+	best.regm4 = best.dsiphy / 48000000;
+	if (best.regm4 > REGM4_MAX)
+		best.regm4 = REGM4_MAX;
+	else if (best.regm4 == 0)
+		best.regm4 = 1;
+	best.dsi2_pll_fclk = best.dsiphy / best.regm4;
+
+	if (cinfo)
+		*cinfo = best;
+
+	dsi2.cache_clk_freq = clk_freq;
+	dsi2.cache_req_pck = 0;
+	dsi2.cache_cinfo = best;
+
+	return 0;
+}
+#endif
+
+int dsi2_pll_program(struct dsi_clock_info *cinfo)
+{
+	int r = 0;
+
+	DSSDBG("dsi2_pll_program\n");
+
+	dsi2.dsiphy = cinfo->dsiphy;
+	dsi2.ddr_clk = dsi2.dsiphy / 4;
+	dsi2.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
+	dsi2.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
+
+	DSSDBG("DSI Fint %ld\n", cinfo->fint);
+
+	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
+			cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
+			cinfo->clkin,
+			cinfo->highfreq);
+
+	/* DSIPHY == CLKIN4DDR */
+	DSSDBG("DSIPHY = 2 * %d / %d * %lu / %d = %lu\n",
+			cinfo->regm,
+			cinfo->regn,
+			cinfo->clkin,
+			cinfo->highfreq + 1,
+			cinfo->dsiphy);
+
+	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
+			dsi2.dsiphy / 1000 / 1000 / 2);
+
+	DSSDBG("Clock lane freq %ld Hz\n", dsi2.ddr_clk);
+
+	DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
+			cinfo->regm3, cinfo->dsi1_pll_fclk);
+	DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
+			cinfo->regm4, cinfo->dsi2_pll_fclk);
+#if 0//sv3
+	REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
+
+	l = dsi2_read_reg(DSI_PLL_CONFIGURATION1);
+	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
+	l = FLD_MOD(l, cinfo->regn - 1, 7, 1);	/* DSI_PLL_REGN */
+	l = FLD_MOD(l, cinfo->regm, 18, 8);	/* DSI_PLL_REGM */
+	l = FLD_MOD(l, cinfo->regm3 - 1, 22, 19);	/* DSI_CLOCK_DIV */
+	l = FLD_MOD(l, cinfo->regm4 - 1, 26, 23);	/* DSIPROTO_CLOCK_DIV */
+	dsi2_write_reg(DSI_PLL_CONFIGURATION1, l);
+
+	l = dsi2_read_reg(DSI_PLL_CONFIGURATION2);
+	l = FLD_MOD(l, 7, 4, 1);		/* DSI_PLL_FREQSEL */
+	/* DSI_PLL_CLKSEL */
+	l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, 11, 11);
+	l = FLD_MOD(l, cinfo->highfreq, 12, 12);	/* DSI_PLL_HIGHFREQ */
+	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
+	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
+	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
+	dsi2_write_reg(DSI_PLL_CONFIGURATION2, l);
+#else
+/*
+	REG_FLD_MOD(DSI_PLL_CONTROL, 0,0,0);
+	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,14,14);
+	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 1,20,20);
+	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,11,11);
+	REG_FLD_MOD(DSI_PLL_CONFIGURATION2, 0,12,12);
+
+	REG_FLD_MOD(DSI_PLL_CONFIGURATION1, 0,12,12);
+
+	l = dsi2_read_reg(DSI_PLL_CONFIGURATION1);
+
+	l = 	FLD_MOD(l, 3,26,30);
+	l = 	FLD_MOD(l, 3,21,25);
+	l = 	FLD_MOD(l, 102,9,20);
+	l = 	FLD_MOD(l, 18,1,8);
+	l = 	FLD_MOD(l, 1,0,0);
+	dsi2_write_reg(DSI_PLL_CONFIGURATION1, l);
+
+	regm4 = 3; 	regm3 = 3;
+	regn = 18; regm = 102;
+*/
+#endif
+
+	dsi2_write_reg(DSI_PLL_CONFIGURATION1, 0x0C60CC25);
+	dsi2_write_reg(DSI_PLL_CONFIGURATION2, 0x0065600C);
+
+	REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
+
+	if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
+		DSSERR("dsi pll go bit not going down.\n");
+		r = -EIO;
+		goto err;
+	}
+
+	if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
+		DSSERR("cannot lock PLL\n");
+		r = -EIO;
+		goto err;
+	}
+	printk(KERN_INFO "\n PLL is locked ");
+	printk(KERN_INFO "\n DSI_PLL_STATUS = 0x%X ", dsi2_read_reg(DSI_PLL_STATUS));
+	dsi2.pll_locked = 1;
+
+#if 0
+	l = dsi2_read_reg(DSI_PLL_CONFIGURATION2);
+	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
+	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
+	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
+	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
+	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
+	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
+	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
+	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */
+	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */
+	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */
+	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */
+	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
+	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
+	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
+	dsi2_write_reg(DSI_PLL_CONFIGURATION2, l);
+#endif
+	DSSDBG("PLL config done\n");
+err:
+	return r;
+}
+
+int dsi2_pll_init(bool enable_hsclk, bool enable_hsdiv)
+{
+	int r = 0;
+	enum dsi2_pll_power_state pwstate;
+	struct dispc_clock_info cinfo;
+
+	DSSDBG("PLL init\n");
+
+//sv3 	enable_clocks(1);
+//sv3	dsi2_enable_pll_clock(1);
+
+	/* XXX this should be calculated depending on the screen size,
+	 * required framerate and DSI speed.
+	 * For now 48MHz is enough for 864x480@60 with 360Mbps/lane
+	 * with two lanes */
+	r = dispc_calc_clock_div(1, 48 * 1000 * 1000, &cinfo);
+	if (r)
+		goto err0;
+
+/*sv3	r = dispc_set_clock_div(&cinfo);
+	if (r) {
+		DSSERR("Failed to set basic clocks\n");
+		goto err0;
+	}
+
+	r = regulator_enable(dsi2.vdds_dsi2_reg);
+	if (r)
+		goto err0;
+*/
+	/* CIO_CLK_ICG, enable L3 clk to CIO */
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); //sv3
+
+	pwstate = DSI_PLL_POWER_ON_ALL;
+	r = dsi2_pll_power(pwstate);
+	if (r)
+		goto err1;
+
+	/* XXX PLL does not come out of reset without this... */
+//sv3 	dispc_pck_free_enable(1);
+
+	if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
+		DSSERR("PLL not coming out of reset.\n");
+		r = -ENODEV;
+		goto err1;
+	}
+
+	/* XXX ... but if left on, we get problems when planes do not
+	 * fill the whole display. No idea about this */
+//sv3	dispc_pck_free_enable(0);
+
+	if (enable_hsclk && enable_hsdiv)
+		pwstate = DSI_PLL_POWER_ON_ALL;
+	else if (enable_hsclk)
+		pwstate = DSI_PLL_POWER_ON_HSCLK;
+	else if (enable_hsdiv)
+		pwstate = DSI_PLL_POWER_ON_DIV;
+	else
+		pwstate = DSI_PLL_POWER_OFF;
+
+	pwstate = DSI_PLL_POWER_ON_ALL;
+	r = dsi2_pll_power(pwstate);
+
+	if (r)
+		goto err1;
+
+	DSSDBG("PLL init done\n");
+
+	return 0;
+err1:
+//sv3	regulator_disable(dsi2.vdds_dsi2_reg);
+err0:
+//sv3 	enable_clocks(0);
+//sv3	dsi2_enable_pll_clock(0);
+	return r;
+}
+
+void dsi2_pll_uninit(void)
+{
+	enable_clocks(0);
+	dsi2_enable_pll_clock(0);
+
+	dsi2.pll_locked = 0;
+	dsi2_pll_power(DSI_PLL_POWER_OFF);
+	//regulator_disable(dsi2.vdds_dsi2_reg);
+	DSSDBG("PLL uninit done\n");
+}
+
+unsigned long dsi2_get_dsi1_pll_rate(void)
+{
+	return dsi2.dsi1_pll_fclk;
+}
+
+unsigned long dsi2_get_dsi2_pll_rate(void)
+{
+	return dsi2.dsi2_pll_fclk;
+}
+
+void dsi2_dump_clocks(struct seq_file *s)
+{
+	int clksel;
+
+	enable_clocks(1);
+
+	clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
+
+	seq_printf(s, "- dsi -\n");
+
+	seq_printf(s, "dsi fclk source = %s\n",
+			dss_get_dsi_clk_source() == 0 ?
+			"dss1_alwon_fclk" : "dsi2_pll_fclk");
+
+	seq_printf(s, "dsi pll source = %s\n",
+			clksel == 0 ?
+			"dss2_alwon_fclk" : "pclkfree");
+
+	seq_printf(s,	"DSIPHY\t\t%lu\nDDR_CLK\t\t%lu\n",
+			dsi2.dsiphy, dsi2.ddr_clk);
+
+	seq_printf(s,	"dsi1_pll_fck\t%lu (%s)\n"
+			"dsi2_pll_fck\t%lu (%s)\n",
+			dsi2.dsi1_pll_fclk,
+			dss_get_dispc_clk_source() == 0 ? "off" : "on",
+			dsi2.dsi2_pll_fclk,
+			dss_get_dsi_clk_source() == 0 ? "off" : "on");
+
+	enable_clocks(0);
+}
+
+void dsi2_dump_regs(struct seq_file *s)
+{
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi2_read_reg(r))
+
+	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
+
+	DUMPREG(DSI_REVISION);
+	DUMPREG(DSI_SYSCONFIG);
+	DUMPREG(DSI_SYSSTATUS);
+	DUMPREG(DSI_IRQSTATUS);
+	DUMPREG(DSI_IRQENABLE);
+	DUMPREG(DSI_CTRL);
+	DUMPREG(DSI_COMPLEXIO_CFG1);
+	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
+	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
+	DUMPREG(DSI_CLK_CTRL);
+	DUMPREG(DSI_TIMING1);
+	DUMPREG(DSI_TIMING2);
+	DUMPREG(DSI_VM_TIMING1);
+	DUMPREG(DSI_VM_TIMING2);
+	DUMPREG(DSI_VM_TIMING3);
+	DUMPREG(DSI_CLK_TIMING);
+	DUMPREG(DSI_TX_FIFO_VC_SIZE);
+	DUMPREG(DSI_RX_FIFO_VC_SIZE);
+	DUMPREG(DSI_COMPLEXIO_CFG2);
+	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
+	DUMPREG(DSI_VM_TIMING4);
+	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
+	DUMPREG(DSI_VM_TIMING5);
+	DUMPREG(DSI_VM_TIMING6);
+	DUMPREG(DSI_VM_TIMING7);
+	DUMPREG(DSI_STOPCLK_TIMING);
+
+	DUMPREG(DSI_VC_CTRL(0));
+	DUMPREG(DSI_VC_TE(0));
+	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
+	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
+	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
+	DUMPREG(DSI_VC_IRQSTATUS(0));
+	DUMPREG(DSI_VC_IRQENABLE(0));
+
+	DUMPREG(DSI_VC_CTRL(1));
+	DUMPREG(DSI_VC_TE(1));
+	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
+	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
+	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
+	DUMPREG(DSI_VC_IRQSTATUS(1));
+	DUMPREG(DSI_VC_IRQENABLE(1));
+
+	DUMPREG(DSI_VC_CTRL(2));
+	DUMPREG(DSI_VC_TE(2));
+	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
+	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
+	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
+	DUMPREG(DSI_VC_IRQSTATUS(2));
+	DUMPREG(DSI_VC_IRQENABLE(2));
+
+	DUMPREG(DSI_VC_CTRL(3));
+	DUMPREG(DSI_VC_TE(3));
+	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
+	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
+	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
+	DUMPREG(DSI_VC_IRQSTATUS(3));
+	DUMPREG(DSI_VC_IRQENABLE(3));
+
+	DUMPREG(DSI_DSIPHY_CFG0);
+	DUMPREG(DSI_DSIPHY_CFG1);
+	DUMPREG(DSI_DSIPHY_CFG2);
+	DUMPREG(DSI_DSIPHY_CFG5);
+
+	DUMPREG(DSI_PLL_CONTROL);
+	DUMPREG(DSI_PLL_STATUS);
+	DUMPREG(DSI_PLL_GO);
+	DUMPREG(DSI_PLL_CONFIGURATION1);
+	DUMPREG(DSI_PLL_CONFIGURATION2);
+
+	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
+#undef DUMPREG
+}
+
+enum dsi2_complexio_power_state {
+	DSI_COMPLEXIO_POWER_OFF		= 0x0,
+	DSI_COMPLEXIO_POWER_ON		= 0x1,
+	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
+};
+
+static int dsi2_complexio_power(enum dsi2_complexio_power_state state)
+{
+#if 0 //sv3
+	int t = 0;
+	/* PWR_CMD */
+	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
+
+	/* PWR_STATUS */
+	while (FLD_GET(dsi2_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
+		udelay(1);
+		if (t++ > 1000) {
+			DSSERR("failed to set complexio power state to "
+					"%d\n", state);
+			return -ENODEV;
+		}
+	}
+#else
+	/* CIO_CLK_ICG, enable L3 clk to CIO */
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); //sv3
+	/* PWR_CMD */
+	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
+	udelay(100);
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void dsi2_complexio_config(struct omap_dss_device *dssdev)
+{
+	u32 r;
+
+	int clk_lane   = dssdev->phy.dsi.clk_lane;
+	int data1_lane = dssdev->phy.dsi.data1_lane;
+	int data2_lane = dssdev->phy.dsi.data2_lane;
+	int clk_pol    = dssdev->phy.dsi.clk_pol;
+	int data1_pol  = dssdev->phy.dsi.data1_pol;
+	int data2_pol  = dssdev->phy.dsi.data2_pol;
+
+	r = dsi2_read_reg(DSI_COMPLEXIO_CFG1);
+	r = FLD_MOD(r, clk_lane, 2, 0);
+	r = FLD_MOD(r, clk_pol, 3, 3);
+	r = FLD_MOD(r, data1_lane, 6, 4);
+	r = FLD_MOD(r, data1_pol, 7, 7);
+	r = FLD_MOD(r, data2_lane, 10, 8);
+	r = FLD_MOD(r, data2_pol, 11, 11);
+	dsi2_write_reg(DSI_COMPLEXIO_CFG1, r);
+
+	/* The configuration of the DSI complex I/O (number of data lanes,
+	   position, differential order) should not be changed while
+	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
+	   the hardware to take into account a new configuration of the complex
+	   I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
+	   follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
+	   then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
+	   DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
+	   DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
+	   DSI complex I/O configuration is unknown. */
+
+	/*
+	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
+	REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
+	REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
+	*/
+}
+#endif
+
+static inline unsigned ns2ddr(unsigned ns)
+{
+	/* convert time in ns to ddr ticks, rounding up */
+	return (ns * (dsi2.ddr_clk/1000/1000) + 999) / 1000;
+}
+
+static inline unsigned ddr2ns(unsigned ddr)
+{
+	return ddr * 1000 * 1000 / (dsi2.ddr_clk / 1000);
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void dsi2_complexio_timings(void)
+{
+	u32 r;
+	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
+	u32 tlpx_half, tclk_trail, tclk_zero;
+	u32 tclk_prepare;
+
+	/* calculate timings */
+
+	/* 1 * DDR_CLK = 2 * UI */
+
+	/* min 40ns + 4*UI	max 85ns + 6*UI */
+	ths_prepare = ns2ddr(70) + 2;
+
+	/* min 145ns + 10*UI */
+	ths_prepare_ths_zero = ns2ddr(175) + 2;
+
+	/* min max(8*UI, 60ns+4*UI) */
+	ths_trail = ns2ddr(60) + 5;
+
+	/* min 100ns */
+	ths_exit = ns2ddr(145);
+
+	/* tlpx min 50n */
+	tlpx_half = ns2ddr(25);
+
+	/* min 60ns */
+	tclk_trail = ns2ddr(60) + 2;
+
+	/* min 38ns, max 95ns */
+	tclk_prepare = ns2ddr(65);
+
+	/* min tclk-prepare + tclk-zero = 300ns */
+	tclk_zero = ns2ddr(260);
+
+	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
+		ths_prepare, ddr2ns(ths_prepare),
+		ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
+	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
+			ths_trail, ddr2ns(ths_trail),
+			ths_exit, ddr2ns(ths_exit));
+
+	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
+			"tclk_zero %u (%uns)\n",
+			tlpx_half, ddr2ns(tlpx_half),
+			tclk_trail, ddr2ns(tclk_trail),
+			tclk_zero, ddr2ns(tclk_zero));
+	DSSDBG("tclk_prepare %u (%uns)\n",
+			tclk_prepare, ddr2ns(tclk_prepare));
+
+	/* program timings */
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG0);
+	r = FLD_MOD(r, ths_prepare, 31, 24);
+	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
+	r = FLD_MOD(r, ths_trail, 15, 8);
+	r = FLD_MOD(r, ths_exit, 7, 0);
+	dsi2_write_reg(DSI_DSIPHY_CFG0, 0x0914060F); //sv3
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG1);
+	r = FLD_MOD(r, tlpx_half, 22, 16);
+	r = FLD_MOD(r, tclk_trail, 15, 8);
+	r = FLD_MOD(r, tclk_zero, 7, 0);
+	dsi2_write_reg(DSI_DSIPHY_CFG1, 0x4203061A); //sv3
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG2);
+	r = FLD_MOD(r, tclk_prepare, 7, 0);
+	dsi2_write_reg(DSI_DSIPHY_CFG2, 0xB8000007); //sv3
+}
+
+
+static int dsi2_complexio_init(struct omap_dss_device *dssdev)
+{
+	int r = 0,t = 0;
+	u32 val;
+	DSSDBG("dsi2_complexio_init\n");
+#if 0 //sv3
+	/* CIO_CLK_ICG, enable L3 clk to CIO */
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
+
+	/* A dummy read using the SCP interface to any DSIPHY register is
+	 * required after DSIPHY reset to complete the reset of the DSI complex
+	 * I/O. */
+	dsi2_read_reg(DSI_DSIPHY_CFG5);
+
+	if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
+		DSSERR("ComplexIO PHY not coming out of reset.\n");
+		r = -ENODEV;
+		goto err;
+	}
+
+	dsi2_complexio_config(dssdev);
+
+//sv5
+	u32 val = 0;
+
+	// Register 12
+        val = val | (0x58 << 0);
+       dsi2_write_reg(DSI_DSIPHY_CFG12, val);
+
+	// Register 14
+        val = 0;
+        val = val | (1 << 31) |  (0x54 << 23) |  (0x7 << 14);
+	val = FLD_MOD(val, 1, 31, 31);
+	val = FLD_MOD(val, 1, 11, 11);
+	val = FLD_MOD(val, 1, 19, 19);
+	val = FLD_MOD(val, 1, 18, 18);
+
+	dsi2_write_reg(DSI_DSIPHY_CFG14, val);
+
+	// Register 8
+	val = 0;
+	val = val | (1 << 11) | (16 << 6) | (0xE << 0);
+	val = FLD_MOD(val, 1, 5, 5);
+	dsi2_write_reg(DSI_DSIPHY_CFG8, val);
+//sv5
+	r = dsi2_complexio_power(DSI_COMPLEXIO_POWER_ON);
+
+	if (r)
+		goto err;
+
+	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
+		DSSERR("ComplexIO not coming out of reset.\n");
+		r = -ENODEV;
+		goto err;
+	}
+//sv5
+#if 0
+	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
+		DSSERR("ComplexIO LDO power down.\n");
+		r = -ENODEV;
+		goto err;
+	}
+#endif
+//sv5
+	dsi2_complexio_timings();
+
+	/*
+	   The configuration of the DSI complex I/O (number of data lanes,
+	   position, differential order) should not be changed while
+	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
+	   hardware to recognize a new configuration of the complex I/O (done
+	   in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
+	   this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
+	   reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
+	   LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
+	   bit to 1. If the sequence is not followed, the DSi complex I/O
+	   configuration is undetermined.
+	   */
+	dsi2_if_enable(1);
+	dsi2_if_enable(0);
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
+	dsi2_if_enable(1);
+	dsi2_if_enable(0);
+#else
+
+
+	dsi2_complexio_config(dssdev);
+
+    	//To do a read of any of the DSIPHY to have a dummy access
+	dsi2_read_reg(DSI_DSIPHY_CFG8);
+
+	dsi2_complexio_timings();
+
+	/*Set Go bit */
+	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, 1, 30, 30);
+	mdelay(1);
+	if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 30, 1) != 1) {
+		DSSERR("ComplexIO PHY not coming out of reset.\n");
+	}
+	mdelay(1);
+
+	dsi2_write_reg(DSI_COMPLEXIO_IRQ_STATUS, 0xFFFFFFFF);
+	dsi2_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0x0);
+
+	r = dsi2_complexio_power(DSI_COMPLEXIO_POWER_ON);
+	if (r)
+		DSSERR("ComplexIO PWR ON cmd fail \n");
+
+	/*Set Go bit */
+	REG_FLD_MOD(DSI_COMPLEXIO_CFG1, 1, 30, 30);
+	udelay(100);
+	/* PLL_PWR_STATUS */
+	t = 0;
+	while (FLD_GET(dsi2_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != DSI_COMPLEXIO_POWER_ON) {
+		udelay(100);
+		if (t++ > 1000) {
+			DSSERR("Failed to set DSI PLL power mode to %d\n",
+					DSI_COMPLEXIO_POWER_ON);
+			return -ENODEV;
+		}
+	}
+
+#endif
+	DSSDBG("CIO init done\n");
+	return r;
+}
+#endif
+
+static void dsi2_complexio_uninit(void)
+{
+	dsi2_complexio_power(DSI_COMPLEXIO_POWER_OFF);
+}
+
+static int _dsi2_wait_reset(void)
+{
+	int i = 0;
+
+	while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
+		if (i++ > 5) {
+			DSSERR("soft reset failed\n");
+			return -ENODEV;
+		}
+		udelay(1);
+	}
+
+	return 0;
+}
+
+static int _dsi2_reset(void)
+{
+	/* Soft reset */
+	REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
+	return _dsi2_wait_reset();
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void dsi2_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
+		enum fifo_size size3, enum fifo_size size4)
+{
+	u32 r = 0;
+	int add = 0;
+	int i;
+
+	dsi2.vc[0].fifo_size = size1;
+	dsi2.vc[1].fifo_size = size2;
+	dsi2.vc[2].fifo_size = size3;
+	dsi2.vc[3].fifo_size = size4;
+
+	for (i = 0; i < 4; i++) {
+		u8 v;
+		int size = dsi2.vc[i].fifo_size;
+
+		if (add + size > 4) {
+			DSSERR("Illegal FIFO configuration\n");
+			BUG();
+		}
+
+		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
+		r |= v << (8 * i);
+		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
+		add += size;
+	}
+
+	dsi2_write_reg(DSI_TX_FIFO_VC_SIZE, r);
+}
+
+static void dsi2_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
+		enum fifo_size size3, enum fifo_size size4)
+{
+	u32 r = 0;
+	int add = 0;
+	int i;
+
+	dsi2.vc[0].fifo_size = size1;
+	dsi2.vc[1].fifo_size = size2;
+	dsi2.vc[2].fifo_size = size3;
+	dsi2.vc[3].fifo_size = size4;
+
+	for (i = 0; i < 4; i++) {
+		u8 v;
+		int size = dsi2.vc[i].fifo_size;
+
+		if (add + size > 4) {
+			DSSERR("Illegal FIFO configuration\n");
+			BUG();
+		}
+
+		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
+		r |= v << (8 * i);
+		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
+		add += size;
+	}
+
+	dsi2_write_reg(DSI_RX_FIFO_VC_SIZE, r);
+}
+#endif
+
+static int dsi2_force_tx_stop_mode_io(void)
+{
+	u32 r;
+
+	r = dsi2_read_reg(DSI_TIMING1);
+	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
+	dsi2_write_reg(DSI_TIMING1, r);
+
+	if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
+		DSSERR("TX_STOP bit not going down\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void dsi2_vc_print_status(int channel)
+{
+	u32 r;
+
+	r = dsi2_read_reg(DSI_VC_CTRL(channel));
+	DSSDBG("vc %d: TX_FIFO_NOT_EMPTY %d, BTA_EN %d, VC_BUSY %d, "
+			"TX_FIFO_FULL %d, RX_FIFO_NOT_EMPTY %d, ",
+			channel,
+			FLD_GET(r, 5, 5),
+			FLD_GET(r, 6, 6),
+			FLD_GET(r, 15, 15),
+			FLD_GET(r, 16, 16),
+			FLD_GET(r, 20, 20));
+
+	r = dsi2_read_reg(DSI_TX_FIFO_VC_EMPTINESS);
+	DSSDBG("EMPTINESS %d\n", (r >> (8 * channel)) & 0xff);
+}
+
+static int dsi2_vc_enable(int channel, bool enable)
+{
+//sv 	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)
+//sv		DSSDBG("dsi2_vc_enable channel %d, enable %d\n",
+//sv				channel, enable);
+
+	enable = enable ? 1 : 0;
+
+	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
+#if 0
+	if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
+			DSSERR("Failed to set dsi2_vc_enable to %d\n", enable);
+			return -EIO;
+	}
+#endif
+	return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void dsi2_vc_initial_config(int channel)
+{
+	u32 r;
+
+	DSSDBGF("%d", channel);
+
+	r = dsi2_read_reg(DSI_VC_CTRL(channel));
+
+	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
+		DSSERR("VC(%d) busy when trying to configure it!\n",
+				channel);
+
+	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
+	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
+	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
+	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
+	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
+	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
+	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
+	r = FLD_MOD(r, 3, 11, 10);  //sv5
+	r = FLD_MOD(r, 3, 18, 17);  //sv5
+	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
+	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
+
+	dsi2_write_reg(DSI_VC_CTRL(channel), r);
+	dsi2.vc[channel].mode = DSI_VC_MODE_L4;
+}
+#endif
+
+static void dsi2_vc_config_l4(int channel)
+{
+	if (dsi2.vc[channel].mode == DSI_VC_MODE_L4)
+		return;
+
+	DSSDBGF("%d", channel);
+
+	dsi2_vc_enable(channel, 0);
+
+	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+		DSSERR("vc(%d) busy when trying to config for L4\n", channel);
+
+	REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
+
+	dsi2_vc_enable(channel, 1);
+
+	dsi2.vc[channel].mode = DSI_VC_MODE_L4;
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static void dsi2_vc_config_vp(int channel)
+{
+	if (dsi2.vc[channel].mode == DSI_VC_MODE_VP)
+		return;
+
+	DSSDBGF("%d", channel);
+
+	dsi2_vc_enable(channel, 0);
+
+	if (REG_GET(DSI_VC_CTRL(channel), 15, 15)) /* VC_BUSY */
+		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
+
+	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
+
+	dsi2_vc_enable(channel, 1);
+
+	dsi2.vc[channel].mode = DSI_VC_MODE_VP;
+}
+#endif
+
+static void dsi2_vc_enable_hs(int channel, bool enable)
+{
+	DSSDBG("dsi2_vc_enable_hs(%d, %d)\n", channel, enable);
+
+	dsi2_vc_enable(channel, 0);
+	dsi2_if_enable(0);
+
+	REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
+
+	dsi2_vc_enable(channel, 1);
+	dsi2_if_enable(1);
+
+	dsi2_force_tx_stop_mode_io();
+}
+
+static void dsi2_vc_flush_long_data(int channel)
+{
+	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+		u32 val;
+		val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
+				(val >> 0) & 0xff,
+				(val >> 8) & 0xff,
+				(val >> 16) & 0xff,
+				(val >> 24) & 0xff);
+	}
+}
+
+static void dsi2_show_rx_ack_with_err(u16 err)
+{
+	DSSERR("\tACK with ERROR (%#x):\n", err);
+	if (err & (1 << 0))
+		DSSERR("\t\tSoT Error\n");
+	if (err & (1 << 1))
+		DSSERR("\t\tSoT Sync Error\n");
+	if (err & (1 << 2))
+		DSSERR("\t\tEoT Sync Error\n");
+	if (err & (1 << 3))
+		DSSERR("\t\tEscape Mode Entry Command Error\n");
+	if (err & (1 << 4))
+		DSSERR("\t\tLP Transmit Sync Error\n");
+	if (err & (1 << 5))
+		DSSERR("\t\tHS Receive Timeout Error\n");
+	if (err & (1 << 6))
+		DSSERR("\t\tFalse Control Error\n");
+	if (err & (1 << 7))
+		DSSERR("\t\t(reserved7)\n");
+	if (err & (1 << 8))
+		DSSERR("\t\tECC Error, single-bit (corrected)\n");
+	if (err & (1 << 9))
+		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
+	if (err & (1 << 10))
+		DSSERR("\t\tChecksum Error\n");
+	if (err & (1 << 11))
+		DSSERR("\t\tData type not recognized\n");
+	if (err & (1 << 12))
+		DSSERR("\t\tInvalid VC ID\n");
+	if (err & (1 << 13))
+		DSSERR("\t\tInvalid Transmission Length\n");
+	if (err & (1 << 14))
+		DSSERR("\t\t(reserved14)\n");
+	if (err & (1 << 15))
+		DSSERR("\t\tDSI Protocol Violation\n");
+}
+
+static u16 dsi2_vc_flush_receive_data(int channel)
+{
+	/* RX_FIFO_NOT_EMPTY */
+	while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+		u32 val;
+		u8 dt;
+		val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+		DSSDBG("\trawval %#08x\n", val);
+		dt = FLD_GET(val, 5, 0);
+		if (dt == DSI_DT_RX_ACK_WITH_ERR) {
+			u16 err = FLD_GET(val, 23, 8);
+			dsi2_show_rx_ack_with_err(err);
+		} else if (dt == DSI_DT_RX_SHORT_READ_1) {
+			DSSDBG("\tDCS short response, 1 byte: %#x\n",
+					FLD_GET(val, 23, 8));
+		} else if (dt == DSI_DT_RX_SHORT_READ_2) {
+			DSSDBG("\tDCS short response, 2 byte: %#x\n",
+					FLD_GET(val, 23, 8));
+		} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
+			DSSDBG("\tDCS long response, len %d\n",
+					FLD_GET(val, 23, 8));
+			dsi2_vc_flush_long_data(channel);
+		} else {
+			DSSERR("\tunknown datatype 0x%02x\n", dt);
+		}
+	}
+	return 0;
+}
+
+static int dsi2_vc_send_bta(int channel)
+{
+	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO &&
+			(dsi2.debug_write || dsi2.debug_read))
+		DSSDBG("dsi2_vc_send_bta %d\n", channel);
+
+	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));
+
+	if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {	/* RX_FIFO_NOT_EMPTY */
+		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
+		dsi2_vc_flush_receive_data(channel);
+	}
+
+	REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
+
+	return 0;
+}
+
+int dsi2_vc_send_bta_sync(int channel)
+{
+	int r = 0;
+	u32 err;
+
+	INIT_COMPLETION(dsi2.bta_completion);
+
+	dsi2_vc_enable_bta_irq(channel);
+
+	r = dsi2_vc_send_bta(channel);
+	if (r)
+		goto err;
+
+	if (wait_for_completion_timeout(&dsi2.bta_completion,
+				msecs_to_jiffies(500)) == 0) {
+		DSSERR("Failed to receive BTA\n");
+		r = -EIO;
+		goto err;
+	}
+
+	err = dsi2_get_errors();
+	if (err) {
+		DSSERR("Error while sending BTA: %x\n", err);
+		r = -EIO;
+		goto err;
+	}
+err:
+	dsi2_vc_disable_bta_irq(channel);
+
+	return r;
+}
+EXPORT_SYMBOL(dsi2_vc_send_bta_sync);
+
+static inline void dsi2_vc_write_long_header(int channel, u8 data_type,
+		u16 len, u8 ecc)
+{
+	u32 val;
+	u8 data_id;
+	ecc = 0; //sv5
+	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));
+
+	/*data_id = data_type | channel << 6; */
+	data_id = data_type | dsi2.vc[channel].dest_per << 6;
+
+	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
+		FLD_VAL(ecc, 31, 24);
+
+	dsi2_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
+}
+
+static inline void dsi2_vc_write_long_payload(int channel,
+		u8 b1, u8 b2, u8 b3, u8 b4)
+{
+	u32 val;
+
+	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
+
+/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
+			b1, b2, b3, b4, val); */
+
+	dsi2_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
+}
+
+static int dsi2_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
+		u8 ecc)
+{
+	/*u32 val; */
+	int i;
+	u8 *p;
+	int r = 0;
+	u8 b1, b2, b3, b4;
+	ecc = 0; //sv5
+
+	if (dsi2.debug_write)
+		DSSDBG("dsi2_vc_send_long, %d bytes\n", len);
+
+
+//sv HS mode
+	printk("we need not come here for send long");
+	/* len + header */
+	if (dsi2.vc[channel].fifo_size * 32 * 4 < len + 4) {
+		DSSERR("unable to send long packet: packet too long.\n");
+		return -EINVAL;
+	}
+	dsi2_vc_config_l4(channel);
+
+	mdelay(2+1);
+	dsi2_vc_write_long_header(channel, data_type, len, ecc);
+
+	/*dsi2_vc_print_status(0); */
+
+	p = data;
+	for (i = 0; i < len >> 2; i++) {
+		if (dsi2.debug_write)
+			DSSDBG("\tsending full packet %d\n", i);
+		/*dsi2_vc_print_status(0); */
+
+		b1 = *p++;
+		b2 = *p++;
+		b3 = *p++;
+		b4 = *p++;
+
+		mdelay(2+1);
+		dsi2_vc_write_long_payload(channel, b1, b2, b3, b4);
+	}
+
+	i = len % 4;
+	if (i) {
+		b1 = 0; b2 = 0; b3 = 0;
+
+		if (dsi2.debug_write)
+			DSSDBG("\tsending remainder bytes %d\n", i);
+
+		switch (i) {
+		case 3:
+			b1 = *p++;
+			b2 = *p++;
+			b3 = *p++;
+			break;
+		case 2:
+			b1 = *p++;
+			b2 = *p++;
+			break;
+		case 1:
+			b1 = *p++;
+			break;
+		}
+
+		mdelay(2+1);
+		dsi2_vc_write_long_payload(channel, b1, b2, b3, 0);
+	}
+
+	return r;
+}
+
+
+#if 0
+int send_short_packet(u8 data_type, u8 vc, u8 data0, u8 data1, bool mode, bool ecc)
+{
+	u32 val,header=0,count=10000;
+
+	/* Configure the Virtual Channel */
+	dsi2_vc_enable(vc,0);
+	/* speed selection (HS or LPS) */
+	val = dsi2_read_reg(DSI_VC_CTRL(vc));
+	if(mode == 1) //HS MODE
+	{
+		val = val | (1<<9);
+	}
+	else if(mode == 0)	 //LP MODE
+	{
+		val = val & ~(1<<9);
+	}
+	dsi2_write_reg(DSI_VC_CTRL(vc),val);
+	/*TODO: can be do the below step before itself, do we need to disable the DSI interface before configuring the 	 * VCs */
+	//	enable_omap_dsi2_interface();
+	dsi2_vc_enable(vc,1);
+	/* Send Short packet */
+	header = (0<<24)|
+			(data1<<16)|
+			(data0<<8)|
+			(0<<6) |
+			(data_type<<0);
+	dsi2_write_reg(DSI_VC_SHORT_PACKET_HEADER(0),header);
+
+	printk("Header = 0x%x",header);
+
+	do	{
+		val = dsi2_read_reg(DSI_VC_IRQSTATUS(vc));
+		}while ( (!(val & 0x00000004)) && (--count));
+	if(count)	{
+		printk("Short packet  success!!! \n\r");
+		/*TODO: this need to be cross check, whether we need to reset the bit */
+		dsi2_write_reg(DSI_VC_IRQSTATUS(vc),0x00000004);
+		return 0;
+		}
+	else	{
+		printk("Failed to send Short packet !!! \n\r");
+		return -1;
+		}
+}
+#endif
+
+static int dsi2_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
+{
+	u32 r;
+	u8 data_id;
+	u32 val, u, count;
+	ecc = 0; //sv5
+	WARN_ON(!mutex_is_locked(&dsi2.bus_lock));
+
+	if (dsi2.debug_write)
+		DSSDBG("dsi2_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
+				channel,
+				data_type, data & 0xff, (data >> 8) & 0xff);
+
+	dsi2_vc_config_l4(channel);
+
+#if 0 //sv3
+	if (FLD_GET(dsi2_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
+		DSSERR("ERROR FIFO FULL, aborting transfer\n");
+		return -EINVAL;
+	}
+#endif
+	data_id = data_type | 0 << 6;
+
+	r = (data_id << 0) | (data << 8) | (0 << 16) | (ecc << 24);
+
+	mdelay(2);
+
+	dsi2_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
+
+	count = 10000;
+
+	do
+	{
+		val = dsi2_read_reg(DSI_VC_IRQSTATUS(channel));
+		for (u=0;u<100000;u++);
+	}while ( (!(val & 0x4)) && (--count));
+
+
+	if(count)
+	{
+		dsi2_write_reg(DSI_VC_IRQSTATUS(channel),val);
+		printk("short Packet  success");
+		return 0;
+	}
+	else
+	{
+		printk("short Packet sent fail");
+	}
+
+	return 0;
+}
+
+int dsi2_vc_send_null(int channel)
+{
+	u8 nullpkg[] = {0, 0, 0, 0};
+	return dsi2_vc_send_long(0, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
+}
+EXPORT_SYMBOL(dsi2_vc_send_null);
+
+int dsi2_vc_dcs_write_nosync(int channel, u8 *data, int len)
+{
+	int r = 0;
+
+	BUG_ON(len == 0);
+
+	if (len == 1) {
+		r = dsi2_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
+				data[0], 0);
+	} else if (len == 2) {
+		r = dsi2_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
+				data[0] | (data[1] << 8), 0);
+	} else {
+		/* 0x39 = DCS Long Write */
+		r = dsi2_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
+				data, len, 0);
+	}
+
+	return r;
+}
+EXPORT_SYMBOL(dsi2_vc_dcs_write_nosync);
+
+int dsi2_vc_dcs_write(int channel, u8 *data, int len)
+{
+	int r =0;
+
+	r = dsi2_vc_dcs_write_nosync(channel, data, len);
+#if 0
+	val = dsi2_read_reg(DSI_VC_IRQSTATUS(channel));
+
+	printk(KERN_ERR "Packet IRQ 0x%x",	val);
+	if(val & 0x4)
+		printk(KERN_ERR "Sent", (val&0x4));
+	if (r)
+		return r;
+#endif
+	/* Some devices need time to process the msg in low power mode.
+	   This also makes the write synchronous, and checks that
+	   the peripheral is still alive */
+//sv3	r = dsi2_vc_send_bta_sync(channel);
+
+	return r;
+}
+EXPORT_SYMBOL(dsi2_vc_dcs_write);
+
+int dsi2_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
+{
+	u32 val;
+	u8 dt;
+	int r;
+
+	if (dsi2.debug_read)
+		DSSDBG("dsi2_vc_dcs_read(ch%d, dcs_cmd %u)\n", channel, dcs_cmd);
+
+	r = dsi2_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
+	if (r)
+		return r;
+
+	r = dsi2_vc_send_bta_sync(channel);
+	if (r)
+		return r;
+
+	/* RX_FIFO_NOT_EMPTY */
+	if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
+		DSSERR("RX fifo empty when trying to read.\n");
+		return -EIO;
+	}
+
+	val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+	if (dsi2.debug_read)
+		DSSDBG("\theader: %08x\n", val);
+	dt = FLD_GET(val, 5, 0);
+	if (dt == DSI_DT_RX_ACK_WITH_ERR) {
+		u16 err = FLD_GET(val, 23, 8);
+		dsi2_show_rx_ack_with_err(err);
+		return -EIO;
+
+	} else if (dt == DSI_DT_RX_SHORT_READ_1) {
+		u8 data = FLD_GET(val, 15, 8);
+		if (dsi2.debug_read)
+			DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
+
+		if (buflen < 1)
+			return -EIO;
+
+		buf[0] = data;
+
+		return 1;
+	} else if (dt == DSI_DT_RX_SHORT_READ_2) {
+		u16 data = FLD_GET(val, 23, 8);
+		if (dsi2.debug_read)
+			DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
+
+		if (buflen < 2)
+			return -EIO;
+
+		buf[0] = data & 0xff;
+		buf[1] = (data >> 8) & 0xff;
+
+		return 2;
+	} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
+		int w;
+		int len = FLD_GET(val, 23, 8);
+		if (dsi2.debug_read)
+			DSSDBG("\tDCS long response, len %d\n", len);
+
+		if (len > buflen)
+			return -EIO;
+
+		/* two byte checksum ends the packet, not included in len */
+		for (w = 0; w < len + 2;) {
+			int b;
+			val = dsi2_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+			if (dsi2.debug_read)
+				DSSDBG("\t\t%02x %02x %02x %02x\n",
+						(val >> 0) & 0xff,
+						(val >> 8) & 0xff,
+						(val >> 16) & 0xff,
+						(val >> 24) & 0xff);
+
+			for (b = 0; b < 4; ++b) {
+				if (w < len)
+					buf[w] = (val >> (b * 8)) & 0xff;
+				/* we discard the 2 byte checksum */
+				++w;
+			}
+		}
+
+		return len;
+
+	} else {
+		DSSERR("\tunknown datatype 0x%02x\n", dt);
+		return -EIO;
+	}
+}
+EXPORT_SYMBOL(dsi2_vc_dcs_read);
+
+
+int dsi2_vc_set_max_rx_packet_size(int channel, u16 len)
+{
+	return dsi2_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
+			len, 0);
+}
+EXPORT_SYMBOL(dsi2_vc_set_max_rx_packet_size);
+
+#ifndef CONFIG_ARCH_OMAP4
+static int dsi2_set_lp_rx_timeout(int ns, int x4, int x16)
+{
+	u32 r;
+	unsigned long fck;
+	int ticks;
+
+	/* ticks in DSI_FCK */
+
+	fck = dsi2_fclk_rate();
+	ticks = (fck / 1000 / 1000) * ns / 1000;
+
+	if (ticks > 0x1fff) {
+		DSSERR("LP_TX_TO too high\n");
+		return -EINVAL;
+	}
+
+	r = dsi2_read_reg(DSI_TIMING2);
+	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
+	r = FLD_MOD(r, x16, 14, 14);	/* LP_RX_TO_X16 */
+	r = FLD_MOD(r, x4, 13, 13);	/* LP_RX_TO_X4 */
+	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
+	dsi2_write_reg(DSI_TIMING2, r);
+
+	DSSDBG("LP_RX_TO %ld ns (%#x ticks)\n",
+			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
+			(fck / 1000 / 1000),
+			ticks);
+
+	return 0;
+}
+
+static int dsi2_set_ta_timeout(int ns, int x8, int x16)
+{
+	u32 r;
+	unsigned long fck;
+	int ticks;
+
+	/* ticks in DSI_FCK */
+
+	fck = dsi2_fclk_rate();
+	ticks = (fck / 1000 / 1000) * ns / 1000;
+
+	if (ticks > 0x1fff) {
+		DSSERR("TA_TO too high\n");
+		return -EINVAL;
+	}
+
+	r = dsi2_read_reg(DSI_TIMING1);
+	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
+	r = FLD_MOD(r, x16, 30, 30);	/* TA_TO_X16 */
+	r = FLD_MOD(r, x8, 29, 29);	/* TA_TO_X8 */
+	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
+	dsi2_write_reg(DSI_TIMING1, r);
+
+//sv3
+	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);
+
+	DSSDBG("TA_TO %ld ns (%#x ticks)\n",
+			(ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1) * 1000) /
+			(fck / 1000 / 1000),
+			ticks);
+
+	return 0;
+}
+
+static int dsi2_set_stop_state_counter(int ns, int x4, int x16)
+{
+	u32 r;
+	unsigned long fck;
+	int ticks;
+
+	/* ticks in DSI_FCK */
+
+	fck = dsi2_fclk_rate();
+	ticks = (fck / 1000 / 1000) * ns / 1000;
+
+	if (ticks > 0x1fff) {
+		DSSERR("STOP_STATE_COUNTER_IO too high\n");
+		return -EINVAL;
+	}
+
+	r = dsi2_read_reg(DSI_TIMING1);
+	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
+	r = FLD_MOD(r, x16, 14, 14);	/* STOP_STATE_X16_IO */
+	r = FLD_MOD(r, x4, 13, 13);	/* STOP_STATE_X4_IO */
+	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
+	dsi2_write_reg(DSI_TIMING1, r);
+//sv3
+	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);
+
+	DSSDBG("STOP_STATE_COUNTER %ld ns (%#x ticks)\n",
+			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
+			(fck / 1000 / 1000),
+			ticks);
+
+	return 0;
+}
+
+static int dsi2_set_hs_tx_timeout(int ns, int x4, int x16)
+{
+	u32 r;
+	unsigned long fck;
+	int ticks;
+
+	/* ticks in TxByteClkHS */
+
+	fck = dsi2.ddr_clk / 4;
+	ticks = (fck / 1000 / 1000) * ns / 1000;
+
+	if (ticks > 0x1fff) {
+		DSSERR("HS_TX_TO too high\n");
+		return -EINVAL;
+	}
+
+	r = dsi2_read_reg(DSI_TIMING2);
+	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
+	r = FLD_MOD(r, x16, 30, 30);	/* HS_TX_TO_X16 */
+	r = FLD_MOD(r, x4, 29, 29);	/* HS_TX_TO_X8 (4 really) */
+	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
+	dsi2_write_reg(DSI_TIMING2, r);
+
+	DSSDBG("HS_TX_TO %ld ns (%#x ticks)\n",
+			(ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1) * 1000) /
+			(fck / 1000 / 1000),
+			ticks);
+
+	return 0;
+}
+static int dsi2_proto_config(struct omap_dss_device *dssdev)
+{
+	u32 r;
+	int buswidth = 0;
+	int div;
+
+	dsi2_config_tx_fifo(DSI_FIFO_SIZE_128,
+			DSI_FIFO_SIZE_0,
+			DSI_FIFO_SIZE_0,
+			DSI_FIFO_SIZE_0);
+
+	dsi2_config_rx_fifo(DSI_FIFO_SIZE_128,
+			DSI_FIFO_SIZE_0,
+			DSI_FIFO_SIZE_0,
+			DSI_FIFO_SIZE_0);
+
+	/* XXX what values for the timeouts? */
+	dsi2_set_stop_state_counter(1000, 0, 0);
+
+	dsi2_set_ta_timeout(50000, 1, 1);
+
+	/* 3000ns * 16 */
+//sv3 	dsi2_set_lp_rx_timeout(3000, 0, 1);
+
+	/* 10000ns * 4 */
+//sv3 	dsi2_set_hs_tx_timeout(10000, 1, 0);
+	dsi2_write_reg(DSI_TIMING2, 0x7FFF7FFF); //sv3
+
+	switch (dssdev->ctrl.pixel_size) {
+	case 16:
+		buswidth = 0;
+		break;
+	case 18:
+		buswidth = 1;
+		break;
+	case 24:
+		buswidth = 2;
+		break;
+	default:
+		BUG();
+	}
+
+	r = dsi2_read_reg(DSI_CTRL);
+//sv3	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
+//sv3	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
+	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
+
+	r = FLD_MOD(r, 1, 11, 11); /*VP_VSYNC_POL */ //sv3
+ 	r = FLD_MOD(r, 1, 9, 9); /*VP_DE_POL */ //sv3
+
+
+	/* TODO: Change for LCD2 support */
+
+	//sv3 div = dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD) /
+		//sv3		dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD);
+	div = 1; //sv3
+	r = FLD_MOD(r, div == 2 ? 0 : 1, 4, 4);	/* VP_CLK_RATIO */
+	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
+	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
+	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
+	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
+//sv3 	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
+//sv3	r = FLD_MOD(r, 1, 24, 24);	/* DISPC_UPDATE_SYNC*/
+	r = FLD_MOD(r, 0, 25, 25);	/* DCS_CMD_CODE, 1=start, 0=continue */
+
+	dsi2_write_reg(DSI_CTRL, r);
+
+	dsi2_vc_initial_config(0);
+
+	/* set all vc targets to peripheral 0 */
+	dsi2.vc[0].dest_per = 0;
+	dsi2.vc[1].dest_per = 0;
+	dsi2.vc[2].dest_per = 0;
+	dsi2.vc[3].dest_per = 0;
+
+	return 0;
+}
+
+static void dsi2_proto_timings(struct omap_dss_device *dssdev)
+{
+	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
+	unsigned tclk_pre, tclk_post;
+	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
+	unsigned ths_trail, ths_exit;
+	unsigned ddr_clk_pre, ddr_clk_post;
+	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
+	unsigned ths_eot;
+	u32 r;
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG0);
+	ths_prepare = FLD_GET(r, 31, 24);
+	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
+	ths_zero = ths_prepare_ths_zero - ths_prepare;
+	ths_trail = FLD_GET(r, 15, 8);
+	ths_exit = FLD_GET(r, 7, 0);
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG1);
+	tlpx = FLD_GET(r, 22, 16) * 2;
+	tclk_trail = FLD_GET(r, 15, 8);
+	tclk_zero = FLD_GET(r, 7, 0);
+
+	r = dsi2_read_reg(DSI_DSIPHY_CFG2);
+	tclk_prepare = FLD_GET(r, 7, 0);
+
+	/* min 8*UI */
+	tclk_pre = 20;
+	/* min 60ns + 52*UI */
+	tclk_post = ns2ddr(60) + 26;
+
+	/* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
+	if (dssdev->phy.dsi.data1_lane != 0 &&
+			dssdev->phy.dsi.data2_lane != 0)
+		ths_eot = 2;
+	else
+		ths_eot = 4;
+
+	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
+			4);
+	ddr_clk_post = DIV_ROUND_UP(tclk_post + tclk_trail, 4) + ths_eot;
+
+	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
+	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
+
+	ddr_clk_pre = 0xA; 	//sv3
+	ddr_clk_post = 0x9;	//sv3
+	r = dsi2_read_reg(DSI_CLK_TIMING);
+	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
+	r = FLD_MOD(r, ddr_clk_post, 7, 0);
+	dsi2_write_reg(DSI_CLK_TIMING, r);
+
+	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
+			ddr_clk_pre,
+			ddr_clk_post);
+
+	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
+		DIV_ROUND_UP(ths_prepare, 4) +
+		DIV_ROUND_UP(ths_zero + 3, 4);
+
+	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
+	enter_hs_mode_lat = 7; //sv3
+	exit_hs_mode_lat = 9; //sv3
+	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
+		FLD_VAL(exit_hs_mode_lat, 15, 0);
+	dsi2_write_reg(DSI_VM_TIMING7, r);
+
+	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
+			enter_hs_mode_lat, exit_hs_mode_lat);
+}
+#endif
+
+#define DSI_DECL_VARS \
+	int __dsi2_cb = 0; u32 __dsi2_cv = 0;
+
+#define DSI_FLUSH(ch) \
+	if (__dsi2_cb > 0) { \
+		/*DSSDBG("sending long packet %#010x\n", __dsi2_cv);*/ \
+		dsi2_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi2_cv); \
+		__dsi2_cb = __dsi2_cv = 0; \
+	}
+
+#define DSI_PUSH(ch, data) \
+	do { \
+		__dsi2_cv |= (data) << (__dsi2_cb * 8); \
+		/*DSSDBG("cv = %#010x, cb = %d\n", __dsi2_cv, __dsi2_cb);*/ \
+		if (++__dsi2_cb > 3) \
+			DSI_FLUSH(ch); \
+	} while (0)
+
+static int dsi2_update_screen_l4(struct omap_dss_device *dssdev,
+			int x, int y, int w, int h)
+{
+	/* Note: supports only 24bit colors in 32bit container */
+	int first = 1;
+	int fifo_stalls = 0;
+	int max_dsi2_packet_size;
+	int max_data_per_packet;
+	int max_pixels_per_packet;
+	int pixels_left;
+	int bytespp = dssdev->ctrl.pixel_size / 8;
+	int scr_width;
+	u32 __iomem *data;
+	int start_offset;
+	int horiz_inc;
+	int current_x;
+	struct omap_overlay *ovl;
+
+	debug_irq = 0;
+
+	DSSDBG("dsi2_update_screen_l4 (%d,%d %dx%d)\n",
+			x, y, w, h);
+
+	ovl = dssdev->manager->overlays[0]; //sv hardcoding of overlays[0] here
+
+	if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
+		return -EINVAL;
+
+	if (dssdev->ctrl.pixel_size != 24)
+		return -EINVAL;
+
+	scr_width = ovl->info.screen_width;
+	data = ovl->info.vaddr;
+
+	start_offset = scr_width * y + x;
+	horiz_inc = scr_width - w;
+	current_x = x;
+
+	/* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
+	 * in fifo */
+
+	/* When using CPU, max long packet size is TX buffer size */
+	max_dsi2_packet_size = dsi2.vc[0].fifo_size * 32 * 4;
+
+	/* we seem to get better perf if we divide the tx fifo to half,
+	   and while the other half is being sent, we fill the other half
+	   max_dsi2_packet_size /= 2; */
+
+	max_data_per_packet = max_dsi2_packet_size - 4 - 1;
+
+	max_pixels_per_packet = max_data_per_packet / bytespp;
+
+	DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
+
+	pixels_left = w * h;
+
+	DSSDBG("total pixels %d\n", pixels_left);
+
+	data += start_offset;
+
+	while (pixels_left > 0) {
+		/* 0x2c = write_memory_start */
+		/* 0x3c = write_memory_continue */
+		u8 dcs_cmd = first ? 0x2c : 0x3c;
+		int pixels;
+		DSI_DECL_VARS;
+		first = 0;
+
+#if 1
+		/* using fifo not empty */
+		/* TX_FIFO_NOT_EMPTY */
+		while (FLD_GET(dsi2_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
+			udelay(1);
+			fifo_stalls++;
+			if (fifo_stalls > 0xfffff) {
+				DSSERR("fifo stalls overflow, pixels left %d\n",
+						pixels_left);
+				dsi2_if_enable(0);
+				return -EIO;
+			}
+		}
+#elif 1
+		/* using fifo emptiness */
+		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
+				max_dsi2_packet_size) {
+			fifo_stalls++;
+			if (fifo_stalls > 0xfffff) {
+				DSSERR("fifo stalls overflow, pixels left %d\n",
+					       pixels_left);
+				dsi2_if_enable(0);
+				return -EIO;
+			}
+		}
+#else
+		while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
+			fifo_stalls++;
+			if (fifo_stalls > 0xfffff) {
+				DSSERR("fifo stalls overflow, pixels left %d\n",
+					       pixels_left);
+				dsi2_if_enable(0);
+				return -EIO;
+			}
+		}
+#endif
+		pixels = min(max_pixels_per_packet, pixels_left);
+
+		pixels_left -= pixels;
+
+		dsi2_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
+				1 + pixels * bytespp, 0);
+
+		DSI_PUSH(0, dcs_cmd);
+
+		while (pixels-- > 0) {
+			u32 pix = __raw_readl(data++);
+
+			DSI_PUSH(0, (pix >> 16) & 0xff);
+			DSI_PUSH(0, (pix >> 8) & 0xff);
+			DSI_PUSH(0, (pix >> 0) & 0xff);
+
+			current_x++;
+			if (current_x == x+w) {
+				current_x = x;
+				data += horiz_inc;
+			}
+		}
+
+		DSI_FLUSH(0);
+	}
+
+	return 0;
+}
+
+static void dsi2_update_screen_dispc(struct omap_dss_device *dssdev,
+		u16 x, u16 y, u16 w, u16 h)
+{
+	int bytespp = dssdev->ctrl.pixel_size / 8;
+	int len;
+	int total_len;
+	int packet_payload;
+	int packet_len;
+	u32 l;
+	bool use_te_trigger;
+	const int channel = 0+1;  //HS mode //sv
+
+	use_te_trigger = dsi2.te_enabled && !dsi2.use_ext_te;
+	if(use_te_trigger)
+		use_te_trigger = 0; //sv HS mode
+
+	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)
+		DSSDBG("dsi2_update_screen_dispc(%d,%d %dx%d)\n",
+				x, y, w, h);
+
+	len = w * h * bytespp;
+
+	/* XXX: one packet could be longer, I think? Line buffer is
+	 * 1024 x 24bits, but we have to put DCS cmd there also.
+	 * 1023 * 3 should work, but causes strange color effects. */
+	packet_payload = min(w, (u16)1020) * bytespp;
+
+	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
+	total_len = (len / packet_payload) * packet_len;
+
+	if (len % packet_payload)
+		total_len += (len % packet_payload) + 1;
+
+	if (0)
+		dsi2_vc_print_status(1);
+
+	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
+	dsi2_write_reg(DSI_VC_TE(channel), l);
+
+	dsi2_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
+
+	if (use_te_trigger)
+		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
+	else
+		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
+	dsi2_write_reg(DSI_VC_TE(channel), l);
+
+	/* We put SIDLEMODE to no-idle for the duration of the transfer,
+	 * because DSS interrupts are not capable of waking up the CPU and the
+	 * framedone interrupt could be delayed for quite a long time. I think
+	 * the same goes for any DSS interrupts, but for some reason I have not
+	 * seen the problem anywhere else than here.
+	 */
+	dispc_disable_sidle();
+
+	dss_start_update(dssdev);
+
+	if (use_te_trigger) {
+		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
+		 * for TE is longer than the timer allows */
+		REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
+
+		dsi2_vc_send_bta(channel);
+	}
+}
+
+static void dsi2_framedone_irq_callback(void *data, u32 mask)
+{
+	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
+	 * turns itself off. However, DSI still has the pixels in its buffers,
+	 * and is sending the data.
+	 */
+
+	/* SIDLEMODE back to smart-idle */
+	dispc_enable_sidle();
+	//sv HS MODE	printk("Framedone IRQ");
+	udelay(100);
+	dsi2.framedone_received = true;
+	wake_up(&dsi2.waitqueue);
+}
+
+static void dsi2_set_update_region(struct omap_dss_device *dssdev,
+		u16 x, u16 y, u16 w, u16 h)
+{
+	spin_lock(&dsi2.update_lock);
+	if (dsi2.update_region.dirty) {
+		dsi2.update_region.x = min(x, dsi2.update_region.x);
+		dsi2.update_region.y = min(y, dsi2.update_region.y);
+		dsi2.update_region.w = max(w, dsi2.update_region.w);
+		dsi2.update_region.h = max(h, dsi2.update_region.h);
+	} else {
+		dsi2.update_region.x = x;
+		dsi2.update_region.y = y;
+		dsi2.update_region.w = w;
+		dsi2.update_region.h = h;
+	}
+
+	dsi2.update_region.device = dssdev;
+	dsi2.update_region.dirty = true;
+
+	spin_unlock(&dsi2.update_lock);
+
+}
+
+static void dsi2_start_auto_update(struct omap_dss_device *dssdev)
+{
+	u16 w, h;
+	int i;
+
+	DSSDBG("starting auto update\n");
+
+	//sv HS mode set the GFX threshold there properly before apply
+
+	/* In automatic mode the overlay settings are applied like on DPI/SDI.
+	 * Mark the overlays dirty, so that we get the overlays configured, as
+	 * manual mode has left them in bad shape after config partia planes */
+	for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
+		struct omap_overlay *ovl;
+		ovl = omap_dss_get_overlay(i);
+		if (ovl->manager == dssdev->manager)
+			ovl->info_dirty = true;
+		printk(KERN_ERR "ovl[%d]->manager = %s", i, ovl->manager->name);
+	}
+
+	printk(KERN_ERR "dssdev->manager->device->driver_name = %s",
+		dssdev->manager->device->driver_name);
+
+	dssdev->manager->apply(dssdev->manager);
+
+	dssdev->get_resolution(dssdev, &w, &h);
+
+	dsi2_set_update_region(dssdev, 0, 0, w, h);
+
+	//sv HS MODE
+//sv	__raw_writel(0x03FC03BC, dispc_base + 0xA4); //DISPC_GFX_THRESHOLD
+
+	dsi2_perf_mark_start_auto();
+
+	wake_up(&dsi2.waitqueue);
+}
+
+static int dsi2_set_te(struct omap_dss_device *dssdev, bool enable)
+{
+	int r;
+
+	dssdev->driver->enable_te(dssdev, enable);
+	r = dssdev->driver->enable_te(dssdev, enable);
+	/* XXX for some reason, DSI TE breaks if we don't wait here.
+	 * Panel bug? Needs more studying */
+	msleep(100);
+	return r;
+}
+
+static void dsi2_handle_framedone(void)
+{
+	bool use_te_trigger;
+
+	use_te_trigger = dsi2.te_enabled && !dsi2.use_ext_te;
+	if(use_te_trigger)
+		use_te_trigger = 0; //sv HS mode
+
+	if (dsi2.update_mode != OMAP_DSS_UPDATE_AUTO)
+		DSSDBG("FRAMEDONE\n");
+
+	if (use_te_trigger) {
+		/* enable LP_RX_TO again after the TE */
+		REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
+	}
+
+	/* Send BTA after the frame. We need this for the TE to work, as TE
+	 * trigger is only sent for BTAs without preceding packet. Thus we need
+	 * to BTA after the pixel packets so that next BTA will cause TE
+	 * trigger.
+	 *
+	 * This is not needed when TE is not in use, but we do it anyway to
+	 * make sure that the transfer has been completed. It would be more
+	 * optimal, but more complex, to wait only just before starting next
+	 * transfer. */
+#if 0
+	r = dsi2_vc_send_bta_sync(channel);
+	if (r)
+		DSSERR("BTA after framedone failed\n");
+#endif
+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
+	dispc_fake_vsync_irq();
+#endif
+}
+
+static int dsi2_update_thread(void *data)
+ {
+	unsigned long timeout;
+	struct omap_dss_device *device;
+	u16 x, y, w, h;
+
+	while (1) {
+		bool sched;
+
+		wait_event_interruptible(dsi2.waitqueue,
+				dsi2.update_mode == OMAP_DSS_UPDATE_AUTO ||
+				(dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL &&
+				 dsi2.update_region.dirty == true) ||
+				kthread_should_stop());
+
+		if (kthread_should_stop())
+			break;
+
+		dsi2_bus_lock();
+
+		if (dsi2.update_mode == OMAP_DSS_UPDATE_DISABLED ||
+			kthread_should_stop()) {
+			dsi2_bus_unlock();
+			break;
+		}
+
+		dsi2_perf_mark_setup();
+
+		if (dsi2.update_region.dirty) {
+			spin_lock(&dsi2.update_lock);
+			dsi2.active_update_region = dsi2.update_region;
+			dsi2.update_region.dirty = false;
+			spin_unlock(&dsi2.update_lock);
+		}
+
+		device = dsi2.active_update_region.device;
+		x = dsi2.active_update_region.x;
+		y = dsi2.active_update_region.y;
+		w = dsi2.active_update_region.w;
+		h = dsi2.active_update_region.h;
+
+		if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
+
+			if (dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL) {
+				dss_setup_partial_planes(device,
+						&x, &y, &w, &h);
+#if 1
+				/* XXX there seems to be a bug in this driver
+				 * or OMAP hardware.  Some updates with certain
+				 * widths and x coordinates fail. These widths
+				 * are always odd, so "fix" it here for now */
+				if (w & 1) {
+					u16 dw, dh;
+					device->get_resolution(device,
+						&dw, &dh);
+					if (x + w == dw)
+						x &= ~1;
+					++w;
+					dss_setup_partial_planes(device,
+							&x, &y, &w, &h);
+				}
+#endif
+			}
+
+			dispc_set_lcd_size(OMAP_DSS_CHANNEL_LCD2, w, h);
+			/* TODO: Correct this while adding support for LCD2 */
+		}
+
+		if (dsi2.active_update_region.dirty) {
+			dsi2.active_update_region.dirty = false;
+			/* XXX TODO we don't need to send the coords, if they
+			 * are the same that are already programmed to the
+			 * panel. That should speed up manual update a bit */
+			device->driver->setup_update(device, x, y, w, h);
+		}
+
+		dsi2_perf_mark_start();
+
+		if (device->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
+			 //sv HS mode dsi2_vc_config_vp(0+1); //Video mode use channel1
+			 /*Since we have already configured the VC Ctrl of Video channel */
+
+			if (dsi2.te_enabled && dsi2.use_ext_te)
+				device->driver->wait_for_te(device);
+
+			dsi2.framedone_received = false;
+			dsi2_update_screen_dispc(device, x, y, w, h);
+
+			/* wait for framedone */
+			timeout = msecs_to_jiffies(1000);
+			timeout = wait_event_timeout(dsi2.waitqueue,
+					dsi2.framedone_received == true,
+					timeout);
+
+			if (timeout == 0) {
+				DSSERR("dsi2 framedone timeout\n"); //svov3
+				printk("DSS_CONTROL = 0x%x", __raw_readl(dss_base + 0x40) );
+				//svov3 DSSERR("failed update %d,%d %dx%d\n",
+						//svov3 x, y, w, h);
+
+				dispc_enable_sidle();
+				/* TODO: update for LCD2 support */
+				dispc_enable_lcd_out(OMAP_DSS_CHANNEL_LCD2, 0);
+			} else {
+				dsi2_handle_framedone();
+				dsi2_perf_show("DISPC");
+			}
+		} else {
+			dsi2_update_screen_l4(device, x, y, w, h);
+			dsi2_perf_show("L4");
+		}
+
+		sched = atomic_read(&dsi2.bus_lock.count) < 0;
+
+		complete_all(&dsi2.update_completion);
+
+		dsi2_bus_unlock();
+
+		/* XXX We need to give others chance to get the bus lock. Is
+		 * there a better way for this? */
+	 	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO && sched)
+			schedule_timeout_interruptible(1);
+	}
+
+	DSSDBG("update thread exiting\n");
+
+	return 0;
+ }
+
+
+/* Display funcs */
+
+static int dsi2_display_init_dispc(struct omap_dss_device *dssdev)
+{
+	int r;
+
+	r = omap_dispc_register_isr(dsi2_framedone_irq_callback, NULL,
+			DISPC_IRQ_FRAMEDONE);
+	if (r) {
+		DSSERR("can't get FRAMEDONE irq\n");
+		return r;
+	}
+#if 1 //sv3
+	/* TODO: Change here for LCD2 support*/
+	dispc_set_lcd_display_type(OMAP_DSS_CHANNEL_LCD2,
+					OMAP_DSS_LCD_DISPLAY_TFT);
+
+	dispc_set_parallel_interface_mode(OMAP_DSS_CHANNEL_LCD2,
+					OMAP_DSS_PARALLELMODE_DSI);
+//sv	dispc_enable_fifohandcheck(1);
+
+	dispc_set_tft_data_lines(OMAP_DSS_CHANNEL_LCD2, dssdev->ctrl.pixel_size);
+
+//sv HS mode
+	{
+		struct omap_video_timings timings = {
+			.hsw		= 4+1,
+			.hfp		= 4+1,
+			.hbp		= 4+1,
+			.vsw		= 0+1, //before writing to the register it subtracts 1
+			.vfp		= 0,
+			.vbp		= 1,
+			.x_res	= 864,
+			.y_res	= 480,
+		};
+
+		dispc_set_lcd_timings(OMAP_DSS_CHANNEL_LCD2, &timings);
+	}
+	dispc_set_pol_freq(OMAP_DSS_CHANNEL_LCD2, dssdev->panel.config,
+			dssdev->panel.acbi, dssdev->panel.acb);
+
+	dispc_set_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, 1/*lck_div*/,
+							0x6/*pck_div*/);
+#else
+	/*DISPC_CONTROL = 0x18B48; */
+	/*DISPC_CONFIG = 0x4; */
+	/*DISPC_DIVISOR = 0x10006; */
+
+	__raw_writel(0xb28, dispc_base + 0x238); //DISPC_CONTROL2
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	// __raw_writel(0x0, dispc_base + 0x620); //DISPC_CONFIG2
+	// __raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x3fc03bc, dispc_base + 0x38c); //VID3_THRESH
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x1df035f, dispc_base + 0x394); //VID3_PICT_SIZE
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x1df035f, dispc_base + 0x3a8); //VID3_SIZE
+	__raw_readl( dispc_base + 0x00);  //sv
+
+//	__raw_writel(0x1df035f, dispc_base + 0x3cc); //SIZE_LCD2
+//	__raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x40008411, dispc_base + 0x62c); //DISPC_VID3_ATTRIBUTES
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x10006, dispc_base + 0x40c); //DISPC_DIVISOR2
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	__raw_writel(0x00400404  , dispc_base + 0x400); //DISPC_H2_TIMING
+	__raw_readl( dispc_base + 0x00);  //sv
+	__raw_writel(0x00100000  , dispc_base + 0x404); //DISPC_V2_TIMING
+	__raw_readl( dispc_base + 0x00);  //sv
+	__raw_writel(0x30000    , dispc_base + 0x408); //DISPC_V_TIMIPOL_FREQ2
+	__raw_readl( dispc_base + 0x00);  //sv
+//sv	__raw_writel(0x01DF035F    , dispc_base + 0x7C); //DISPC_SIZE_LCD1
+//sv	__raw_readl( dispc_base + 0x00);  //sv
+
+	//__raw_writel(0x03FC03BC, dispc_base + 0xA4); //DISPC_GFX_THRESHOLD
+  	__raw_writel(0x1F, dispc_base + 0x3aC); //DISPC_DEF_COLOR2
+
+	__raw_dumpl(DISPC_CONTROL2, dispc_base + 0x238);
+	__raw_dumpl(VID3_THRESH, dispc_base + 0x38c);
+	__raw_dumpl(VID3_PICT_SIZE, dispc_base + 0x394);
+	__raw_dumpl(VID3_SIZE, dispc_base + 0x3a8);
+	__raw_dumpl(DISPC_VID3_ATTRIBUTES, dispc_base + 0x62c);
+	__raw_dumpl(DISPC_DIVISOR2, dispc_base + 0x40c);
+	__raw_dumpl(DISPC_H2_TIMING, dispc_base + 0x400);
+	__raw_dumpl(DISPC_V2_TIMING, dispc_base + 0x404);
+	__raw_dumpl(DISPC_V_TIMIPOL_FREQ2, dispc_base + 0x408);
+	__raw_dumpl(DISPC_DEF_COLOR2, dispc_base + 0x3aC);
+#endif
+	return 0;
+}
+
+static void dsi2_display_uninit_dispc(struct omap_dss_device *dssdev)
+{
+	omap_dispc_unregister_isr(dsi2_framedone_irq_callback, NULL,
+			DISPC_IRQ_FRAMEDONE);
+}
+
+static int dsi2_display_init_dsi(struct omap_dss_device *dssdev)
+{
+	int r;
+#if 0 //comment everything
+#if 0 //sv3
+	struct dsi_clock_info cinfo;
+	u32 val,l;
+	u32 control_core_base;
+	val = dsi2_read_reg(DSI_CLK_CTRL);
+	printk(KERN_INFO "\n DSI_CLK_CONTROL = 0x%X (bit 14 should be 1 ", val);
+	val = val |(1<<14);
+	dsi2_write_reg(DSI_CLK_CTRL, val);
+	val = dsi2_read_reg(DSI_CLK_CTRL);
+	printk(KERN_INFO "\n DSI_CLK_CONTROL = 0x%X (bit 14 should be 1 ", val);
+
+	_dsi2_print_reset_status();
+#else
+
+	omap_writel(0xFFFF0000, 0x4A100618);
+	printk(KERN_INFO "\n CONTROL_DSIPHY = 0x%X ", omap_readl(0x4A100618));
+
+
+	dsi2_if_enable(0);
+	dsi2_vc_enable(0,0); //videochannel
+	dsi2_vc_enable(1,0); //cmdchannel
+
+/*************SIVAL ***************/
+
+	l = dsi2_read_reg(DSI_CLK_CTRL);
+	l = ( l |
+		(0x2 << 30) |
+		(0x1 << 21) |
+		(0x1 << 20) |
+		(0x1 << 18));
+	dsi2_write_reg(DSI_CLK_CTRL, l);
+	l = dsi2_read_reg(DSI_CLK_CTRL);
+	l = (l & (~(0x3 << 15)) );
+	dsi2_write_reg(DSI_CLK_CTRL, l);
+	l = dsi2_read_reg(DSI_CLK_CTRL);
+	l = ( l |
+		(0x1 << 14) |
+		(0x1 << 13));
+	dsi2_write_reg(DSI_CLK_CTRL, l);
+
+	printk(KERN_INFO "Checking pll pwr status");
+	/* PLL_PWR_STATUS */
+	while (FLD_GET(dsi2_read_reg(DSI_CLK_CTRL), 29, 28) != 0x2) ;
+
+/***************************************/
+
+#if 1 //Sival
+
+	/*Config Video port */
+	dsi2_write_reg(DSI_CTRL,0x00006A18);
+
+	/*Config VideoMode Timing */
+	dsi2_write_reg(DSI_CLK_CTRL,0x00346006);
+	dsi2_write_reg(DSI_VM_TIMING1,0x02004006);
+	dsi2_write_reg(DSI_VM_TIMING2,0x04010001);
+	dsi2_write_reg(DSI_VM_TIMING3,0x036F01E0);
+	dsi2_write_reg(DSI_VM_TIMING4,0x00487296);
+	dsi2_write_reg(DSI_VM_TIMING5,0x0082DF3B);
+	dsi2_write_reg(DSI_VM_TIMING6,0x7A6731D1);
+	dsi2_write_reg(DSI_VM_TIMING7,0x00090007);
+
+	/*Config VC channel */
+	dsi2_write_reg(DSI_VC_CTRL(0),0x60809382);  //video channel
+	dsi2_write_reg(DSI_VC_CTRL(1),0x20868D80); //cmd channel
+
+	//Clear all IRQ
+	dsi2_write_reg(DSI_VC_IRQSTATUS(0), 0xFF);
+	dsi2_write_reg(DSI_VC_IRQENABLE(0), 0x0);
+
+	//Clear all IRQ
+	dsi2_write_reg(DSI_VC_IRQSTATUS(1), 0xFF);
+	dsi2_write_reg(DSI_VC_IRQENABLE(1), 0x0);
+
+	/* Config FIfo size */
+	dsi2_write_reg(DSI_TX_FIFO_VC_SIZE,0x00004040);
+	dsi2_write_reg(DSI_RX_FIFO_VC_SIZE,0x00001010);
+
+	dsi2_write_reg(DSI_IRQSTATUS, 0x1FFFFF);
+#endif
+#endif
+
+	r = dsi2_pll_init(1, 0);
+	if (r)
+		goto err0;
+
+	r = dsi2_pll_calc_ddrfreq(dssdev->phy.dsi.ddr_clk_hz, &cinfo);
+	if (r)
+		goto err1;
+
+	r = dsi2_pll_program(&cinfo);
+	if (r)
+		goto err1;
+
+	DSSDBG("PLL OK\n");
+
+
+//sv3	/*Switch to dsi2 pll DSS_CONTROL Func switch to pll1 for lcd1,dsi1 */
+	val = __raw_readl(dss_base + 0x0040); //DSS_CONTROL
+	val = val | (1<<1) | (1<<0);
+	__raw_writel(val, dss_base + 0x0040); //DSS_CONTROL
+	__raw_readl( dss_base + 0x00);  //sv
+
+//sv3	/*Switch to dsi2 pll DSS_CONTROL  Func switch to pll1 for dispc */
+	val = __raw_readl(dss_base + 0x0040); //DSS_CONTROL
+	val = val | (1<<8);
+	val = val & (~(1<<9));
+	__raw_writel(val, dss_base + 0x0040); //DSS_CONTROL
+	__raw_readl( dss_base + 0x00);  //sv
+
+//sv3  /*GO Digital or GO LCd bit to be updated */
+	__raw_writel(0x18B69, dispc_base + 0x0040); //DISPC_CONTROL - Go LCD bit 5
+	__raw_readl( dispc_base + 0x00);  //sv
+
+	udelay(100);
+
+	r = dsi2_complexio_init(dssdev);
+	if (r)
+		goto err1;
+#if 0 //sv3
+	_dsi2_print_reset_status();
+
+	dsi2_proto_timings(dssdev);
+
+//sv3
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 13, 13); /* DDR_CLK_ALWAYS_ON*/
+	REG_FLD_MOD(DSI_CLK_CTRL, 1, 18, 18); /* HS_AUTO_STOP_ENABLE*/
+//sv3
+
+	dsi2_set_lp_clk_divisor(dssdev);
+
+	if (1)
+		_dsi2_print_reset_status();
+
+	r = dsi2_proto_config(dssdev);
+	if (r)
+		goto err2;
+#else
+	dsi2_write_reg(DSI_TIMING1, 0x7FFF7FFF);
+	dsi2_vc_enable(1,0);
+	dsi2_vc_enable(1,1);
+	dsi2_write_reg(DSI_TIMING2, 0x7FFF7FFF);
+	dsi2_write_reg(DSI_CLK_TIMING, 0xA09);
+	udelay(100); //added for trial
+#endif
+	/* enable interface */
+	dsi2_if_enable(1);
+	dsi2_vc_enable(1, 1); //cmd channel
+	dsi2_vc_enable(0, 1);  //video channel
+	dsi2_force_tx_stop_mode_io();
+
+	udelay(100); //added for trial
+
+    // Register 12
+    	val = 0;
+       val = val | (0x58 << 0);
+       dsi2_write_reg(DSI_DSIPHY_CFG12,val);
+
+        // Register 14
+        val = 0;
+        val = val | (1 << 31) |  (0x54 << 23) |  (0x7 << 14);
+	val = FLD_MOD(val,1,31,31);
+	val = FLD_MOD(val,1,11,11);
+	val = FLD_MOD(val,1,19,19);
+	val = FLD_MOD(val,1,18,18);
+
+       dsi2_write_reg(DSI_DSIPHY_CFG14,val);
+
+        // Register 8
+        val = 0;
+        val = val | (1 << 11) | (16 << 6) | (0xE << 0);
+	val = FLD_MOD(val,1,5,5);
+	dsi2_write_reg(DSI_DSIPHY_CFG8,val);
+
+#if 1 //testing
+	mdelay(100);
+	{
+	volatile int i = 1;
+	while(i){
+	send_short_packet(0x5, 1, 0x1, 0, 0, 0);
+	}
+	}
+#endif
+#endif
+
+	dsi2.vc[0].fifo_size = DSI_FIFO_SIZE_96;
+	dsi2.vc[1].fifo_size = DSI_FIFO_SIZE_128;
+	dsi2.vc[2].fifo_size = DSI_FIFO_SIZE_0;
+	dsi2.vc[3].fifo_size = DSI_FIFO_SIZE_0;
+
+	Setup_SDP((void *)dsi2.base, 1);
+	if (dssdev->driver->enable) {
+		r = dssdev->driver->enable(dssdev);
+		if (r)
+			goto err3;
+	}
+#if 0 //svov3
+//sv	/*Enable Lcd interface */
+	val = __raw_readl( dispc_base + 0x238);  //sv
+	val |= (0x1 << 0) | (1 << 5);
+	__raw_writel(val, dispc_base + 0x238); //DISPC_CONTROL  should be 0x18B29 now
+#endif
+	/* enable high-speed after initial config */
+//sv3	dsi2_vc_enable_hs(0, 1);
+
+	return 0;
+	// MJ
+err3:
+#if 0
+	dsi_if_enable(0);
+err2:
+	dsi_complexio_uninit();
+err1:
+	dsi_pll_uninit();
+err0:
+#endif
+	return r;
+}
+
+static void dsi2_display_uninit_dsi(struct omap_dss_device *dssdev)
+{
+	if (dssdev->driver->disable)
+		dssdev->driver->disable(dssdev);
+
+	dsi2_complexio_uninit();
+	dsi2_pll_uninit();
+}
+
+#ifndef CONFIG_ARCH_OMAP4
+static int dsi2_core_init(void)
+{
+	REG_FLD_MOD(DSI_SYSCONFIG, 0, 0, 0);
+
+#if 0
+	/* ENWAKEUP */
+	REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
+
+	/* SIDLEMODE smart-idle */
+	REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
+#endif
+	_dsi2_initialize_irq();
+
+	return 0;
+}
+#endif
+
+#define GPIO_OE		0x134
+#define GPIO_DATAOUT	0x13C
+#define OMAP24XX_GPIO_CLEARDATAOUT	0x190
+#define OMAP24XX_GPIO_SETDATAOUT	0x194
+
+static int dsi2_display_enable(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+
+	DSSDBG("dsi2_display_enable\n");
+
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	r = omap_dss_start_device(dssdev);
+	if (r) {
+		DSSERR("failed to start device\n");
+		goto err0;
+	}
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
+		DSSERR("dssdev already enabled\n");
+		r = -EINVAL;
+		goto err1;
+	}
+
+//sv	enable_clocks(1);
+//sv	dsi2_enable_pll_clock(1);
+
+	omap_writel(0x00030007  , 0x4A307100);  //DSS_PWR_DSS_DSS_CTRL
+
+//sv3  /*GO Digital or GO LCd bit to be updated */
+//sv3  	__raw_writel(0x18B29, dispc_base + 0x0040); //DISPC_CONTROL - LCD en Bit 0
+//sv3  	__raw_writel(0x18B29, dispc_base + 0x0040); //DISPC_CONTROL - Go LCD bit 5
+//sv3  	mdelay(10);
+
+	r = _dsi2_reset();
+	if (r)
+		goto err2;
+/*
+	{
+	volatile int i =1;
+	printk("Doing GPIO reset");
+	while(i)
+	{*/
+#if 0
+	gpio_base_dsi2=ioremap(0x48059000,0x1000);
+
+
+	val = __raw_readl(gpio_base_dsi2+GPIO_OE);
+	val &= ~0x140;
+	__raw_writel(val, gpio_base_dsi2+GPIO_OE);
+
+	mdelay(120);
+
+	/* To output signal high */
+	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);
+	val |= 0x140;
+	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);
+	mdelay(120);
+
+	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_CLEARDATAOUT);
+	val |= 0x140;
+	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_CLEARDATAOUT);
+	mdelay(120);
+
+	val = __raw_readl(gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);
+	val |= 0x140;
+	__raw_writel(val, gpio_base_dsi2+OMAP24XX_GPIO_SETDATAOUT);
+
+	mdelay(120);
+//		}
+//		}
+	printk("GPIO 104 reset done ");
+
+#endif
+#if 0
+	*(volatile int*)(GPIO_OE) = (*(volatile int*)(GPIO_OE) & ~0x40);
+	/* To output signal high */
+	*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) =
+			(*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) | 0x40);
+	mdelay(10);
+	/* To output signal low */
+	*(volatile int*)(OMAP24XX_GPIO_CLEARDATAOUT) =
+			(*(volatile int*)(OMAP24XX_GPIO_CLEARDATAOUT) | 0x40);
+	mdelay(10);
+	/* To output signal high */
+	*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) =
+			(*(volatile int*)(OMAP24XX_GPIO_SETDATAOUT) | 0x40);
+	mdelay(10);
+#endif
+
+#if 0 //comment everything
+	dsi2_core_init();
+#if 0
+	dsi2_write_reg(DSI_SYSCONFIG, 0x10);
+#endif
+#endif
+#if 1
+	r = dsi2_display_init_dispc(dssdev);
+	if (r)
+		goto err2;
+
+	r = dsi2_display_init_dsi(dssdev);
+	if (r)
+		goto err3;
+
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	dsi2.use_ext_te = dssdev->phy.dsi.ext_te;
+	r = dsi2_set_te(dssdev, dsi2.te_enabled);
+	if (r)
+		goto err3;
+
+	dsi2.user_update_mode = OMAP_DSS_UPDATE_AUTO; //svov3
+	dsi2.update_mode = dsi2.user_update_mode;
+
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO)
+		dsi2_start_auto_update(dssdev);
+
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+#endif
+
+#if 0 //svov3 not a good one
+	printk("DSI2_PLL %x\n", __raw_readl(dsi2_base+0x304));
+	//printk("DSI_PLL %x\n", __raw_readl(dsi2_base+0x304));
+
+	val = __raw_readl(dss_base+0x40);
+	val |= 0x1503;
+	__raw_writel(val, dss_base+0x40);
+	printk("DSS_STATUS %x\n", __raw_readl(dss_base+0x5c));
+#endif
+	return 0;
+// MJ
+err3:
+//	dsi2_display_uninit_dispc(dssdev);
+err2:
+//	enable_clocks(0);
+//	dsi2_enable_pll_clock(0);
+err1:
+//	omap_dss_stop_device(dssdev);
+err0:
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+	DSSDBG("dsi2_display_enable FAILED\n");
+	return 0; //r
+
+
+}
+
+static void dsi2_display_disable(struct omap_dss_device *dssdev)
+{
+	DSSDBG("dsi2_display_disable\n");
+
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
+			dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
+		goto end;
+
+	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;
+	dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+	dsi2_display_uninit_dispc(dssdev);
+
+	dsi2_display_uninit_dsi(dssdev);
+
+	enable_clocks(0);
+	dsi2_enable_pll_clock(0);
+
+	omap_dss_stop_device(dssdev);
+end:
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+}
+
+static int dsi2_display_suspend(struct omap_dss_device *dssdev)
+{
+	DSSDBG("dsi2_display_suspend\n");
+#if 0 //svov3
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED ||
+			dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED)
+		goto end;
+
+	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;
+	dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
+
+	dsi2_display_uninit_dispc(dssdev);
+
+	dsi2_display_uninit_dsi(dssdev);
+
+	enable_clocks(0);
+	dsi2_enable_pll_clock(0);
+end:
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+#endif
+	return 0;
+}
+
+static int dsi2_display_resume(struct omap_dss_device *dssdev)
+{
+	int r = 0;
+
+	DSSDBG("dsi2_display_resume\n");
+#if 0 //svov3
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) {
+		DSSERR("dssdev not suspended\n");
+		r = -EINVAL;
+		goto err0;
+	}
+
+	enable_clocks(1);
+	dsi2_enable_pll_clock(1);
+
+	r = _dsi2_reset();
+	if (r)
+		goto err1;
+
+	dsi2_core_init();
+
+	r = dsi2_display_init_dispc(dssdev);
+	if (r)
+		goto err1;
+
+	r = dsi2_display_init_dsi(dssdev);
+	if (r)
+		goto err2;
+
+	dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+	r = dsi2_set_te(dssdev, dsi2.te_enabled);
+	if (r)
+		goto err2;
+
+	dsi2.update_mode = dsi2.user_update_mode;
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO)
+		dsi2_start_auto_update(dssdev);
+
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+
+	return 0;
+
+err2:
+	dsi2_display_uninit_dispc(dssdev);
+err1:
+	enable_clocks(0);
+	dsi2_enable_pll_clock(0);
+err0:
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+	DSSDBG("dsi2_display_resume FAILED\n");
+#endif
+	return r;
+}
+
+static int dsi2_display_update(struct omap_dss_device *dssdev,
+			u16 x, u16 y, u16 w, u16 h)
+{
+	int r = 0;
+	u16 dw, dh;
+
+	DSSDBG("dsi2_display_update(%d,%d %dx%d)\n", x, y, w, h);
+
+	mutex_lock(&dsi2.lock);
+
+	if (dsi2.update_mode != OMAP_DSS_UPDATE_MANUAL)
+		goto end;
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+		goto end;
+
+	dssdev->get_resolution(dssdev, &dw, &dh);
+
+	if  (x > dw || y > dh)
+		goto end;
+
+	if (x + w > dw)
+		w = dw - x;
+
+	if (y + h > dh)
+		h = dh - y;
+
+	if (w == 0 || h == 0)
+		goto end;
+
+	dsi2_set_update_region(dssdev, x, y, w, h);
+
+	wake_up(&dsi2.waitqueue);
+
+end:
+	mutex_unlock(&dsi2.lock);
+
+	return r;
+}
+
+static int dsi2_display_sync(struct omap_dss_device *dssdev)
+{
+	bool wait;
+
+	DSSDBG("dsi2_display_sync()\n");
+
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_MANUAL &&
+			dsi2.update_region.dirty) {
+		INIT_COMPLETION(dsi2.update_completion);
+		wait = true;
+	} else {
+		wait = false;
+	}
+
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+
+	if (wait)
+		wait_for_completion_interruptible(&dsi2.update_completion);
+
+	DSSDBG("dsi2_display_sync() done\n");
+	return 0;
+}
+
+static int dsi2_display_set_update_mode(struct omap_dss_device *dssdev,
+		enum omap_dss_update_mode mode)
+{
+	DSSDBGF("%d", mode);
+
+	mutex_lock(&dsi2.lock);
+	dsi2_bus_lock();
+
+	if (dsi2.update_mode != mode) {
+		dsi2.user_update_mode = mode;
+		dsi2.update_mode = mode;
+
+		if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE &&
+				mode == OMAP_DSS_UPDATE_AUTO)
+			dsi2_start_auto_update(dssdev);
+	}
+
+	dsi2_bus_unlock();
+	mutex_unlock(&dsi2.lock);
+
+	return 0;
+}
+
+static enum omap_dss_update_mode dsi2_display_get_update_mode(
+		struct omap_dss_device *dssdev)
+{
+	return dsi2.update_mode;
+}
+
+
+static int dsi2_display_enable_te(struct omap_dss_device *dssdev, bool enable)
+{
+	int r = 0;
+	DSSDBGF("%d", enable);
+
+	if (!dssdev->driver->enable_te)
+		return -ENOENT;
+
+	dsi2_bus_lock();
+
+	dsi2.te_enabled = enable;
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+		goto end;
+
+	r = dsi2_set_te(dssdev, enable);
+end:
+	dsi2_bus_unlock();
+
+	return r;
+}
+
+static int dsi2_display_get_te(struct omap_dss_device *dssdev)
+{
+	return dsi2.te_enabled;
+}
+
+static int dsi2_display_set_rotate(struct omap_dss_device *dssdev, u8 rotate)
+{
+
+	DSSDBGF("%d", rotate);
+
+	if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
+		return -EINVAL;
+
+	dsi2_bus_lock();
+	dssdev->driver->set_rotate(dssdev, rotate);
+	if (dsi2.update_mode == OMAP_DSS_UPDATE_AUTO) {
+		u16 w, h;
+		/* the display dimensions may have changed, so set a new
+		 * update region */
+		dssdev->get_resolution(dssdev, &w, &h);
+		dsi2_set_update_region(dssdev, 0, 0, w, h);
+	}
+	dsi2_bus_unlock();
+
+	return 0;
+}
+
+static u8 dsi2_display_get_rotate(struct omap_dss_device *dssdev)
+{
+	if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
+		return 0;
+
+	return dssdev->driver->get_rotate(dssdev);
+}
+
+static int dsi2_display_set_mirror(struct omap_dss_device *dssdev, bool mirror)
+{
+	DSSDBGF("%d", mirror);
+
+	if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
+		return -EINVAL;
+
+	dsi2_bus_lock();
+	dssdev->driver->set_mirror(dssdev, mirror);
+	dsi2_bus_unlock();
+
+	return 0;
+}
+
+static bool dsi2_display_get_mirror(struct omap_dss_device *dssdev)
+{
+	if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
+		return 0;
+
+	return dssdev->driver->get_mirror(dssdev);
+}
+
+static int dsi2_display_run_test(struct omap_dss_device *dssdev, int test_num)
+{
+	int r;
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+		return -EIO;
+
+	DSSDBGF("%d", test_num);
+
+	dsi2_bus_lock();
+
+	/* run test first in low speed mode */
+	dsi2_vc_enable_hs(0, 0);
+
+	if (dssdev->driver->run_test) {
+		r = dssdev->driver->run_test(dssdev, test_num);
+		if (r)
+			goto end;
+	}
+
+	/* then in high speed */
+	dsi2_vc_enable_hs(0, 1);
+
+	if (dssdev->driver->run_test) {
+		r = dssdev->driver->run_test(dssdev, test_num);
+		if (r)
+			goto end;
+	}
+
+end:
+	dsi2_vc_enable_hs(0, 1);
+
+	dsi2_bus_unlock();
+
+	return r;
+}
+
+static int dsi2_display_memory_read(struct omap_dss_device *dssdev,
+		void *buf, size_t size,
+		u16 x, u16 y, u16 w, u16 h)
+{
+	int r;
+
+	DSSDBGF("");
+
+	if (!dssdev->driver->memory_read)
+		return -EINVAL;
+
+	if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+		return -EIO;
+
+	dsi2_bus_lock();
+
+	r = dssdev->driver->memory_read(dssdev, buf, size,
+			x, y, w, h);
+
+	dsi2_bus_unlock();
+
+	return r;
+}
+
+void dsi2_get_overlay_fifo_thresholds(enum omap_plane plane,
+		u32 fifo_size, enum omap_burst_size *burst_size,
+		u32 *fifo_low, u32 *fifo_high)
+{
+	unsigned burst_size_bytes;
+#ifndef CONFIG_ARCH_OMAP4
+	*burst_size = OMAP_DSS_BURST_16x32;
+	burst_size_bytes = 16 * 32 / 8;
+	*fifo_high = fifo_size - burst_size_bytes;
+	*fifo_low = 0;
+#else
+	*burst_size = OMAP_DSS_BURST_4x32; /* OMAP4: same as 2x128*/
+	burst_size_bytes = 2 * 128 / 8;
+	*fifo_high = 1020; /* check SV comment*/
+	*fifo_low = 956;
+#endif
+}
+
+int dsi2_init_display(struct omap_dss_device *dssdev)
+{
+	DSSDBG("DSI2 init\n");
+
+	dssdev->enable = dsi2_display_enable;
+	dssdev->disable = dsi2_display_disable;
+	dssdev->suspend = dsi2_display_suspend;
+	dssdev->resume = dsi2_display_resume;
+	dssdev->update = dsi2_display_update;
+	dssdev->sync = dsi2_display_sync;
+	dssdev->set_update_mode = dsi2_display_set_update_mode;
+	dssdev->get_update_mode = dsi2_display_get_update_mode;
+	dssdev->enable_te = dsi2_display_enable_te;
+	dssdev->get_te = dsi2_display_get_te;
+
+	dssdev->get_rotate = dsi2_display_get_rotate;
+	dssdev->set_rotate = dsi2_display_set_rotate;
+
+	dssdev->get_mirror = dsi2_display_get_mirror;
+	dssdev->set_mirror = dsi2_display_set_mirror;
+
+	dssdev->run_test = dsi2_display_run_test;
+	dssdev->memory_read = dsi2_display_memory_read;
+
+	dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
+
+	dsi2.vc[0].dssdev = dssdev;
+	dsi2.vc[1].dssdev = dssdev;
+
+	return 0;
+}
+
+int dsi2_init(struct platform_device *pdev)
+{
+	u32 rev;
+
+	struct sched_param param = {
+		.sched_priority = MAX_USER_RT_PRIO-1
+	};
+
+	spin_lock_init(&dsi2.errors_lock);
+	dsi2.errors = 0;
+
+	/* XXX fail properly */
+
+	init_completion(&dsi2.bta_completion);
+	init_completion(&dsi2.update_completion);
+
+	dsi2.thread = kthread_create(dsi2_update_thread, NULL, "dsi2");
+	if (IS_ERR(dsi2.thread)) {
+		DSSERR("cannot create kthread\n");
+		return PTR_ERR(dsi2.thread);
+	}
+	sched_setscheduler(dsi2.thread, SCHED_FIFO, &param);
+
+	init_waitqueue_head(&dsi2.waitqueue);
+	spin_lock_init(&dsi2.update_lock);
+
+	mutex_init(&dsi2.lock);
+	mutex_init(&dsi2.bus_lock);
+
+	dsi2.update_mode = OMAP_DSS_UPDATE_DISABLED;
+	dsi2.user_update_mode = OMAP_DSS_UPDATE_DISABLED;
+
+	dsi2_base = dsi2.base = ioremap(DSI2_BASE, 2000);// MJ DSI_SZ_REGS);
+	if (!dsi2.base) {
+		DSSERR("can't ioremap DSI\n");
+		return -ENOMEM;
+	}
+#if 0
+	ret = twl_i2c_write_u8(TWL6030_MODULE_PWM, 0xFF, PWM2ON); //0xBD = 0xFF
+	ret = twl_i2c_write_u8(TWL6030_MODULE_PWM, 0x7F, PWM2OFF); //0xBE = 0x7F
+	ret = twl_i2c_write_u8(TWL6030_MODULE_AUX, 0x30, TOGGLE3);
+/*
+	dsi2.vdds_dsi2_reg = regulator_get(&pdev->dev, "vdds_dsi");
+	if (IS_ERR(dsi2.vdds_dsi2_reg)) {
+		iounmap(dsi2.base);
+		DSSERR("can't get VDDS_DSI regulator\n");
+		return PTR_ERR(dsi2.vdds_dsi2_reg);
+	}
+*/
+
+	gpio1_base=ioremap(0x4a310000,0x1000);
+	gpio2_base=ioremap(0x48055000,0x1000);
+	rev = __raw_readl(gpio2_base+GPIO_OE);
+	rev &= ~(1<<27);
+	__raw_writel(rev, gpio2_base+GPIO_OE);
+	/* To output signal low */
+	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	mdelay(120);
+	/* To output signal high */
+	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_SETDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_SETDATAOUT);
+	mdelay(120);
+	/* To output signal low */
+	rev = __raw_readl(gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio2_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	mdelay(120);
+	rev = __raw_readl(gpio1_base+GPIO_OE);	rev &= ~(1<<27);
+	__raw_writel(rev, gpio1_base+GPIO_OE);	mdelay(120);
+	/* To output signal high */
+	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_SETDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_SETDATAOUT);
+	mdelay(120);
+	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_CLEARDATAOUT);
+	mdelay(120);
+	/* To output signal high */
+	rev = __raw_readl(gpio1_base+OMAP24XX_GPIO_SETDATAOUT);
+	rev |= (1<<27);
+	__raw_writel(rev, gpio1_base+OMAP24XX_GPIO_SETDATAOUT);
+	mdelay(120);
+#endif
+
+	enable_clocks(1);
+
+	rev = dsi2_read_reg(DSI_REVISION);
+	printk(KERN_INFO "OMAP DSI2 rev %d.%d\n",
+	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
+
+	enable_clocks(0);
+
+	wake_up_process(dsi2.thread);
+
+	return 0;
+}
+
+void dsi2_exit(void)
+{
+	kthread_stop(dsi2.thread);
+
+	//regulator_put(dsi.vdds_dsi_reg);
+
+	iounmap(dsi2.base);
+
+	DSSDBG("omap_dsi2_exit\n");
+}
+
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index a711b990d9c9..31b21ec85225 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -237,12 +237,14 @@ int dss_get_dispc_clk_source(void)
 	return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0);
 }
 
+#ifndef CONFIG_ARCH_OMAP4
 static irqreturn_t dss_irq_handler_omap2(int irq, void *arg)
 {
 	dispc_irq_handler();
 
 	return IRQ_HANDLED;
 }
+#endif
 
 static irqreturn_t dss_irq_handler_omap3(int irq, void *arg)
 {
@@ -275,6 +277,7 @@ static int _omap_dss_reset(void)
 	REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
 	return _omap_dss_wait_reset();
 #endif
+	return 0;
 }
 
 void dss_set_venc_output(enum omap_dss_venc_type type)